High-reliability high-voltage fast-recovery diode and preparation method thereof

Abstract

The application discloses a high-reliability high-voltage fast-recovery diode and a preparation method thereof. The preparation method comprises the following steps: growing an epitaxial layer on the upper surface of a high-doped silicon substrate; forming a P-type doped active region as an anode during normal operation of the device on the central region of the upper surface of the epitaxial layer; forming symmetrical P-type doped field limiting rings as voltage dividing rings of the device on both sides of the active region; forming an N-type doped cutoff ring on the periphery of the field limiting ring; forming a metal field plate on the upper surface of the field limiting ring; directly depositing a metal on the upper surface of the active region as an anode of the device; and forming a back electrode metal layer as a cathode of the device on the bottom of the high-doped silicon substrate. The diode can improve the surface coverage and continuity of the passivation layer and improve the reliability when applied to high-temperature and high-humidity related devices.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and more specifically to a high-reliability high-voltage fast recovery diode and a method for fabricating the diode. Background Technology

[0002] Fast recovery diodes (FRDs) are semiconductor devices with unique switching characteristics and extremely short reverse recovery times. Their internal structure employs a PIN junction design, forming a PIN silicon wafer by adding a thin base region between P-type and N-type silicon materials. This special structure allows the fast recovery diode to recover rapidly after reverse bias, transitioning from the conducting state to the cutoff state, thus effectively reducing switching losses and electromagnetic interference in high-frequency applications. Fast recovery diodes are mainly used in electronic circuits such as switching power supplies, PWM pulse width modulators, and frequency converters, serving as high-frequency rectifier diodes and freewheeling diodes. Their excellent switching performance and reverse recovery characteristics make them indispensable key components in modern electronic equipment. With the continuous development of the new energy industry, fast recovery diodes (FRDs) are increasingly being used in modules packaged with IGBTs. In these applications, the modules typically operate under harsh conditions of high temperature, high humidity, and high pressure. While most module packaging uses silicone gel sealing, which provides good buffering, it offers poor protection against external moisture. When moisture enters the chip's terminal area, it can damage the terminal structure under the influence of the electric field, ultimately preventing the device from withstanding high voltage. Therefore, higher requirements are placed on the moisture resistance of the FRD chip itself. A key optimization direction for improving the chip's moisture resistance is the step coverage and integrity of the passivation layer in the terminal area, ensuring that moisture is blocked outside the passivation layer. Current mainstream FRD chip terminal designs, due to their high surface oxygen steps, suffer from poor passivation layer coverage after processing, making them prone to cracking and discontinuity. This allows moisture to penetrate below the passivation layer during use, damaging the chip's terminal structure under high temperature, high humidity, and high pressure, thus affecting the long-term reliability of the module. Therefore, developing a new high-voltage fast recovery diode that can improve the surface coverage and continuity of the passivation layer and enhance its reliability when applied to high-temperature and high-humidity related devices, in order to meet the ever-growing market demand for new energy and other technologies, is a direction that those skilled in the art need to research. Summary of the Invention

[0003] The purpose of this invention is to provide a high-reliability high-voltage fast recovery diode and its fabrication method, which enables the fabricated high-voltage fast recovery diode to improve the surface coverage and continuity of the passivation layer, thereby enhancing its reliability when applied to high-temperature and high-humidity related devices.

[0004] This invention discloses a method for fabricating a high-reliability high-voltage fast recovery diode, comprising:

[0005] An epitaxial layer is grown on the upper surface of a highly silicon-doped substrate; a P-type doped active region is formed in the central region of the upper surface of the epitaxial layer as the anode when the device is in forward operation; symmetrical P-type doped field limiting rings are formed on both sides of the active region as voltage dividing rings of the device; an N-type doped cutoff ring is formed around the field limiting rings; a metal field plate is formed on the upper surface of the field limiting rings; metal is directly deposited on the upper surface of the active region as the anode of the device; and a back electrode metal layer is formed at the bottom of the highly silicon-doped substrate as the cathode of the device.

[0006] Preferably, the above-mentioned method for fabricating a high-voltage fast recovery diode includes the following steps:

[0007] Step 1: A first epitaxial layer and a second epitaxial layer are sequentially grown on the surface of the highly doped silicon substrate by epitaxy, with the second epitaxial layer located on the surface of the first epitaxial layer; the first epitaxial layer and the second epitaxial layer have the same doping type but different doping concentrations;

[0008] Step 2: A first silicon nitride layer and a top oxide layer are sequentially grown on the upper surface of the second epitaxial layer by chemical vapor deposition or physical vapor deposition;

[0009] Step 3: Using photoresist as a mask layer, define the field oxygen growth region through exposure and development processes; open the window of the field oxygen growth region through wet etching or dry etching processes;

[0010] Step 4: A shallow silicon trench is etched on the second epitaxial layer using a dry etching method;

[0011] Step 5: Remove the top oxide layer by wet etching, retaining the first silicon nitride layer as a masking layer for subsequent field oxygen growth; completing step 5 yields the first intermediate component;

[0012] Step 6: A field oxide layer composed of silicon dioxide is grown on the upper surface of the first intermediate using a high-temperature thermo-oxidative growth method. The first silicon nitride layer is removed using a wet method, so that the upper surface of the field oxide layer is at the same height as the upper surface of the second epitaxial layer, and the ratio of the thickness of the field oxide layer to the depth of the silicon shallow trench is maintained at 1:0.56.

[0013] Step 7: Using photoresist as a mask layer, define the field limit ring implantation region window and the active region implantation region window through exposure and development. Simultaneously implant boron ion impurities into the field limit ring implantation region window and the active region implantation region window using a photoresist-based ion implantation process. Activate the boron ion impurities through a high-temperature furnace tube diffusion process, causing the boron ion impurities implanted in the field limit ring implantation region window to diffuse into the field limit ring implantation region window to form a field limit ring, and causing the boron ion impurities implanted in the active region implantation region window to diffuse into the active region implantation region window to form an active region.

[0014] Step 8: Using photoresist as a mask layer, define the exit stop ring implantation region window through exposure and development processes. Use photoresist-based ion implantation to inject phosphorus ion impurities into the exit stop ring implantation region window. Activate the phosphorus ion impurities through a high-temperature furnace tube diffusion process, causing the phosphorus ion impurities injected into the exit stop ring implantation region window to diffuse into the exit stop ring implantation region window to form a stop ring. Completing Step 8 yields the second intermediate.

[0015] Step 9: Deposit a boron-phosphorus oxide layer as a dielectric layer on the upper surface of the second intermediate part using physical vapor deposition or chemical vapor deposition, and then reflow it using an annealing process.

[0016] Step 10: Using photoresist as a mask layer, define the metal contact area window through exposure and development processes; remove the dielectric layer corresponding to the metal contact area window through wet etching or dry etching processes to form contact holes located on the active region, field limiting ring, and stop ring, respectively; remove the photoresist, implant boron impurities or boron difluoride impurities into the contact holes through ion implantation processes, and anneal to activate the boron difluoride impurities to form P + Contact area; completing step ten yields the third middleware;

[0017] Step 11: Deposit a layer of platinum or gold metal on the upper surface of the third intermediate using a sputtering process. Incorporate the platinum or gold metal into the silicon epitaxial layer of the second epitaxial layer through the contact holes using a furnace tube heat treatment process. Perform high-temperature heat treatment, followed by aqua regia etching to remove the platinum or gold metal above the silicon epitaxial layer. Deposit a uniform aluminum metal layer using a sputtering or evaporation process. Use photoresist as a masking layer and define the active metal electrode region and metal field plate region of the device through exposure and development processes. Etch the aluminum metal layer using wet etching or dry etching processes to form the active metal electrode and metal field plate. Perform low-temperature heat treatment to ensure good ohmic contact between the active metal electrode and the second epitaxial layer. Completing Step 11 yields the fourth intermediate.

[0018] Step 12: Deposit a second silicon nitride layer on the upper surface of the fourth intermediate using a physical deposition or chemical deposition process; use photoresist as a mask layer, define the active area contact hole opening window through exposure and development processes, etch the second silicon nitride layer corresponding to the active area contact hole opening window through dry etching, and remove the photoresist; completing Step 12 yields the fifth intermediate.

[0019] Step 13: A layer of polyimide is coated on the upper surface of the fifth intermediate component to form a polyimide layer. The polyimide layer is used as the second passivation protection layer of the device. The polyimide layer at the contact hole of the source region is removed by exposure and development process and then cured at high temperature.

[0020] Step Fourteen: Thin the lower side of the highly silicon-doped substrate, remove the back damage layer formed by the thinning process by etching, and deposit a back electrode metal layer on the lower side of the highly silicon-doped substrate using physical vapor deposition.

[0021] Preferably, in the above-mentioned method for preparing a high-voltage fast recovery diode, the boron ion impurity is implanted to the field limiting ring and the active region at a dose of 5E12-4E14 and the implantation energy is 50-100Kev.

[0022] Preferably, in the above-mentioned method for preparing a high-voltage fast recovery diode, the phosphorus ion impurity is implanted into the cutoff ring at a dose of 1E14-1E15 and the implantation energy is 60-150keV.

[0023] The present invention also discloses a high-reliability high-voltage fast recovery diode, which is prepared by any of the above-described preparation methods.

[0024] Among them, the central region located above the second epitaxial layer is P. + The contact area serves as the anode when the device is in forward operation; symmetrically distributed on both sides of the active region are P-type doped field limiting rings, which also serve as voltage dividing rings for the device; an N-type doped cutoff ring is located outside the field limiting rings; a metal field plate is placed above each field limiting ring to improve the distribution of the external electric field and enhance the stability of the device; the active region metal electrode serves as the anode of the device; and the back electrode metal layer serves as the cathode of the device.

[0025] Preferably, in the above-mentioned high-reliability high-voltage fast recovery diode, the highly silicon-doped substrate is an N-type substrate, and the highly silicon-doped substrate is configured with a resistivity ≤0.005Ω·cm and a thickness of 400-700μm; the second epitaxial layer is configured with a thickness of 70-200μm and a resistivity of 50-150Ω·cm.

[0026] Preferably, in the aforementioned high-reliability high-voltage fast recovery diode, the thickness of each field limiting ring is 8-20 μm; and the width of the spacing between adjacent field limiting rings increases with the increase of the distance between the spacing and the vertical center of the high-voltage fast recovery diode. Specifically: the spacing between the two adjacent field limiting rings closest to the vertical center of the high-voltage fast recovery diode has the smallest width, and its width value is configured to be 15-30 μm; the width of the other spacing segments increases sequentially by 3-8 μm.

[0027] Preferably, in the above-mentioned high-reliability high-voltage fast recovery diode, the distance between the cutoff ring and the field limiting ring closest to the cutoff ring is 70-150 μm.

[0028] Preferably, in the above-mentioned high-reliability high-voltage fast recovery diode, the field oxide layer is configured to have a thickness of 0.8µm-3µm.

[0029] Compared with the prior art, the beneficial effects of the present invention are:

[0030] The high-voltage fast recovery diode prepared in this invention uses a hard mask layer composed of an oxide layer and silicon nitride for blocking during shallow silicon trench etching. Then, it uses silicon nitride as a shielding layer for localized thermo-oxidative growth. The thickness of the grown field oxide layer matches the depth of the shallow silicon trench in a ratio of 1:0.56. This ensures that after the field oxide growth is completed, the surface step is flush with the epitaxial layer surface. After the passivation layer is applied in subsequent processes, the overall height of the surface step is greatly reduced, improving the surface coverage and continuity of the passivation layer compared to current mainstream processes. This significantly improves the reliability of devices related to high temperature and high humidity. Attached Figure Description

[0031] Figure 1 This is a structural diagram after implementing step one. This product is a centrally symmetrical shape; this diagram only shows the structure from its center to one edge. The left side of the diagram represents the product's center, and the right side represents the product's edge.

[0032] Figure 2 This is a structural diagram after implementing step two. This product is a centrally symmetrical shape; this diagram only shows the structure from its center to one edge. The left side of the diagram represents the product's center, and the right side represents the product's edge.

[0033] Figure 3 This is a structural diagram after implementing step three. This product is a centrally symmetrical graphic; this diagram only shows the structure from its center to one edge. The left side of the diagram represents the product's center, and the right side represents the product's edge.

[0034] Figure 4This is a structural diagram after implementing step four. This product is a centrally symmetrical graphic; this diagram only shows the structure from its center to one edge. The left side of the diagram represents the product's center, and the right side represents the product's edge.

[0035] Figure 5 This is a structural diagram after implementing step five. This product is a centrally symmetrical graphic; this diagram only shows the structure from its center to one edge. The left side of the diagram represents the product's center, and the right side represents the product's edge.

[0036] Figure 6 This is a structural diagram after implementing step six. This product is a centrally symmetrical graphic; this diagram only shows the structure from its center to one edge. The left side of the diagram represents the product's center, and the right side represents the product's edge.

[0037] Figure 7 This is a structural diagram after implementing step seven. This product is a centrally symmetrical graphic; this diagram only shows the structure from its center to one edge. The left side of the diagram represents the product's center, and the right side represents the product's edge.

[0038] Figure 8 This is a structural diagram after implementing step eight. This product is a centrally symmetrical graphic; this diagram only shows the structure from its center to one edge. The left side of the diagram represents the product's center, and the right side represents the product's edge.

[0039] Figure 9 This is a structural diagram after implementing step nine. This product is a centrally symmetrical graphic; this diagram only shows the structure from its center to one edge. The left side of the diagram represents the product's center, and the right side represents the product's edge.

[0040] Figure 10 This is a structural diagram after implementing step ten. This product is a centrally symmetrical graphic; this diagram only shows the structure from its center to one edge. The left side of the diagram represents the product's center, and the right side represents the product's edge.

[0041] Figure 11 This is a structural diagram after implementing step eleven in Example 1. This product is a centrally symmetrical graphic; this diagram only shows the structure from its center to one edge. The left side of the diagram represents the center of the product, and the right side represents its edge.

[0042] Figure 12 This is a structural diagram after implementing step 12 in Example 1. This product is a centrally symmetrical graphic; this diagram only shows the structure from its center to one side edge. The left side of the diagram represents the center of the product, and the right side represents the edge of the product.

[0043] Figure 13This is a structural diagram after implementing step thirteen in Example 1. This product is a centrally symmetrical graphic; this diagram only shows the structure from its center to one side edge. The left side of the diagram represents the center of the product, and the right side represents the edge of the product.

[0044] Figure 14 This is a structural diagram after implementing step fourteen in Example 1. This product is a centrally symmetrical graphic; this diagram only shows the structure from its center to one side edge. The left side of the diagram represents the center of the product, and the right side represents the edge of the product.

[0045] In the diagram: The component names corresponding to the various reference numerals are as follows:

[0046] 100. Highly doped silicon substrate; 210. First epitaxial layer; 220. Second epitaxial layer; 310. First silicon nitride layer; 320. Top oxide layer; 330. Window of field oxide growth region; 400. Silicon trench; 500. Field oxide layer; 610. Active region; 620. Field limiting ring; 630. Cut-off ring; 700. Dielectric layer; 710. P + Contact area; 810, active area metal electrode; 820, metal field plate; 830, second silicon nitride layer; 910, polyimide layer; 920, back electrode metal layer. Detailed Implementation

[0047] The present invention will now be further described with reference to the accompanying drawings.

[0048] Example 1, please refer to Figure 1-14 :

[0049] A method for fabricating a high-reliability high-voltage fast recovery diode includes the following steps:

[0050] Step 1: A first epitaxial layer 210 and a second epitaxial layer 220 are sequentially grown on the upper surface of the highly doped silicon substrate 100 by epitaxy, wherein the second epitaxial layer 220 is located on the upper surface of the first epitaxial layer 210; the first epitaxial layer 210 and the second epitaxial layer 220 have the same doping type but different doping concentrations;

[0051] Step 2: A first silicon nitride layer 310 and a top oxide layer 320 are sequentially grown on the upper surface of the second epitaxial layer 220 by chemical vapor deposition or physical vapor deposition;

[0052] Step 3: Using photoresist as a mask layer, define the field oxygen growth region through exposure and development processes; open the window 330 of the field oxygen growth region through wet etching or dry etching processes;

[0053] Step 4: A shallow silicon trench 400 is etched on the second epitaxial layer 220 using a dry etching method;

[0054] Step 5: Remove the top oxide layer 320 by wet etching, retaining the first silicon nitride layer 310 as a masking layer for subsequent field oxygen growth; assume that the first intermediate is obtained after completing step 5;

[0055] Step 6: A field oxide layer 500 composed of silicon dioxide is grown on the upper surface of the first intermediate using a high-temperature thermo-oxidative growth method. The first silicon nitride layer 310 is removed using a wet method, so that the upper surface of the field oxide layer 500 is at the same height as the upper surface of the second epitaxial layer 220.

[0056] Step 7: Using photoresist as a mask layer, define the field limit ring 620 implantation region window and the active region 610 implantation region window through exposure and development. Simultaneously implant boron ion impurities into both the field limit ring 620 and the active region 610 implantation region windows using a photoresist-based ion implantation process. Activate the boron ion impurities using a high-temperature furnace tube diffusion process, causing the boron ion impurities implanted into the field limit ring 620 implantation region window to diffuse into the field limit ring 620 implantation region window to form the field limit ring 620, and causing the boron ion impurities implanted into the active region 610 implantation region window to diffuse into the active region 610 implantation region window to form the active region 610. In this step, the implantation dose of the boron ion impurities is 5E12-4E14, and the implantation energy is 50-100 KeV.

[0057] Step 8: Using photoresist as a mask layer, define the exit stop ring implantation region window through exposure and development processes. Inject phosphorus ion impurities into the exit stop ring implantation region window using a photoresist-based ion implantation process. Activate the phosphorus ion impurities through a high-temperature furnace tube diffusion process, causing the phosphorus ion impurities injected into the exit stop ring implantation region window to diffuse into the exit stop ring implantation region window to form a stop ring. Assume that Step 8 is completed to obtain a second intermediate component. The implantation dose of the phosphorus ion impurities is 1E14-1E15, and the implantation energy is 60-150keV.

[0058] Step 9: Deposit a boron-phosphorus oxide layer as a dielectric layer 700 on the upper surface of the second intermediate part using physical vapor deposition or chemical vapor deposition, and then reflow it using an annealing process.

[0059] Step 10: Using photoresist as a mask layer, define the metal contact area window through exposure and development processes; remove the dielectric layer 700 corresponding to the metal contact area window through wet etching or dry etching processes to form contact holes located on the active region 610, field limiting ring 620, and stop ring 630, respectively; remove the photoresist, implant boron impurities or boron difluoride impurities into the contact holes through ion implantation and anneal, activate the boron difluoride impurities to form P+ contact region 710; completing Step 10 yields the third intermediate part;

[0060] Step 11: A layer of platinum or gold is deposited on the upper surface of the third intermediate using a sputtering process. The platinum or gold is then incorporated into the silicon epitaxial layer 220 through the contact holes using a furnace tube heat treatment process. High-temperature heat treatment is performed, followed by etching with aqua regia to remove the platinum or gold above the silicon epitaxial layer. A uniform aluminum layer is deposited using a sputtering or evaporation process. Photoresist is used as a masking layer, and the active metal electrode 810 region and the metal field plate 820 region of the device are defined using exposure and development processes. The aluminum layer is etched using wet etching or dry etching processes to form the active metal electrode 810 and the metal field plate 820. A low-temperature heat treatment process is then performed to ensure good ohmic contact between the active metal electrode 810 and the second epitaxial layer 220. Completing Step 11 yields the fourth intermediate.

[0061] Step 12: Deposit a second silicon nitride layer 830 on the upper surface of the fourth intermediate using a physical deposition or chemical deposition process; use photoresist as a mask layer, define the contact hole opening window of the active region 610 through exposure and development processes, and etch the second silicon nitride layer 830 corresponding to the contact hole opening window of the active region 610 through dry etching, and remove the photoresist; completing step 12 yields the fifth intermediate;

[0062] Step 13: A layer of polyimide is coated on the upper surface of the fifth intermediate to form a polyimide layer 910. The polyimide layer is used as the second passivation protection layer of the device. The polyimide layer at the contact hole of the source region is removed by exposure and development process and then cured at high temperature.

[0063] Step Fourteen: Thin the lower side of the highly silicon-doped substrate 100, remove the back damage layer formed by the thinning process by etching, and deposit a back electrode metal layer 920 on the lower side of the highly silicon-doped substrate 100 by physical vapor deposition.

[0064] The high-reliability high-voltage fast recovery diode prepared based on the above steps includes:

[0065] A highly doped silicon substrate 100 has a first epitaxial layer 210 and a second epitaxial layer 220 grown on its upper surface. The left side of the upper surface of the second epitaxial layer 220 is a P-type doped active region 610, which serves as the anode region when the device is in forward operation. P-type doped field limiting rings 620 are symmetrically distributed on both sides of the active region 610, and the field limiting rings 620 serve as voltage dividing rings of the device, and are doped simultaneously with the active region 610. The periphery of the field limiting rings 620 is an N-type doped cutoff ring. A metal field plate 820 is provided on the upper surface of each field limiting ring 620 to improve the distribution of the electric field on the peripheral surface and enhance the stability of the device. A back electrode metal layer 920 is deposited on the bottom of the highly doped silicon substrate 100 after thinning to serve as the cathode of the device.

[0066] The highly silicon-doped substrate 100 is an N-type substrate, and the highly silicon-doped substrate 100 is configured such that its resistivity is ≤0.005 Ω·cm and its thickness is 400-700 μm; the second epitaxial layer 220 is configured such that its thickness is 70-200 μm and its resistivity is 50-150 Ω·cm.

[0067] In this example, in the high-voltage fast recovery diode: the upper surface of the second epitaxial layer 220, except for the contact hole region of the active region 610, the field plate contact hole region of the field limiting ring 620, and the contact hole region of the cutoff ring, is covered with a field oxide layer 500 or a dielectric layer 700. The thickness of each field limiting ring 620 is 8~20μm; and the width of the spacing between adjacent field limiting rings 620 increases with the distance between the spacing and the vertical center of the high-voltage fast recovery diode. Specifically, the distance between the cutoff ring and the field limiting ring 620 closest to the cutoff ring is 70-150μm. The field oxide layer 500 is configured to have a thickness of 0.8μm~3μm.

[0068] The above are merely preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for fabricating a high-reliability high-voltage fast recovery diode, characterized in that, include: An epitaxial layer is grown on the upper surface of a highly silicon-doped substrate; a P-type doped active region is formed in the central region of the upper surface of the epitaxial layer as the anode when the device is in forward operation; symmetrical P-type doped field limiting rings are formed on both sides of the active region as voltage dividing rings of the device; an N-type doped cutoff ring is formed around the field limiting rings; a metal field plate is formed on the upper surface of the field limiting rings; metal is directly deposited on the upper surface of the active region as the anode of the device; and a back electrode metal layer is formed at the bottom of the highly silicon-doped substrate as the cathode of the device.

2. The preparation method according to claim 1, characterized in that: Includes the following steps: Step 1: A first epitaxial layer and a second epitaxial layer are sequentially grown on the surface of the highly doped silicon substrate by epitaxy, with the second epitaxial layer located on the surface of the first epitaxial layer; the first epitaxial layer and the second epitaxial layer have the same doping type but different doping concentrations; Step 2: A first silicon nitride layer and a top oxide layer are sequentially grown on the upper surface of the second epitaxial layer by chemical vapor deposition or physical vapor deposition; Step 3: Using photoresist as a mask layer, define the field oxygen growth region through exposure and development processes; open the window of the field oxygen growth region through wet etching or dry etching processes; Step 4: A shallow silicon trench is etched on the second epitaxial layer using a dry etching method; Step 5: Remove the top oxide layer by wet etching, retaining the first silicon nitride layer as a masking layer for subsequent field oxygen growth; completing step 5 yields the first intermediate component; Step 6: A field oxide layer composed of silicon dioxide is grown on the upper surface of the first intermediate using a high-temperature thermo-oxidative growth method. The first silicon nitride layer is removed using a wet method, so that the upper surface of the field oxide layer is at the same height as the upper surface of the second epitaxial layer. Step 7: Using photoresist as a mask layer, define the field limit ring implantation region window and the active region implantation region window through exposure and development. Simultaneously implant boron ion impurities into the field limit ring implantation region window and the active region implantation region window using a photoresist-based ion implantation process. Activate the boron ion impurities through a high-temperature furnace tube diffusion process, causing the boron ion impurities implanted in the field limit ring implantation region window to diffuse into the field limit ring implantation region window to form a field limit ring, and causing the boron ion impurities implanted in the active region implantation region window to diffuse into the active region implantation region window to form an active region. Step 8: Using photoresist as a mask layer, define the exit stop ring implantation region window through exposure and development processes. Use photoresist-based ion implantation to inject phosphorus ion impurities into the exit stop ring implantation region window. Activate the phosphorus ion impurities through a high-temperature furnace tube diffusion process, causing the phosphorus ion impurities injected into the exit stop ring implantation region window to diffuse into the exit stop ring implantation region window to form a stop ring. Completing Step 8 yields the second intermediate. Step 9: Deposit a boron-phosphorus oxide layer as a dielectric layer on the upper surface of the second intermediate part using physical vapor deposition or chemical vapor deposition, and then reflow it using an annealing process. Step 10: Use photoresist as a mask layer and define the metal contact area window through exposure and development processes; The dielectric layer corresponding to the window of the metal contact area is removed by wet etching or dry etching process to form contact holes; After removing the photoresist, boron or boron difluoride impurities are implanted into the contact holes using an ion implantation process, followed by annealing to activate the boron difluoride impurities to form P. + Contact area; completing step ten yields the third middleware; Step 11: A layer of platinum or gold metal is deposited on the upper surface of the third intermediate using a sputtering process, and the platinum or gold metal is incorporated into the silicon epitaxial layer of the second epitaxial layer through the contact hole using a furnace tube heat treatment process. High-temperature heat treatment is performed, followed by etching with aqua regia to remove platinum or gold metal on the silicon epitaxial layer; a uniform aluminum metal layer is deposited using sputtering or evaporation processes, and photoresist is used as a masking layer. The active metal electrode region and the metal field plate region of the device are defined by exposure and development processes. The aluminum metal layer is etched using wet etching or dry etching processes to form an active region metal electrode and a metal field plate; a low-temperature heat treatment process is used to form a good ohmic contact between the active region metal electrode and the second epitaxial layer; completing step eleven yields the fourth intermediate part. Step 12: Deposit a second silicon nitride layer on the upper surface of the fourth intermediate using a physical deposition process or a chemical deposition process; use photoresist as a mask layer, define the active area contact hole opening window by exposure and development process, etch the second silicon nitride layer corresponding to the active area contact hole opening window by dry etching, and remove the photoresist. Upon completing step twelve, the fifth middleware will be obtained; Step 13: A layer of polyimide is coated on the upper surface of the fifth intermediate component to form a polyimide layer. The polyimide layer is used as the second passivation protection layer of the device. The polyimide layer at the contact hole of the source region is removed by exposure and development process and then cured at high temperature. Step Fourteen: Thin the lower side of the highly silicon-doped substrate, remove the back damage layer formed by the thinning process by etching, and deposit a back electrode metal layer on the lower side of the highly silicon-doped substrate using physical vapor deposition.

3. The preparation method according to claim 2, characterized in that: The boron ion impurity is injected at a dose of 5E12-4E14 into the field confinement ring and the active region, and the injection energy is 50-100Kev.

4. The preparation method according to claim 3, characterized in that: The phosphorus ion impurity is implanted into the stop ring at a dose of 1E14-1E15 and an implantation energy of 60-150 keV.

5. A high-reliability high-voltage fast recovery diode, characterized in that: It is prepared by the preparation method according to any one of claims 1-4.

6. The high-voltage fast recovery diode according to claim 5, characterized in that: The highly doped silicon substrate is an N-type substrate, and the highly doped silicon substrate is configured such that the resistivity of the highly doped silicon substrate is ≤0.005Ω·cm and the thickness of the highly doped silicon substrate is 400-700μm; the second epitaxial layer is configured such that the thickness of the second epitaxial layer is 70-200μm and the resistivity of the second epitaxial layer is 50-150Ω·cm.

7. The high-voltage fast recovery diode according to claim 6, characterized in that: The thickness of each field limiting ring is 8~20μm; and the width of the gap between adjacent field limiting rings increases with the increase of the distance between the gap and the vertical center of the high voltage fast recovery diode.

8. The high-voltage fast recovery diode according to claim 7, characterized in that: The distance between the cutoff ring and the field limiting ring closest to the cutoff ring is 70-150 μm.

9. The high-voltage fast recovery diode according to claim 8, characterized in that: The field oxygen layer is configured such that its thickness is 0.8 μm to 3 μm.

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