Wire configured bipolar transistor

Abstract

The present disclosure relates to a line configured bipolar transistor. A bipolar transistor includes a semiconductor stack having a three-dimensional wiring shape, which includes, in order, a collector portion, a base portion, and an emitter portion. A lower insulating layer at least partially surrounds and contacts side edge sides of the collector portion. An intermediate doped layer at least partially surrounds and contacts side edges of the base portion. An upper insulating portion at least partially surrounds and contacts side edges of the emitter portion.

Description

[0001] Priority requirements

[0002] This application claims priority to French patent application No. FR2504310, filed on April 23, 2025, the entire contents of which are incorporated herein by reference to the fullest extent permitted by law. Technical Field

[0003] This description generally relates to bipolar transistors in line configurations, whether homojunction or heterojunction, and methods of their manufacture. Background Technology

[0004] It is well known that bipolar transistors, especially SiGe heterojunction bipolar transistors (HBTs), exhibit particularly good performance in high-frequency applications, especially in the millimeter-wave and terahertz frequency ranges. Such transistors demonstrate high performance in terms of gain, 1 / f noise, and breakdown voltage.

[0005] Typically, a bipolar transistor corresponds to two PN diodes facing each other. It includes: an emitter doped according to a first conductivity type, which generates carriers in the emitter and injects them into the base; a base doped according to a second conductivity type opposite to the first type, wherein the transistor current is controlled at the base; and a collector doped according to the first conductivity type, wherein carriers are collected at the collector.

[0006] To improve performance, a bipolar transistor configuration with a three-dimensional wire shape is desired. Summary of the Invention

[0007] According to one aspect of this disclosure, a bipolar transistor in a three-dimensional line configuration is proposed, the structure of which can be fabricated using conventional methods and processes in microelectronics.

[0008] Therefore, the bipolar transistor includes: a substrate made of a crystalline semiconductor material and having an upper surface; a lower doped region located in the substrate and flush with the upper surface of the substrate; a semiconductor stack having a three-dimensional linear shape, extending from the substrate and sequentially including: a collector portion located on and in contact with the lower doped region; a base portion located on and in contact with the collector portion; and an emitter portion located on and in contact with the base portion; a lower insulating layer located on the substrate and at least partially surrounding and in contact with the side edge of the collector portion; an intermediate doped layer made of a crystalline semiconductor material located on the lower insulating layer and at least partially surrounding and in contact with the side edge of the base portion; and an upper insulating portion at least partially surrounding and in contact with the side edge of the emitter portion.

[0009] According to one embodiment, the material of the lower doped region and the material of the semiconductor stack are single crystals.

[0010] According to one embodiment, the lower doped region, the semiconductor stack, and the intermediate doped layer are made of silicon.

[0011] According to one embodiment, the bipolar transistor includes an epitaxial regenerated layer located on a lower insulating layer, laterally spaced around a base portion, and made of a crystalline (preferably, single-crystal) semiconductor material, with an intermediate doped layer located on and in contact with the epitaxial regenerated layer.

[0012] According to one embodiment, the lower insulating layer contacts the collector portion over its entire height and perimeter, and contacts the lower portion of the side edge of the base portion over its entire perimeter, thereby electrically insulating the intermediate doped layer from the collector portion.

[0013] According to one embodiment, the upper insulating portion contacts the emitter portion over its entire height and perimeter, and contacts the upper portion of the side edge of the base portion over its entire perimeter, thereby electrically insulating the intermediate doped layer from the emitter portion.

[0014] According to one embodiment, the semiconductor stack has a constant lateral dimension over its entire height.

[0015] According to one embodiment, the bipolar transistor includes a filling layer made of an electrically insulating material, through which extend: a collector contact in contact with a lower doped region; a base contact in contact with an intermediate doped layer; and an emitter contact in contact with an emitter portion.

[0016] According to one embodiment, the lower doped region includes on its upper surface a non-siliconized portion of a semiconductor stack in contact with it, and a siliconized portion in contact with a collector contact; the intermediate doped layer has on its upper surface a siliconized portion in contact with a base contact; and the emitter portion has on its upper surface a siliconized portion in contact with an emitter contact.

[0017] According to one embodiment, the base portion is made of silicon-germanium.

[0018] According to another aspect, an integrated circuit is proposed, which includes a plurality of bipolar transistors according to any of the aforementioned features.

[0019] According to another aspect, a method for manufacturing a bipolar transistor is proposed, comprising the following steps: creating a lower doped region in a substrate made of a crystalline semiconductor material and having an upper surface flush with the upper surface of the substrate; creating a lower insulating layer on the substrate and the lower doped region; creating an epitaxial regeneration layer on the lower insulating layer and having through-holes; creating a sacrificial layer covering the epitaxial regeneration layer and the through-holes; creating an upper insulating layer covering the sacrificial layer; creating a cavity extending downward to the lower doped region and through the through-holes; and creating a semiconductor stack having a three-dimensional line shape in the cavity by epitaxial growth, the stack extending from the substrate and sequentially including: a collector portion, the collector portion... Located on and in contact with the lower doped region; a base portion located on and in contact with the collector portion; and an emitter portion located on and in contact with the base portion; an upper insulating portion created by partial etching of an upper insulating layer, the upper insulating portion at least partially surrounding and in contact with the side edge of the emitter portion, wherein the upper insulating layer is completed to cover the emitter portion; selectively removing the sacrificial layer to release the surface of the epitaxial regrown layer and the surface of the base portion; and creating an intermediate doped layer made of a crystalline semiconductor material by epitaxial growth starting from the released surface of the epitaxial regrown layer and the released surface of the base portion.

[0020] According to one embodiment, the semiconductor stack is created in a single epitaxial step.

[0021] According to one embodiment, during the step of creating the lower insulating layer, a first sublayer is deposited on the substrate and the lower doped region; then a second sublayer is transferred to the first sublayer and bonded to it, the second sublayer having an epitaxial regrowth layer, made of a single crystal material, coated on its opposite surface.

[0022] According to one embodiment, the method further includes the following steps: creating a non-siliconized portion and a siliconized portion of a semiconductor stack in contact thereon on the upper surface of the lower doped region; creating a siliconized portion on the upper surface of the intermediate doped layer; creating a siliconized portion on the upper surface of the emitter portion; creating a fill layer made of an electrically insulating material covering the semiconductor stack, the intermediate doped layer, and the lower insulating layer; creating a collector contact in contact with the siliconized portion of the lower doped region through the fill layer; creating a base contact in contact with the siliconized portion of the intermediate doped layer; and creating an emitter contact in contact with the siliconized portion of the emitter portion. Attached Figure Description

[0023] Other advantages and features of the invention will become apparent from the following non-limiting detailed description and accompanying drawings of embodiments and implementations, wherein:

[0024] Figure 1 It is a schematic partial view of an integrated circuit including at least one bipolar transistor in a line configuration; and

[0025] Figures 2A to 2O Various steps of a method for manufacturing an integrated circuit comprising at least one bipolar transistor in a line configuration are shown. Detailed Implementation

[0026] In the accompanying drawings and the following description, the same reference numerals denote the same or similar elements. Furthermore, the various elements are not drawn to scale to improve clarity. Moreover, the various embodiments and alternatives are not mutually exclusive and can be combined with each other.

[0027] Unless otherwise stated, the terms “basically,” “about,” and “approximately” mean within 10%, and preferably within 5%. Furthermore, the terms “between… and…” and their equivalents include the limits, unless otherwise stated.

[0028] Figure 1 This is a schematic partial view of an integrated circuit including bipolar transistors in a wiring configuration according to one embodiment. Here, for clarity of the drawings, only one bipolar transistor 1 is shown.

[0029] Here and in the remainder of the description, a three-dimensional right-handed coordinate system XYZ is defined, in which the plane XY is parallel to the principal plane of the bipolar transistor 1, and the axis Z is oriented along the thickness of the latter. Furthermore, the terms "lower" and "upper" refer to relative positions increasing along the +Z direction.

[0030] Bipolar transistor 1 here is a homojunction and is of NPN type. However, it can also be a heterojunction, such as Si / SiGe type, and it can also be of PNP type.

[0031] The bipolar transistor 1 includes a substrate 2 made of a crystalline semiconductor material, and preferably of a single-crystal material, such as silicon. The substrate 2 may be unintentionally or slightly doped with P-type or N-type doping. It has a generally flat upper surface 2a. This can be a monolithic substrate or a substrate formed by stacking multiple layers, in which case the upper layer defining the upper surface is made of single-crystal silicon.

[0032] The bipolar transistor 1 also includes a lower doped region 3, also referred to as the external collector layer. This external collector layer 3 is made of a crystalline semiconductor material and is doped with the same type of conductivity as the collector portion 11 described below, which is N-type in the case of the NPN bipolar transistor 1.

[0033] Region 3 is located in substrate 2 and is flush with a portion of its upper surface 2a. The outer collector layer 3 can be formed by localized ion implantation of dopants into substrate 2.

[0034] When the external collector layer 3 is formed by deposition on a support substrate, the assembly formed by the support substrate and the external collector layer 3 is referred to as substrate 2.

[0035] In the remainder of the description, collector layer 3 and base layer 6 will be referred to as “external” in terms of their characteristics not being modulated by polarization conditions. However, collector portion 11, base portion 12, and emitter portion 13, described below, form the “internal” portion of bipolar transistor 1.

[0036] The unsiliconized portion 3.1 of the upper surface 2a of the external collector layer 3 corresponds to the nucleation region for forming the linear semiconductor stack 10 described below by epitaxial regeneration.

[0037] Another portion 3.2 of the upper surface 2a of the outer collector layer 3 can be siliconized, thereby improving the resistance of the contact with the collector contact 31.

[0038] The bipolar transistor 1 includes a semiconductor stack 10, which is formed sequentially from the substrate 2 by the following: a collector portion 11, a base portion 12, and then an emitter portion 13.

[0039] The semiconductor stack 10 has a three-dimensional line shape. In other words, it has an elongated shape extending vertically along axis Z, which is substantially perpendicular to the plane XY of the substrate 2, and has a lateral dimension (in the plane XY) smaller than its longitudinal dimension. The term "line" is synonymous with "rod". It can be referred to as a "nanowire" or "microwire", depending on the value of the lateral dimension. The linear semiconductor stack will be referenced below.

[0040] For example, in the case of "microwires," the lateral dimension can be approximately one micrometer, or even ten or one hundred micrometers, while in the case of "nanowires," they can be approximately ten to one hundred nanometers. The longitudinal dimension (or height) of the linear stack can be greater than two, five, or more times its lateral dimension. For a height of approximately several hundred nanometers, "nanowires" can have a diameter of approximately tens to approximately one hundred nanometers.

[0041] Here, height refers to the longitudinal dimension of portions 11, 12, 13 along axis Z of the linear stack 10, or the longitudinal dimension of the linear stack 10, between the lower and upper surfaces of the element under consideration, along axis Z. These lower and upper surfaces are connected to each other by peripheral side surfaces forming side edges.

[0042] The cross-section (in the plane XY) of the wire semiconductor stack 10 can have various shapes, such as circular, elliptical, polygonal, such as square, rectangular, hexagonal, etc. Preferably, the cross-section is circular.

[0043] Here, the diameter is defined as a value associated with the perimeter of the wire stack at its transverse cross-section. It can be the diameter of a disk having the same area as the transverse cross-section of the wire semiconductor stack 10. The local diameter is the diameter of the wire semiconductor stack 10 at its given height along the longitudinal axis Z.

[0044] Preferably, the local diameter is substantially constant over the entire height of the line semiconductor stack 10. In other words, the collector portion 11, the base portion 12, and the emitter portion 13 have substantially the same local diameter. This configuration allows for optimization of the collector current Ic.

[0045] Alternatively, the local diameter may not be constant over the height of the entire line semiconductor stack 10. Thus, for example, the emitter portion 13 may have an average diameter smaller than the average diameter of the collector portion 11, and the base portion 12 may have a local diameter variation that changes from the diameter of the emitter portion 13 to the diameter of the collector portion 11. This configuration can allow for a reduction in the recombination rate of electrons injected near the holes injected by the outer base layer 6.

[0046] The collector portion 11 extends and contacts the unsiliconized portion 3.1 (nucleation region) of the outer collector layer 3. It extends longitudinally along the longitudinal axis Z. Preferably, it is made of the same single-crystal semiconductor material as the outer collector layer 3 (with the substrate). In this example, it is made of single-crystal silicon. In the case of an NPN transistor, this material is N-type doped.

[0047] The base portion 12 extends over and contacts the collector portion 11. It extends longitudinally along the longitudinal axis Z. It is made of a crystalline semiconductor material, such as silicon or silicon-germanium, preferably single-crystal. In this example, where the transistor is a homojunction transistor, it is made of single-crystal silicon. In the case of an NPN transistor, the material is P-type doped. In the case of a heterojunction (HBT) transistor, the material can be silicon-germanium, preferably single-crystal. The vertical distribution of the germanium concentration can have a triangular shape, as described in the article entitled “SiGe-based Nanowire HBT for THz Applications” by Panda et al. (2023 IEEE Conference on Electronic Device Technology and Manufacturing (EDTM), Seoul, South Korea, 2023, pp. 1–3, which is incorporated herein by reference). It can have other types of variations.

[0048] The emitter portion 13 extends over and contacts the base portion 12. It extends longitudinally along the longitudinal axis Z. It is made of a crystalline (preferably single-crystal) semiconductor material, such as the same material as the collector portion 11. In this example, it is made of single-crystal silicon. In the case of an NPN transistor, this material is strongly N-type doped.

[0049] The wire semiconductor stack 10 is located in a vertical cavity 25 (through-hole, see below) formed in a multilayer stack. Figure 2G )middle.

[0050] Therefore, the lower insulating layers 4.1 and 4.2 extend over the substrate 2 and the intrinsic external collector layer 3. They are formed of an electrically insulating material such as silicon oxide. These lower insulating layers 4.1 and 4.2 surround and contact the lateral edge of the collector portion 11 in the XY plane, preferably along its entire periphery.

[0051] It also contacts the lower portion of the lateral edge of the base portion 12 in the plane XY and along its entire periphery in the plane XY, preferably along its entire periphery. Thus, the lower insulating layer (formed by sublayers 4.1, 4.2) has a thickness along axis Z slightly greater than the height of the collector portion 11, so as to fully contact the collector portion 11 and the bottom portion of the base portion 12 here.

[0052] In this example, the lower insulating layer is formed by a first insulating layer 4.1 and a second insulating layer 4.2. The first insulating layer 4.1 is positioned to contact the substrate 2 and the external collector layer 3, and the second insulating layer 4.2 covers the first insulating layer. Layer 4.1 may be deposited silicon oxide, and layer 4.2 may be transferred and assembled to the silicon oxide of layer 4.1 by direct bonding. The transferred and bonded oxide may be a buried oxide layer (BOX) of the SOI substrate. Alternatively, the lower insulating layer may be the same oxide layer created by deposition.

[0053] Then, the epitaxial regeneration layer 5 (also called the nucleation layer) is located on the lower insulating layer, here on layer 4.2. It surrounds the base portion 12 in the XY plane, preferably along its entire periphery, while being laterally spaced from it. In other words, in the XY plane, there is a space between the lateral edges of the base portion 12 and the lateral edges of the epitaxial regeneration layer 5 facing it. This layer is made of a crystalline semiconductor material, allowing the creation of the external base layer 6 by selective epitaxy. It is preferably single-crystal. The single-crystal nature of the epitaxial regeneration layer 5 allows for high-quality selective epitaxial growth of the external base and reduces the base junction resistance. It can be a layer made of silicon or silicon-germanium. Here, the material can be unintentionally or intentionally doped.

[0054] On one hand, the outer base layer 6 is located on and in contact with the epitaxial regenerated layer 5. On the other hand, it surrounds the base portion 12 in the XY plane, preferably along its entire periphery, while also contacting its lateral edges. It is formed of a crystalline semiconductor material, in this case silicon, because the bipolar transistor 1 is a homojunction. In the case of a SiGe HBT transistor, it can be made of silicon germanium.

[0055] When the base portion 12 and the epitaxial regrown layer 5 are made of single-crystal material, the outer base layer 6 can be single-crystal at the interface with the base portion 12, and also at the interface with the epitaxial regrown layer 5. It can be polycrystalline in the connection region located between the epitaxial regrown layer 5 and the upper insulating portion 7.

[0056] The upper insulating portion 7 surrounds and contacts the lateral edge of the emitter portion 13 in the XY plane, along its entire periphery. It is made of an electrically insulating material (e.g., silicon oxide). Furthermore, it extends over the top portion of the lateral edge of the base portion 12. Therefore, it prevents contact between the outer base layer 6 and the emitter portion 13. Thus, it forms a protective shell located at the conductor tip.

[0057] Therefore, the outer base layer 6 contacts the base portion 12 only at the central portion of its lateral edge height, thus avoiding any electrical contact between the outer base layer 6 and the collector portion 11 on one hand, and any electrical contact between the emitter portion 13 and the base portion 12 on the other hand. Indeed, the lower insulating layer 4.2 also extends over the lower portion of the lateral edge of the base portion 12, thereby preventing contact between the outer base layer 6 and the collector portion 11. And the upper insulating portion 7 extends over the top portion of the lateral edge of the base portion 12, thereby preventing contact between the outer base layer 6 and the emitter portion 13. As a result, the outer base layer 6 contacts only the central portion of the lateral edge of the base portion 12, and therefore does not contact the base portion 12 over its entire height.

[0058] Finally, according to one embodiment, a silicided region is present to reduce contact resistance. The outer collector layer 3 has a silicided portion 3.2 on its upper surface 2a, where the collector contact 31 contacts. This silicided portion 3.2 is spaced apart in the plane XY from the non-silicided portion 3.1 on which the wire semiconductor stack 10 is located, wherein the wire semiconductor stack 10 is located on the non-silicided portion 3.1.

[0059] The outer base layer 6 has a silicided portion 6.1 on its upper surface, where the base contact 32 makes contact.

[0060] The emitter portion 13 includes a siliconized portion 13.1 on its upper surface, where the emitter contact 33 makes contact.

[0061] The collector contact 31, base contact 32, and emitter contact 33 are made of an electrically conductive material, such as one or more metals. They extend perpendicularly through a fill layer 27 made of an electrically insulating material to contact the corresponding silicided portions 3.2, 6.1, and 13.1. The fill layer 27 extends in a plane XY to cover the bipolar transistor 1 (semiconductor stack 10, outer base layer 6, and lower insulating layers 4.1 and 4.2).

[0062] Therefore, the bipolar transistor 1 has a wire configuration in which the electrical contacts of the collector portion 11, the base portion 12, and the emitter portion 13 are formed on the front surface, i.e., on the side opposite to the substrate 2. Furthermore, the electrical contacts of the collector portion 11 are implemented by an external collector layer 3 made of preferably monocrystalline silicon. This bipolar transistor 1 can be created using conventional techniques in microelectronics (layer deposition, local etching, transfer, and bonding, etc.).

[0063] To reiterate, the bipolar transistor 1 can be a homojunction or a heterojunction. It can also be NPN or PNP type.

[0064] Furthermore, according to one embodiment, the bipolar transistor 1 may have a structure symmetrical about a vertical axis passing through the center of the semiconductor stack 10. Therefore, it may include collector contacts 31 and base contacts 32 symmetrically positioned relative to this vertical axis.

[0065] The collector portion 11, base portion 12, and emitter portion 13 can be made of single-crystal material, thereby improving the performance of the bipolar transistor 1. Moreover, the lateral dimensions of the collector portion 11, base portion 12, and emitter portion 13 can be constant along the entire height of the semiconductor stack 10 along the lead wires, which also helps to improve performance.

[0066] Figures 2A to 2O Various steps of a method for manufacturing an integrated circuit including bipolar transistors with a line configuration, according to one embodiment, are illustrated. In this example, as in... Figure 1 As shown in the previous example, a single transistor is illustrated. This is an NPN type homojunction transistor, but it could be a PNP type, or even a heterojunction, such as a Si / SiGe type.

[0067] refer to Figure 2A The substrate 2 is made of monocrystalline silicon. As mentioned above, it can be unintentionally doped or slightly P-doped or N-doped. It has a flat upper surface 2a.

[0068] refer to Figure 2B An external collector layer 3 is created. Here, this is an N-doped region in the substrate 2, created by ion implantation of dopant into the substrate 2 in a localized manner via an ion implantation mask 21. The external collector layer 3 is flush with the upper surface 2a.

[0069] refer to Figure 2C A silicided portion 3.2 is formed at the upper surface 2a to create an external collector layer 3, while a non-silicided portion 3.1 is maintained at the same upper surface 2a.

[0070] To this end, a mask 22 is deposited on substrate 2 to cover a portion of the external collector layer 3 and expose another portion. Silicification can be performed in a conventional manner, such as by deposition of a metal layer, followed by one or more rapid annealing operations, and finally removal of unreacted metal.

[0071] refer to Figure 2D A first insulating layer 4.1 (here made of silicon oxide) is deposited to cover the substrate 2 and the external collector layer 3, both at the unsiliconized portion 3.1 and the siliconized portion 3.2. A chemical mechanical planarization step can be performed to obtain a flat upper surface.

[0072] refer to Figure 2EThe second insulating layer 4.2 (here made of silicon oxide) is assembled by oxide / oxide type transfer and direct bonding. For this purpose, a stack created by the epitaxial regrown layer 5 (here made of single-crystal silicon) and the second insulating layer 4.2 is transferred onto the first insulating layer 4.1. This stack can be derived from a silicon-on-insulator (SOI) substrate. The two insulating layers 4.1 and 4.2 are placed in contact and assembled together by direct bonding.

[0073] It should be noted that, alternatively, a single insulating layer may have already been deposited on substrate 2, and then an epitaxial regrown layer may be deposited on the insulating layer. The epitaxial regrown layer may be made of, for example, polycrystalline silicon or amorphous silicon.

[0074] refer to Figure 2F A creation window 5.1 (through-hole) is formed in the epitaxial regeneration layer 5 by local etching. This window 5.1 is designed to allow the formation of a creation cavity 25 therein (see...). Figure 2G ), which will form a wired semiconductor stack 10 within its cavity (see Figure 2G ).

[0075] A sacrificial layer 23 is then deposited to cover the epitaxial regrown layer 5 and fill window 5.1. It can be made of silicon nitride. A chemical mechanical planarization step can then be performed to obtain a flat upper surface. The sacrificial layer 23 is made of a material that can be selectively removed by isotropic chemical etching. In other words, the chemicals used will only remove the sacrificial layer 23, without removing the silicon or oxide present.

[0076] Finally, an upper insulating layer 24 is deposited to cover the sacrificial layer 23. This layer is made of an electrically insulating material (here, an oxide). It is designed to allow portions 11, 12, and 13 to be selectively epitaxially grown within cavity 25 (see [link to documentation]). Figure 2G ), and subsequently form the protective housing 7 that creates the emitter portion 13 (see Figure 2J ).

[0077] refer to Figure 2G A cavity 25 (through-hole) is formed, which extends vertically through the upper insulating layer 24, the sacrificial layer 23, and the two insulating layers 4.2 and 4.1, to open at the upper surface 2a onto the non-siliconized portion 3.1 of the outer collector layer 3. Thus, the cavity 25 is located in the window 5.1 defined by the epitaxial regrown layer 5.

[0078] refer to Figure 2HA wired semiconductor stack 10 is formed in the cavity 25 by epitaxial growth. First, a collector portion 11 is formed by epitaxial growth starting from the non-siliconized portion 3.1 of the outer collector layer 3, then a base portion 12 is formed, and finally an emitter portion 13 is formed.

[0079] The epitaxial growth here is selective epitaxy, because the crystalline material of the linear semiconductor stack 10 is grown only from the material of the outer collector layer 3 (here, single-crystal silicon) and not from the oxide or nitride layer.

[0080] Deposition can be performed by chemical vapor deposition, for example at reduced pressure (LPCVD, for low-pressure chemical vapor deposition) or at rapid temperature (RTCVD, for rapid thermal chemical vapor deposition). It should be noted that this epitaxy of the collector portion 11, the base portion 12, and the emitter portion 13 can be performed during the same consecutive epitaxial step, which helps to improve the crystallinity of the material.

[0081] Therefore, the collector portion 11 is first created by epitaxial formation starting from the non-siliconized portion 3.1 made of monocrystalline silicon in the outer collector layer 3. Its height is less than the cumulative thickness of the two insulating layers 4.1, 4.2. Therefore, the entire side edge of the collector portion 11 is in contact with the oxide of the insulating layers 4.1, 4.2 over its entire periphery.

[0082] The base portion 12 is then created by an epitaxial formation starting from the upper surface of the collector portion 11. Its height is such that its side edges first contact the second insulating layer 4.2 over its entire periphery, then contact the sacrificial layer 23 over its entire thickness, and finally contact a portion of the upper insulating layer 24.

[0083] Finally, the emitter portion 13 is created by an epitaxial formation starting from the upper surface of the base portion 12. Its height is such that its side edges are in complete contact with the upper insulating layer 24 over its entire periphery.

[0084] refer to Figure 2I An additional insulating layer 26 (here, an oxide) is deposited to cover the upper insulating layer 24 and the emitter portion 13. Planarization can be performed to obtain a flat upper surface.

[0085] refer to Figure 2J This forms the upper insulating portion 7. To this end, anisotropic local etching is performed on the upper insulating layer 24 and the additional insulating layer 26 to retain only the portion surrounding the head of the wired semiconductor stack 10 (and more precisely the emitter portion 13) and covering that portion. This thus releases (i.e. exposes) the surface of the sacrificial layer 23.

[0086] refer to Figure 2K The sacrificial layer 23 is removed by chemical selective etching. The etchant removes only the sacrificial layer 23 and remains inert relative to the oxide of the upper insulating portion 7, the silicon of the epitaxial regrown layer 5, the material of the base portion 12, and the oxide of the second insulating layer 4.2. Therefore, the upper surface of the epitaxial regrown layer 5 and the central portion of the side edges of the base portion 12 are released.

[0087] refer to Figure 2L An outer base layer 6 is created by epitaxial formation, which begins on the free (i.e., exposed) surface of the base portion 12 on the one hand and on the free surface of the epitaxial regeneration layer 5 on the other hand.

[0088] It is made of a p-type doped semiconductor material. Preferably, the material is selected such that it is single-crystal at the interface with the base portion 12 and at the interface with the epitaxial regrown layer 5. At the junction between these two regions, the material can be polycrystalline. The epitaxial regrown layer 5 can have a thickness such that it surrounds the upper insulating portion 7, covering a portion of its height.

[0089] refer to Figure 2M The outer base layer 6 and the epitaxial regenerated layer 5 are partially etched to retain only the portion surrounding and in contact with the wired semiconductor stack 10. This releases a portion of the upper surface of the second insulating layer 4.2.

[0090] refer to Figure 2N The upper surface of the external base layer 6 is siliconized. The upper surface of the emitter portion 13 is also siliconized.

[0091] For this purpose, the portion of the upper insulating portion 7 covering the emitter portion 13 can be removed by anisotropic dry etching to release its upper surface. Siliconization can then be performed. It should be noted that during this dry etching step, a portion of the second insulating layer may be slightly etched.

[0092] Thus, the silicided portion 6.1 of the outer base layer 6 and the silicided portion 13.1 of the emitter portion 13 are obtained.

[0093] refer to Figure 2O The fabrication of bipolar transistor 1 is completed. This component is covered by a fill layer 27 (which is made of an electrically insulating material, such as nitride and / or silicon oxide). Planarization can be performed to obtain a flat upper surface. Collector contacts 31, base contacts 32, and emitter contacts 33 are created, which penetrate vertically through the fill layer 27 and respectively contact the silicided portion 3.2 of the outer collector layer 3, the silicided region 6.1 of the outer base layer 6, and finally the silicided portion 13.1 of the emitter portion 13.

[0094] Therefore, a bipolar transistor 1 with a linear configuration is obtained, whose inherent portion is formed by a collector portion 11, a base portion 12, and an emitter portion 13 of a line semiconductor stack 10, and includes a lower external collector layer 3 and an intermediate external base layer 6. This bipolar transistor is created using conventional microelectronic techniques (deposition of deposited layers, local etching, etc.).

[0095] The collector portion 11, base portion 12, and emitter portion 13 have good crystal quality because they can be made of one or more single-crystal materials. The material of the intermediate outer base layer 6 can also be single-crystal in a portion of its volume, especially at the interface with the base portion 12, which improves the transistor's performance.

[0096] The embodiments have just been described. Various alternatives and modifications will be readily apparent to those skilled in the art.

Claims

1. A bipolar transistor, comprising: A substrate, made of crystalline semiconductor material and having an upper surface; The lower doped region is a lower doped region located in the substrate and flush with the upper surface of the substrate. A semiconductor stack having a three-dimensional linear shape, the semiconductor stack extending from a substrate and comprising, in sequence: The collector portion is supported on and in contact with the lower doped region; The base portion, which is located on and in contact with the collector portion; and The emitter portion is located on and in contact with the base portion; A lower insulating layer is located on the substrate and at least partially surrounds and contacts the side edge of the collector portion; An intermediate doped layer, made of a crystalline semiconductor material, is located on the lower insulating layer and at least partially surrounds and contacts the side edges of the base portion; and An upper insulating portion that at least partially surrounds and contacts the side edge of the emitter portion.

2. The bipolar transistor according to claim 1, wherein, The lower doped region and semiconductor stack are made of single-crystal semiconductor material.

3. The bipolar transistor according to claim 1, wherein, The lower doped region, semiconductor stack, and intermediate doped layer are made of silicon.

4. The bipolar transistor according to claim 1, further comprising an epitaxial regrown layer, the epitaxial regrown layer being located on the lower insulating layer and laterally spaced from the base portion, wherein, The epitaxial regeneration layer is made of a crystalline semiconductor material, wherein an intermediate doped layer is located on the epitaxial regeneration layer and in contact with the epitaxial regeneration layer.

5. The bipolar transistor according to claim 4, wherein, The epitaxial regenerated layer is made of single-crystal semiconductor material.

6. The bipolar transistor according to claim 1, wherein, The lower insulating layer contacts the collector portion over its entire height and periphery, and the lower insulating layer contacts the lower portion of the side edge of the base portion over its entire periphery, thereby electrically insulating the intermediate doped layer from the collector portion.

7. The bipolar transistor according to claim 1, wherein, The upper insulating portion contacts the emitter portion over its entire height and periphery, and wherein the upper insulating portion contacts the upper portion of the side edge of the base portion over its entire periphery, thereby electrically insulating the intermediate doped layer from the emitter portion.

8. The bipolar transistor according to claim 1, wherein, The semiconductor stack, which provides a three-dimensional linear shape, has a constant lateral dimension throughout its entire height.

9. The bipolar transistor according to claim 1, further comprising: A filler layer made of electrically insulating material; Collector contact that extends through the fill layer and contacts the underlying doped region; The base contact extends through the fill layer and contacts the intermediate doped layer; and Emitter contact, which extends through the filler layer and makes contact with the emitter portion.

10. The bipolar transistor according to claim 8, wherein: The lower doped region includes a non-siliconized portion on its upper surface, a semiconductor stack in contact with the non-siliconized portion, and a siliconized portion, where a collector contact is in contact with the siliconized portion. The intermediate doped layer has a silicided portion on its upper surface, and the base contact is in contact with the silicided portion; and The emitter portion has a silicided portion on its upper surface, and the emitter contact contacts the silicided portion.

11. The bipolar transistor according to claim 1, wherein, The base portion is made of silicon-germanium.

12. An integrated circuit comprising a plurality of bipolar transistors according to claim 1.

13. A method for manufacturing a bipolar transistor, comprising the following steps: A lower doped region is created in a substrate made of a crystalline semiconductor material and having an upper surface flush with the upper surface of the substrate. A lower insulating layer is created on the substrate and the lower doped region; Create an epitaxial regeneration layer located on the lower insulating layer and having through-holes; Create a sacrificial layer that covers the epitaxial regrowth layer and the vias; Create an upper insulating layer that covers the sacrificial layer; Create a cavity that extends downward to the lower doped region and passes through a via; A semiconductor stack is epitaxially grown in a cavity. The semiconductor stack has a three-dimensional linear shape and extends from a substrate, comprising, in sequence: a collector portion located on and in contact with a lower doped region; a base portion located on and in contact with the collector portion; and an emitter portion located on and in contact with the base portion. An upper insulating portion is created by partial etching of an upper insulating layer, the upper insulating portion at least partially surrounding and contacting the side edge of the emitter portion, wherein the upper insulating layer is completed to cover the emitter portion; An intermediate doped layer is created by removing the upper portion of the upper insulating layer, the sacrificial layer, and the epitaxial regenerated layer. This intermediate doped layer is located on the lower insulating layer and at least partially surrounds and contacts the side edge of the base portion. Selectively removing the sacrificial layer to release the surface of the epitaxial regrowth layer and the surface of the base portion; and An intermediate doped layer made of crystalline semiconductor material is epitaxially grown starting from the free surface of the epitaxial regenerated layer and the free surface of the base portion.

14. The manufacturing method according to claim 13, wherein the epitaxial regrowth layer is made of a single-crystal semiconductor material.

15. The manufacturing method of claim 13, wherein epitaxial growth of the semiconductor stack comprises performing a single epitaxial step.

16. The manufacturing method of claim 13, further comprising, during the step of creating the lower insulating layer: depositing a first sublayer on the substrate and the lower doped region; and then transferring a second sublayer to bond with the first sublayer, the second sublayer having an epitaxial regeneration layer covered on its opposite side by a layer made of a single-crystal material.

17. The manufacturing method according to claim 13, further comprising the following step: A semiconductor stack is created on the upper surface of the lower doped region, with non-siliconized and siliconized portions in contact thereon; A silicided portion is created on the upper surface of the intermediate doped layer; A silicide portion is created on the upper surface of the emitter portion; Create a fill layer made of electrically insulating material covering the semiconductor stack, intermediate doped layer, and lower insulating layer; Collector contacts are created by passing through the fill layer to contact the silicide portion of the lower doped region, base contacts to contact the silicide portion of the intermediate doped layer, and emitter contacts to contact the silicide portion of the emitter region.

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