Semiconductor device and method of manufacturing the same

Abstract

Provided is a semiconductor device capable of improving reliability with a simple configuration and a manufacturing method thereof. The semiconductor device includes a semiconductor layer containing a P-type dopant, a variation in an integrated concentration of the P-type dopant in an entire region of the semiconductor layer is within a prescribed proportion, and an activation rate of the P-type dopant in the semiconductor layer decreases from a central portion to a peripheral portion of the semiconductor layer in stages or continuously.

Description

Related applications:

[0001] This application enjoys priority based on Japanese Patent Application No. 2025-067098 (filed on April 15, 2025). This application incorporates the entire contents of that basic application by reference. Technical Field

[0002] This embodiment relates to a semiconductor device and a method for manufacturing the same. Background Technology

[0003] Power semiconductors capable of high-power, high-speed switching include IGBTs (Insulated Gate Bipolar Transistors). In power semiconductors such as IGBTs, P-type impurity ions are sometimes implanted into the collector. In this case, depending on the amount of P-type impurity ions implanted, holes implanted from the collector layer of the region where the IGBT element is located (hereinafter also referred to as the cell section) concentrate at the end, potentially damaging the semiconductor device and becoming a major cause of reduced reliability. Summary of the Invention

[0004] In one embodiment of the invention, a semiconductor device and a method for manufacturing the same are provided that can improve reliability with a simple construction.

[0005] The semiconductor device of this embodiment includes a semiconductor layer containing a P-type dopant, which serves as the collector of a semiconductor element. The variation in the integral concentration of the P-type dopant throughout the entire region of the semiconductor layer is within a specified proportion. The activation rate of the P-type dopant in the semiconductor layer decreases in stages or continuously from the center to the periphery of the semiconductor layer. Attached Figure Description

[0006] Figure 1 This is a schematic cross-sectional view of a first example of a semiconductor device according to a first embodiment of the present disclosure.

[0007] Figure 2 This is a schematic cross-sectional view of a second example of a semiconductor device according to the first embodiment of the present disclosure.

[0008] Figure 3 This is a top view of a semiconductor chip according to the first embodiment of this disclosure.

[0009] Figure 4 This is a top view showing the configuration of the protection ring region in the first embodiment of the present disclosure.

[0010] Figure 5This is a diagram illustrating the laser annealing process of the first embodiment of this disclosure.

[0011] Figure 6 This is a diagram illustrating the first laser irradiation process.

[0012] Figure 7 This is a diagram illustrating the second laser irradiation process.

[0013] Figure 8 It is a waveform diagram showing the relationship between the number of laser irradiations and the resistance value of the thin film.

[0014] Figure 9 This is a top view of a modified semiconductor chip.

[0015] Figure 10 This is the first figure illustrating a modified laser annealing process.

[0016] Figure 11 The second figure illustrates a modified laser annealing process.

[0017] Figure 12 This is a top view of a comparative example semiconductor chip.

[0018] Figure 13 It means Figure 9 A diagram showing the first irradiation range of a laser in a semiconductor chip.

[0019] Figure 14 It means Figure 9 A diagram showing the second irradiation range of a laser in a semiconductor chip.

[0020] Figure 15 This is a diagram illustrating the laser irradiation process for the collector layer according to the second embodiment of this disclosure.

[0021] Figure 16 It means Figure 15 A top view of the protective film. Detailed Implementation

[0022] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. These embodiments are not intended to limit the present invention. The drawings are schematic or conceptual, and the proportions of the parts may not be identical to reality. In the specification and drawings, the same reference numerals are used for elements identical to those described with respect to the prior drawings, and detailed descriptions are omitted where appropriate.

[0023] Additionally, in the following explanation, to indicate the relative levels of impurity concentration in each conductivity type, n is sometimes used. + n (or N), n - and p + p (or P), p -The marker. That is, n + This indicates that the concentration of n-type impurities is relatively high compared to n. - This indicates that the concentration of n-type impurities is relatively low compared to n. Additionally, p... + This indicates that the concentration of p-type impurities is relatively high compared to p-type impurities. - This indicates that the concentration of p-type impurities is relatively low compared to p-type impurities. When both p-type and n-type impurities are present in each region, these markings indicate the relative levels of net impurity concentration after these impurities compensate for each other. In this specification, p-type, p-type, and n-type impurities will also be used interchangeably. + type and p - This type is referred to as the first conductivity type. Additionally, in this specification, n-type and n-type will also be referred to as... + type and n - This type is called the second conductivity type. Furthermore, in the following explanation, the n-type and p-type can also be reversed.

[0024] Furthermore, the impurity concentration in the semiconductor region can be measured, for example, by secondary ion mass spectrometry (SIMS). Additionally, the relative level of impurity concentration can be determined, for example, by the carrier concentration obtained using scanning capacitive microscopy (SCM).

[0025] (First Implementation) Figure 1 This is a schematic cross-sectional view illustrating a first example of a semiconductor device according to a first embodiment of the present disclosure. The semiconductor device 1a is a vertical trench IGBT.

[0026] Semiconductor device 1a has a semiconductor substrate 2, a collector electrode 3, an emitter electrode 4, a gate electrode 5, a collector layer 11, a buffer layer 12, a drift layer 13, a base region 14, an emitter region 15, a contact region 16, a gate insulating film 17, an interlayer insulating film 18, and a guard ring region 19.

[0027] Semiconductor device 1a has a unit portion (first region) 21 and a terminal portion (second region) 22. The unit portion 21 of semiconductor device 1a is provided with an emitter electrode 4, a gate electrode 5, a base region 14, an emitter region 15, a contact region 16, a gate insulating film 17, and an interlayer insulating film 18. The terminal portion 22 is provided with a guard ring region 19.

[0028] For ease of explanation, an XYZ orthogonal coordinate system is used in this specification. The X-axis, Y-axis, and Z-axis directions are referred to as the first direction X, the second direction Y, and the third direction Z, respectively. The stacking direction of the semiconductor substrate 2 ( Figure 1The longitudinal direction is referred to as the third direction Z. Additionally, one of the directions in the plane of the semiconductor substrate 2 that intersects the third direction Z is ( Figure 1 The horizontal direction is called the second direction Y, and the other direction ( Figure 1 The depth direction is called the first direction X. Additionally, in the Z-axis direction, Figure 1 The upper side of the etc. is also called "upper". Figure 1 The lower side of the plane is also called "bottom". However, this representation is for convenience and is unrelated to the direction of gravity. Figure 1 This is a schematic cross-sectional view of semiconductor device 1a in the YZ plane.

[0029] In this specification, an example of using a silicon (Si) substrate as the semiconductor substrate 2 is described. However, the semiconductor substrate 2 may also be a substrate containing other semiconductor materials, such as a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, or a gallium arsenide (GaAs) substrate.

[0030] When the semiconductor substrate 2 is a Si substrate, boron (B) can be used as a p-type impurity. Alternatively, arsenic (As), phosphorus (P), or antimony (Sb) can be used as an n-type impurity when the semiconductor substrate 2 is a Si substrate.

[0031] The semiconductor substrate 2 has a first surface A1 and a second surface A2 opposite to the first surface A1. The first surface and the second surface are parallel to the XY plane.

[0032] The semiconductor substrate 2 is connected to the collector electrode 3 on its first surface A1. Additionally, the semiconductor substrate 2 is connected to the emitter electrode 4 on its second surface A2.

[0033] The collector electrode 3 and the emitter electrode 4 contain conductive materials such as Al (aluminum).

[0034] A collector layer 11 is disposed within the semiconductor substrate 2. The collector layer 11 is electrically connected to the collector electrode 3. The collector layer 11 may contain, for example, a p-type semiconductor material. The concentration distribution of p-type impurities in the collector layer 11 will be described later.

[0035] Buffer layer 12 is disposed, for example, on collector layer 11. Buffer layer 12 may contain, for example, an n-type semiconductor material.

[0036] Drift layer 13 is disposed, for example, above buffer layer 12. Drift layer 13, for example, contains n - The n-type semiconductor material. The n-type impurity concentration in the drift layer 13 is lower than that in the buffer layer 12.

[0037] The base region 14 is disposed within the semiconductor substrate 2. The base region 14 is disposed, for example, on the drift layer 13. The base region 14 contains, for example, a p-type semiconductor material.

[0038] Emitter region 15 is disposed within semiconductor substrate 2. Emitter region 15 may be disposed, for example, on base region 14. Emitter region 15 is electrically connected to emitter electrode 4. Emitter region 15 may contain, for example, n... + The semiconductor material is of the n-type type. The n-type impurity concentration in the emitter region 15 is higher than that in the drift layer 13.

[0039] Contact region 16 is disposed within semiconductor substrate 2. Contact region 16 is, for example, disposed above base region 14. Contact region 16 is, for example, disposed between two emitter regions 15. Contact region 16, for example, includes p + The semiconductor material is p-type. The p-type impurity concentration in contact region 16 is higher than that in base region 14.

[0040] Additionally, the semiconductor substrate 2 has a trench T1 extending from the second surface A2 to the drift layer 13. A gate electrode 5, a gate insulating film 17, and an interlayer insulating film 18 are disposed within the trench T1.

[0041] The gate electrode 5 is disposed in the trench T1 in a manner that is opposite to the base region 14 through the gate insulating film 17.

[0042] An interlayer insulating film 18 is disposed between the gate electrode 5 and the emitter electrode 4. The interlayer insulating film 18 insulates the gate electrode 5 and the emitter electrode 4 from each other.

[0043] The gate insulating film 17 and the interlayer insulating film 18 contain insulating materials such as SiO2 (silicon oxide).

[0044] Figure 1 The semiconductor device 1a has one or more semiconductor elements 10a. The semiconductor elements 10a are configured, for example, with each gate electrode 5.

[0045] The end portion 22 of the semiconductor device 1a has a guard ring region 19. The guard ring region 19 is, for example, disposed within a trench T2 extending from the second surface A2 to the drift layer 13. The guard ring region 19, for example, contains a p-type semiconductor material. Figure 1 As shown, multiple protection ring regions 19 can also be configured. Furthermore, when multiple protection ring regions 19 are configured, they are arranged separately from each other. Additionally, in this specification, the protection ring region 19 is sometimes simply referred to as a protection ring.

[0046] Figure 2 This is a schematic cross-sectional view of a second example of a semiconductor device according to the first embodiment of the present disclosure. Figure 2 The semiconductor device 1b has one or more semiconductor elements 10b. The semiconductor element 10b is a vertical planar IGBT.

[0047] Semiconductor device 1b includes a semiconductor substrate 2, a collector electrode 3, an emitter electrode 4, a gate electrode 5, a collector layer 11, a buffer layer 12, a drift layer 13, a base region 14, an emitter region 15, a gate insulating film 17, and an interlayer insulating film 18.

[0048] exist Figure 2 The diagram shows two base regions 14.

[0049] The emitter region 15 is disposed within the base region 14. Figure 2 The diagram shows two emitter regions 15 respectively disposed inside the two base regions 14.

[0050] The gate electrode 5 is disposed on the base region 14.

[0051] A gate insulating film 17 is disposed between the gate electrode 5 and the base region 14.

[0052] The emitter electrode 4 is disposed on the emitter region 15 and the gate electrode 5. The emitter electrode 4 is electrically connected to the emitter region 15.

[0053] Figure 3 This is a top view of a semiconductor chip according to the first embodiment of this disclosure. Figure 3 The planar structure of the semiconductor device (semiconductor chip) 1 shown can be applied to Figure 1 and Figure 2 Either of semiconductor devices 1a and 1b. The following describes... Figure 3 Planar construction applied to Figure 1 An example of semiconductor device 1a will be used for illustration.

[0054] exist Figure 3 The diagram shows... Figure 1 The semiconductor device 1 is a rectangular chip, but it is not limited to this; the shape of the chip in the semiconductor device 1 can be arbitrary.

[0055] Figure 3 The unit portion 21 is disposed in the central portion of the semiconductor device 1. The end portion 22 is disposed in a ring shape to surround the unit portion 21.

[0056] Unit 21 in Figure 1 The second side A2 has multiple semiconductor elements 10a (or 10b). The end portion 22 is... Figure 1 The second side A2 has a protective ring area 19.

[0057] exist Figure 3 In the middle, a special illustration is shown from Figure 1 The planar structure of the collector layer 11 when viewed from the first side A1.

[0058] The collector layer 11 contains p-type impurities such as boron (hereinafter also referred to as dopants). Furthermore, the collector layer 11 has a substantially uniform p-type dopant concentration within the chip. The variation in the p-type dopant concentration throughout the entire region of the collector layer 11 is within a specified percentage, for example, within ±5%. In this specification, the dopant integral concentration refers to the concentration obtained by integrating the dopant concentration along the depth direction over each unit area of ​​the chip. Additionally, in this specification, the dopant integral concentration is sometimes referred to as the impurity concentration.

[0059] against Figure 3 The average dose (number of ions per unit area) of the current collector layer 11 is, for example, 1.0 × 10⁻⁶. 13 [ions / cm2].

[0060] That is, the dopant integral concentrations of the region of the collector layer 11 corresponding to the unit portion 21 (hereinafter also referred to as the unit portion 21) and the region of the collector layer 11 corresponding to the end portion 22 (hereinafter also referred to as the end portion 22) are approximately uniform, for example, the variation in the dopant integral concentration is within ±5%.

[0061] Furthermore, the dopant activation rate is lower at the outer periphery of the collector layer 11 than at the center. That is, the dopant activation rate is lower at the end portion 22 compared to the unit portion 21. Figure 3 In the diagram, the activation rates of the dopants are plotted in descending order using dark shading.

[0062] In this specification, dopant activation refers to the electrical activation of the dopant contained in the semiconductor device 1 through heat treatment such as laser annealing. If a dopant is injected into a silicon wafer, the silicon crystal structure collapses, generating crystal defects or amorphization (hereinafter also collectively referred to as crystal defects, etc.). If crystal defects, etc., are generated in silicon, carrier mobility decreases and resistivity increases. A silicon wafer with crystal defects, etc., can have its crystal structure restored by incorporating the dopant into the crystal structure through heat treatment, etc. Furthermore, the dopant is electrically activated. As a result, carrier mobility increases and resistivity decreases. By adjusting the activation rate of the dopant, carrier mobility and resistivity can be adjusted.

[0063] The dopant in the terminal portion 22 has a low activation rate and low carrier mobility. Compared to the cell portion 21, the hole carrier concentration in the terminal portion 22 is reduced, suppressing hole injection to the second surface A2. This prevents holes injected into the terminal portion 22 from concentrating at the end of the cell portion 21. In other words, it alleviates electric field concentration in the cell portion 21 and improves the breakdown voltage of the semiconductor device 1.

[0064] Compared to the terminal portion 22, the unit portion 21 has a higher carrier mobility, thus improving the current driving capability of the semiconductor element 10a (or 10b).

[0065] In the collector layer 11, it is not necessary to establish a difference in the integral concentration of the dopant between the unit portion 21 and the end portion 22 to make the unit portion 21 and the end portion 22 have different electrical characteristics. This simplifies the formation process of the collector layer 11. The formation process of the collector layer 11 will be described later.

[0066] The terminal portion 22 has multiple terminal portions (third regions) 22a disposed at the corners (specifically, the four corners) of the semiconductor device 1 and a terminal portion (fourth region) 22b disposed between two terminal portions 22a. Since the electric field tends to concentrate at the corners of the cell portion 21, it is preferable that the hole carrier concentration is lower in the terminal portions 22a disposed near the corners of the cell portion 21 compared to the terminal portions 22b.

[0067] In the collector layer 11, the activation rate of the dopant at the end portion 22a can be lower than that at the end portion 22b. As a result, the hole carrier concentration at the end portion 22a is lower than that at the end portion 22b.

[0068] The dopant integral concentration of collector layer 11 can be measured, for example, by SIMS analysis.

[0069] Furthermore, the activation rate of the dopant in collector layer 11 can be measured using the Spreading Resistance Analysis (SRA) or Spreading Resistance Profiling (SRP) method. In the SRA method, the calculated resistivity can be... Converted to carrier concentration[ / cm] 3 As mentioned above, the higher the dopant activation rate, the lower the resistivity that can be measured in the extended resistance measurement method.

[0070] Figure 4 This is a top view showing the configuration of the protection ring region 19 in the first embodiment of the present disclosure. Figure 4 The diagram is from Figure 1 The planar structure of the protective ring region 19 when viewed from the second side A2. Furthermore, in Figure 4 The illustration of semiconductor element 10a, etc., is omitted.

[0071] like Figure 4 As shown, the protective ring region 19 has a ring-shaped structure. The protective ring region 19 is configured to surround the unit section 21 (the semiconductor element 10a or 10b inside) when viewed from above.

[0072] use Figure 5 ,right Figure 3 The method for forming the collector layer 11 will be described. Figure 5 This is a diagram illustrating the laser annealing process of the first embodiment of this disclosure. Figure 5 The diagram shows a wafer 30 containing multiple semiconductor devices 1. More precisely, the wafer 30 can be divided into multiple semiconductor devices 1 through processes such as dicing following the laser annealing process.

[0073] In the ion implantation process, which is a pre-process of laser annealing, a p-type dopant (e.g., boron) is implanted into the collector layer 11. Figure 5 In the laser annealing process, by means of... Figure 1 Laser light is irradiated onto the collector layer 11 on the first side A1 to activate the injected p-type dopant.

[0074] Figure 5 The laser annealing process includes a first laser irradiation process, a second laser irradiation process, and a third laser irradiation process. The order of the first to third laser irradiation processes is arbitrary. In this specification, for convenience, the lasers used in the first, second, and third laser irradiation processes are referred to as the first laser La, the second laser Lh, and the third laser Lv, respectively. The irradiation ranges of the first laser La, the second laser Lh, and the third laser Lv are different from each other.

[0075] The first laser La, the second laser Lh, and the third laser Lv can also use the same laser. That is, the wavelength, intensity, and beam diameter of the first laser La, the second laser Lh, and the third laser Lv can also be the same. However, this is not a limitation; the wavelength, intensity, and beam diameter of the first laser La, the second laser Lh, and the third laser Lv can also be different from each other.

[0076] exist Figure 5 In the diagram, the irradiation ranges of the first laser La, the second laser Lh, and the third laser Lv on wafer 30 are shown by double-dotted lines, solid lines, and single-dotted lines, respectively.

[0077] The first laser La irradiates approximately the entire surface of wafer 30. Specifically, the first laser La scans in a two-dimensional direction. Figure 6 This diagram illustrates the first laser irradiation process. In the first laser irradiation process, a first laser La scans the wafer 30 along a first direction X and a second direction Y. During the scanning of the first laser La, for example, the irradiation port of the laser is fixed, and a movable stage (hereinafter also referred to as the stage) on which the wafer 30 is placed moves in the first direction X and the second direction Y. Figure 6In the example, firstly, the stage is moved to scan in the first direction X by the first laser La. When the first laser La illuminates the end of the wafer 30 in the first direction X, the stage moves one step in the second direction Y. Figure 6 In the process, the first laser La scans in the first direction X and the worktable moves one step in the second direction Y. Figure 6 The figure shows the laser beam as the worktable moves one step in the second direction Y (in...). Figure 6 The irradiation range 36 of the first laser (La) is shown in the figure. Here, the moving distance sa of each step in the second direction Y is set to be the same as or smaller than the emission size r of the second direction Y of the first laser La. As a result, no gaps are generated between the multiple irradiation ranges 36, so that the first laser La can irradiate approximately the entire surface of the wafer 30.

[0078] The irradiation range of the second laser Lh is a strip-shaped range extending in one direction (e.g., the first direction X). Furthermore, the irradiation range of the second laser Lh is arranged at predetermined intervals in directions intersecting the direction in which the irradiation range of the second laser Lh extends (e.g., the second direction Y).

[0079] Figure 7 This is a diagram illustrating the second laser irradiation process. In the second laser irradiation process, for example, with... Figure 6 Similarly, the second laser Lh scans in a two-dimensional direction. Furthermore, during the irradiation by the second laser Lh, for example, the moving distance sh per step in the second direction Y is set to be greater than the emission size r of the second laser Lh in the second direction Y. This creates gaps between the multiple irradiation ranges 36, thus enabling the second laser Lh to irradiate the wafer 30 in a striation pattern. The emission size r of the second laser Lh can be the same as or different from the emission size r of the first laser La (e.g., smaller than the emission size r of the first laser La). Furthermore, Figure 7 The scanning speed of the second laser Lh in the first direction X can also be, for example, the same as... Figure 6 The first laser, La, has the same velocity. However, this is not a limitation. Figure 7 The scanning speed of the second laser Lh in the first direction X can also be... Figure 6 The scanning speed of the first laser La in the first direction X is different. For example, with the same laser irradiation speed (pulse interval), the number of times the second laser Lh irradiates the wafer 30 can be increased by reducing the scanning speed of the second laser Lh in the first direction X. As a result, as will be described later, the thin film resistance and resistivity in the irradiation range 36 can be reduced.

[0080] The irradiation range of the third laser Lv is a strip-shaped range extending in a direction intersecting the extension direction of the second laser Lh (e.g., the second direction Y). Furthermore, the irradiation range of the third laser Lv is arranged at predetermined intervals in a direction intersecting the irradiation ranges of the second laser Lh (e.g., the first direction X).

[0081] The irradiation process of the third laser Lv is the same as that of the second laser Lh. For example, by rotating the wafer 30 90 degrees relative to the laser annealing device, and scanning the laser in a two-dimensional direction in the same way as the second laser Lh, the wafer 30 can be irradiated with the third laser Lv in a vertical stripe pattern.

[0082] Figure 5 The wafer 30 has a first irradiation range 31, a second irradiation range 32, and a third irradiation range 33. The first irradiation range 31 is the overlapping range of the irradiation ranges of the first laser La, the second laser Lh, and the third laser Lv. The second irradiation range 32 is the overlapping range of the irradiation range of the first laser La with the irradiation range of either the second laser Lh or the third laser Lv. The third irradiation range 33 is the range of the irradiation range of the first laser La excluding the overlapping ranges with the irradiation ranges of the second laser Lh and the third laser Lv.

[0083] The laser irradiation ranges 31, 32, and 33 were performed 3, 2, and 1 times, respectively. Among the three irradiation ranges, the dopant activation rate was highest in the first irradiation range 31 and lowest in the third irradiation range 33. Figure 5 In the diagram, the activation rates of the dopants are illustrated using darker shaded dots in descending order. Furthermore, the number of laser irradiations performed on a specified range after one laser scan is counted as one instance of laser irradiation within that range.

[0084] By cutting (dividing) the semiconductor device 1 from the wafer 30 in such a way that a first irradiation range 31 is included in the center of the semiconductor device 1, it is possible to form Figure 3 The collector layer 11. The first irradiation range 31 corresponds to Figure 3 Unit 21. The second irradiation range 32 corresponds to the end portion 22b. The third irradiation range 33 corresponds to the end portion 22a.

[0085] The irradiation ranges of the second laser Lh and the third laser Lv are preferably extended or arranged along any one of the cutting directions of the wafer 30 (e.g., the first direction X and the second direction Y). This allows the third irradiation range 33, with its low dopant activation rate, to be positioned at a corner of the semiconductor device 1.

[0086] Figure 8 This indicates the number of laser irradiations and the thin film resistance value. The waveform diagram showing the relationship between ] and . Figure 8 The horizontal axis represents the number of laser irradiations, and the vertical axis represents the thin-film resistance value. The inventors implanted boron into the collector layer 11, and measured the thin-film resistance value while varying the number of laser irradiations. Figure 8 As shown, the more laser irradiation times there are, the more monotonically the thin film resistance decreases.

[0087] As mentioned above, increasing the number of laser irradiations increases the activation rate of the dopant in the collector layer 11. Consequently, increasing the number of laser irradiations further reduces the thin-film resistance and resistivity.

[0088] To obtain the desired activation rate of the dopant, it can also be adjusted Figure 3 The number of times the unit portion 21 and the end portion 22 are irradiated by laser. That is, the unit portion 21 can be irradiated by laser more than 4 times. That is, any one of the first laser La, the second laser Lh, and the third laser Lv can scan the wafer 30 more than twice. Similarly, the end portion 22a can be irradiated by laser more than twice.

[0089] Alternatively, the acceleration of the p-type dopant during ion implantation can be adjusted (e.g., increased). By implanting the p-type dopant at a high acceleration, crystal defects are easily generated in silicon. By increasing the acceleration during p-type dopant implantation, it is sometimes possible to form a larger resistivity difference between the portion that is fully irradiated by the laser (e.g., unit portion 21) and the portion that is not fully irradiated by the laser (e.g., end portion 22).

[0090] exist Figure 8 In this context, the laser is irradiated multiple times in a manner that ensures identical irradiation conditions, including laser intensity, irradiation range, and irradiation time. In contrast, Figure 5 The irradiation ranges of the first laser La and the second laser Lh (and the third laser Lv) are different. Furthermore, the intensity and irradiation time of the first laser La and the second laser Lh (and the third laser Lv) sometimes differ. Therefore, both the first irradiation range 31 and the third irradiation range 33 are irradiated by the first laser La. In addition, the first irradiation range 31 is also irradiated by the second laser Lh and the third laser Lv. That is, the first irradiation range 31 is simply irradiated with more laser light than the third irradiation range 33. Therefore, it is believed that the thin-film resistivity is lower in the first irradiation range 31 compared to the third irradiation range 33. The relationship between the first irradiation range 31 (or the third irradiation range 33) and the second irradiation range 32 is the same.

[0091] Figure 9 This is a top view of a modified semiconductor chip. Figure 9 In the semiconductor device (semiconductor chip) 1c, the dopant activation rate is approximately uniform at the annular end portion 22. Figure 9Semiconductor device 1c and Figure 3 The semiconductor device 1 can also be made to withstand high voltage.

[0092] Figure 10 This is the first diagram illustrating a modified laser annealing process. For example... Figure 10 As shown, a laser can be used to irradiate a wafer 30 with an array of irradiation areas (hereinafter also referred to as arrayed irradiation areas) spaced at predetermined intervals to form a structure. Figure 9 Semiconductor device 1c.

[0093] Figure 10 The laser annealing process includes a first laser irradiation step (irradiating with a first laser La) and a second laser irradiation step (irradiating with a fourth laser Ld). The order of the first and second laser irradiation steps is arbitrary. The irradiation range of the fourth laser Ld includes, for example: Figure 10 The array-shaped irradiation range is shown. The irradiation range of the first laser La is approximately the entire surface of wafer 30.

[0094] Figure 10 The wafer 30 has multiple first irradiation ranges 31a and second irradiation ranges 33a. The first irradiation range 31a is the overlapping range of the irradiation ranges of the first laser La and the fourth laser Ld. The second irradiation range 33a is the range within the irradiation range of the first laser La, excluding the area overlapping with the irradiation range of the fourth laser Ld. The dopant activation rate in the first irradiation range 31a is higher than that in the second irradiation range 33a.

[0095] In the irradiation process of the fourth laser Ld, for example, with Figure 7 Similarly, while moving the stage in the first direction X and the second direction Y, the wafer 30 is intermittently irradiated with the fourth laser Ld. By setting a spatial interval (spacing) between the irradiation range of the fourth laser Ld at a certain irradiation timing (i.e., the first irradiation range 31a) and the irradiation range of the fourth laser Ld at the next irradiation timing (the first irradiation range 31a), the fourth laser Ld can be irradiated into an array of irradiation ranges on the wafer 30.

[0096] Figure 11 This is the second figure illustrating a modified example of the laser annealing process. Figure 11 The irradiation process of the fourth laser Ld is described in the text. Figure 11 The diagram illustrates two semiconductor devices 1c on wafer 30 (more precisely, semiconductor devices 1c are formed through subsequent dicing processes). Figure 11 In the example, the fourth laser Ld scans in the first direction X.

[0097] exist Figure 11The diagram illustrates the length d [mm] of one side of the semiconductor device 1c, the beam diameter r [mm] of the fourth laser Ld, the scanning speed (moving speed of the stage) V [mm / s] of the fourth laser Ld, and the pulse interval T [s] of the fourth laser Ld (the reciprocal of the repetition frequency f).

[0098] like Figure 11 As shown, the beam diameter r of the fourth laser Ld is adjusted to be smaller than its length d. Furthermore, the scanning speed V of the fourth laser Ld is adjusted, for example, to V = d / T. Thus, as... Figure 11 As shown, the fourth laser Ld can be irradiated with a spatial interval in the first direction X. Furthermore, in the irradiation process of the fourth laser Ld, the movement distance s of the worktable in each step of the second direction Y can be adjusted, for example, to be the same as the length d (s=d). Therefore, the same spatial interval as in the first direction X can also be set in the second direction Y.

[0099] The fourth laser Ld can also be a laser with an irradiation area (emission size or beam diameter) smaller than that of the first laser La for each irradiation time. In this case, the scanning speed of the fourth laser Ld and the first laser La can also be the same.

[0100] The irradiation range of the fourth laser Ld (i.e., the first irradiation range 31a) is arranged in two dimensions, for example, along the direction in which the wafer 30 is cut (e.g., the first direction X and the second direction Y).

[0101] exist Figure 3 In the semiconductor device 1, the activation rate of the dopant in the collector layer 11 decreases progressively in three stages from the central portion to the peripheral portion. Figure 9 In the semiconductor device 1c, the activation rate of the dopant in the collector layer 11 decreases progressively in two stages from the center to the periphery. Alternatively, the activation rate of the dopant in the collector layer 11 can be adjusted to decrease progressively in four or more stages from the center to the periphery by irradiating with a laser in an irradiation range different from that of the first laser La, the second laser Lh, and the third laser Lv.

[0102] Figure 12 This is a top view of a comparative example semiconductor chip. Figure 12 The dose of the semiconductor device (semiconductor chip) 100 is not uniform within the chip. Figure 12 Unit 21 was injected with 1.5 × 10 13 [ions / cm2] p-type dopant (boron). Figure 12 The distal end 22 was injected with 5.0 × 10 12 Boron in [ions / cm2]. That is, Figure 12 The dose difference between unit portion 21 and terminal portion 22 is 3 times. Figure 12In the semiconductor device 100, the electric field concentration at the end of the unit section 21 can also be mitigated.

[0103] but, Figure 12 The formation process of the collector layer 11 and Figure 3 and Figure 9 Compared to the formation process of the collector layer 11, the number of processes increases. Specifically, in order to form Figure 12 The collector layer 11 requires at least five processes: (1) a first p-type ion implantation process for the unit portion 21 and the end portion 22, (2) a process of coating (Lithography) photoresist on the end portion 22, (3) a second p-type ion implantation process for the unit portion 21, (4) a process of stripping the photoresist (ashing) from the end portion 22, and (5) a laser annealing process.

[0104] In contrast, Figure 3 as well as Figure 9 The steps required for forming the collector layer 11 are (1) implantation of p-type ions into the unit portion 21 and the end portion 22, and (2) laser annealing. That is, it can reduce... Figure 12 The process of forming the current collector layer 11 involves three steps: the PEP process, the second p-type ion implantation process, and the ashing process. Therefore, in Figure 3 and Figure 9 In the semiconductor devices 1 (and 1c), with Figure 12 Compared to semiconductor device 100, it simplifies the manufacturing process and reduces manufacturing costs.

[0105] As described above, the semiconductor device 1 of the first embodiment of this disclosure has a collector layer 11 in which the dopant integral concentration is substantially uniform throughout the chip, and the dopant activation rate decreases progressively or continuously from the center to the periphery. As a result, the thin-film resistance of the collector layer 11 increases progressively or continuously from the center to the periphery.

[0106] Semiconductor device 1 has a unit portion 21 with multiple semiconductor elements 10a or 10b and an end portion 22 with a guard ring, etc. The collector layer 11 makes the dopant activation rate of the end portion 22 lower than that of the unit portion 21. As a result, hole concentration at the end of the unit portion 21 can be mitigated, and the reliability (damage resistance) of semiconductor device 1 can be improved.

[0107] Furthermore, the collector layer 11 can suppress hole implantation in the terminal portion 22 without setting a high-low difference in dopant integration concentration between the cell portion 21 and the terminal portion 22. Therefore, in the formation process of the collector layer 11, photolithography and ion implantation processes after photolithography are not required. That is, the number of steps in the formation process of the collector layer 11 can be reduced. As described above, the semiconductor device 1 can improve reliability with a simple structure.

[0108] The end portion 22 may also include the end portion 22a of the corner of the chip (e.g., the four corners of a rectangular chip) where the dopant activation rate is lower. This can further alleviate hole concentration at the corners of the chip and further improve the reliability of the semiconductor device 1.

[0109] By reducing the number of laser irradiations on the end portion 22 compared to the number of laser irradiations on the unit portion 21, the dopant activation rate of the end portion 22 can be reduced compared to that of the unit portion 21. Specifically, laser (e.g., a first laser La) is irradiated onto approximately the entire surface of the wafer 30, while the irradiation of the lattice-shaped area on the wafer 30 (e.g., Figure 5 The irradiation range of the second laser Lh and the third laser Lv) or an array-shaped irradiation range (e.g., Figure 10 The fourth laser Ld is irradiated with laser, thereby enabling the formation of the aforementioned unit portion 21 and end portion 22 in the cut chip.

[0110] Whether the collector layer 11 of the first embodiment of this disclosure has been formed can be determined by means of SIMS analysis, extended resistance measurement, etc. In SIMS analysis, the distribution of dopant integral concentration can be analyzed. The distribution of dopant activation rate can be analyzed by means of extended resistance measurement, etc. For example, if, relative to the case where the dopant integral concentration within the chip is found to be approximately uniform by SIMS analysis, but the dopant activation rate at the outer periphery of the chip is lower than that at the center of the chip by extended resistance measurement, it can be determined that a collector layer 11 with a lower dopant activation rate at the outer periphery than at the center of the chip has been formed on the chip.

[0111] (Second Implementation) The method for forming the collector layer 11 in the first embodiment of this disclosure can be various. Hereinafter, the method for forming... Figure 9 The method for the collector layer 11 in the semiconductor device 1c will be described. Furthermore, the method described below can also be applied to... Figure 3 A method for forming the collector layer 11 in the semiconductor device 1.

[0112] First, as a first method for forming the collector layer 11 (basic example), such as Figure 10As explained in the text, an example is shown in which the irradiation range of the first laser La is different from that of the fourth laser Ld. Figure 13 This is a diagram showing the irradiation range of the first laser La in the semiconductor device (semiconductor chip) 1c. Figure 14 This diagram shows the irradiation range of the fourth laser Ld in the semiconductor device 1c. As described above, the irradiation range of the first laser La includes approximately the entire surface of the collector layer 11 in the semiconductor device 1c. Furthermore, the irradiation range of the fourth laser Ld ( Figure 10 The multiple first irradiation ranges 31a) include multiple unit parts 21.

[0113] The first laser La and the fourth laser Ld can also be lasers with different wavelengths. In the second method of forming the collector layer 11, the fourth laser Ld and the first laser La, whose wavelength is shorter than that of the fourth laser Ld, are irradiated onto the collector layer 11. As a result, the dopant activation rate of the end portion 22 can be lower than that of the unit portion 21.

[0114] In this case, the irradiation range of the first laser La may include the end portion 22 but not the unit portion 21. For example, the first laser La may also be irradiated via a photomask having a mask pattern that blocks light from the unit portion 21.

[0115] The first laser La and the fourth laser Ld can also be lasers with different irradiation energy densities. In the third method of forming the collector layer 11, the fourth laser Ld and the first laser La, which has a lower energy density than the fourth laser Ld, are irradiated onto the collector layer 11. Similarly, the irradiation range of the first laser La can also be the range that includes the end portion 22 but excludes the unit portion 21.

[0116] Figure 15 as well as Figure 16 This is a diagram illustrating the fourth method for forming the collector layer 11. Figure 15 This diagram illustrates the laser irradiation process of the collector layer 11. Figure 15 The diagram shows a semiconductor substrate 2, a collector layer 11, a protective film (first protective film) 41, and a protective film (second protective film) 42.

[0117] Protective films 41 and 42 are formed on the second surface (first main surface) A2 side of the semiconductor substrate 2 in the process preceding the laser irradiation process. Protective film 41 is disposed on the unit portion 21. Protective film 42 is disposed on the end portion 22.

[0118] Figure 16 This is a top view showing the protective films 41 and 42. Figure 15 Cross-sectional view illustration Figure 16 The cross-section of line A-A' and line BB.

[0119] Protective film 42 contains a material with a higher thermal conductivity than protective film 41. Protective film 41 contains, for example, acrylic resin. Protective film 42 contains, for example, glass.

[0120] In the laser irradiation process, for example, the entire surface of the collector layer 11 is irradiated (e.g., as shown in the image). Figure 6 (Such a scanning) First laser La. The end portion 22 has a protective film 42 on the laser irradiation surface, that is, the second surface A2 opposite to the first surface (second main surface) A1. The protective film 42, which has high thermal conductivity, that is, high heat dissipation, dissipates the heat generated by laser irradiation of the end portion 22. As a result, the dopant activation rate of the end portion 22 of the collector layer 11 can be lower than that of the unit portion 21.

[0121] Furthermore, in the fourth method for forming the collector layer 11, the irradiation step of the fourth laser Ld can also be omitted.

[0122] exist Figure 15 In the laser irradiation process, the protective film 41 can be omitted. In this case, the unit portion 21 of the collector layer 11 is in contact with the air layer. Furthermore, the material of the protective film 42 can be, for example, acrylic resin or glass. Acrylic resin and glass have higher thermal conductivity than the air layer. Therefore, even when the protective film 41 is omitted, the dopant activation rate of the end portion 22 of the collector layer 11 can be lower than that of the unit portion 21.

[0123] The fourth method for forming the collector layer 11 can also be applied to Figure 3 The semiconductor device 1 is formed in a process whereby a protective film with a higher thermal conductivity than the protective film at the end portion 22a of the semiconductor substrate 2 can be disposed therein. Alternatively, a protective film with a higher thermal conductivity than the protective film at the unit portion 21 can be disposed at the end portion 22b. Alternatively, the formation of the protective film in the unit portion 21 can be omitted. In the fourth method for forming the collector layer 11, the irradiation steps of the second laser Lh and the third laser Lv can also be omitted.

[0124] Alternatively, the collector layer 11 can be formed by combining two or more of the first to fourth forming methods described above.

[0125] Furthermore, the present invention is not limited to the embodiments described above, and can be modified and embodied by adapting the constituent elements without departing from its spirit during the implementation phase. Additionally, various inventions can be formed by appropriately combining the multiple constituent elements disclosed in the above embodiments. Furthermore, for example, a configuration obtained by deleting several constituent elements from all the constituent elements shown in each embodiment can also be considered. Moreover, the constituent elements described in different embodiments can be appropriately combined.

[0126] [Postscript] [Project 1] A semiconductor device, It has a semiconductor layer containing p-type dopant. The variation in the integral concentration of the P-type dopant throughout the entire region of the semiconductor layer is within a specified proportion. The activation rate of the P-type dopant in the semiconductor layer decreases in stages or continuously from the center to the periphery of the semiconductor layer.

[0127] [Project 2] The semiconductor device according to Project 1 The specified ratio is 5%.

[0128] [Project 3] The semiconductor device according to item 1 or 2 The thin-film resistance of the semiconductor layer increases progressively or continuously from the center to the periphery.

[0129] [Project 4] The semiconductor device according to any one of items 1 to 3, The thin-film resistance of the semiconductor layer increases in stages from the center to the periphery of the semiconductor layer in more than three stages.

[0130] [Project 5] The semiconductor device according to any one of items 1 to 3, The thin-film resistance of the semiconductor layer increases in two stages from the center to the periphery.

[0131] [Project 6] The semiconductor device according to any one of items 1 to 5, The semiconductor layer has a protective ring at its periphery.

[0132] [Project 7] The semiconductor device according to item 6 The semiconductor layer is rectangular in shape when viewed from above. The activation rate of the P-type dopant at the four corners of the collector is lower than that of the P-type dopant at locations other than the four corners of the collector.

[0133] [Project 8] The semiconductor device according to any one of items 1 to 7, The semiconductor device is an IGBT (Insulated Gate Bipolar Transistor).

[0134] [Project 9] The semiconductor device as described in any one of items 1 to 8, comprising: A first semiconductor layer, having the semiconductor layer; The second semiconductor layer is disposed on top of the first semiconductor layer and contains an N-type dopant; A third semiconductor layer is disposed on top of the second semiconductor layer and contains the N-type dopant, having a lower N-type impurity concentration than the second semiconductor layer; A fourth semiconductor layer is disposed on top of the third semiconductor layer and contains the P-type dopant; The fifth semiconductor layer, disposed above the fourth semiconductor layer, contains the N-type dopant and has a higher N-type impurity concentration than the third semiconductor layer; The collector electrode is electrically connected to the first semiconductor layer; The emitter electrode is electrically connected to the fifth semiconductor layer; and The gate electrode is positioned opposite the fourth semiconductor layer, separated by a gate insulating film.

[0135] [Project 10] A method for manufacturing a semiconductor device includes the following steps: The process of implanting P-type dopant into the entire area of ​​a semiconductor layer; The process of activating the semiconductor layer by irradiating a first portion of the semiconductor layer implanted with the p-type dopant with a laser; and The process of activating the semiconductor layer by irradiating a second portion of the semiconductor layer with a laser, the second portion comprising the first portion or configured to surround the first portion when viewed from above.

[0136] [Project 11] According to the manufacturing method described in Project 10 The laser irradiating the first part includes at least one of a laser with a longer wavelength than the laser irradiating the second part or a laser with a higher energy density than the laser irradiating the second part.

[0137] [Project 12] According to the manufacturing method described in item 10 or 11 The first portion is irradiated with a laser of the first emission size. The second part is irradiated with a laser of a second emission size that is larger than the first emission size.

[0138] [Project 13] The manufacturing method according to any one of items 10 to 12, The laser irradiating the first portion irradiates a plurality of strip-shaped irradiation ranges extending in a first direction and a plurality of strip-shaped irradiation ranges extending in a second direction intersecting the first direction on a semiconductor wafer including the semiconductor layer, or irradiates a plurality of irradiation ranges arranged in a two-dimensional direction on the semiconductor wafer.

[0139] [Project 14] According to the manufacturing method described in item 13 It also includes a process of cutting the semiconductor device from the semiconductor wafer. The semiconductor device is cut from the semiconductor wafer in such a manner that the intersection of a plurality of strip-shaped irradiation ranges extending in the first direction and a plurality of strip-shaped irradiation ranges extending in the second direction, or one of a plurality of irradiation ranges arranged in the two-dimensional direction, is centrally located.

[0140] [Project 15] A method for manufacturing a semiconductor device includes the following steps: The process of forming a first protective film on a first portion of a first main surface of a semiconductor layer, forming a second protective film with a higher thermal conductivity than the first protective film on a second portion on the periphery side of the first portion, and forming a second protective film with a higher thermal conductivity than the air layer on the second portion when the first portion is in contact with an air layer. The process of implanting a P-type dopant into the entire region of the second main surface side of the semiconductor layer; and The process of irradiating the entire area of ​​the second main surface of the semiconductor layer with laser light.

Claims

1. A semiconductor device, wherein, It has a semiconductor layer containing p-type dopant. The variation in the integral concentration of the P-type dopant throughout the entire region of the semiconductor layer is within a specified proportion. The activation rate of the P-type dopant in the semiconductor layer decreases in stages or continuously from the center to the periphery of the semiconductor layer.

2. The semiconductor device according to claim 1, wherein, The specified ratio is 5%.

3. The semiconductor device according to claim 1, wherein, The thin-film resistance of the semiconductor layer increases progressively or continuously from the center to the periphery.

4. The semiconductor device according to claim 1, wherein, The semiconductor layer has a protective ring at its periphery.

5. The semiconductor device according to any one of claims 1 to 4, wherein, The semiconductor device is an insulated gate bipolar transistor (IGBT).

6. A method for manufacturing a semiconductor device, wherein, It has the following processes: The process of implanting P-type dopant into the entire area of ​​a semiconductor layer; The process of activating a semiconductor layer by irradiating a first portion of the semiconductor layer implanted with the p-type dopant with a laser. as well as The process of activating the semiconductor layer by irradiating a second portion of the semiconductor layer with a laser, the second portion comprising the first portion or configured to surround the first portion when viewed from above.

7. The method for manufacturing a semiconductor device according to claim 6, wherein, The laser irradiating the first part includes at least one of a laser with a longer wavelength than the laser irradiating the second part or a laser with a higher energy density than the laser irradiating the second part.

8. The method for manufacturing a semiconductor device according to claim 6, wherein, The first portion is irradiated with a laser of the first emission size. The second part is irradiated with a laser of a second emission size that is larger than the first emission size.

9. A method for manufacturing a semiconductor device, wherein, It has the following processes: The process of forming a first protective film on a first portion of a first main surface of a semiconductor layer, forming a second protective film with a higher thermal conductivity than the first protective film on a second portion on the periphery side of the first portion, and forming a second protective film with a higher thermal conductivity than the air layer on the second portion when the first portion is in contact with an air layer. The process of implanting a P-type dopant into the entire region of the second main surface side of the semiconductor layer; as well as The process of irradiating the entire area of ​​the second main surface of the semiconductor layer with laser light.

Images