Semiconductor device

Abstract

One embodiment provides a semiconductor device for suppressing an increase in peak voltage and an oscillation after turn-off. A semiconductor device includes a first electrode, a collector layer, a first buffer layer, a second buffer layer, a drift layer, a base layer, an emitter layer, a second electrode, a third electrode, and a gate insulating film. R1 < R2 < (R3 - R4 - Wmax) is satisfied. R1 is a distance from an upper surface to a top of a first peak. R2 is a distance from the upper surface to a top of a second peak. R3 is a distance from the upper surface to a lower surface. R4 is a distance from a lower portion to the lower surface. Wmax is a width of a maximum depletion layer of the drift layer at turn-off.

Description

Cross-reference to related applications

[0001] This application is based on and claims priority to Japanese Patent Application No. 2025-068131, filed on April 17, 2025; the entire contents of which are incorporated herein by reference. Technical Field

[0002] The implementation scheme described in this article generally relates to a semiconductor device. Background Technology

[0003] For example, in semiconductor devices, it is desirable to suppress the increase in peak voltage and suppress oscillations after shutdown. Summary of the Invention

[0004] One embodiment provides a semiconductor device for suppressing the increase of peak voltage and suppressing oscillations after shutdown.

[0005] Generally, according to one embodiment, a semiconductor device includes a first electrode, a collector layer, a first buffer layer, a second buffer layer, a drift layer, a base layer, an emitter layer, a second electrode, a third electrode, and a gate insulating film. The first electrode includes an upper surface. The collector layer is located on the first electrode. The collector layer is of a second conductivity type. The first buffer layer is located on the collector layer. The first buffer layer is of a first conductivity type and includes a first impurity. The second buffer layer is located on the first buffer layer. The second buffer layer is of the first conductivity type and includes a second impurity. The drift layer is located on the second buffer layer. The drift layer is of the first conductivity type and includes a third impurity. The base layer is located on the drift layer. The base layer is of the second conductivity type. The emitter layer is located on the base layer. The emitter layer is of the first conductivity type. The second electrode is located on the emitter layer. The second electrode includes a lower surface. The third electrode is located between a portion of the second electrode and a portion of the drift layer. The gate insulating film is located at least between the third electrode and the base layer. The gate insulating film includes a lower portion. The first buffer layer includes a first peak of the concentration of the first impurity in a first direction. The first direction is a direction from the first electrode toward the second electrode. The second buffer layer includes a second peak of the concentration of the second impurity in the first direction. R1<R2<(R3-R4-Wmax) is satisfied. R1 is the distance from the upper surface to the vertex of the first peak. R2 is the distance from the upper surface to the vertex of the second peak. R3 is the distance from the upper surface to the lower surface. R4 is the distance from the lower portion to the lower surface. Wmax is the maximum depletion layer width of the drift layer at turn-off. Wmax is expressed by formula (1), q is the absolute value of the electron charge, ε is the dielectric constant of the drift layer, Nd is the concentration of the third impurity in the drift layer, Vs is the saturation velocity of holes, Vce is the voltage between the first electrode and the third electrode, Ic is the rated current, γ h is the ratio of the hole current at turn-off, and AA is the area of the second electrode in a plane including a second direction and a third direction. The second direction intersects the first direction. The third direction intersects the first direction and the second direction.

[0006] Qdp>4.27×10 -3 ×Nd+2.41×10 11 cm -2 , Qdp (cm -2 ) is the total dose of the dose of the drift layer and the dose of the second buffer layer, and the unit of Nd is cm -3 . Nproton<1.8×10 15 / cm 3Nproton is the concentration of the second peak. Attached Figure Description

[0007] Figure 1 This is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment; Figure 2 This is a schematic diagram illustrating the impurity concentration of each buffer layer between the first and second electrodes according to an embodiment, and the distances between components of the semiconductor device; Figure 3 This is a schematic diagram showing the carrier concentration relative to the depth from the first electrode of the semiconductor device according to the embodiment; Figure 4 This is a schematic diagram illustrating the width of the maximum depletion layer of a semiconductor device according to an implementation scheme; Figure 5 The total dose of the drift layer and the second buffer layer of the semiconductor device according to the embodiment is described; Figure 6 The conditions for the total dose of a semiconductor device based on an implementation scheme based on simulation results are described; Figure 7 The characteristics are shown when the distance from the top surface to the vertex of the second peak is less than a specified distance; Figure 8 The relationship between the peak voltage between the first and third electrodes and the distance from the top surface to the apex of the second peak is shown. Figure 9 It shows Figure 7 The presence or absence of oscillation waveforms in regions A3 and A4 results in changes in total dose Qdp and distance R2; Figure 10 The relationship between the peak voltage between the first and third electrodes and the distance from the top surface to the apex of the second peak is shown. Figure 11 The relationship between the peak voltage between the first and third electrodes and the distance from the top surface to the apex of the second peak is shown. Figure 12 The relationship between the peak voltage between the first and third electrodes and the distance from the top surface to the apex of the second peak is shown. Figure 13 The relationship between the peak voltage between the first and third electrodes and the distance from the top surface to the apex of the second peak is shown; and Figure 14 This is a simulation result showing the presence or absence of oscillations in the voltage waveform of the sample relative to the concentration peak of the second impurity concentration. Detailed Implementation

[0008] Various implementation schemes are described below with reference to the accompanying drawings.

[0009] The accompanying drawings are schematic or conceptual; and the relationships between the thickness and width of parts, the dimensional proportions between parts, etc., may not be the same as the actual values. Even for the same parts, dimensions and scale factors may be shown differently in the accompanying drawings.

[0010] In the specification and drawings, parts similar to those previously described or shown in the preceding drawings are labeled with the same reference numerals; and detailed descriptions are omitted where appropriate.

[0011] Figure 1 This is a schematic cross-sectional view showing a semiconductor device according to an embodiment.

[0012] Figure 2 This is a schematic diagram illustrating the impurity concentration of each buffer layer between the first and second electrodes according to an embodiment, as well as the distance between components of the semiconductor device. Figure 2 The impurity concentration of each buffer layer, the distance from the upper surface 51a of the first electrode 51 to the peak of the impurity concentration, the width of the maximum depletion layer of the drift layer 11 when turned off, the trench depth, etc. are shown.

[0013] Figure 3 This is a schematic diagram showing the carrier concentration relative to the depth from the first electrode of the semiconductor device according to the embodiment.

[0014] In the description, the direction from the first electrode 51 toward the second electrode 52 is referred to as "up / above"; and the opposite direction is referred to as "down / below". These directions are based on the relative positional relationship between the first electrode 51 and the second electrode 52 and are independent of the direction of gravity.

[0015] like Figure 1 As shown, the semiconductor device 100 includes a first electrode 51, a collector layer 12, a first buffer layer 13a, a second buffer layer 13b, a drift layer 11, a substrate layer 15, an emitter layer 16, a second electrode 52, a third electrode 53, and a gate insulating film 41. The semiconductor device 100 may also include a contact layer 17 and an insulating layer 40.

[0016] The first electrode 51 includes an upper surface 51a. The upper surface 51a is the surface of the first electrode 51 on the side of the collector layer 12. The collector layer 12 is located on the first electrode 51. The collector layer 12 is of a second conductivity type.

[0017] A first buffer layer 13a is located on the collector layer 12. The first buffer layer 13a includes a first impurity. The first buffer layer 13a is of a first conductivity type. A second buffer layer 13b is located on the first buffer layer 13a. The second buffer layer 13b includes a second impurity. The second buffer layer 13b is of a first conductivity type. The first conductivity type can be, for example, n-type. The second conductivity type can be, for example, p-type.

[0018] The substrate layer 15 is located on the drift layer 11. The substrate layer 15 is of the second conductivity type. The emitter layer 16 is located on a portion of the substrate layer 15. The emitter layer 16 is of the first conductivity type. The contact layer 17 is located on a portion of the substrate layer 15.

[0019] The impurity concentration of the contact layer 17 can be greater than that of the substrate layer 15.

[0020] The second electrode 52 is positioned on the substrate layer 15, the emitter layer 16, and the contact layer 17, and is electrically connected to these regions. The third electrode 53 is insulated from the second electrode 52 by the insulating layer 40.

[0021] The second electrode 52 includes a lower surface 52a. The lower surface 52a is the surface of the second electrode 52 on the drift layer 11 side. The lower surface 52a of the second electrode 52 contacts the emitter layer 16. The third electrode 53 is located between a portion of the second electrode 52 and a portion of the drift layer 11. A gate insulating film 41 is located at least between the third electrode 53 and the substrate layer 15. The gate insulating film 41 insulates the drift layer 11, the substrate layer 15, and the emitter layer 16 from the third electrode 53. The gate insulating film 41 includes a lower portion 41a. The lower portion 41a is the portion of the gate insulating film 41 positioned on the second buffer layer 13b side. The lower portion 41a is also the portion of the trench positioned on the second buffer layer 13b side.

[0022] With a positive voltage relative to the second electrode 52 applied to the first electrode 51, a voltage not less than a threshold is applied to the third electrode 53. As a result, a channel (inversion layer) is formed in the p-type substrate layer 15. The current flowing between the first electrode 51 and the second electrode 52 can be controlled according to the potential of the third electrode 53. The first electrode 51 is, for example, a collector electrode. The second electrode 52 is, for example, an emitter electrode. The third electrode 53 is, for example, a gate electrode. The semiconductor device 100 is, for example, an IGBT (Insulated Gate Bipolar Transistor). Figure 1 Only the IGBT region is shown. Semiconductor device 100 may include IGBT regions and diode regions. Multiple IGBT regions and multiple diode regions may be arranged in the X and Y directions. IGBT regions and diode regions may be arranged alternately in the X direction.

[0023] Here, if the drift layer 11 is mainly thinned, there is a risk that the peak voltage may increase and oscillation may occur after turn-off. Therefore, in the semiconductor device 100 according to the embodiment, this problem is solved by forming the first buffer layer 13a and the second buffer layer 13b by proton irradiation, by setting appropriate positions of the apexes of the first peak P1 and the second peak P2 (which will be described later), and by setting appropriate impurity concentrations. The details are described below.

[0024] as shown in Figure 1 , 2 and 3, the first buffer layer 13a includes a first peak P1 having a first impurity concentration in the first direction D1; and the first direction D1 is from the first electrode 51 toward the second electrode 52. The first direction D1 from the first electrode 51 toward the second electrode 52 is the Z-axis direction. A direction perpendicular to the Z-axis direction is taken as the X-axis direction. A direction perpendicular to the Z-axis direction and the X-axis direction is taken as the Y-axis direction. The X-axis direction is, for example, the second direction D2. The second buffer layer 13b includes a second peak P2 having a second impurity concentration in the first direction D1. The impurity concentration of the first peak P1 is greater than the impurity concentration of the second peak P2. Figure 3 shows the peak of the impurity concentration of the collector layer 12 positioned between the first buffer layer 13a and the first electrode 51. The impurity concentration at the peak of the impurity concentration distribution of the collector layer 12 is greater than the impurity concentration of the first peak P1.

[0025] Figure 1 and Figure 2 show the distance R1 from the upper surface 51a to the apex of the first peak P1, the distance R2 from the upper surface 51a to the apex of the second peak P2, the distance R3 from the upper surface 51a to the lower surface 52a, the distance R4 from the lower portion 41a to the lower surface 52a, and the maximum depletion layer width Wmax of the drift layer 11 at turn-off. The width Wmax can be estimated as a quantity depending on the physical characteristics of the device; and it is desirable that the semiconductor device 100 satisfies R1<R2<(R3-R4-Wmax). The distance R3 from the upper surface 51a to the lower surface 52a is the total thickness of the collector layer 12, the first buffer layer 13a, the second buffer layer 13b, the drift layer 11, the base layer 15, and the emitter layer 16. The distance R4 from the lower portion 41a to the lower surface 52a is the trench depth of the semiconductor device 100. The occurrence of oscillation can be suppressed by making the impurity concentration of the first peak P1 greater than the impurity concentration of the second peak P2, that is, by satisfying R1<R2. By satisfying R2<(R3-R4-Wmax), the increase in peak voltage can be suppressed.

[0026] In semiconductor device 100, Wmax is represented by the following formula (1), where q is the absolute value of the electron charge, ε is the dielectric constant of the drift layer 11, Nd is the third impurity concentration per unit volume of the drift layer 11, Vs is the saturation velocity of the hole, Vce is the voltage between the first electrode 51 and the third electrode 53, Ic is the rated current, and γ h It is the ratio of hole current when turned off, and AA is the area of ​​the second electrode 52 in a plane including a second direction D2 intersecting the first direction D1 and a third direction D3 intersecting the second direction D2. Area AA is the area of ​​the region in which current mainly flows during the operation of the semiconductor device 100. Area AA is the area of ​​the second electrode 52 in the XY plane, and is the area of ​​the active region.

[0027] [Formula 1] The dielectric constant ε is, for example, the dielectric constant of the silicon included in the drift layer 11. The voltage Vce is, for example, the rated voltage or approximately 80% of the rated voltage. The ratio γ of the hole current during turn-off is estimated based on actual measurement data from the turn-off operation. h For example, it should be no less than 0.7 and no greater than 0.9. For example, a value of 0.8 is substituted into formula (1) as the ratio γ of the hole current when turned off. h It is expected that the value of Wmax estimated by formula (1) satisfies R2 < (R3 - R4 - Wmax).

[0028] Figure 4 This is a schematic diagram illustrating the width of the maximum depletion layer of a semiconductor device according to an implementation scheme.

[0029] For the width Wmax of the maximum depletion layer of the drift layer 11 in the semiconductor device 100 during shutdown, the lower end J0 of the maximum depletion layer is more oriented toward the second electrode 52 than the second peak P2 of the second buffer layer 13b. The combined length of the width Wmax of the maximum depletion layer and the distance R2 is less than the difference between the distance R3 and the distance R4. Therefore, as shown in characteristic E1, the increase in peak voltage is suppressed. If the lower end J0 of the maximum depletion layer is more oriented toward the first electrode 51 (i.e., the side opposite to the second electrode 52) than the apex of the second peak P2 of the second buffer layer 13b, the peak voltage increases, as shown in characteristic E0. The junction position is described below.

[0030] Therefore, it is expected that the semiconductor device 100 will satisfy R1. <R2<(R3-R4-Wmax)。

[0031] The desired result is Qdp > 4.27 × 10⁻⁶. -3 ×Nd+2.41×10 11 cm -2 , where Qdp(cm -2) is the total dose of the drift layer 11 and the second buffer layer 13b, and Nd(cm) -3 () represents the impurity concentration of drift layer 11. Here, the unit for Nd is cm⁻¹. -3 The total dose Qdp is as follows.

[0032] Figure 5 The total dose Qdp describes the dose of the drift layer 11 and the dose of the second buffer layer 13b.

[0033] Figure 5 The vertical axis is the carrier concentration per unit volume relative to the depth from the first electrode 51 to the second electrode 52. Figure 5 The diagram also shows the first peak P1 of the first buffer layer 13a, the second peak P2 of the second buffer layer 13b, the junction J1 (first junction position) between the first buffer layer 13a and the second buffer layer 13b, the center position M1 (midpoint in the thickness direction of the second buffer layer 13b) of the second buffer layer 13b in the first direction D1, and the junction J2 (second junction position) between the second buffer layer 13b and the drift layer 11. Junction J1 is the depth position where the carrier concentration between the first peak P1 and the second peak P2 is at its minimum. Center position M1 is the midpoint in the depth direction between junction positions J1 and J2. Junction J2 is, for example, a depth position where the impurity concentration reaches the value of the impurity concentration of the drift layer 11 plus 5% of the absolute value of the difference between the impurity concentration of the drift layer 11 and the impurity concentration of the second peak P2 of the second buffer layer 13b.

[0034] The total dose Qdp of the dose of the drift layer 11 and the dose of the second buffer layer 13b is the amount of impurities per unit area (XY-plane) of the carrier concentration per unit volume integrated in the depth direction from the junction position J1 (i.e., the point where the carrier concentration has a minimum value between the first peak P1 and the second peak P2) to the lower portion 41a.

[0035] Figure 6 The simulation results describe the conditions for the total dose of the semiconductor device according to the implementation scheme. Figure 6 Simulation results are shown for the changes in impurity concentration Nd (third impurity concentration) and total dose Qdp in the drift layer.

[0036] Figure 7 The characteristics are shown when the distance from the top surface to the vertex of the second peak is less than a specified distance. Figure 7 An example of the time variation of voltage Vce and rated current Ic is shown.

[0037] Figure 6 And the following Figure 9 and 14The circles shown are the result of a simulation, where there are no indicators. Figure 7 The waveform of the oscillation near the peak voltage shown in region A3 is absent, as is the waveform of the oscillation in region A4, or one of the waveforms that would cause the absence of the peak voltage increase shown in region A3 or the oscillation in region A4. Crossover is the result of simulation in which both the waveform of the oscillation near the peak voltage shown in region A3 and the waveform of the oscillation in region A4 are present.

[0038] like Figure 6 As shown, if Qdp decreases to 4.27 × 10 -3 ×Nd+2.41×10 11 cm -2 The following will result in multiple peaks in the voltage waveform, such as... Figure 7 Region A3, enclosed by a dashed line, is shown in the diagram. Furthermore, as shown in region A4, the oscillation waveform occurs after the turn-off. As a result, it is expected that the semiconductor device 100 will satisfy Qdp > 4.27 × 10⁻⁶. -3 ×Nd+2.41×10 11 This can suppress the occurrence of oscillations.

[0039] Figure 8 The relationship between the peak voltage between the first and third electrodes and the distance from the top surface to the apex of the second peak is shown. Figure 8 The peak concentration of Nproton is shown to be 5.5 × 10⁻⁶. 14 / cm 3 9.5×10 14 / cm 3 and 1.8×10 15 / cm 3 The sample, where Nproton is the peak concentration of the second impurity.

[0040] like Figure 8 As shown, with the distance R2 from the upper surface 51a to the vertex of the second peak P2 at 1.8 × 10⁻⁶, 15 / cm 3 In samples where the voltage increases, the peak voltage rises steeply. If the distance R2 increases, there is a risk of exceeding the reference voltage. For example, the reference voltage is a constant multiple (80 to 90%) of the rated voltage, and... Figure 8 In the example, the voltage is 675 V (750 V × 90%). Therefore, it is expected that semiconductor device 100 will satisfy Nproton ≤ 1.8 × 10⁻⁶. 15 / cm 3 Or Nproton < 1.8 × 10 15 / cm 3This can suppress the increase in peak voltage. Since the increase in peak voltage can be suppressed as the concentration peak Nproton decreases, it is desirable to satisfy Nproton ≤ 9.5 × 10⁻⁶. 14 / cm 3 and Nproton≤5.5×10 14 / cm 3 .

[0041] According to the semiconductor device 100, by setting the positions of the apexes of the first peak P1 and the second peak P2 and the impurity concentration to have the above configuration, the increase in peak voltage can be suppressed and the oscillation after shutdown can be suppressed.

[0042] like Figure 3 As shown, the concentration of the second impurity gradually decreases towards the first electrode 51. The concentration of the second impurity also gradually decreases from the second peak P2 towards the drift layer 11. The first peak P1 and the second peak P2 have steeper shapes rather than wider shapes. The second peak P2 has a steeper shape on the side of the second electrode 52. Figure 5 In this configuration, the center position M1 is positioned further towards the first electrode 51 than the position of the second peak P2. In other words, the depth distance between the junction position J2 and the position of the second peak P2 is less than the depth distance between the junction position J1 and the position of the second peak P2. The half-peak width of the first peak P1 and the second peak P2 can be 3 μm or less.

[0043] The number of second peaks P2 of the second impurity concentration can be 1. On the other hand, the second peak P2 can include multiple second peaks P2. In this case, the distance R2 from the upper surface 51a to the vertex of the second peak P2 is the distance to the vertex of the peak among the multiple second peaks P2 closest to the drift layer 11.

[0044] Figure 9 It is shown Figure 7 The presence or absence of oscillation waveforms in regions A3 and A4 results in changes in total dose Qdp and distance R2.

[0045] exist Figure 9 Simulations were performed for two types of distances R3 (thicknesses of collector layer 12, first buffer layer 13a, second buffer layer 13b, drift layer 11, base layer 15, and emitter layer 16).

[0046] like Figure 9As shown, if the distance R2 from the upper surface 51a to the peak of the second peak P2 is not greater than 3 μm, there is a risk of oscillation after shutdown if the total dose Qdp is too small. On the other hand, when the distance R2 is not less than 4 μm, favorable results are obtained for various values ​​of the total dose Qdp, and favorable waveforms are obtained for oscillation after shutdown. As a result, it is advantageous for the semiconductor device 100 to satisfy 4 μm ≤ R2 and 4 μm <R2。

[0047] Increasing the lower limit of R2 tends to better suppress oscillations. As a result, advantageously, semiconductor device 100 satisfies 5μm≤R2, 6μm≤R2, 7μm≤R2 and 8μm≤R2.

[0048] Figures 10 to 13 The relationship between the peak voltage between the first and third electrodes and the distance from the top surface to the apex of the second peak is shown. The peak voltage is... Figure 7 The maximum value of the Vce waveform is called Vcep. Figures 10 to 13 The peak concentration Nproton of the second impurity is shown to be 1.8 × 10⁻⁶. 15 / cm 3 The sample. Figure 10 A sample with a resistivity of 30 Ωcm is shown. Figure 11 A sample with a resistivity of 35 Ωcm is shown. Figure 12 A sample with a resistivity of 40 Ωcm is shown. Figure 13 A sample with a resistivity of 46 Ωcm is shown.

[0049] At a resistivity of 30 Ωcm Figure 10 In the sample shown, the peak voltage Vcep tends to increase to over 12 μm. Therefore, it is advantageous for the distance R2 from the upper surface 51a to the vertex of the second peak P2 to satisfy R2 < 12 μm. At a resistivity of 35 Ωcm Figure 11 In the samples shown, the peak voltage Vcep tends to increase by 11 μm or more. As a result, it is advantageous for semiconductor device 100 to satisfy R2 < 11 μm. At a resistivity of 40 Ωcm... Figure 12 In the samples shown, the peak voltage Vcep tends to increase by 10 μm or more. As a result, it is advantageous for semiconductor device 100 to satisfy R2 < 10 μm. At a resistivity of 46 Ωcm... Figure 13 In the samples shown, the peak voltage Vcep tends to increase by 9 μm or more. As a result, it is advantageous for semiconductor device 100 to satisfy R2 < 9 μm. Figure 10 , 11 Samples 12 and 13 are shown, where the resistivity is expressed as... Figure 10 , 11The order of 1, 2, and 3 increases, but the distance R2 of the peak voltage Vcep jump decreases with increasing resistivity, so a shorter distance R2 is better.

[0050] Figure 14 The simulation results are shown, illustrating the presence or absence of oscillations in the voltage waveform of the sample relative to the concentration peak of the second impurity concentration.

[0051] exist Figure 14 In sample A1, the resistivity is 46 Ωcm; and the distance R3 from the upper surface 51a to the lower surface 52a is 70 μm. In sample B1, the resistivity is 35 Ωcm; and the distance R3 from the upper surface 51a to the lower surface 52a is 65 μm. The distance R2 from the upper surface 51a to the apex of the second peak P2 is 4 μm.

[0052] like Figure 14 As shown, the peak concentration Nproton of the second impurity is 6.5 × 10⁻⁶. 14 / cm 3 Compared to the previous time, the peak concentration Nproton of the second impurity was 7.5 × 10⁻⁶. 14 / cm 3 The oscillation waveform characteristics are better at this time. As the peak concentration Nproton of the second impurity increases, the characteristics tend to improve. Therefore, Nproton satisfies 6.5 × 10⁻⁶. 14 / cm 3 <Nproton is advantageous. Satisfying 7.5 × 10 14 / cm 3 ≤Nproton is also advantageous.

[0053] The first impurity may include phosphorus. The peak concentration of the first impurity may be no less than 2 × 10⁻⁶. 16 / cm 3 and not greater than 3×10 16 / cm 3 .

[0054] The peak concentration of the second impurity can be no less than 0.02 times and no more than 0.06 times the peak concentration of the first impurity (for example, the peak concentration of the first impurity can be 3 × 10⁻⁶). 16 / cm 3 The peak concentration of the second impurity can be no less than 0.03 times and no more than 0.09 times the peak concentration of the first impurity (for example, the peak concentration of the first impurity can be 2 × 10⁻⁶). 16 / cm 3 ).

[0055] The second buffer layer 13b is formed by proton irradiation. The second impurity may include protons.

[0056] The first electrode 51, second electrode 52, and third electrode 53 comprise metallic materials such as aluminum and copper. The drift layer 11, collector layer 12, first buffer layer 13a, second buffer layer 13b, substrate layer 15, emitter layer 16, and contact layer 17 may comprise silicon, silicon carbide, gallium nitride, or gallium arsenide as semiconductor materials. When silicon is used as the semiconductor material, arsenic, phosphorus, or antimony may be used as impurities of a first conductivity type. A third impurity includes, for example, arsenic, phosphorus, or antimony. Boron may be used as an impurity of a second conductivity type. The third electrode 53 may comprise conductive polycrystalline silicon with added impurities or another conductive material. The insulating layer 40 and gate insulating film 41 comprise insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.

[0057] In this specification, "perpendicular" and "parallel" include not only strictly perpendicular and strictly parallel, but also fluctuations caused by manufacturing processes, etc.; and basically perpendicular and basically parallel are sufficient.

[0058] In the foregoing, exemplary embodiments of the invention have been described with reference to specific examples. However, embodiments of the invention are not limited to these specific examples. For instance, those skilled in the art can similarly practice the invention by appropriately selecting specific configurations of components (e.g., a first buffer layer, a second buffer layer, etc.) included in semiconductor devices from known technologies. Such practice is within the scope of the invention and achieves similar effects.

[0059] Furthermore, any two or more components of the specific example may be combined to the extent technically feasible, and the claims of the invention are included within the scope of the invention.

[0060] Furthermore, all semiconductor devices that can be practiced by those skilled in the art based on the semiconductor devices described above as exemplary embodiments of the present invention through appropriate design variations are also within the scope of the present invention, as long as they contain the objectives of the present invention.

[0061] Various other changes and modifications can be conceived by those skilled in the art within the spirit of this invention, and it should be understood that these changes and modifications are also included within the scope of this invention.

[0062] While certain embodiments have been described, these embodiments are presented by way of example only and are not intended to limit the scope of the invention. In fact, the novel embodiments described herein can be embodied in various other forms; furthermore, various omissions, substitutions, and changes can be made to the form of the embodiments described herein without departing from the spirit of the invention. The appended claims and their equivalents are intended to cover these forms or variations that fall within the scope and spirit of the invention.

Claims

1. A semiconductor apparatus, comprising: a first electrode, including an upper surface; a collector layer, located on the first electrode, the collector layer being of a second conductivity type; a first buffer layer, located on the collector layer, the first buffer layer being of a first conductivity type and including a first impurity; a second buffer layer, located on the first buffer layer, the second buffer layer being of the first conductivity type and including a second impurity; a drift layer, located on the second buffer layer, the drift layer being of the first conductivity type and including a third impurity; a base layer, located on the drift layer, the base layer being of the second conductivity type; an emitter layer, located on the base layer, the emitter layer being of the first conductivity type; a second electrode, located on the emitter layer, the second electrode including a lower surface; a third electrode, located between a portion of the second electrode and a portion of the drift layer; and a gate insulating film, located at least between the third electrode and the base layer, the gate insulating film including a lower portion, the first buffer layer includes a first peak of concentration of the first impurity in a first direction, the first direction being a direction from the first electrode toward the second electrode, the second buffer layer includes a second peak of concentration of the second impurity in the first direction, R1<R2<(R3-R4-Wmax) is satisfied, wherein R1 is a distance from the upper surface to a vertex of the first peak, R2 is a distance from the upper surface to a vertex of the second peak, R3 is a distance from the upper surface to the lower surface, R4 is a distance from the lower portion to the lower surface, and Wmax is a maximum depletion layer width of the drift layer at turn-off, Wmax is expressed by formula (1), where q is the absolute value of the electron charge, ε is the dielectric constant of the drift layer, Nd is the concentration of the third impurity in the drift layer, Vs is the saturation velocity of the hole, Vce is the voltage between the first and third electrodes, Ic is the rated current, and γ h It is the ratio of hole current when turned off, and AA is the area of ​​the second electrode in a plane including the second direction and the third direction. The second direction intersects the first direction, and the third direction intersects the first and second directions. The condition Qdp > 4.27 × 10 is satisfied. -3 ×Nd+2.41×10 11 cm -2 Qdp is the total dose of the drift layer and the second buffer layer, and Nd is measured in cm³. -3 The unit of Qdp is cm. -2 , Satisfying Nproton < 1.8 × 10 15 / cm 3 Nproton is the concentration of the second peak.

2. The semiconductor apparatus according to claim 1, wherein, a half-peak width of the second peak is no greater than 3 μm.

3. The semiconductor apparatus according to claim 1, wherein, the concentration of the second impurity gradually decreases from the second peak toward the drift layer.

4. The semiconductor apparatus according to claim 3, wherein, the number of the second peak of the concentration of the second impurity is 1.

5. The semiconductor apparatus according to claim 1, wherein, the second buffer layer includes a plurality of peaks, the plurality of peaks include the second peak, and the distance R2 is a distance from the upper surface to a vertex of a peak that is closest to the drift layer among the plurality of peaks.

6. The semiconductor apparatus according to claim 1, wherein, the distance R2 satisfies 4 μm<R2<12 μm, and The concentration of Nproton satisfies 7.5 × 10⁻⁶. 14 / cm 3 ≤Nproton.

7. The semiconductor apparatus according to claim 1, wherein, the first impurity comprises phosphorus, and The concentration of the first peak is not less than 2×10 16 / cm 3 and not greater than 3×10 16 / cm 3 .

8. The semiconductor apparatus according to claim 7, wherein, the concentration of the second peak is no less than 0.02 times and no greater than 0.06 times the concentration of the first peak.

9. A semiconductor apparatus, comprising: a first electrode, including an upper surface; a collector layer, located on the first electrode, the collector layer being of a second conductivity type; A first buffer layer is located on the collector layer, the first buffer layer having a first conductivity type and including a first impurity; A second buffer layer is located on the first buffer layer, the second buffer layer being of the first conductivity type and including a second impurity; A drift layer, located on the second buffer layer, wherein the drift layer is of the first conductivity type and includes a third impurity; A base layer, located on the drift layer, wherein the base layer is of the second conductivity type; An emitter layer is located on the substrate layer, and the emitter layer is of the first conductivity type; A second electrode is located on the emitter layer, and the second electrode includes a lower surface; The third electrode is located between a portion of the second electrode and a portion of the drift layer; as well as A gate insulating film, at least located between the third electrode and the substrate layer, the gate insulating film including a lower portion. The first buffer layer includes a first peak value of the concentration of the first impurity in a first direction, the first direction being from the first electrode toward the second electrode. The second buffer layer includes a second peak value of the concentration of the second impurity in the first direction. The center position is the midpoint between the first joint position between the first buffer layer and the second buffer layer and the second joint position between the second buffer layer and the drift layer. The center position is located further towards the first electrode than the position of the second peak. The distance R2 from the upper surface to the vertex of the second peak satisfies 4 μm. <R2<12μm。 10. The semiconductor device according to claim 9, wherein, The half-peak width of the second peak is no greater than 3μm.

11. The semiconductor device according to claim 9, wherein, The concentration of the second impurity gradually decreases from the second peak toward the drift layer.

12. The semiconductor device according to claim 11, wherein, The number of the second peak values ​​of the concentration of the second impurity is 1.

13. The semiconductor device according to claim 9, wherein, The second buffer layer includes multiple peaks, the multiple peaks including the second peak, and The distance R2 is the distance from the upper surface to the vertex of the peak that is closest to the drift layer among the plurality of peaks.

14. The semiconductor device according to claim 9, wherein, The first impurity includes phosphorus, and The concentration of the first peak is not less than 2×10 16 / cm 3 and not greater than 3×10 16 / cm 3 .

15. The semiconductor device according to claim 14, wherein, The concentration of the second peak is not less than 0.02 times the concentration of the first peak and not greater than 0.06 times the concentration of the first peak.

16. The semiconductor device according to claim 9, wherein, Satisfy 7.5×10 14 cm -3 ≤Nproton<1.8×10 15 cm -3 ,and Nproton is the concentration of the second peak.

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