A semiconductor power device and a manufacturing method thereof

Abstract

The application discloses a semiconductor power device, comprising a substrate, an epitaxial layer, a cell region and a terminal region; the substrate has a first surface and a second surface arranged oppositely; the epitaxial layer is arranged on the first surface of the substrate; the cell region comprises a well region, the well region extends from the upper surface of the epitaxial layer to the interior of the epitaxial layer; the terminal region is located at the periphery of the cell region, and the terminal region comprises a first doped region, which extends from the upper surface of the epitaxial layer to the interior of the epitaxial layer, wherein the doping concentration of the first doped region is the same as that of the well region, and the depth of the first doped region in the epitaxial layer is the same as that of the well region in the epitaxial layer. The semiconductor power device provided by the application matches the depletion characteristics of the terminal region and the cell region completely by arranging the doped region with the same doping concentration and the same depth as the well region in the terminal region, so that the device no longer depends on the optimal dose of the narrow range of dopants, the depletion abnormality caused by the injection deviation is weakened, and the breakdown voltage and the voltage withstanding performance of the device are improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor power device and a method for manufacturing the same. Background Technology

[0002] Semiconductor power devices, also known as power electronic devices, are core components in circuits that realize electrical energy conversion or control, and can be applied in various fields such as industry, automobiles, rail traction, and home appliances. Taking the Insulated Gate Bipolar Transistor (IGBT) as an example, its excellent performance has led to its widespread use in inverters, frequency converters, switching power supplies, lighting circuits, and traction drives. Meanwhile, semiconductor power devices made with wide-bandgap materials such as SiC and GaN show great application potential in emerging fields such as new energy vehicles and smart grids due to their higher efficiency and stability.

[0003] Semiconductor power devices consist of a cell region and a termination region. The cell region, located in the center of the device, is used to initiate current flow between the source and drain under the control of a bias voltage. The termination region surrounds the cell region and serves as a transition area between the cell region and the external environment, enhancing the device's breakdown voltage and reliability. Besides the structural design of the cell region, the design of the termination region is crucial to the electrical parameters (avalanche breakdown voltage, etc.), long-term reliability (HTRB / H3TRB, etc.), and device cost of semiconductor power devices.

[0004] Existing technologies mainly employ two termination structures: field limiting ring (FLR) and junction termination extension (JTE). The FLR termination structure, designed to improve breakdown voltage, uses a large number of field limiting rings, leading to an increased lateral dimension of the termination region and a larger footprint, thus limiting the device's current-carrying capacity. Furthermore, this termination structure is highly sensitive to surface charge; fluctuations in surface charge affect the surface electric field distribution, consequently impacting the device's breakdown voltage and reliability. The JTE termination structure introduces additional charge by incorporating a lightly doped P-type region on the outer edge of the main junction, thereby modulating the electric field distribution at the main junction. The fabrication of this lightly doped P-type region requires extremely precise control over parameters such as doping concentration and width; even minute deviations can significantly affect the device's blocking characteristics, thereby impacting its reliability. Summary of the Invention

[0005] This application provides a semiconductor power device and its manufacturing method. By setting a doped region with the same doping concentration and depth as the well region in the terminal region, the depletion characteristics of the terminal region and the cell region are perfectly matched. No additional doping dose needs to be precisely injected into the terminal region A2, which weakens the depletion anomaly caused by injection deviation. At the same time, the electric field transition from the cell region to the terminal region is continuous and smooth, which suppresses the local electric field distortion caused by the interface charge in the terminal region, thereby improving the tolerance of the terminal region to doping dose and surface charge, and improving the breakdown voltage and withstand voltage performance of the device.

[0006] According to an embodiment of the present invention, a semiconductor power device is provided, the device comprising a substrate, an epitaxial layer, a cell region, and a termination region; the substrate has a first surface and a second surface disposed opposite to each other; the epitaxial layer is disposed on the first surface of the substrate; the cell region includes a well region extending from the upper surface of the epitaxial layer into the epitaxial layer; the termination region is located on the periphery of the cell region, and the termination region includes a first doped region extending from the upper surface of the epitaxial layer into the epitaxial layer, wherein the doping concentration of the first doped region is the same as the doping concentration of the well region, and the depth of the first doped region in the epitaxial layer is the same as the depth of the well region in the epitaxial layer.

[0007] According to an embodiment of the present invention, a method for manufacturing a semiconductor power device is also provided, comprising: providing a substrate; growing an epitaxial layer on the substrate; forming a patterned first hard mask layer on the epitaxial layer, wherein the first hard mask layer has a first opening and a second opening, the first opening spanning a cell region and a termination region, and the second opening located in the termination region; performing ion implantation on the epitaxial layer based on the first hard mask layer to form a well region and a first doped region distributed around the well region, the well region being located in the cell region and the first doped region being located in the termination region; performing ion implantation on the well region to form a source region; sequentially etching the source region, the well region, and the epitaxial layer at the source region to form a gate trench; forming a gate dielectric layer at the bottom and sidewalls of the gate trench; filling the gate trench after forming the gate dielectric layer with a gate electrode, the depth of the gate trench being greater than the depth of the well region; generating a dielectric layer at a corresponding position of the epitaxial layer, the dielectric layer covering the gate trench and part of the source region; and generating a field oxide layer at a corresponding position of the epitaxial layer, the field oxide layer covering the first doped region. Attached Figure Description

[0008] The above and other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings:

[0009] Figure 1 This is a schematic diagram of a cross-sectional structure of a semiconductor power device 100 in the prior art, perpendicular to the device surface.

[0010] Figure 2 This is a schematic diagram of a cross-sectional structure of a semiconductor power device 200 in the prior art, perpendicular to the device surface.

[0011] Figure 3A A partial cross-sectional view of a semiconductor power device 300 according to an embodiment of the present invention is shown;

[0012] Figure 3B It shows Figure 3A A magnified view of a portion of the image, C1;

[0013] Figure 4 A method 400 for manufacturing a semiconductor power device according to an embodiment of the present invention is shown;

[0014] Figures 5-15 A cross-sectional view of the device is shown during the implementation of each step of a manufacturing method 400 according to an embodiment of the present invention;

[0015] Figure 16 and Figure 17 The electric field distribution of a semiconductor power device 300 under avalanche breakdown state according to an embodiment of the present invention is shown. Detailed Implementation

[0016] Specific embodiments of the present invention will now be described in detail. It should be noted that the embodiments described herein are for illustrative purposes only and are not intended to limit the invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that these specific details are not necessary to practice the invention. In other instances, well-known circuits, materials, or methods have not been specifically described to avoid obscuring the invention.

[0017] Throughout this specification, references to "an embodiment," "an example," or "an example" mean that a particular feature, structure, or characteristic described in connection with that embodiment or example is included in at least one embodiment of the invention. Therefore, the phrases "in an embodiment," "in an embodiment," "an example," or "an example" appearing in various places throughout the specification do not necessarily refer to the same embodiment or example. Furthermore, specific features, structures, or characteristics can be combined in one or more embodiments or examples in any suitable combination and / or sub-combination. Moreover, those skilled in the art will understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale. The same reference numerals indicate the same elements. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items. The drawings are not drawn to scale and are for illustrative purposes only. For clarity, unless otherwise stated, the same elements have been designated by corresponding reference numerals in different drawings.

[0018] The terms “having,” “comprising,” “including,” “include,” etc., are open-ended, and these terms indicate the presence of the said structure, element, or feature, but do not exclude additional elements or features.

[0019] When describing the structure of a device, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above another layer or region, or that it contains other layers or regions between it and another layer or region. Furthermore, if the device is flipped, the layer or region will be located "below" or "under" another layer or region.

[0020] To describe a situation where it is directly above another layer or another region, this paper will use the expressions "directly above..." or "above and adjacent to...". Furthermore, when describing the structure of a device, this paper uses the term "depth," which refers to the vertical distance from a reference plane to the bottom of a component. For example, the depth of A could refer to the vertical distance from the upper surface of the epitaxial layer to the bottom of A.

[0021] In some of the accompanying figures, relative doping concentrations are indicated by a "-" or "+" sign next to the doping type "n" or "p". For example, "n-" indicates a lower doping concentration than the "n" doped region, while the "n" doped region has a higher doping concentration than the "n-" doped region. Doped regions with the same relative doping concentration do not necessarily have the same absolute doping concentration. For example, two different "n"-type doped regions may have the same or different absolute doping concentrations.

[0022] In embodiments of the present invention, each semiconductor layer or region has a first conductivity type or a second conductivity type. The first conductivity type refers to either n-type or p-type, and the second conductivity type is the other. That is, a semiconductor layer with the first conductivity type can be an n-type semiconductor layer or a p-type semiconductor layer. When the semiconductor layer with the first conductivity type is an n-type semiconductor layer, the semiconductor layer with the second conductivity type is a p-type semiconductor layer. An n-type semiconductor layer is formed by doping an n-type impurity into the semiconductor layer. The n-type impurity can be a pentavalent element such as nitrogen, phosphorus, or arsenic. A p-type semiconductor layer is formed by doping a p-type impurity into the semiconductor layer. The p-type impurity can be a trivalent element such as boron, indium, gallium, or aluminum. Unless otherwise specified, the doping type is equivalent to the conductivity type.

[0023] Figure 1 This is a schematic diagram of a cross-sectional structure of a prior art semiconductor power device 100 perpendicular to the surface of the device 100. (See diagram below.) Figure 1As shown, the semiconductor power device 100 includes a substrate 101, an epitaxial layer 102, a cell region A1 and a connection region A3 located in the epitaxial layer 102, a terminal region A2, a source metal layer 114, a drain metal layer 115, a dielectric layer 112 located above the cell region A1, and a field oxide layer 113 located above the terminal region A2 and part of the connection region A3.

[0024] exist Figure 1 In the diagram, cell region A1 includes a gate trench 107. The gate trench 107 is located in the epitaxial layer 102 and extends from the upper surface of the epitaxial layer 102 into the interior of the epitaxial layer 102. A gate electrode 108 is located in the gate trench 107, and the gate trench 107 is filled with a gate dielectric layer 109, which isolates the gate electrode 108 from the gate trench 107.

[0025] like Figure 1 As shown, a well region 103 is disposed in the epitaxial layer 102 between the gate trenches 107, extending from the upper surface of the epitaxial layer 102 into the interior of the epitaxial layer 102 and exposed on the upper surface of the epitaxial layer 102. A source region 104 is disposed in the well region 103, extending from the upper surface of the epitaxial layer 102, i.e., the surface of the well region 103, into the interior of the well region 103. A source metal layer 114 is connected to the source region 104 through a connection structure (contact pin or via), thereby connecting the potential of the source region 104 to the source potential of the semiconductor power device 100.

[0026] Figure 1 In the epitaxial layer 102, there are a drift layer 1021 and a current spreading layer 1022, and a buffer layer 1023 located between the drift layer 1021 and the current spreading layer 1022. The terminal region A2 includes a plurality of spaced field limiting rings (FLRs), each of which includes a buffer unit 1024 and a target doped region 1025. The target doped region 1025 is located in the current spreading layer 1022 and extends from the upper surface of the current spreading layer 1022 into the interior of the current spreading layer 1022. The buffer unit 1024 is located in the buffer layer 1023 and extends from the upper surface of the buffer layer 1023 into the interior of the buffer layer 1023.

[0027] In the semiconductor power device 100, due to its high surface electric field, to improve the breakdown voltage, it is necessary to reduce the peak surface electric field during the design of device 100, requiring the design of a large number of field limiting rings (FLRs) in the termination region. During the design, many factors, such as the number, width, and spacing of the FLRs, affect the surface electric field distribution. Furthermore, the termination region A2 of multiple FLRs occupies a large area of ​​device 100, affecting the current carrying capacity of device 100. This termination region A2 is also highly sensitive to surface charge; interface defects and charges accumulated within the field oxide layer 113 will affect the surface electric field distribution of device 100, thereby affecting the breakdown voltage and reliability of device 100.

[0028] Figure 2 This is a schematic diagram of a partial cross-sectional structure of a prior art semiconductor power device 200 perpendicular to the surface of the device 200. (See diagram below.) Figure 2 As shown, device 200 includes a substrate 201, an epitaxial layer 202, a cell region A1 and a connection region A3 located in the epitaxial layer 202, a terminal region A2, a source metal layer 214, a drain metal layer 215, a dielectric layer 212 located above the cell region A1, and a field oxide layer 213 located above the terminal region A2 and part of the connection region A3.

[0029] exist Figure 2 In the diagram, cell region A1 includes a gate trench 207. The gate trench 207 is located in the epitaxial layer 202 and extends from the upper surface of the epitaxial layer 202 into the interior of the epitaxial layer 202. A gate electrode 208 is located in the gate trench 207, and the gate trench 207 is filled with a gate dielectric layer 209, which isolates the gate electrode 208 from the gate trench 207.

[0030] like Figure 2 As shown, a well region 203 is disposed in the epitaxial layer 202 between the gate trenches 207, extending from the upper surface of the epitaxial layer 202 into the interior of the epitaxial layer 202 and exposed on the upper surface of the epitaxial layer 202. A source region 204 is disposed in the well region 203, extending from the upper surface of the epitaxial layer 202, i.e., the surface of the well region 203, into the interior of the well region 203. A source metal layer 214 is connected to the source region 204 through a connection structure (contact pin or via), thereby connecting the potential of the source region 204 to the source potential of the device 200.

[0031] exist Figure 2 In the epitaxial layer 202, there are a drift layer 2021 and a current spreading layer 2022, and a buffer layer 2023 located between the drift layer 2021 and the current spreading layer 2022. The cell region A1 and the connection region A3 also include a buffer unit 2024, which is located in the buffer layer 2023 and extends from the upper surface of the buffer layer 2023 into the interior of the buffer layer 2023.

[0032] Figure 2 In the middle, the terminal region A2 includes a first P-type extension region 205 and a second P-type extension region 206, which extend from the upper surface of the current extension layer 2022 into the interior of the current extension layer 2022.

[0033] In device 200, the additional charge introduced by the first P-type extension region 205 and the second P-type extension region 206 can modulate the electric field distribution at the main junction, thereby reducing the electric field peak and expanding the depletion region width to obtain a more optimized electric field distribution. The first P-type extension region 205 and the second P-type extension region 206 each have their corresponding figure of merit concentrations, and the breakdown voltage of the terminal region of device 200 is sensitive to the figure of merit concentrations of the first P-type extension region 205 and the second P-type extension region 206. When the first P-type extension region 205 and the second P-type extension region 206 are doped with a certain figure of merit concentration, the first P-type extension region 205 and the second P-type extension region 206 can effectively share the high electric field at the connection region A3 or the cell region A2, thereby improving the breakdown voltage performance of device 200. However, the fabrication of the first P-type extension region 205 and the second P-type extension region 206 requires extremely precise control over parameters such as doping concentration and width. The process is highly complex and challenging; even minor process deviations can affect the surface electric field distribution of device 200, thereby impacting its breakdown voltage and reliability. Furthermore, this terminal structure fabrication process requires additional hard masks for the first P-type extension region 205 and the second P-type extension region 206, significantly increasing manufacturing costs.

[0034] Figure 3A A partial cross-sectional view of a semiconductor power device 300 according to an embodiment of the present invention is shown, the cross-section being perpendicular to the surface of the device 300. For example... Figure 3A As shown, the semiconductor power device 300 includes a substrate 301, an epitaxial layer 302, a source metal layer 314, a drain metal layer 315, a dielectric layer 312, and a field oxide layer 313.

[0035] Substrate 301 has a first surface SS1 and a second surface SS2 disposed opposite to each other. Epitaxial layer 302 is located on the first surface SS1 of substrate 301, that is, epitaxial layer 302 is located on substrate 301. Drain metal layer 315 is located on the second surface SS2 of substrate 301 and is electrically connected to substrate 301. Epitaxial layer 302 has an upper surface ES1 and a lower surface ES2. The upper surface ES1 and the lower surface ES2 of epitaxial layer 302 are parallel and opposite to each other, and the lower surface ES2 of epitaxial layer 302 is in contact with the first surface SS1 of substrate 301. The upper surface ES1 of epitaxial layer 302 is also the upper surface of semiconductor layer of device 300. Source metal layer 314, dielectric layer 312 and field oxide layer 313 are located on the upper surface ES1 of epitaxial layer 302, that is, on the front side of device 300. Drain metal layer 315 is located on the second surface SS2 of substrate 301 and is in contact with substrate 301, that is, on the back side of device 300. The dielectric layer 312 and the field oxide layer 313 may include insulating materials, such as oxides or nitrides.

[0036] exist Figure 3AIn the device 300, according to the different functions of each part, it can be divided into a cell region A1, a connection region A3, and a termination region A2. All three are distributed in the epitaxial layer 302 and share the epitaxial layer 302. The cell region A1 is located in the central region of the device 300, the connection region A3 is located on the periphery of the cell region A1 and is distributed in a ring around the cell region A1, and the termination region A2 is located on the periphery of the cell region A1 and the connection region A3 and is distributed in a ring around the cell region A1.

[0037] Figure 3B It shows Figure 3A A magnified view of a portion, C1. (See image C1.) Figure 3A and Figure 3B As shown, well regions 303 and gate trenches 307 located between adjacent well regions 303 are distributed in cell region A1, wherein the depth of the gate trenches 307 is greater than the depth of the well regions 303. The gate trenches 307 are located in epitaxial layer 302 and extend from the upper surface ES1 of epitaxial layer 302 into the interior of epitaxial layer 302. Gate electrodes 308 are distributed in the gate trenches 307, and a gate dielectric layer 309 is filled in the gate trenches 307, which isolates the gate electrodes 308 from the gate trenches 307. The gate dielectric layer 309 may include an insulating material, such as an oxide or a nitride.

[0038] The well region 303 is located in the epitaxial layer 302 and extends from the upper surface ES1 of the epitaxial layer 302 into the interior of the epitaxial layer 302. A source region 304 is distributed within the well region 303. The source region 304 extends from the surface of the well region 303, i.e., the upper surface ES1 of the epitaxial layer 302, into the interior of the well region 303. The depth of the source region 304 is less than the depth of the well region 303. In some embodiments, the well region 303 is provided with a well contact region. Both the well contact region and the source region 304 are electrically connected to the source metal layer 314, making the well region 303 and the source region 304 at the same potential.

[0039] The substrate 301, epitaxial layer 302, and source region 304 have a first doping type, and the well region 303 has a second doping type. In some embodiments, the first doping type is n-type doping, and the second doping type is p-type doping. In other embodiments, the first doping type is p-type doping, and the second doping type is n-type doping.

[0040] The terminal region A2 includes a first doped region 305, which is located in the epitaxial layer 302 and extends from the upper surface of the epitaxial layer 302 into the interior of the epitaxial layer 302. The doping concentration of the first doped region 305 is the same as that of the well region 303, and the depth of the first doped region 305 in the epitaxial layer 302 is the same as that of the well region 303. Furthermore, the doping type of the first doped region 305 is also the same as that of the well region 303, including doping with the same element, such as aluminum. Specifically, the substrate 301, the epitaxial layer 302, and the source region 304 have a first doping type, while the well region 303 and the first doped region 305 have a second doping type, which are different from the first doping type. In some embodiments, the terminal region A2 includes at least two first doped regions 305, wherein the widths of the first doped regions 305 may be different, such as... Figure 3A and Figure 3B As shown, the width of the first doped region 305 near the connection region A3 is much larger than that of the first doped region 305 far from the connection region A3.

[0041] The field oxide layer 313 at least covers the first doped region 305, which can isolate the first doped region 305 of the terminal region A2 from the source metal layer 314. The thickness of the field oxide layer 313 is greater than the thickness of the dielectric layer 312.

[0042] In embodiments of the present invention, such as Figure 3A As shown, in the epitaxial layer 302, a first doped region 305 with the same doping concentration and depth as the well region 303 is provided at the corresponding position of the terminal region A2. The doping type of the first doped region 305 is the same as that of the well region 303, including doping with the same element. This makes the depletion characteristics of the terminal region A2 and the cell region A1 completely matched, eliminating the need to set up an additional widening or stepped buffer doping structure in the terminal region A2 to compensate for the depletion difference between the cell region A1 and the terminal region A2. Therefore, the area occupied by the terminal region A2 can be significantly reduced. Moreover, since the doping dose of the first doped region 305 in the terminal region A2 is consistent with that of the well region 303 in the cell region A1, there is no need to precisely inject additional doping dose in the terminal region A2. This can significantly broaden the fault tolerance of the doping process of the terminal region A2 and weaken the depletion anomaly caused by process fluctuations such as ion implantation dose drift, implantation angle deviation, and mask offset during the production process. That is, while achieving a smaller area of ​​the terminal region A2, the depletion anomaly caused by ion implantation deviation is weakened. Meanwhile, the well region 303 and the first doped region 305 have the same doping, which makes the doping distribution continuous from cell region A1 to terminal region A2 on the side of epitaxial layer 302 away from substrate 301. The depletion layer elongation rate has no abrupt change, and the interface electric field transition is continuous and smooth. This can suppress the local electric field concentration distortion caused by the accumulation of interface charge in terminal region A2, thereby improving the tolerance of terminal region A2 to interface charge and improving the breakdown voltage and withstand voltage performance of device 300.

[0043] In one embodiment, the epitaxial layer 302 includes a drift layer 3021 and a current spreading layer 3022, and a buffer layer 3023 located between the drift layer 3021 and the current spreading layer 3022. The current spreading layer 3022, the buffer layer 3023, and the drift layer 3021 have the same doping type, wherein the doping concentration of the buffer layer 3023 is greater than that of the drift layer 3021, and the doping concentration of the current spreading layer 3022 is greater than that of the buffer layer 3023.

[0044] exist Figure 3A In the buffer layer 3023, several buffer units 3024 are distributed laterally. The buffer units 3024 extend from the upper surface of the buffer layer 3023 into its interior, and longitudinally penetrate the entire thickness of the buffer layer 3023. Each buffer unit 3024 includes extended buffer units 3024a and non-extended buffer units 3024b, with the non-extended buffer units 3024b located around the extended buffer units 3024a. The extended buffer units 3024a extend from cell region A1 to connection region A3 and terminal region A2, while the non-extended buffer units 3024b are located in terminal region A2. Figure 3A and Figure 3B In the embodiment, in addition to the extended buffer unit 3024a, the terminal area A2 also includes at least two non-extended buffer units 3024b.

[0045] In one embodiment, such as Figure 3B As shown, the cell region A1 also includes a shielding layer 310, located at the bottom of the gate trench 307, extending from the bottom of the gate trench 307 toward the drift layer 3021. The gate electrode 308 is isolated from the shielding layer 310 by the gate dielectric layer 309.

[0046] exist Figure 3B In this design, the shielding layer 310 is arranged in a multi-step stepped configuration, extending from the bottom of the gate trench 307 towards the drift layer 3021. A total high voltage difference exists between the drift layer 3021 and the shielding layer 310. This total high voltage difference no longer acts concentrated on a single insulating interface, but is distributed and amortized along the multi-step configuration to the segmented insulating regions corresponding to each step. This causes the potential to change slowly along the steps, significantly reducing the potential drop borne by a single insulating layer and smoothing the overall potential gradient of the device 300. Therefore, it can weaken the potential abrupt change at the corner of the gate trench 307 and effectively suppress the electric field concentration at the corner of the gate trench 307. Furthermore, the shielding layer 310 and the well region 303 have the same doping type.

[0047] exist Figure 3BIn this design, the shielding layer 310 includes a first shielding layer 310a and a second shielding layer 310b. The first shielding layer 310a is located below the gate trench 307, and the gate electrode 308 is isolated from the first shielding layer 310a by the gate dielectric layer 309. The second shielding layer 310b is located below the first shielding layer 310a. The width of the second shielding layer 310b is smaller than that of the first shielding layer 310a, and the width of the first shielding layer 310a is not greater than the width of the gate trench 307.

[0048] Connection region A3 is located between cell region A1 and terminal region A2. Connection region A3 includes a connection layer 311 extending from the upper surface ES1 of epitaxial layer 302 into the interior of epitaxial layer 302, i.e., extending from the upper surface of current spreading layer 3022 into the interior of current spreading layer 3022. Connection layer 311 extends longitudinally through the entire thickness of current spreading layer 3022. Connection layer 311 is located between well region 303 and first doped region 305, adjacent to both well region 303 and first doped region 305. This connection layer 311 connects the entire cell region A1 and terminal region A2, simplifying the structure of connection region A3.

[0049] In one embodiment, the well region 303, the first doped region 305, and the interconnect layer 311 have the same doping type, but the doping concentration of the interconnect layer 311 is greater than that of the well region 303 and the first doped region 305. For example, the doping concentration of the interconnect layer 311 is 1e18cm⁻¹. -3 -~1e20cm -3 The doping concentration of well region 303 and the first doped region 305 is 1e17cm. -3 -~1e18cm -3 .

[0050] Figure 4 A method 400 for manufacturing a semiconductor power device according to an embodiment of the present invention is shown. Figures 5-15 A cross-sectional view of the device is shown during the implementation of each step of a manufacturing method 400 according to an embodiment of the present invention.

[0051] like Figure 4 As shown, the manufacturing method 400 of the semiconductor power device 300 includes steps 401-407. The following is in conjunction with... Figures 5-15 The manufacturing method 400 is described in detail.

[0052] Step 401: Provide a substrate 301 and grow an epitaxial layer 302 on the substrate 301; wherein the cell region A1, the connection region A3 and the terminal region A2 are all distributed in the epitaxial layer 302.

[0053] The epitaxial layer 302 includes a drift layer 3021, a buffer layer 3023, and a current spreading layer 3022. The current spreading layer 3022, the buffer layer 3023, and the drift layer 3021 have the same doping type. The doping concentration of the buffer layer 3023 is greater than that of the drift layer 3021, and the doping concentration of the current spreading layer 3022 is greater than that of the buffer layer 3023.

[0054] Step 401 involves growing an epitaxial layer 302 on the substrate 301, including the following steps 4011-4015:

[0055] Step 4011: A drift layer 3021 is generated on the substrate 301.

[0056] Step 4012 involves ion implantation on the drift layer 3021 to form a buffer layer 3023. In one embodiment, ion implantation on the drift layer 3021 may be, for example, nitrogen ion implantation, with an implantation energy of 50 keV to 1000 keV and an implantation dose of 1e12 cm⁻¹. -2 ~9e12cm -2 A buffer layer 3023 of a certain thickness is formed on the drift layer 3021, and the cross-section of the device 300 after forming the buffer layer 3023 is as follows. Figure 5 As shown.

[0057] In step 4013, a patterned second hard mask layer 317 is formed on the buffer layer 3023. The second hard mask layer 317 has a third opening 317a and a fourth opening 317b, wherein the third opening 317a spans the cell region A1, the connection region A3, and the terminal region A2, and the fourth opening 317b is located in the terminal region A2. In one embodiment, the patterned second hard mask layer 317 can be obtained by depositing an oxide layer on the buffer layer 3023 and then etching the oxide layer. It should be noted that the number of third openings 317a and fourth openings 317b can be one, two, or more, depending on the number of locations requiring ion implantation or etching.

[0058] Step 4014: Ion implantation is performed on the buffer layer 3023 based on the second hard mask layer 317 to form extended buffer units 3024a and non-extended buffer units 3024b distributed around the extended buffer units 3024a. The extended buffer units 3024a extend from the cell region A1 to the connection region A3 and the terminal region A2. The terminal region A2 includes non-extended buffer units 3024b in addition to the extended buffer units 3024a.

[0059] In one embodiment, ion implantation, for example aluminum ion implantation, can be performed on the buffer layer 3023 based on the second hard mask layer 317, with an implantation energy of 150 keV to 500 keV and an implantation dose of 1.0e13 cm⁻¹. -2~1.8e13cm -2 This forms extended buffer units 3024 and non-extended buffer units. The cross-section of the device 300 after forming the extended buffer units 3024 and non-extended buffer units (without removing the second hard mask layer 317) is as follows. Figure 6 As shown. Figure 6 In the buffer layer 3023, two extended buffer units 3024a and two non-extended buffer units 3024b are formed, and the two non-extended buffer units 3024b are both located in the terminal area A2.

[0060] Step 4015: Remove the second hard mask layer 317 and grow a current spreading layer 3022 on the buffer layer 3023. The cross-section of the device 300 after growing the current spreading layer 3022 on the buffer layer 3023 is shown below. Figure 7 As shown.

[0061] Step 402: A patterned first hard mask layer 316 is formed on the current spreading layer 3022. The first hard mask layer 316 has a first opening 316a and a second opening 316b. The first opening 316a spans the cell region A1, the connection region A3, and the terminal region A2, and the second opening 316b is located in the terminal region A2. The specific method for forming the patterned first hard mask layer 316 can be the same as the method for forming the second hard mask layer 317 in step 4013, and will not be repeated here. The number of first openings 316a and second openings 316b can be one, two, or more, depending on the number of locations requiring ion implantation or etching.

[0062] Step 403: Ion implantation is performed on the current extension layer 3022 based on the first hard mask layer 316 to form a well region 303 and a first doped region 305 distributed around the well region 303. The well region 303 is located in the cell region A1, and the first doped region 305 is located in the terminal region A2.

[0063] In one embodiment, ion implantation, for example aluminum ion implantation, can be performed on the epitaxial layer 302, i.e., the current spreading layer 3022, based on the first hard mask layer 316. The implantation energy can be 80keV~500keV, and the implantation dose can be 8.0e12cm. -2 ~1.0e13cm -2 The well region 303 and the first doped region 305 are formed. The formation of the first doped region 305 and the formation of the well region 303 can be completed in the same step using a single mask, eliminating the need for hard masks for junction termination extension or field-limiting ring termination, thus significantly reducing process complexity and cost. The cross-section of the device 300 after forming the well region 303 and the first doped region 305 (without removing the first hard mask layer 316) is shown below. Figure 8 As shown. Figure 8In the process, the formed well region 303 extends from the cell region A1 to the connection region A3 and the terminal region A2. The part of the well region 303 that extends to the terminal region A2 can also be understood as the first doped region 305.

[0064] In one embodiment, after step 403, the manufacturing method 400 further includes steps 4031 and 4032:

[0065] Step 4031: A patterned third hard mask layer 318 is formed on the current spreading layer 3022. The third hard mask layer 318 has connection region openings 318a located in connection region A3. The specific method for forming the patterned third hard mask layer 318 can be the same as the method for forming the second hard mask layer 317 in step 4013, and will not be repeated here. The number of connection region openings 318a can be one, two, or more, depending on the number of locations requiring ion implantation or etching.

[0066] Step 4032: Ion implantation is performed on the current spreading layer 3022 based on the third hard mask layer 318 to form a connecting layer 311. The connecting layer 311 penetrates the entire thickness of the current spreading layer 3022 longitudinally. The connecting layer 311 is located in the connecting region A3, between the well region 303 and the first doped region 305, and adjacent to both the well region 303 and the first doped region 305. The well region 303, the first doped region 305, and the connecting layer 311 have the same doping type, but the doping concentration of the connecting layer 311 is greater than that of the well region 303 and the first doped region 305. For example, the doping concentration of the connecting layer 311 is 1e18cm. -3 -~1e20cm -3 The doping concentration of well region 303 and the first doped region 305 is 1e17cm. -3 -~1e18cm -3 .

[0067] In one embodiment, ion implantation, for example aluminum ion implantation, can be performed on the epitaxial layer 302, i.e., the current spreading layer 3022, based on the third hard mask layer 318. The implantation energy can be 100keV~1000keV, and the implantation dose can be 1.0e14cm. -2 ~1.0e15cm -2 This forms the interconnect layer 311. The cross-section of the device 300 after forming the interconnect layer 311 (without removing the third hard mask layer 318) is as follows: Figure 9 As shown, another Figure 9 In the buffer layer 3023, at least two first doped regions 305 are distributed.

[0068] Step 404: Ion implantation is performed in the well region 303 to generate the source region 304.

[0069] In one embodiment, ion implantation is performed on the well region 303 based on a corresponding hard mask layer, for example, aluminum ion implantation, with an implantation energy of 50 keV to 150 keV and an implantation dose of 5.0e14 cm⁻¹. -2 ~1.0e15cm -2 This generates source region 304. The cross-section of device 300 after generating source region 304 (without removing the corresponding hard mask layer) is shown below. Figure 10 As shown.

[0070] The substrate 301, the epitaxial layer 302 (which includes a drift layer 3021, a buffer layer 3023, and a current spreading layer 3022), and the source region 304 have a first doping type, and the well region 303 has a second doping type. In some embodiments, the first doping type is n-type doping, and the second doping type is p-type doping. In other embodiments, the first doping type is p-type doping, and the second doping type is n-type doping.

[0071] Step 405: Source region 304, well region 303, and epitaxial layer 302 are sequentially etched at the source region 304 to form a gate trench 307. A gate dielectric layer 309 is formed at the bottom and sidewalls of the gate trench 307. A gate electrode 308 is then filled into the gate trench 307 after the formation of the gate dielectric layer 309. The depth of the gate trench 307 is greater than the depth of the well region 303. It should be noted that, based on the corresponding hard mask layer, carbon tetrafluoride (CF4) or trifluoromethane (CHF3) can be used to sequentially etch the source region 304, well region 303, and epitaxial layer 302 to form a U-shaped trench, i.e., the gate trench 307. It should be further noted that the etching method can include photolithography, dry etching, wet etching, etc.

[0072] In one embodiment, a gate dielectric layer 309 is formed at the bottom and sidewalls of a gate trench 307. A method for filling the gate trench 307 with a gate electrode 308 after the formation of the gate dielectric layer 309 includes: forming a gate dielectric layer 309 covering the sidewalls and bottom wall of the gate trench 307 and the surfaces of the source regions 304 on both sides; depositing polysilicon in the remaining portion of the gate trench 307 in the middle of the gate dielectric layer 309 to form a gate electrode 308; and insulating the gate electrode 308 from the well region 303 and the source region 304 through the gate dielectric layer 309. Anisotropic etching is performed on the gate dielectric layer 309 and the gate electrode 308 on the surface of the source region 304, and planarization is performed on the gate dielectric layer 309 and the gate 211, such that the upper surface of the gate electrode 308 is lower than the upper surface of the source region 304. A gate dielectric layer 309 is then formed again on the surface of the gate electrode 308, thus achieving the covering of the gate electrode 308 by the gate dielectric layer 309.

[0073] In one embodiment, after forming the gate trench 307 in step 405 and before forming the gate dielectric layer 309, the manufacturing method 400 further includes the following steps: performing a first ion implantation inside the gate trench 307 and forming a shielding layer 310 below the gate trench 307.

[0074] In one embodiment, the shielding layer 310 is in the form of several stepped levels, such as a two-step or three-step structure. In one embodiment, a first ion implantation is performed inside the gate trench 307 to form the shielding layer 310 below the gate trench 307, including steps 4051-4053:

[0075] Step 4051: Perform the first ion implantation inside the gate trench 307 to form a first shielding layer 310a below the gate trench 307.

[0076] In one embodiment, the energy range of the first ion implantation can be 50 keV to 150 keV, and the implantation dose of the first ion implantation can be 1.0e14cm. -2 ~5e14cm -2 The first ion implantation can be, for example, aluminum ion implantation. The cross-section of the device 300 after forming the first shielding layer 310a (without removing the corresponding hard mask layer) is as follows: Figure 11 As shown.

[0077] Step 4052: Sidewalls 319 are formed on both sides of the gate trench 307. A second ion implantation is performed inside the gate trench 307 to form a second shielding layer 310b below the first shielding layer 310a. The width of the second shielding layer 310b is smaller than that of the first shielding layer 310a. The distance between the two sidewalls 319 formed on both sides of the gate trench 307 is equal to the width of the second shielding layer 310b. The energy range of the first ion implantation is different from that of the second ion implantation. The dose of the first ion implantation is the same as that of the second ion implantation.

[0078] In one embodiment, the method for forming sidewalls 319 on both sides of the gate trench 307 may include: firstly isotropically depositing an oxide layer (e.g., silicon dioxide) of a certain thickness inside the gate trench 307 and on the upper surface of the current spreading layer 3022; then anisotropically etching the gate trench 307 to remove the oxide layer on the upper surface of the current spreading layer 3022 and part of the oxide layer inside the gate trench 307, thereby forming oxide sidewalls 319 on both sides of the gate trench 307. Further, after forming the sidewalls 319 on both sides of the gate trench 307, a second ion implantation is performed inside the gate trench 307, for example, aluminum ion implantation. The energy range of the second ion implantation is 100keV~250keV, and the implantation dose is 1.0e14cm. -2 ~5e14cm -2A second shielding layer 310b is formed below the first shielding layer 310a. The width of the second shielding layer 310b is smaller than that of the first shielding layer 310a, meaning the overall shielding layer 310, including both the first and second shielding layers 310a, has a multi-level stepped shape. The stepped shielding layer 310 below the gate trench 307 in cell region A1 can suppress electric field concentration at the corners of the gate trench 307. The stepped shielding layer 310 is fabricated using a self-aligned process with the sidewalls 319 of the gate trench 307, employing two aluminum ion implantations without additional photolithography. The cross-section of the device 300 after forming the second shielding layer 310b (without removing the corresponding hard mask layer and sidewalls 319) is shown below. Figure 12 As shown.

[0079] Step 4053: Remove the sidewalls 319 of both sides of the gate trench 307 to form a gate dielectric layer 309 at the bottom and sidewalls of the gate trench 307. The gate dielectric layer 309 may include an insulating material, such as an oxide or nitride. In one embodiment, the method of forming the gate dielectric layer 309 includes filling the gate trench 307 with a dielectric material, and then using a photolithography process to remove the excess dielectric material in the gate trench 307, leaving the dielectric material as the gate dielectric layer 309.

[0080] Step 406: A dielectric layer 312 is generated at the corresponding position of the epitaxial layer 302, i.e., the current extension layer 3022. The dielectric layer 312 covers the gate trench 307 and part of the source region 304.

[0081] Step 407: A field oxide layer 313 is generated at the corresponding position of the epitaxial layer 302, i.e., the current extension layer 3022, and the field oxide layer 313 at least covers the first doped region 305.

[0082] In one embodiment, the field oxide layer 313 covers a portion of the connection layer 311 in the first doped region 305 and the connection region A3, wherein the thickness of the field oxide layer 313 is greater than the thickness of the dielectric layer 312. The dielectric layer 312 and the field oxide layer 313 may comprise insulating materials, such as oxides or nitrides, and the dielectric layer 312 and the field oxide layer 313 may be made of the same material as or different from the material of the gate dielectric layer 309 formed in step 4053.

[0083] The cross-section of device 300 after the dielectric layer 312 is formed at the corresponding position of epitaxial layer 302 is as follows: Figure 13 As shown, the cross-section of device 300 after the field oxide layer 313 is formed at the corresponding position of epitaxial layer 302 is as follows. Figure 14 As shown.

[0084] After the semiconductor layer fabrication steps are completed, a source metal layer 314 and a drain metal layer 315 are fabricated on the front and back sides of device 300, along with other back-end processes for device 300. The source metal layer 314 is located on the front side of device 300, above the epitaxial layer 302. A dielectric layer 312 is disposed below the source metal layer 314 and above the gate structure (which includes a gate trench 307, a gate dielectric layer 309, and a gate electrode 308). The dielectric layer 312 completely covers the gate structure and also covers portions of the source regions 304 on both sides of the gate structure. The completely covered gate electrode 308 can be led out through other independent contact holes, without passing through the dielectric layer 312 below the source metal layer 314. The dielectric layer 312 only covers a portion of the source region 304; the exposed area can be etched with source contact holes, allowing the source metal layer 314 to form an electrical connection with the source region 304. The complete coverage of the gate structure by the dielectric layer 312 achieves electrical isolation between the gate structure and the source metal layer 314 and the source region 304, preventing gate-source leakage. The drain metal layer 315 covers the back side of device 300 and is located on two opposite sides of substrate 301, respectively, as is the epitaxial layer 302. The drain metal layer 315 is electrically connected to substrate 301. The fabrication process of the metal layer and other back-end processes are common techniques in the art and will not be described in detail here. The cross-section of device 300 after forming the source metal layer 314 and drain metal layer 315 is shown below. Figure 15 As shown.

[0085] It should be noted that in this manufacturing method 400, the doping of the terminal region A2 (including the doping of the first doped region 305 and the second doped region 306), photolithography, dielectric, and metal processes fully utilize the cell region layout, eliminating the need for a hard mask for junction terminal expansion / field confinement rings, which can significantly reduce process complexity and cost.

[0086] It should be understood that the above steps do not necessarily have to be performed in the correct order; the order can be reversed, for example, steps 404 and 405. Step 405 can be performed first, i.e., etching the well region 303 and the epitaxial layer 302 sequentially at the well region 303 to generate the gate trench 307, and then step 404 can be performed, i.e., ion implantation is performed on the well regions 303 on both sides of the gate trench 307 to generate the source region 304. It should be understood that... Figure 4 The embodiments only illustrate some of the process steps in the fabrication of device 300, not all of them. Those skilled in the art, after understanding the essence of this invention, can add or remove process steps according to application needs, following the guidance of the embodiments of this application.

[0087] like Figure 16 The electric field distribution of a semiconductor power device 300 under avalanche breakdown state according to an embodiment of the present invention is shown. Figure 17The diagram illustrates the electric field distribution at two different interface cutoff lines on the same cross section of a semiconductor power device 300 under avalanche breakdown in its terminal region, according to an embodiment of the present invention. The AA' cutoff line represents the electric field distribution at the PN junction where the second doped region 306 and the epitaxial layer 302 meet, and the BB' cutoff line represents the electric field distribution at the junction where the field oxide layer 313 and the epitaxial layer 302 meet. The horizontal axis defines the lateral spatial coordinates of the device 300, and the vertical axis represents the electric field intensity at the corresponding location. Figure 17 As shown, the electric field amplitude at the BB' cutoff line of the field oxide interface is lower overall, and the lateral electric field gradient change is gentle, with no local high-field spikes. At the PN junction, the electric field at the AA' cutoff line is higher overall, and multiple electric field spikes are effectively suppressed. This scheme optimizes the electric field morphology in the terminal region, avoiding premature avalanche breakdown induced by concentrated electric field at the PN junction and alleviating the long-term high electric field load on the field oxide layer 313, significantly improving the device's breakdown voltage and operational reliability.

[0088] As described above, these embodiments of the present application do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the present application, thereby enabling those skilled in the art to make good use of the present application and modifications based on it. The present application is limited only by the claims and their full scope and equivalents.

Claims

1. A semiconductor power device, characterized in that, include: A substrate having a first surface and a second surface disposed opposite to each other; An epitaxial layer is disposed on the first surface of the substrate; The cell region includes a well region that extends from the upper surface of the epitaxial layer into the interior of the epitaxial layer. The terminal region is located on the periphery of the cell region. The terminal region includes a first doped region extending from the upper surface of the epitaxial layer into the interior of the epitaxial layer. The doping concentration of the first doped region is the same as the doping concentration of the well region, and the depth of the first doped region in the epitaxial layer is the same as the depth of the well region in the epitaxial layer.

2. The semiconductor power device as described in claim 1, characterized in that, The epitaxial layer includes: A drift layer is disposed on the first surface of the substrate; A buffer layer is disposed above the drift layer; A current spreading layer is disposed above the buffer layer, and the first doped region is located in the current spreading layer.

3. The semiconductor power device as described in claim 2, characterized in that, The buffer layer has a plurality of buffer units distributed laterally, extending from the upper surface of the buffer layer into the interior of the buffer layer. The buffer unit includes extended buffer units and non-extended buffer units located around the extended buffer units. The extended buffer units extend from the cell region to the terminal region, and the terminal region includes the non-extended buffer units in addition to the extended buffer units.

4. The semiconductor power device as described in claim 3, characterized in that, Both the extended buffer unit and the non-extended buffer unit extend longitudinally through the entire thickness of the buffer layer.

5. The semiconductor power device as described in claim 2, characterized in that, The current spreading layer, the buffer layer, and the drift layer have the same doping type, wherein the doping concentration of the buffer layer is greater than that of the drift layer, and the doping concentration of the current spreading layer is greater than that of the buffer layer.

6. The semiconductor power device as described in claim 1, characterized in that, The cell region also includes: A gate trench, located between adjacent well regions, extends from the upper surface of the epitaxial layer into the interior of the epitaxial layer, wherein the depth of the gate trench is greater than the depth of the well region; The gate electrode is located in the gate trench; and A gate dielectric layer is filled in the gate trench to isolate the gate electrode from the gate trench.

7. The semiconductor power device as described in claim 6, characterized in that, The cell region also includes a shielding layer located at the bottom of the gate trench, and the gate electrode is isolated from the shielding layer by the gate dielectric layer.

8. The semiconductor power device as described in claim 7, characterized in that, The shielding layer is arranged in a multi-level stepped pattern.

9. The semiconductor power device as described in claim 7, characterized in that, The shielding layer includes a first shielding layer and a second shielding layer. The first shielding layer is located below the gate trench, and the gate electrode is isolated from the first shielding layer through the gate dielectric layer. The second shielding layer is located below the first shielding layer. The width of the second shielding layer is smaller than that of the first shielding layer, and the width of the first shielding layer is not greater than the width of the gate trench.

10. The semiconductor power device as claimed in claim 2, characterized in that, It also includes a connection region located between the cell region and the terminal region. The connection region includes a connection layer located between the well region and the first doped region, extending from the upper surface of the current spreading layer into the interior of the current spreading layer. The well region, the first doped region, and the connection layer have the same doping type, and the doping concentration of the connection layer is greater than that of the well region and the first doped region.

11. The semiconductor power device as claimed in claim 1, characterized in that, The terminal region further includes a field oxide layer that covers the first doped region.

12. A method for manufacturing a semiconductor power device, comprising: A substrate is provided on which an epitaxial layer is grown, wherein cellular regions and terminal regions are distributed in the epitaxial layer; A patterned first hard mask layer is formed on the epitaxial layer. The first hard mask layer has a first opening and a second opening. The first opening spans the cell region and the terminal region, and the second opening is located in the terminal region. Ion implantation is performed on the epitaxial layer based on the first hard mask layer to form a well region and a first doped region distributed around the well region. The well region is located in the cell region, and the first doped region is located in the terminal region. Ion implantation is performed in the well region to form a source region; The source region, the well region, and the epitaxial layer are etched sequentially at the source region to form a gate trench. A gate dielectric layer is formed at the bottom and sidewalls of the gate trench. A gate electrode is filled in the gate trench after the gate dielectric layer is formed. The depth of the gate trench is greater than the depth of the well region. A dielectric layer is generated at a corresponding location on the epitaxial layer, the dielectric layer covering the gate trench and a portion of the source region; A field oxide layer is formed at a corresponding location in the epitaxial layer, the field oxide layer at least covering the first doped region.

13. The method for manufacturing a semiconductor power device as described in claim 12, characterized in that, The step of growing an epitaxial layer on the substrate includes: A drift layer is formed on the substrate; Ion implantation is performed on the drift layer to form a buffer layer on the drift layer; A patterned second hard mask layer is formed on the buffer layer. The second hard mask layer has a third opening and a fourth opening. The third opening spans the cell region and the terminal region, and the fourth opening is located in the terminal region. Ion implantation is performed on the buffer layer based on the second hard mask layer to form extended buffer units and non-extended buffer units distributed around the extended buffer units. The extended buffer units extend from the cell region to the terminal region, and the terminal region includes the non-extended buffer units in addition to the extended buffer units. Remove the second hard mask layer and grow a current spreading layer on the buffer layer. The epitaxial layer includes the drift layer, the buffer layer, and the current spreading layer. The current spreading layer, the buffer layer, and the drift layer have the same doping type. The doping concentration of the buffer layer is greater than that of the drift layer, and the doping concentration of the current spreading layer is greater than that of the buffer layer.

14. The method for manufacturing a semiconductor power device as described in claim 12, characterized in that, After forming the gate trench and before forming the gate dielectric layer, the method further includes: The first ion implantation is performed inside the gate trench to form a shielding layer below the gate trench.

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