Semiconductor device and electronic apparatus

Abstract

The disclosure provides a semiconductor device and an electronic device, relates to the technical field of semiconductor, and aims to improve the gate oxide reliability of the semiconductor device. The semiconductor device comprises a drift layer, a collector structure, two emitter structures, a gate, a gate dielectric layer and a gate protection doping structure; the collector structure is arranged on one side of the drift layer; the two emitter structures are arranged at intervals and embedded in the surface of the drift layer away from the collector structure; the drift layer comprises a first part between the two emitter structures; the gate is arranged on the side of the first part away from the collector structure; the gate dielectric layer is arranged between the gate and the first part; the gate protection doping structure is embedded in the surface of the first part away from the collector structure and comprises a first doping layer and a second doping layer, at least part of the first doping layer is located on the side of the second doping layer away from the gate dielectric layer and is opposite to the doping type of the drift layer, and the doping type of the second doping layer is opposite to that of the first doping layer; the semiconductor device is applied to the electronic device.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a semiconductor device and electronic device. Background Technology

[0002] Insulated Gate Bipolar Transistor (IGBT) is a composite power semiconductor device that combines the advantages of high input impedance of Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and low on-state voltage drop of Bipolar Junction Transistor (BJT). It is widely used in power electronic systems, such as new energy power generation converters, electric vehicle drive modules, and industrial motor controllers.

[0003] Currently, increasing the width of the junction field-effect transistor (JFET) region in IGBT devices reduces the on-state voltage drop. However, this leads to an increase in the electric field at the gate dielectric layer, affecting the gate oxide reliability of the IGBT device. Summary of the Invention

[0004] Embodiments of this disclosure provide a semiconductor device and an electronic device designed to improve the gate oxide reliability of the semiconductor device.

[0005] To achieve the above objectives, the embodiments of this disclosure adopt the following technical solutions: On one hand, a semiconductor device is provided. The semiconductor device includes a drift layer, a collector structure, two emitter structures, a gate, a gate dielectric layer, and a gate protection doped structure. The collector structure is disposed on one side of the drift layer. The two emitter structures are spaced apart along a first direction and respectively embedded in the surface of the drift layer on the side away from the collector structure; the drift layer includes a first portion located between the two emitter structures. The gate is disposed on the side of the first portion of the drift layer away from the collector structure; the gate overlaps with the two emitter structures along a second direction; the second direction is perpendicular to the surface of the drift layer away from the collector structure. Along the second direction, the gate dielectric layer is disposed between the gate and the first portion of the drift layer, and between the gate and the two emitter structures. The gate protection doped structure is embedded in the surface of the first portion of the drift layer on the side away from the collector structure; the gate protection doped structure includes a first doped layer and a second doped layer; at least a portion of the first doped layer is located on the side of the second doped layer away from the gate dielectric layer, and has a doping type opposite to that of the drift layer; the second doped layer has a doping type opposite to that of the first doped layer. For example, the first doped layer is P-type and the second doped layer is N-type.

[0006] In this configuration, by incorporating a first doped layer with a doping type opposite to that of the drift layer, a PN junction can be formed between the first doped layer and the drift layer. When the semiconductor device is in a breakdown state, the depletion region generated within the first doped layer pushes the high electric field originally located at the interface with the gate dielectric layer away from the gate dielectric layer, thereby reducing the peak electric field at the interface between the gate dielectric layer and the first portion. This alleviates the electric field stress on the gate dielectric layer and improves the gate oxide reliability of the semiconductor device. Simultaneously, by positioning at least a portion of the first doped layer on the side of the second doped layer away from the gate dielectric layer, and by incorporating a doping type opposite to that of the first doped layer, the second doped layer can reduce the contact area between the first doped layer and the gate dielectric layer when the semiconductor device is in the on-state or off-state. This significantly reduces the path for holes to be injected into the gate dielectric layer, improving gate oxide reliability. Furthermore, it can reduce the charging of the gate capacitance by holes when the device is on, thereby improving gate control capability.

[0007] In some embodiments, the first doped layer includes a first portion, a second portion, and a third portion connected in sequence, wherein the first portion and the third portion are located on opposite sides of the second doped layer along the first direction, and the second portion is located on the side of the second doped layer away from the gate dielectric layer.

[0008] In some embodiments, the second doped layer includes a plurality of first sub-regions spaced apart along the first direction; portions of the first doped layer are located between two adjacent first sub-regions.

[0009] In some embodiments, the first doped layer is stacked on the side of the second doped layer away from the gate dielectric layer.

[0010] In some embodiments, the first doped layer includes a plurality of second sub-sections spaced apart along the first direction; portions of the drift layer are located between two adjacent second sub-sections.

[0011] In some embodiments, the number of gate protection doped structures is multiple, and the multiple gate protection doped structures are spaced apart along the first direction.

[0012] In some embodiments, the semiconductor device further includes two first carrier storage layers, which are respectively disposed between the two emitter structures and the drift layer; the first carrier storage layers and the drift layer have the same doping type, and the doping concentration of the first carrier storage layers is greater than that of the drift layer.

[0013] In some embodiments, the semiconductor device further includes a second carrier storage layer disposed between the gate protection doped structure and the drift layer; the second carrier storage layer has the same doping type as the drift layer, and the doping concentration of the second carrier storage layer is greater than that of the drift layer.

[0014] In some embodiments, the semiconductor device further includes a third doped layer disposed between at least one of the two first carrier storage layers and the drift layer; the third doped layer has a doping type opposite to that of the first carrier storage layers.

[0015] In some embodiments, the semiconductor device further includes a fourth doped layer disposed between the second carrier storage layer and the drift layer; the fourth doped layer has a doping type opposite to that of the second carrier storage layer.

[0016] In some embodiments, the gate includes two sub-gates spaced apart along the first direction; one of the sub-gates overlaps with one of the emitter structures along the second direction.

[0017] In some embodiments, the two sub-gates overlap with the gate protection doped structure along the second direction.

[0018] In some embodiments, the emitter structure includes a first well region and a doped portion, the doped portion being embedded in the surface of the first well region on the side away from the drift layer; the first well region has a doping type opposite to that of the drift layer; the doped portion includes a first doped portion and a second doped portion with opposite doping types, the second doped portion being located on the side of the first doped portion away from the gate; the first doped portion has a doping type opposite to that of the first well region.

[0019] In some embodiments, the semiconductor device further includes an interlayer dielectric layer, an emitter, and a collector. The interlayer dielectric layer covers the gate. The emitter covers the interlayer dielectric layer, and its two ends are respectively in contact with the two emitter structures. The collector is disposed on the side of the collector structure away from the drift layer and is in contact with the collector structure.

[0020] On the other hand, an electronic device is provided, the electronic device including a circuit board and a semiconductor device as described in the preceding aspect disposed on one side of the circuit board.

[0021] It is understood that the beneficial effects that the electronic devices provided in the above embodiments of this disclosure can achieve can be referred to the beneficial effects of the semiconductor structure described above, and will not be repeated here. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below.

[0023] Figure 1 This is a structural block diagram of an electronic device according to some embodiments; Figure 2 This is one of the structural diagrams of a semiconductor device according to some embodiments; Figure 3 This is a graph showing the relationship between the width of the first part of the related technology and the on-state voltage drop and the electric field of the gate dielectric layer. Figure 4 This is a second structural diagram of a semiconductor device according to some embodiments; Figure 5 This is the third structural diagram of a semiconductor device according to some embodiments; Figure 6 This is the fourth structural diagram of a semiconductor device according to some embodiments; Figure 7 This is the fifth structural diagram of a semiconductor device according to some embodiments; Figure 8 This is the sixth structural diagram of a semiconductor device according to some embodiments; Figure 9 This is the seventh structural diagram of a semiconductor device according to some embodiments; Figure 10 This is the eighth structural diagram of a semiconductor device according to some embodiments; Figure 11 This is the ninth structural diagram of a semiconductor device according to some embodiments; Figure 12 This is the tenth structural diagram of a semiconductor device according to some embodiments. Detailed Implementation

[0024] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0025] In the description of this disclosure, it should be understood that the terms “center,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0026] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0027] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0028] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0029] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0030] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0031] The technical terms used in the embodiments of this application are explained below: Semiconductor: A semiconductor is a material whose conductivity at room temperature is between that of a conductor and an insulator; semiconductors include intrinsic semiconductors and impurity semiconductors. A pure semiconductor without impurities or defects, in which the concentration of electrons and holes is equal, is called an intrinsic semiconductor. A semiconductor doped with a certain amount of impurities is called an impurity semiconductor or an intrinsic semiconductor. When the impurities doped into an impurity semiconductor can provide a certain concentration of charge carriers (such as holes or electrons), the conductivity of the intrinsic semiconductor can be improved. Generally, the higher the charge carrier concentration, the lower the resistivity of the semiconductor and the better the conductivity. In the embodiments of this application, this type of impurity semiconductor is also called a conductive semiconductor, for example, conductive silicon carbide material doped with nitrogen (N), boron (B), aluminum (Al), etc. Furthermore, when impurities doped into an impurity semiconductor can compensate for impurities, the donor electrons are just enough to fill the acceptor level, but cannot provide electrons and holes to the conduction and valence bands, resulting in a semiconductor material with a wide bandgap having a resistivity similar to that of an insulator. For example, in the embodiments of this application, doping silicon carbide with transition metals achieves impurity compensation, thereby increasing the resistivity of the silicon carbide material. This type of impurity semiconductor is also called a semi-insulating semiconductor or a semi-insulator, or has semi-insulating characteristics.

[0032] like Figure 1As shown, some embodiments of this disclosure provide an electronic device 1000. This electronic device 1000 can be applied to scenarios such as power grids, high-voltage photovoltaic systems, automobiles, and high-speed rail. The embodiments of this disclosure do not specifically limit the application scenarios of this electronic device.

[0033] The electronic device 1000 can be a power electronic device, that is, a device whose main functional components are power electronic devices (also known as power semiconductor devices). For example, the electronic device 1000 can be a converter, electronic switch, electronic AC power controller, power factor correction (PFC) circuit, etc. The converter includes, but is not limited to, DC-DC choppers, AC-DC rectifiers, and DC-AC inverters, etc., and the electronic switch includes, but is not limited to, power switching power supply circuits, etc.

[0034] Please continue reading. Figure 1 The electronic device 1000 includes a semiconductor device 100 and a circuit board 200. The semiconductor device 100 is disposed on one side of the circuit board 200 and electrically connected to the circuit board 200. The circuit board 200 is used to provide the semiconductor device 100 with the required electrical signals. For example, the circuit board 200 may include multiple conductive layers. The multiple conductive layers within the circuit board 200 can be separated from each other by dielectric layers.

[0035] It is understood that the structure illustrated in the embodiments of this disclosure does not constitute a specific limitation on the electronic device 1000.

[0036] In other embodiments of this disclosure, the electronic device 1000 may include more components than those illustrated, or combine some components, or split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0037] In some embodiments, such as Figure 2As shown, some embodiments of this disclosure also provide a semiconductor device 100. This semiconductor device can be applied in the aforementioned electronic device 1000. Optionally, the semiconductor device 100 provided in the embodiments of this disclosure can be used as a semiconductor device in the aforementioned electronic device 1000. Of course, the specific application scenarios of the aforementioned semiconductor device 100 are not limited thereto. It is understood that any electronic device that requires the use of the semiconductor device 100 falls within the application scenarios of the embodiments of this disclosure. Alternatively, the semiconductor device 100 provided in the embodiments of this disclosure can be used alone.

[0038] In some embodiments, such as Figure 2 As shown, the semiconductor device 100 includes a drift layer 10, a collector structure 20, two emitter structures 30, a gate 50, and a gate dielectric layer 40. The collector structure 20 is disposed on one side of the drift layer 10. The two emitter structures 30 are spaced apart along a first direction X and are respectively embedded in the surface of the drift layer 10 away from the collector structure 20. The drift layer 10 includes a first portion 11 located between the two emitter structures 30. The gate 50 is disposed on the first portion 11 of the drift layer 10 away from the collector structure 20. The gate 50 overlaps with the two emitter structures 30 along a second direction Z, which is perpendicular to the surface of the drift layer 10 away from the collector structure 20. Along the second direction Z, the gate dielectric layer 40 is disposed between the gate 50 and the first portion 11 of the drift layer 10, and between the gate 50 and the two emitter structures 30.

[0039] It is understood that when the two emitting structures 30 are embedded in the surface of the drift layer 10 on the side away from the collector structure 20, it means that the two emitting structures 30 are embedded in a portion of the surface of the drift layer 10, rather than completely covering the surface of the drift layer 10. The embedding in the following text can be understood in a similar way, and will not be elaborated further.

[0040] In some examples, such as Figure 2 As shown, the emitter structure 30 includes a first well region 31, which has the opposite doping type to the drift layer 10. For example, the drift layer 10 is doped with N-type, and the first well region 31 is doped with P-type. In this case, the first portion 11 in the drift layer 10 located between the two emitter structures 30 can serve as a carrier transport channel between the collector structure 20 and the emitter structure 30.

[0041] Understandably, when the semiconductor device 100 is in the ON state, the gate 50 is connected to a positive potential, the emitter structure 30 is connected to zero potential, and the collector structure 20 is connected to a positive potential. Holes move from the collector structure 20 through the first part 11 to the emitter structure 30 under the influence of the electric field. When the semiconductor device 100 is in the OFF state, the gate 50 changes from a positive potential to a zero potential or a negative potential, the emitter structure 30 is connected to zero potential, and the collector structure 20 is connected to a positive potential. The remaining holes in the drift layer 10 continue to move through the first part 11 to the emitter structure 30 under the influence of the electric field. When the semiconductor device 100 is in the OFF state, the gate 50 is connected to a zero potential or a negative potential, the emitter structure 30 is connected to zero potential, and the collector structure 20 is connected to a positive potential. At this time, the PN junction formed by the drift layer 10 and the first well region 31 is fully reverse biased, and the first part 11 forms a stable charge depletion region with no continuous carrier transport inside. The longitudinal withstand voltage is borne by the depletion region, achieving stable high-voltage blocking.

[0042] It should be noted that the doping type of the drift layer 10 can also be P-type, and this disclosure does not specifically limit this. The following uses an N-type doping type for the drift layer 10 as an example to illustrate some embodiments of this disclosure.

[0043] In related technologies, such as Figure 3 As shown, by increasing the width of the first portion along the first direction, the extraction of holes by the first well region can be reduced, enhancing the conductivity modulation effect in the drift layer, thereby reducing the on-state voltage drop of the semiconductor device. However, under the withstand voltage condition, due to the increased width of the first portion along the first direction, the depletion regions of the first well regions on both sides cannot completely cover the first portion, resulting in undepleted regions remaining in the first portion. The electric field tends to concentrate at the interface between the gate dielectric layer and the first portion, causing an increase in the electric field at the gate dielectric layer and reducing the gate oxide reliability of the semiconductor device.

[0044] Based on this, such as Figure 2 As shown, the semiconductor device 100 provided in this disclosure further includes a gate protection doped structure 60, which is embedded in the surface of the first portion 11 of the drift layer 10 on the side away from the collector structure 20. The gate protection doped structure 60 includes a first doped layer 61 and a second doped layer 62. At least a portion of the first doped layer 61 is located on the side of the second doped layer 62 away from the gate dielectric layer 40 and has a doping type opposite to that of the drift layer 10. The second doped layer 62 has a doping type opposite to that of the first doped layer 61. For example, the first doped layer 61 has a P-type doping type, and the second doped layer has an N-type doping type.

[0045] In this configuration, by providing a first doped layer 61 with a doping type opposite to that of the drift layer 10, a PN junction can be formed between the first doped layer 61 and the drift layer 10. When the semiconductor device 100 is in a breakdown voltage state, the depletion region generated inside the first doped layer 61 will push the high electric field originally located at the interface with the gate dielectric layer 40 away from the gate dielectric layer 40, thereby reducing the peak electric field at the interface between the gate dielectric layer 40 and the first portion 11, thus alleviating the electric field stress borne by the gate dielectric layer 40 and improving the gate oxide reliability of the semiconductor device 100. Simultaneously, by providing at least a portion of the first doped layer 61 located on the side of the second doped layer 62 away from the gate dielectric layer 40, and by providing a second doped layer 62 with a doping type opposite to that of the first doped layer 61, when the semiconductor device 100 is in a conduction state or a turn-off process, the second doped layer 62 can reduce the contact area between the first doped layer 61 and the gate dielectric layer 40, thereby significantly reducing the path for holes to be injected into the gate dielectric layer 40 and improving gate oxide reliability. At the same time, it can also reduce the charging of the gate capacitance by holes when the device is turned on, thereby improving the gate control capability.

[0046] In some examples, such as Figure 2 and Figure 4 As shown, the first doped layer 61 includes a first portion, a second portion, and a third portion connected in sequence. The first portion and the third portion are located on opposite sides of the second doped layer 62 along the first direction X, and the second portion is located on the side of the second doped layer 62 away from the gate dielectric layer 40. In other words, the first doped layer 61 surrounds the surfaces of the second doped layer 62 on opposite sides along the first direction X and the surface away from the gate dielectric layer 40.

[0047] At this time, when the semiconductor device 100 is in a withstand voltage state, the second doped layer 62 can generate a depletion region extension along the first direction X with the first and third portions, and also generate a depletion region extension along the second direction Y with the second portion, where the second direction is the thickness direction of the semiconductor device 100. In other words, the second doped layer 62 can generate depletion region extensions in multiple directions with the first doped layer 61, achieving multi-directional electric field modulation of the first portion 11, significantly reducing the electric field stress borne by the gate dielectric layer 40, and improving the gate oxide reliability of the semiconductor device 100.

[0048] For example, such as Figure 2 As shown, the second doped layer 62 includes a first sub-section 621 extending along the first direction X. When the semiconductor device 100 is in the on-state or off-state, the first sub-section 621 can form a complete electron barrier layer below the gate dielectric layer 40, significantly suppressing hole injection into the gate dielectric layer 40, reducing hole charging of the gate capacitance, and improving gate oxide reliability and gate control capability. It also features a simple fabrication process.

[0049] For example, such as Figure 4 As shown, the second doped layer 62 includes a plurality of first sub-sections 621 spaced apart along the first direction X, with portions of the first doped layer 61 located between two adjacent first sub-sections 621. When the semiconductor device 100 is in a breakdown voltage state, each first sub-section 621 can generate depletion region expansion in multiple directions with the first doped layer 61, thereby further achieving multi-directional electric field modulation of the first portion 11, significantly reducing the electric field stress borne by the gate dielectric layer 40, and improving the gate oxide reliability of the semiconductor device 100.

[0050] In other examples, such as Figure 5 and Figure 6 As shown, the first doped layer 61 is stacked on the side of the second doped layer 62 away from the gate dielectric layer 40. In other words, the first doped layer 61 has no surface in contact with the gate dielectric layer 40. At this time, the second doped layer 62 completely separates the first doped layer 61 from the gate dielectric layer 40. That is, when the semiconductor device 100 is in the on-state or in the off-state, the electron barrier layer formed by the second doped layer 62 can significantly suppress the injection of holes into the gate dielectric layer 40, reduce the charging of the gate capacitance by holes, and improve the gate oxide reliability and gate control capability.

[0051] For example, such as Figure 5 As shown, the first doped layer 61 includes a second sub-section 611 extending along the first direction X. When the semiconductor device 100 is in the on-state or in the off-state, the electron barrier layer formed by the second doped layer 62 can significantly suppress the injection of holes into the gate dielectric layer 40, reduce the charging of the gate capacitance by holes, and improve the gate oxide reliability and gate control capability. At the same time, it also has the advantage of simple fabrication process.

[0052] For example, such as Figure 6 As shown, the first doped layer 61 includes a plurality of second sub-sections 611 spaced apart along the first direction X, with a portion of the drift layer 10 located between two adjacent second sub-sections 611. When the semiconductor device 100 is in a breakdown voltage state, each second sub-section 611 can form depletion diffusion in multiple directions with the drift layer 10, thereby further modulating the electric field of the first sub-section 11 in multiple directions, significantly reducing the electric field stress on the gate dielectric layer 40, and improving the gate oxide reliability of the semiconductor device 100. Simultaneously, when the semiconductor device 100 is in a conduction state or a turn-off process, the electron barrier layer formed by the second doped layer 62 can significantly suppress hole injection into the gate dielectric layer 40, reduce hole charging of the gate capacitance, and improve gate oxide reliability and gate control capability.

[0053] In some other examples, such as Figure 7As shown, there are multiple gate protection doped structures 60, which are spaced apart along the first direction X. When the semiconductor device 100 is in a withstand voltage state, the first doped layer 61 in each gate protection doped structure 60 can form depletion diffusion in multiple directions with the drift layer 10, thereby further modulating the electric field of the first portion 11 in multiple directions, significantly reducing the electric field stress on the gate dielectric layer 40, and improving the gate oxide reliability of the semiconductor device 100. Simultaneously, when the semiconductor device 100 is in a conduction state or a turn-off process, the electron barrier layer formed by the second doped layer 62 in each gate protection doped structure 60 can significantly suppress hole injection into the gate dielectric layer 40, reduce hole charging of the gate capacitance, and improve gate oxide reliability and gate control capability.

[0054] In some embodiments, such as Figure 2 , Figures 4-7 As shown, the semiconductor device 100 further includes two first carrier storage layers 71, which are respectively disposed between the two emitter structures 30 and the drift layer 10. The first carrier storage layers 71 and the drift layer 10 have the same doping type, and the doping concentration of the first carrier storage layers 71 is greater than that of the drift layer 10. For example, the doping type of the first carrier storage layers 71 is N-type. At this time, when the semiconductor device 100 is in the on-state, the holes injected by the collector structure 20 are partially blocked by the first carrier storage layers 71 after diffusing in the drift layer 10, forming local hole accumulation, thereby increasing the carrier concentration in the drift layer 10 and reducing the on-state voltage drop of the semiconductor device 100. In addition, compared with related technologies, since setting the gate protection doping structure 60 can reduce the electric field at the junction of the gate dielectric layer 40 and the first portion 11, the doping concentration of the first carrier storage layer 71 can be higher under the same voltage, thereby further enhancing the carrier storage effect, reducing the on-state voltage drop of the semiconductor device 100, and improving the switching performance of the semiconductor device 100.

[0055] In some embodiments, such as Figure 8 and Figure 9As shown, the semiconductor device 100 further includes a second carrier storage layer 72, which is disposed between the gate protection doped structure 60 and the drift layer 10. The second carrier storage layer 72 has the same doping type as the drift layer 10, and the doping concentration of the second carrier storage layer 72 is greater than that of the drift layer 10. In this case, when the semiconductor device 100 is in the on-state or off-state, the second carrier storage layer 72 can further suppress hole injection into the gate protection doped structure 60, thereby forming local hole accumulation on one side of the gate protection doped structure 60, further increasing the carrier concentration in the drift layer 10, and significantly reducing the on-state voltage drop of the semiconductor device 100. Furthermore, it can also reduce hole charging of the gate capacitance when the device is on, thereby improving gate control capability.

[0056] In some examples, such as Figure 8 As shown, the two ends of the second carrier storage layer 72 are respectively connected to the two first carrier storage layers 71, that is, the two first carrier storage layers 71 and the second carrier storage layer 72 are an integral structure with the same doping concentration. In this way, the two first carrier storage layers 71 and the second carrier storage layer 72 are prepared simultaneously, which reduces the difficulty of the preparation process and improves the production efficiency.

[0057] In other examples, such as Figure 9 As shown, the second carrier storage layer 72 is spaced apart from the two first carrier storage layers 71, and a portion of the drift layer 10 is located between the adjacent second carrier storage layer 72 and the first carrier storage layer 71.

[0058] In some embodiments, such as Figure 10 As shown, the semiconductor device 100 further includes a third doped layer 63, which is disposed between at least one of the two first carrier storage layers 71 and the drift layer 10. The doping type of the third doped layer 63 is opposite to that of the first carrier storage layers 71. For example, the doping type of the third doped layer 63 is P-type. In this case, the third doped layer 63 can form a reverse-biased PN junction with the first carrier storage layer 71. When the semiconductor device 100 is in a breakdown voltage state, the depletion region generated by the third doped layer 63 and the first carrier storage layer 71 can reduce the electric field peak at the bottom of the first carrier storage layer 71 and alleviate the electric field concentration problem at the bottom of the first carrier storage layer 71. This allows for an increase in the doping concentration of the first carrier storage layer 71, thereby enhancing the carrier storage effect and reducing the on-state voltage drop of the semiconductor device 100.

[0059] In some examples, such as Figure 10As shown, the semiconductor device 100 includes two third doped layers 63, which are respectively disposed between the two first carrier storage layers 71 and the drift layer 10. In this case, the two third doped layers 63 can form reverse-biased PN junctions with their respective first carrier storage layers 71. When the semiconductor device 100 is in a breakdown voltage state, the depletion regions generated by the two third doped layers 63 and the first carrier storage layers 71 can respectively reduce the electric field peak at the bottom of the corresponding first carrier storage layers 71, alleviating the electric field concentration problem. This allows for an increase in the doping concentration of the first carrier storage layers 71, thereby enhancing the carrier storage effect and reducing the on-state voltage drop of the semiconductor device 100.

[0060] In some embodiments, such as Figure 11 As shown, the semiconductor device 100 further includes a fourth doped layer 64, which is disposed between the second carrier storage layer 72 and the drift layer 10. The fourth doped layer 64 has the opposite doping type to the second carrier storage layer 72. For example, the fourth doped layer 64 is P-type. In this case, the third doped layer 63 can form a reverse-biased PN junction with the second carrier storage layer 72. When the semiconductor device 100 is in a breakdown voltage state, the depletion region generated by the fourth doped layer 64 and the second carrier storage layer 72 can reduce the electric field peak at the bottom of the second carrier storage layer 72 and alleviate the electric field concentration problem at the bottom of the second carrier storage layer 72. This allows for an increase in the doping concentration of the second carrier storage layer 72, thereby enhancing the carrier storage effect and reducing the on-state voltage drop of the semiconductor device 100.

[0061] In some embodiments, such as Figure 12 As shown, the emitter structure 30 also includes a doped portion 32, which is embedded in the surface of the first well region 31 on the side away from the drift layer 10. The doped portion 32 includes a first doped portion 321 and a second doped portion 322 with opposite doping types. The second doped portion 322 is located on the side of the first doped portion 321 away from the gate 50, and the first doped portion 321 has a doping type opposite to that of the first well region 31. The gate 50 includes two sub-gates 51 spaced apart along a first direction X, and one sub-gate 51 overlaps with an emitter structure 30 along a second direction Z. This reduces the area of ​​the gate 50, thereby reducing the gate capacitance and improving the switching characteristics of the semiconductor device 100.

[0062] In some examples, such as Figure 12As shown, the two sub-gates 51 overlap with the gate protection doped structure 60 along the second direction Z. In other words, one sub-gate 51 overlaps with the gate protection doped structure 60 along the second direction Z at one end closer to the other sub-gate 51. Thus, when the semiconductor device 100 is in a breakdown voltage state, the first doped layer 61 forming a reverse PN junction with the drift layer 10 can reduce the peak electric field of the gate dielectric layer 40 below the sub-gate 51, reduce the electric field stress of the gate dielectric layer 40, and extend the lifetime of the gate dielectric layer 40. When the semiconductor device 100 is in the on-state or off-state, the second doped layer 62 can reduce the contact area between the first doped layer 61 and the gate dielectric layer 40, thereby significantly reducing the path for holes to be injected into the gate dielectric layer 40 below the sub-gate 51 and improving gate oxide reliability. Simultaneously, it can also reduce the charging of the gate capacitance by holes when the device is on, thereby improving gate control capability.

[0063] In some embodiments, such as Figure 2 , Figures 4-12 As shown, the semiconductor device 100 further includes an interlayer dielectric layer 80, an emitter 91, and a collector 92. The interlayer dielectric layer 80 covers the gate 50, and the emitter 91 covers the interlayer dielectric layer 80, with both ends of the emitter 91 contacting the two emitter structures 30 respectively. The collector 92 is disposed on the side of the collector structure 20 away from the drift layer 10 and is in contact with the collector structure 20. The emitter 91 provides a signal transmission path for the emitter structure 30, and the collector 92 provides a signal transmission path for the collector structure 20. The interlayer dielectric layer 80 provides electrical insulation between the emitter 91 and the gate 50, preventing a short circuit between them.

[0064] In some examples, the interlayer dielectric layer 80 and the gate dielectric layer 40 surround and enclose the gate 50. The material of the interlayer dielectric layer 80 is the same as the material of the gate dielectric layer 40. For example, the materials of the interlayer dielectric layer 80 and / or the gate dielectric layer 40 include any one or a combination of silicon oxide, hafnium oxide, aluminum oxide, and silicon nitride.

[0065] Please continue reading. Figure 2 , Figures 4-12The semiconductor device 100 may further include a buffer layer 12 disposed between the drift layer 10 and the collector structure 20. The doping type of the buffer layer 12 is the same as that of the drift layer 10, and the doping concentration of the buffer layer 12 is greater than that of the drift layer 10. In this case, when the semiconductor device 100 is in a breakdown voltage state, the buffer layer 12 can prevent the depletion region in the drift layer 10 from transitioning to the collector structure 20, smoothing the electric field peak distribution of the drift layer 10 and improving the breakdown voltage performance of the semiconductor device 100. When the semiconductor device 100 is in a turn-off process, the buffer layer 12 can form an electron barrier layer to limit the hole injection amount in the collector structure 20, thereby reducing the turn-off loss of the semiconductor device 100.

[0066] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A semiconductor device, characterized in that, include: Drift layer; A current collector structure is disposed on one side of the drift layer; Two emitting structures are spaced apart along a first direction and are respectively embedded in the surface of the drift layer on the side away from the current collector structure; the drift layer includes a first portion located between the two emitting structures; A gate is disposed on the side of the first portion of the drift layer away from the collector structure; the gate overlaps with the two emitter structures along a second direction; the second direction is perpendicular to the surface of the drift layer away from the collector structure; Gate dielectric layer; Along the second direction, the gate dielectric layer is disposed between the gate and the first portion of the drift layer, and between the gate and the two emitter structures; A gate protection doped structure, with the first portion of the drift layer embedded on the surface of the side away from the collector structure; The gate protection doped structure includes a first doped layer and a second doped layer; at least a portion of the first doped layer is located on the side of the second doped layer away from the gate dielectric layer and is of the opposite doping type to the drift layer; the second doped layer is of the opposite doping type to the first doped layer; along the second direction, at least a portion of the second doped layer is located between the first doped layer and the gate dielectric layer.

2. The semiconductor device according to claim 1, characterized in that, The first doped layer includes a first part, a second part, and a third part connected in sequence. The first part and the third part are located on opposite sides of the second doped layer along the first direction, and the second part is located on the side of the second doped layer away from the gate dielectric layer.

3. The semiconductor device according to claim 2, characterized in that, The second doped layer includes a plurality of first sub-sections spaced apart along the first direction; portions of the first doped layer are located between two adjacent first sub-sections.

4. The semiconductor device according to claim 1, characterized in that, The first doped layer is stacked on the side of the second doped layer away from the gate dielectric layer.

5. The semiconductor device according to claim 4, characterized in that, The first doped layer includes a plurality of second sub-sections spaced apart along the first direction; portions of the drift layer are located between two adjacent second sub-sections.

6. The semiconductor device according to any one of claims 1-5, characterized in that, The number of gate protection doped structures is multiple, and the multiple gate protection doped structures are spaced apart along the first direction.

7. The semiconductor device according to claim 1, characterized in that, Also includes: Two first carrier storage layers are respectively disposed between the two emitter structures and the drift layer; the first carrier storage layers and the drift layer have the same doping type, and the doping concentration of the first carrier storage layers is greater than that of the drift layer.

8. The semiconductor device according to claim 7, characterized in that, Also includes: A second carrier storage layer is disposed between the gate protection doped structure and the drift layer; the second carrier storage layer has the same doping type as the drift layer, and the doping concentration of the second carrier storage layer is greater than that of the drift layer.

9. The semiconductor device according to claim 7, characterized in that, Also includes: A third doped layer is disposed between at least one of the two first carrier storage layers and the drift layer; The third doped layer has the opposite doping type to the first carrier storage layer.

10. The semiconductor device according to claim 8, characterized in that, Also includes: A fourth doped layer is disposed between the second carrier storage layer and the drift layer; the doping type of the fourth doped layer is opposite to that of the second carrier storage layer.

11. The semiconductor device according to claim 1, characterized in that, The gate includes two sub-gates spaced apart along the first direction; one of the sub-gates overlaps with one of the emission structures along the second direction.

12. The semiconductor device according to claim 11, characterized in that, The two sub-gates overlap with the gate protection doped structure along the second direction.

13. The semiconductor device according to claim 1, characterized in that, The emitter structure includes a first well region and a doped portion, the doped portion being embedded in the surface of the first well region on the side away from the drift layer; the first well region has a doping type opposite to that of the drift layer; the doped portion includes a first doped portion and a second doped portion with opposite doping types, the second doped portion being located on the side of the first doped portion away from the gate; the first doped portion has a doping type opposite to that of the first well region.

14. The semiconductor device according to claim 1, characterized in that, Also includes: Interlayer dielectric layer, covering the gate; An emitter covers the interlayer dielectric layer, and both ends of the emitter are in contact with the two emitter structures, respectively. The collector electrode is disposed on the side of the collector structure away from the drift layer and is in contact with the collector structure.

15. An electronic device, characterized in that, It includes a circuit board and a semiconductor device as described in any one of claims 1 to 14 disposed on one side of the circuit board.

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