A vertical composite ring-shaped InGaO thin film transistor and a preparation method thereof

Abstract

The application provides a vertical composite ring-shaped InGaO thin film transistor and a preparation method thereof. The preparation method comprises the following steps: step 1, obtaining the electrical performance parameters and electron concentration distribution of the vertical composite ring-shaped InGaO thin film transistor through theoretical simulation, and obtaining a process manufacturing scheme meeting target requirements; step 2, depositing an upper metal layer / insulating layer / lower metal layer on a substrate, etching the upper metal layer / insulating layer / lower metal layer to form a cavity, the upper metal layer being a drain electrode, and the lower metal layer being a source electrode; step 3, depositing an InGaO thin film as a channel layer, the number of layers of the channel layer being greater than or equal to 2, and the carrier concentration in different channel layers being designed differently according to charge transport requirements; step 4, depositing a gate dielectric layer and a gate electrode, the gate electrode being located at the center; and step 5, performing device isolation through dry etching, without any post-annealing treatment, to obtain the vertical composite ring-shaped InGaO thin film transistor.

Description

Technical Field

[0001] This invention belongs to the field of oxide thin film transistor technology, specifically relating to a vertical composite ring InGaO thin film transistor and its fabrication method. Background Technology

[0002] Micro-LED displays are a novel self-emissive display technology with device sizes on the micrometer scale, representing the next generation of high-resolution displays. Due to their high resolution, high luminous efficiency, low power consumption, and long lifespan, their overall performance far surpasses that of liquid crystal displays (LCDs) and organic light-emitting diode displays (OLEDs), making them suitable for applications such as wearable electronic devices, virtual reality, and augmented reality.

[0003] Micro-LEDs are driven by thin-film transistors, which requires the size of individual thin-film transistors to be reduced to submicron (0.1-1 μm). As the device size shrinks, short-channel effects arise, leading to a decrease in the drain barrier, a roll-off threshold voltage, and non-negligible parasitic resistance, thus affecting device performance.

[0004] Currently, to effectively suppress short-channel effects and improve gate control capabilities, device structures have shifted from planar to vertical structures, such as fin field-effect transistors (FETs), ring gates, and vertical ring channel structures. Vertical ring channel structures, where the channel layer completely surrounds the gate, can effectively improve gate control capabilities and compensate for short-channel effects. However, the channel layer is a single-layer structure, making the device performance susceptible to its limitations. Regarding channel materials, to further improve device mobility, reduce fabrication costs, and suitability for large-area production, the choice of channel materials has gradually shifted from early amorphous silicon and polycrystalline silicon to metal oxides, including InGaZnO, In2O3, SnO2, and ZnO. However, thin-film transistors require annealing to some extent during fabrication, making them unsuitable for flexible electronic device fabrication. Furthermore, the performance of thin-film transistors still needs improvement. Summary of the Invention

[0005] This invention addresses the aforementioned problems and aims to provide a vertically composite ring-shaped InGaO thin-film transistor and its fabrication method. The method involves constructing a channel layer of two or more vertically composite ring-shaped InGaO thin films, with differentiated carrier concentrations in different channel layers. This eliminates the need for subsequent annealing and effectively improves the mobility and stability of the metal-oxide-slim thin-film transistor while suppressing short-channel effects. To achieve the above objectives, this invention employs the following technical solution:

[0006] This invention provides a method for fabricating a vertically composite ring InGaO thin-film transistor, comprising the following steps: 1. Designing a structural model of the vertically composite ring InGaO thin-film transistor in semiconductor process and device simulation software, obtaining the electrical performance parameters and electron concentration distribution of the InGaO thin-film transistor through theoretical simulation, and obtaining a process manufacturing scheme that meets the target requirements through theoretical simulation; 2. Depositing an upper metal layer / insulating layer / lower metal layer on a substrate, etching the upper metal layer / insulating layer / lower metal layer to form voids, with the upper metal layer serving as the drain and the lower metal layer as the source; 3. Depositing an InGaO thin film as a channel layer, with the number of channel layers ≥ 2, and the carrier concentration in different channel layers being designed differently according to charge transport requirements; 4. Sequentially depositing a gate dielectric layer and a gate, with the gate located at the center of the device; 5. Isolating the device by dry etching without any post-annealing treatment, obtaining the vertically composite ring InGaO thin-film transistor.

[0007] Furthermore, the insulating layer has a thickness of 0.1-1 μm, which is the channel length of the thin-film transistor.

[0008] Furthermore, the upper and lower metal layers are made of one or more of Au, Ag, Cu, Al, Mo, Ti, and Sn.

[0009] Furthermore, in step 3, the carrier concentration of the channel layer is changed by altering the In / Ga doping ratio.

[0010] Furthermore, a high carrier concentration InGaO thin film serves as the front channel, located near the gate dielectric layer, while a low carrier concentration InGaO thin film serves as the back channel, located near the upper metal layer / insulating layer / lower metal layer.

[0011] Furthermore, the insulating layer is one or more of SiO2, Al2O3, HfO2, ZrO2, and TiO2.

[0012] Furthermore, in step 4, the gate dielectric layer is one or more of SiO2, Al2O3, HfO2, ZrO2, and TiO2.

[0013] The present invention also provides a vertical composite ring InGaO thin film transistor, which is prepared by the above-described preparation method.

[0014] The beneficial technical effects of this invention are:

[0015] 1. The vertical composite ring thin film transistor of the present invention has two or more channel layers. Compared with the existing vertical single-layer ring channel structure, it can build a carrier concentration gradient in the channel layer. The energy band of the channel layer bends at the interface to form a two-dimensional electron gas. In addition, the two or more channel layers completely surround the gate, and the gate is located in the center to control the multiple channel layers. The short-channel effect of the thin film transistor can be further suppressed, thereby achieving device size reduction while improving device mobility.

[0016] 2. The vertical composite ring thin film transistor of the present invention uses a ternary compound InGaO with two or more layers as the channel layer material and does not introduce Zn element for doping, which can reduce the crystallization temperature of the channel layer. In addition, the design of two or more channel layers eliminates the need for any subsequent annealing treatment, which can easily improve the mobility and stability of the device and is suitable for the fabrication of flexible electronic devices. Attached Figure Description

[0017] Figure 1. Schematic diagram of a vertical annular channel structure in the prior art.

[0018] Figure 2 is a three-dimensional schematic diagram of the vertical composite ring InGaO thin film transistor of the present invention.

[0019] Figure 3 is a schematic cross-sectional view of the vertical composite ring InGaO thin film transistor of the present invention.

[0020] 1: Substrate; 2: Source; 3: Insulating layer; 4: Drain; 5: Back channel InGaO film; 6: Front channel InGaO film; 71: Vertical ring InGaZnO film; 7: Vertical composite ring InGaO film; 8: Gate dielectric layer; 9: Gate. Detailed Implementation

[0021] The following detailed description, in conjunction with the accompanying drawings, of the specific embodiments of the vertical composite ring InGaO thin film transistor and its fabrication method involved in this invention. Example

[0022] Regarding the fabrication of vertical composite ring InGaO thin film transistors as described in this application, such as... Figure 2 , 3 As shown, it includes the following steps:

[0023] Step 1: Obtain the structural model of the vertical composite ring InGaO thin film transistor in the semiconductor process and device simulation software. By setting the thickness parameter of the insulating layer 3, obtain the vertical composite channel InGaO thin film transistor structure with the channel length varying from 0.1 to 1 μm. The electrical performance and electron concentration distribution of the InGaO thin film transistor are obtained through theoretical simulation, thereby obtaining the transfer characteristic curve and output characteristic curve of the device, and determining the process manufacturing scheme with excellent device performance (high mobility, high on / off ratio, low subthreshold swing, and high stability).

[0024] Step 2: Experimentally verify the theoretical simulation results from semiconductor process and device simulation software. A lower metal layer, an insulating layer 3, and an upper metal layer are sequentially deposited on substrate 1. The thickness of the insulating layer 3 (which is the channel length) is adjustable from 0.1 to 1 μm. The substrate is patterned, and the upper metal layer / insulating layer 3 / lower metal layer structure is etched to form voids. The etching depth reaches the lower metal layer. The lower metal layer after etching the voids becomes the source 2, and the upper metal layer becomes the drain 4, facilitating the subsequent formation of a vertical annular channel structure. By observing the size of the voids etched in the source 2 and drain 4, the channel width of the device is determined, thus determining the optimal process parameters. The perimeter of the voids is the channel width.

[0025] Step 3: Using atomic layer deposition (ALD), sequentially grow the back-channel InGaO film 5 and the front-channel InGaO film 6 to form a vertical composite annular InGaO film 7 as the channel layer. The carrier concentration in different channel layers is designed differently according to charge transport requirements. By adjusting the In / Ga doping ratio, the high carrier concentration InGaO is used as the front-channel InGaO film 6, which has more oxygen vacancies and provides a fast electron channel, improving mobility. At the same time, the low carrier concentration InGaO is used as the back-channel InGaO film 5, which has fewer oxygen vacancies and can serve as a passivation layer to improve device stability, resulting in an InGaO vertical composite annular channel with optimal overall performance.

[0026] High-k gate dielectric layers were grown using atomic layer deposition (ALD). Oxides such as SiO2, Al2O3, HfO2, ZrO2, and TiO2 were preferentially grown as gate dielectric layers, with H2O, O2, and O3 used as oxidants, respectively. The growth temperatures ranged from 100 to 300 °C, and the thicknesses ranged from 10 to 70 nm. Performance testing was used to determine the growth process of the gate dielectric layers, and the gate dielectric layer thickness and leakage characteristics under different growth conditions were investigated. The growth conditions were optimized to determine the optimal thickness and growth process.

[0027] The gate 9 was fabricated using atomic layer deposition (ALD) and the device was isolated using dry etching. The gate 9, located at the center, was grown using ALD. Finally, the device was isolated using dry etching to fabricate the desired result. Figure 2 ,3 The vertically composite ring InGaO thin film transistor shown.

[0028] In the above experiments, the channel layer material was set as a ternary compound InGaO with two or more layers, without the introduction of Zn element for doping, which can reduce the crystallization temperature of the channel layer. No post-annealing treatment was performed, which can easily improve the mobility and stability of the device, making it suitable for the fabrication of flexible electronic devices.

[0029] The above embodiments are merely illustrative examples of the technical solutions of the present invention. The vertical composite ring InGaO thin film transistor and its fabrication method involved in the present invention are not limited to the contents described in the above embodiments, but are subject to the scope defined by the claims. Any modifications, additions, or equivalent substitutions made by those skilled in the art based on these embodiments are within the scope of protection claimed by the claims of the present invention.

Claims

1. A method for fabricating a vertically composite ring-shaped InGaO thin-film transistor, characterized in that, Includes the following steps: Step 1. Design a structural model of the vertically composite ring InGaO thin film transistor in semiconductor process and device simulation software, and obtain the electrical performance parameters and electron concentration distribution of the InGaO thin film transistor through theoretical simulation; obtain a process manufacturing scheme that meets the target requirements through theoretical simulation. Step 2. Based on the simulation results in Step 1, deposit an upper metal layer / insulating layer / lower metal layer on the substrate, and etch the upper metal layer / insulating layer / lower metal layer to form a cavity. The upper metal layer is the drain and the lower metal layer is the source. Step 3. Deposit an InGaO thin film as a channel layer. The number of channel layers is ≥2. The carrier concentration in different channel layers is designed differently according to the charge transport requirements. Step 4. Sequentially deposit the gate dielectric layer and the gate, with the gate located at the center of the device; Step 5. Device isolation is performed by dry etching without any post-annealing process to obtain a vertical composite ring InGaO thin film transistor.

2. The method for fabricating a vertical composite ring InGaO thin film transistor according to claim 1, characterized in that: The insulating layer has a thickness of 0.1-1 μm, which is the channel length of the thin-film transistor.

3. The method for fabricating a vertical composite ring InGaO thin film transistor according to claim 2, characterized in that: The upper and lower metal layers are made of one or more of Au, Ag, Cu, Al, Mo, Ti, and Sn.

4. The method for fabricating a vertical composite ring InGaO thin film transistor according to claim 1, characterized in that: in, In step 3, the carrier concentration of the channel layer is changed by altering the In / Ga doping ratio.

5. The method for fabricating a vertical composite ring InGaO thin film transistor according to claim 4, characterized in that: A high carrier concentration InGaO thin film serves as the front channel, located on the gate dielectric layer side, while a low carrier concentration InGaO thin film serves as the back channel, located on the upper metal layer / insulating layer / lower metal layer side.

6. The method for fabricating a vertical composite ring InGaO thin film transistor according to claim 5, characterized in that: The insulating layer is one or more of SiO2, Al2O3, HfO2, ZrO2, and TiO2.

7. The method for fabricating a vertical composite ring InGaO thin film transistor according to claim 1, characterized in that: wherein, In step 4, the gate dielectric layer is one or more of SiO2, Al2O3, HfO2, ZrO2, and TiO2.

8. A vertically composite ring-shaped InGaO thin-film transistor, characterized in that: It is prepared by any one of the preparation methods described in claims 1 to 7.

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