Method for preparing carbon nanotube three-dimensional fin field effect transistor by thermal scanning probe

Abstract

The application belongs to the technical field of semiconductor device preparation, and particularly relates to a method for preparing a carbon nanotube three-dimensional fin field effect transistor by using a thermal scanning probe. A substrate with a thermosensitive polymer sacrificial layer on a surface is provided; a three-dimensional fin array structure pattern is formed on the thermosensitive polymer sacrificial layer by using a thermal scanning probe direct writing process; the three-dimensional fin array structure pattern is transferred to the substrate by dry etching; carbon nanotubes are directionally assembled on the three-dimensional fin structure, so that the carbon nanotubes are directionally arranged along the fin direction; an active region and a source-drain electrode region are defined on the fin region, a source electrode and a drain electrode metal layer are deposited, and a top gate electrode is manufactured. The three-dimensional fin structure is directly written on the thermosensitive polymer sacrificial layer with nanometer precision by using the thermal scanning probe direct writing technology, so that the traditional photolithography process is replaced, the size and pattern of the fin structure can be flexibly adjusted, and the flexible and rapid preparation of the carbon nanotube three-dimensional fin field effect transistor is realized.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device fabrication technology, specifically relating to a method for fabricating three-dimensional fin field-effect transistors of carbon nanotubes using a thermal scanning probe. Background Technology

[0002] As Moore's Law continues to advance, the feature size of traditional silicon-based field-effect transistors (FETs) is approaching its physical limit, leading to increasingly serious problems such as short-channel effects and increased leakage current. Carbon nanotubes, due to their superior carrier mobility, ultra-thin bulk structure, and excellent resistance to short-channel effects, are considered one of the most promising channel materials in the post-silicon era. However, the drive current of a single carbon nanotube FET is limited, making it difficult to meet the needs of practical circuits. To improve the drive current, arranging multiple carbon nanotubes in parallel and integrating them into a three-dimensional fin field-effect transistor (FinFET) structure has become a research hotspot. The three-dimensional fin structure can effectively increase the number of carbon nanotubes per unit device width, thereby significantly increasing the device's drive current and integration density.

[0003] Patent CN104979402A discloses a three-dimensional carbon nanotube fin-shaped field-effect transistor and its fabrication method. This involves etching insulating fins on an insulating substrate and depositing carbon nanotubes via electrophoresis or the LB method. However, electrophoresis requires pre-fabrication of metal electrodes and subsequent etching, making the process complex. Patent 110416308A discloses another method for fabricating a three-dimensional carbon nanotube fin-shaped field-effect transistor. This method uses embedded metal fins and a Dirac two-dimensional semi-metal as source and drain electrodes, and deposits carbon nanotubes via self-assembly to form an embedded gate fin structure. The ultrathin properties of the semi-metal are utilized to reduce the short-channel effect. However, in the above methods for fabricating three-dimensional carbon nanotube fin-shaped field-effect transistors, the fabrication of the fin structure relies on traditional micro / nano fabrication techniques such as photolithography, electron beam lithography, or nanoimprint lithography. These methods suffer from expensive equipment, long processing cycles, and inflexible pattern modification. Summary of the Invention

[0004] The purpose of this invention is to provide a method for fabricating three-dimensional carbon nanotube fin field-effect transistors using a thermal scanning probe. This method utilizes thermal scanning probe direct writing technology to directly write three-dimensional fin structures with nanometer precision onto a thermosensitive polymer sacrificial layer, replacing traditional photolithography. Thermal scanning probe direct writing technology can complete three-dimensional grayscale direct writing without a mask. Furthermore, the thermal scanning probe has nanometer-level resolution, allowing for flexible adjustment of the size and pattern of the fin structure, thus enabling flexible and rapid fabrication of three-dimensional carbon nanotube fin field-effect transistors.

[0005] The present invention solves the above-mentioned technical problems through the following technical solutions.

[0006] The purpose of this invention is to provide a method for fabricating three-dimensional fin field-effect transistors of carbon nanotubes using a thermal scanning probe, comprising the following steps: S1. A substrate having a thermosensitive polymer sacrificial layer on its surface is provided.

[0007] S2. A three-dimensional fin array structure pattern is formed by direct writing and etching on the thermal polymer sacrificial layer using a thermal scanning probe direct writing process.

[0008] S3. Dry etching is used to transfer the three-dimensional fin array structure pattern onto the substrate.

[0009] S4. Assemble carbon nanotubes in an orientational manner on each three-dimensional fin structure, so that the carbon nanotubes are oriented along the fin direction and cover the outer wall of the three-dimensional fin structure to form a three-dimensional carbon nanotube channel layer, and then perform annealing treatment.

[0010] S4. Using a thermal scanning probe direct writing process, the active region and source / drain electrode regions of the transistor are defined on the fin region. Source and drain electrode metal layers are deposited, followed by the deposition of a high-k gate dielectric layer. The top gate electrode is then fabricated in situ to obtain a carbon nanotube three-dimensional fin field-effect transistor.

[0011] Furthermore, the thermosensitive polymer is selected from poly(o-phthalaldehyde), and a thermosensitive polymer sacrificial layer is formed on the substrate by spin coating. After the thermosensitive polymer sacrificial layer is formed, it is cured at 180°C for 90 seconds.

[0012] Furthermore, the thickness of the thermosensitive polymer sacrificial layer is 20 nm to 120 nm.

[0013] Furthermore, during the etching process to form a three-dimensional fin array structure, the probe temperature is controlled at 700℃, the scan line spacing is 200nm, and a multi-probe parallel direct writing technique is adopted. N probes are used to simultaneously write N trenches, where N is 2 to 128. The probes are controlled to scan and write along a predetermined path on the surface of the thermal adhesive at a direct writing pixel size of 2nm to 50nm to perform etching.

[0014] Furthermore, in the three-dimensional fin array structure pattern, each three-dimensional fin structure includes alternating fins and grooves, with the width of the fins ranging from 10 nm to 500 nm and the height ranging from 10 nm to 100 nm, and the width of the grooves between adjacent fins ranging from 10 nm to 500 nm.

[0015] Furthermore, during the dry etching process, the dry etching gas is at least one of CHF3, SF6 / C4F8, and C4F8 / H2 / He, with a total flow rate of 10 sccm to 200 sccm, a ignition power of 15 W to 300 W, and an etching power of 500 W to 1500 W.

[0016] Furthermore, the directional assembly method is selected from dimension-constrained self-assembly, two-dimensional liquid crystal directional assembly, electrophoretic deposition, dip-coating or LB film transfer, and the carbon nanotubes are semiconductor single-walled carbon nanotubes with a semiconductor purity of not less than 99.99% and a diameter of 1.2 nm to 2 nm.

[0017] Furthermore, the density of carbon nanotubes covering each fin is 300 to 1000 nanotubes per micrometer, and the deviation between the direction of the carbon nanotubes and the direction of the grooves is within 5°.

[0018] Furthermore, after defining the active region and source / drain electrode regions of the transistor, a polymer release layer and a thermosensitive polymer photosensitive layer are formed on the surface. Then, the active region is etched on the poly(p-phenylene terephthalamide) layer using a thermal scanning probe direct writing process. The polymer release layer and the thermosensitive polymer photosensitive layer are removed by development, and the source electrode and drain electrode metal layers are deposited.

[0019] Furthermore, the thickness of the gate dielectric layer is 1nm to 20nm, and the material of the gate dielectric layer is selected from hafnium oxide, zirconium oxide, aluminum oxide or yttrium oxide; the thickness of the gate electrode is 10nm to 100nm, and the material of the gate electrode is selected from palladium, platinum, gold, titanium, copper, aluminum, tungsten or scandium.

[0020] Compared with the prior art, the present invention has the following advantages: The fabrication method provided by this invention uses a thermosensitive polymer sacrificial layer as the mask material for the fin structure. A three-dimensional fin array mask pattern is directly constructed on the substrate using a thermal scanning probe direct writing method. This eliminates the need for a mask, enabling three-dimensional grayscale direct writing and avoiding the reliance on expensive equipment and long processing cycles inherent in traditional photolithography. The thermal scanning probe offers nanometer-level resolution, allowing for flexible adjustment of the fin structure's size and pattern, facilitating rapid prototyping and customized device fabrication. Furthermore, the use of a thermosensitive adhesive as the mask material for the fin structure provides high patterning accuracy, high selectivity for dry etching, and easy adjustment of the fin structure's aspect ratio, increasing the density of carbon nanotubes per unit area and providing favorable conditions for enhancing on-state current. It is also compatible with silicon-based device manufacturing processes, significantly reducing overall manufacturing costs. This method is suitable for the complete fabrication of carbon nanotube three-dimensional fin field-effect transistors. It offers advantages such as no need for a mask, rapid adjustment of pattern parameters, high nanometer-level processing accuracy, small local heat-affected zones, suitability for small-batch rapid verification, and multi-parameter device optimization. Attached Figure Description

[0021] Figure 1 This is a flowchart illustrating the method for fabricating three-dimensional fin field-effect transistors using a thermal scanning probe according to the present invention.

[0022] Figure 2 This is a schematic diagram of the three-dimensional fin-like structure after the thermal scanning probe of this invention directly writes to the thermal adhesive.

[0023] Figure 3 This is a schematic diagram of the three-dimensional fin-like structure on the substrate after reactive ion etching according to the present invention.

[0024] Figure 4 This is a schematic cross-sectional view of the assembled carbon nanotube array on the fin-like structure in an embodiment of the present invention.

[0025] Figure 5 This is a schematic cross-sectional view of the device in the ZX direction after the deposition of the gate dielectric layer, source electrode, drain electrode, and gate electrode of the present invention.

[0026] Figure 6 This is a schematic cross-sectional view of the device in the ZY direction after the gate dielectric layer and source, drain and gate electrodes have been deposited according to the present invention. Detailed Implementation

[0027] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0028] It should be noted that the technical terms used in this invention are only for the purpose of describing specific embodiments and are not intended to limit the scope of protection of this invention. Unless otherwise specified, all raw materials, reagents, instruments and equipment used in the following embodiments of this invention can be purchased from the market or prepared by existing methods.

[0029] The purpose of this invention is to provide a method for flexibly and cost-effectively fabricating three-dimensional carbon nanotube fin field-effect transistors, replacing traditional photolithography processes and combining it with existing silicon-based manufacturing processes to achieve flexible and rapid fabrication of carbon nanotube three-dimensional fin field-effect transistors. Figure 1 As shown, it includes the following steps:

[0030] S1. A substrate having a thermosensitive polymer sacrificial layer on its surface is provided.

[0031] In this invention, the substrate material includes, but is not limited to, one of the following: silicon wafers with a silicon dioxide layer (thickness of 100nm to 500nm), quartz substrates, sapphire substrates, or flexible polymer substrates. Flexible polymer materials include, but are not limited to, polydimethylsiloxane (PDMS) and polyethylene terephthalate (PET). Preferably, the substrate material is selected from silicon wafers with a silicon dioxide layer (thickness of 500nm), purchased from Guangzhou Tianhe Crystal Semiconductor E-commerce Firm.

[0032] In this invention, the thermosensitive polymer is selected from poly(phthalaldehyde) (PPA). A thermosensitive polymer sacrificial layer is formed on the substrate using a spin coating method. After formation, the thermosensitive polymer sacrificial layer is cured at 170°C to 190°C for 60 to 120 seconds. In a preferred embodiment, the thermosensitive polymer sacrificial layer is formed on the substrate using a spin coating method with a spin coating speed of 2000 rpm to 6000 rpm and a spin coating time of 30 to 60 seconds. The thickness of the thermosensitive polymer sacrificial layer is 20 nm to 120 nm.

[0033] S2. A three-dimensional fin array structure pattern is formed by direct writing and etching on the thermal polymer sacrificial layer using a thermal scanning probe direct writing process.

[0034] In this invention, a three-dimensional fin structure is formed by direct writing on a thermosensitive polymer sacrificial layer using thermal scanning probe technology. The probe tip's thermal-mechanical coupling effect directly etches trench structures into the thermosensitive adhesive, and further direct writing forms a parallel three-dimensional fin array structure. The probe temperature is controlled at 700℃~1300℃, the scan line spacing is 100nm~500nm, and a multi-probe parallel direct writing technique is employed, using N probes to simultaneously write N trenches, where N is 2~128, to improve writing efficiency. The probes are controlled to scan and write along a predetermined path on the surface of the thermosensitive polymer sacrificial layer at a direct writing pixel size of 2nm~50nm for etching. The three-dimensional fin structure includes alternating thermosensitive adhesive fins and trenches. The width of the thermosensitive polymer sacrificial layer fins is 10nm~500nm, the height is 10nm~100nm, and the trench width between adjacent thermosensitive adhesive fins is 10nm~500nm.

[0035] S3. The three-dimensional fin array structure pattern is transferred to the substrate by dry etching, and the remaining heat-sensitive polymer sacrificial layer is removed by solvent.

[0036] In this invention, a three-dimensional fin array structure is etched onto a substrate using a dry etching method, employing a three-dimensional fin array pattern. During the dry etching process, the etching gas is at least one of CHF3, SF6 / C4F8, and C4F8 / H2 / He, with a total flow rate of 10 sccm to 200 sccm, a start-up power of 15 W to 300 W, and an etching power of 500 W to 1500 W. This method offers high patterning precision, excellent etching resistance, high selectivity in dry etching, and easy adjustment of the fin structure's aspect ratio.

[0037] This invention employs a thermal scanning probe direct-writing method to directly form three-dimensional fin-like patterns on a thermosensitive polymer. By controlling the probe temperature, direct-writing pixel size, scan line spacing, and thermosensitive adhesive thickness, nanoscale trench structures can be formed in the thermosensitive adhesive, and the patterns are further transferred to a substrate via dry etching. This method achieves grayscale direct writing of three-dimensional fin-like structures without the need for a pre-fabricated mask, and is suitable for rapid adjustment of fin width, fin height, period, and trench depth, thereby improving the structural design flexibility and prototyping efficiency of carbon nanotube three-dimensional fin field-effect transistors.

[0038] S4. Assemble carbon nanotubes in an orientational manner on each three-dimensional fin structure, so that the carbon nanotubes are oriented along the fin direction and cover the outer wall of the three-dimensional fin structure to form a three-dimensional carbon nanotube channel layer, and then perform annealing treatment.

[0039] In this invention, directional assembly is achieved by methods selected from dimensional confinement self-assembly, two-dimensional liquid crystal directional assembly, electrophoretic deposition, dip-coating, or LB film transfer to align carbon nanotubes along the fin-like direction and cover at least two sidewalls of each polymer fin, forming a three-dimensional carbon nanotube channel layer. The deviation between the direction of the carbon nanotubes and the direction of the channels is within 5°. The carbon nanotubes are semiconducting single-walled carbon nanotubes with a semiconductor purity of not less than 99.99% and a diameter of 1.2 nm to 2 nm. The density of carbon nanotubes covering each polymer fin is 300 nanotubes / micrometer to 1000 nanotubes / micrometer.

[0040] Understandably, after the three-dimensional array of carbon nanotubes is assembled, the substrate is annealed. The annealing methods include tube furnace, rapid annealing furnace, laser annealing, etc.

[0041] S4. Using a thermal scanning probe direct writing process, the active region and source / drain electrode regions of the transistor are defined on the fin region. Source and drain electrode metal layers are deposited, followed by the deposition of a high-k gate dielectric layer. The top gate electrode is then fabricated in situ to obtain a carbon nanotube three-dimensional fin field-effect transistor.

[0042] In this invention, after defining the active region and source / drain electrode regions of the transistor, a polymer release layer and a thermosensitive polymer photosensitive layer are formed on the surface. Then, a thermal scanning probe direct writing process is used to etch the active region onto the thermosensitive polymer photosensitive layer. Development removes the polymer release layer and the thermosensitive polymer photosensitive layer, and the source and drain electrode metal layers are deposited. It is understood that the polymer release layer can be made of polymethyl methacrylate (PMMA), and the thermosensitive polymer photosensitive layer can be made of poly(phthalaldehyde) (PPA). Spin coating is used, with the polymer release layer having a thickness of 120 nm and the thermosensitive polymer photosensitive layer having a thickness of 20 nm. It is understood that development uses a 5% water / isopropanol mixture with a water / isopropanol volume ratio of 1:19, a development speed of 1 nm / s, and a development time of 180 s.

[0043] In this invention, the thickness of the gate dielectric layer is 1 nm to 20 nm, formed by atomic layer deposition (ALD); the material of the gate dielectric layer is selected from hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), or yttrium oxide (Y2O3); the thickness of the gate electrode is 10 nm to 100 nm, and the material of the gate electrode is selected from palladium (Pd), platinum (Pt), gold (Au), titanium (Ti), copper (Cu), aluminum (Al), tungsten (W), or scandium (Sc). The gate electrode spans the carbon nanotube channel layer and is located between the source electrode and drain electrode metal layers.

[0044] It should be noted that the innovation of this application lies not in simply proposing thermal scanning probe lithography itself, but in combining thermal scanning probe direct writing, patterning of a thermosensitive polymer sacrificial layer, etching and transfer of insulating fin structures, and directional assembly of carbon nanotubes. This allows for 3D grayscale direct writing without a mask. Simultaneously, the thermal scanning probe possesses nanometer-level resolution, allowing for flexible adjustment of the fin structure's size and pattern, facilitating rapid prototyping and customized device fabrication. Furthermore, by using a thermosensitive adhesive as the mask material for the fin structure, high patterning precision is achieved, increasing the density of carbon nanotubes per unit area and significantly enhancing the on-state current. The high selectivity of dry etching facilitates adjustment of the fin structure's aspect ratio, forming a complete fabrication method suitable for carbon nanotube 3D fin field-effect transistors. This method offers advantages such as no need for a mask, rapid adjustment of pattern parameters, high nanometer-level processing precision, small local heat-affected zones, suitability for small-batch rapid verification, and multi-parameter device optimization.

[0045] The following specific examples will provide further explanation.

[0046] Example 1 A method for fabricating three-dimensional fin field-effect transistors from carbon nanotubes using a thermal scanning probe, such as... Figure 2 As shown, it includes the following steps: S1. Provide a silicon wafer with a silicon dioxide layer (thickness of 500nm), namely substrate 102. The thickness of the silicon wafer is 500nm. Spin-coat a 5% thermal adhesive poly(phthalaldehyde) anisole solution on the surface of the silicon dioxide layer at a rotation speed of 2000rpm. Bake on a hot plate at 180°C for 90s to obtain a PPA film with a thickness of about 80nm.

[0047] S2. A three-dimensional fin array structure is formed on the PPA film by direct writing and etching using a thermal scanning probe. The probe heating temperature is set to 700℃. The direct writing pixel size is set to 5nm. The probe scans line by line along a direction perpendicular to the long axis of the probe cantilever beam, with an adjacent scan line spacing of 200nm. Under the thermal-mechanical coupling of the probe, the PPA film is locally removed along the scanning path, such as... Figure 2 As shown, nanoscale trenches with a width of about 50 nm and a depth of about 30 nm are formed. The length of each nanoscale trench is 5 μm, and the width of the trench between adjacent thermosensitive fins is 50 nm. A total of 20 parallel trenches are written to obtain a pattern of parallel three-dimensional fin array structure.

[0048] S3. Use dry etching method, such as Figure 3 As shown, a pattern with a parallel three-dimensional fin array structure was transferred onto a substrate. The dry etching gas was CHF3 with a total flow rate of 20 sccm, a start-up power of 50 W, and an etching power of 500 W. After etching, an array of three-dimensional fins with a depth of 50 nm, a period of 200 nm, and a length of 5 μm was obtained. After dry etching, the excess PPA film was removed by heating to 50 °C with cyclohexanone.

[0049] S4. Carbon nanotubes were assembled using a dimensional confinement self-assembly method. Semiconductor single-walled carbon nanotubes (SUVs) with a diameter of approximately 1.5 nm were dispersed in toluene. The substrate was pulled at a speed of 2 μm / s along the direction parallel to the trenches. The deviation between the orientation of the SUVs and the trenches was within 5°. The carbon nanotubes were oriented along the trenches, covering the outer wall of each three-dimensional fin structure. After pulling, the substrate was soaked in toluene and isopropanol for 20 minutes each, and then dried with nitrogen. The density of carbon nanotubes covering each polymer fin was 600 nanotubes / micrometer. Figure 4 As shown. After the three-dimensional array of carbon nanotubes was assembled, the substrate was annealed using an argon-hydrogen mixture (argon:hydrogen = 9:1, volume ratio) at a flow rate of 50 sccm and an annealing temperature of 600℃ for 1 hour.

[0050] S5. After the three-dimensional carbon nanotube array is assembled, a 50nm PPA film is spin-coated on the substrate surface. The active region of the carbon nanotube field-effect transistor is defined by direct writing with a thermal scanning probe. The carbon nanotubes outside the active region are removed by etching with a 75W oxygen plasma cleaner for 30s to prevent short circuits.

[0051] The source and drain electrode regions of the transistor were patterned by spin-coating a double layer of adhesive on the surface of substrate 102. First, 120 nm of PMMA was spin-coated, followed by 2.5% concentration of thermal adhesive PPA, with a film thickness of 30 nm. The source and drain electrodes were directly written on the PPA film using a thermal scanning probe direct writing system. After the direct writing was completed, a 5% deionized water / isopropanol mixture (water / isopropanol volume ratio of 1:19) was used for development at a rate of 1 nm / s for 180 s. Then, 0.3 nm / 50 nm / 50 nm Ti / Pd / Au were deposited sequentially by thermal evaporation. Finally, the source and drain electrodes 104 were fabricated by stripping.

[0052] A high-k gate dielectric layer 101 was deposited on substrate 102 using ALD at a deposition temperature of 250°C. Figure 5 As shown, the high-K gate dielectric layer material in this invention is HfO2.

[0053] Using the same double-layer adhesive process, and employing the in-situ direct writing function of a thermal scanning probe, the source and drain regions are first scanned and located, then the top gate region pattern is written in situ. After development, a thermal evaporation deposition method is used to sequentially deposit 50nm / 50nm Ti / Au films. Finally, the top gate electrode 100 is fabricated by lift-off. After lift-off, an air sidewall 103 is etched between the source / drain electrodes 104 and the top gate electrode 100, thus obtaining a carbon nanotube three-dimensional fin field-effect transistor. Figure 6 As shown.

[0054] Example 2 A method for batch fabrication of three-dimensional fin field-effect transistors using carbon nanotubes via thermal scanning probes includes the following steps: S1. Provide a 4 / 6-inch silicon wafer (500nm thick) as the substrate. The silicon wafer is 500nm thick. Spin-coat a 5% thermal adhesive poly(phthalaldehyde) anisole solution at 2000rpm onto the surface of the silicon dioxide layer. Bake on a hot plate at 180°C for 90s to obtain a PPA film with a thickness of about 80nm.

[0055] S2. A three-dimensional fin array structure is formed by direct writing and etching on a PPA film using a thermal scanning probe process. The probe heating temperature is set to 700℃. The direct writing pixel size is set to 5nm. The probe scans line by line along a direction perpendicular to the long axis of the probe cantilever beam, with an adjacent scan line spacing of 200nm. Under the thermal-mechanical coupling of the probe, the PPA film is locally removed along the scanning path, forming nanoscale trenches with a width of approximately 30nm and a depth of approximately 30nm. Each nanoscale trench is 5μm long, and a total of 64 parallel trenches are directly written to obtain a pattern of parallel three-dimensional fin array structure.

[0056] S3. A pattern with a parallel three-dimensional fin array structure is transferred onto the substrate using a dry etching method. The dry etching gas is CHF3 with a total flow rate of 20 sccm, a start-up power of 50 W, and an etching power of 500 W. After etching, an array with a depth of 50 nm, a period of 200 nm, and a length of 5 μm is obtained for each three-dimensional fin. After dry etching, the excess PPA film is removed by heating to 50 °C with cyclohexanone.

[0057] S4. Carbon nanotubes were assembled using a dimension-constrained self-assembly method. Single-walled carbon nanotubes were dispersed in toluene. The substrate was pulled up at a speed of 2 μm / s along the direction parallel to the grooves. The carbon nanotubes were oriented along the direction of the grooves. After pulling up, the substrate was soaked in toluene and isopropanol for 20 minutes, and then dried with nitrogen.

[0058] S5. After the three-dimensional carbon nanotube array is assembled, the polymer on the surface of the carbon nanotube array is removed using a femtosecond laser. Then, a 50nm PPA film is spin-coated on the substrate surface and directly written using a thermal scanning probe to define the active region of the carbon nanotube field-effect transistor. The carbon nanotubes outside the active region are removed by etching for 30s using a 75W oxygen plasma cleaner to prevent short circuits.

[0059] The source and drain electrode regions of the transistor were patterned by spin-coating a double layer of adhesive on the substrate surface. First, a 120 nm PMMA layer was spin-coated, followed by a 2.5% concentration of thermal adhesive PPA, resulting in a film thickness of 30 nm. The source and drain electrodes were directly written onto the PPA film using a thermal scanning probe direct writing system. After direct writing, a 5% deionized water / isopropanol mixture (water / isopropanol volume ratio of 1:19) was used for development at a rate of 1 nm / s for 180 s. Then, 0.3 nm / 50 nm / 50 nm Ti / Pd / Au layers were sequentially deposited using thermal evaporation. Finally, the source and drain electrodes were stripped to complete the fabrication.

[0060] A high-k gate dielectric layer is grown on the substrate using ALD at a deposition temperature of 250°C. The material of the high-k gate dielectric layer in this invention is HfO2.

[0061] Using the same double-layer adhesive process, the source and drain regions are first scanned and located using the in-situ direct writing function of the thermal scanning probe. Then, the top gate region pattern is written in-situ. After development, the 50nm / 50nm Ti / Au is deposited sequentially using the thermal evaporation coating method. Finally, the top gate electrode 100 is fabricated by stripping. After stripping, an air sidewall 103 is formed between the source and drain electrodes 104 and the top gate electrode 100, which means that carbon nanotube three-dimensional fin field-effect transistors are mass-produced.

[0062] It should be noted that when numerical ranges are involved in this invention, it should be understood that both endpoints of each numerical range and any value between the two endpoints can be selected. Since the steps and methods used are the same as in the embodiments, preferred embodiments are described here to avoid redundancy. Although preferred embodiments of the invention have been described, those skilled in the art, once they understand the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this invention.

[0063] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A method for fabricating three-dimensional fin field-effect transistors using a thermal scanning probe, characterized in that, Includes the following steps: Provide a substrate with a heat-sensitive polymer sacrificial layer on its surface; A three-dimensional fin array structure pattern was formed by direct writing and etching on a thermally sensitive polymer sacrificial layer using a thermal scanning probe direct writing process. The three-dimensional fin array structure pattern was transferred onto the substrate using dry etching. Carbon nanotubes are oriented and assembled on each three-dimensional fin structure, so that the carbon nanotubes are oriented along the fin direction and cover the outer wall of each three-dimensional fin structure to form a three-dimensional carbon nanotube channel layer, and then annealed. A three-dimensional carbon nanotube fin field-effect transistor is obtained by using a thermal scanning probe direct writing process to define the active region and source / drain electrode regions of the transistor on the fin region, depositing source and drain electrode metal layers, depositing a high-k gate dielectric layer, and then fabricating the top gate electrode in situ.

2. The method for fabricating three-dimensional fin field-effect transistors of carbon nanotubes using a thermal scanning probe according to claim 1, characterized in that, The thermosensitive polymer is selected from poly(o-phthalaldehyde). A thermosensitive polymer sacrificial layer is formed on the substrate by spin coating. After the thermosensitive polymer sacrificial layer is formed, it is cured at 180°C for 90 seconds.

3. The method for fabricating three-dimensional fin field-effect transistors of carbon nanotubes using a thermal scanning probe according to claim 1, characterized in that, The thickness of the thermosensitive polymer sacrificial layer is 20nm to 120nm.

4. The method for fabricating three-dimensional fin field-effect transistors of carbon nanotubes using a thermal scanning probe according to claim 1, characterized in that, During the etching process to form a three-dimensional fin array structure, the probe temperature is controlled at 700℃ and the scan line spacing is 200nm. A multi-probe parallel direct writing technique is adopted, using N probes to simultaneously write N trenches, where N is 2 to 128. The probes are controlled to scan and write along a predetermined path on the surface of the thermal adhesive at a direct writing pixel size of 2nm to 50nm to perform etching.

5. The method for fabricating three-dimensional fin field-effect transistors of carbon nanotubes using a thermal scanning probe according to claim 1, characterized in that, In the three-dimensional fin array structure pattern, each three-dimensional fin structure includes alternating fins and grooves. The width of the fins is 10nm to 500nm, the height is 10nm to 100nm, and the width of the grooves between adjacent fins is 10nm to 500nm.

6. The method for fabricating three-dimensional fin field-effect transistors of carbon nanotubes using a thermal scanning probe according to claim 1, characterized in that, During the dry etching process, the dry etching gas is at least one of CHF3, SF6 / C4F8, and C4F8 / H2 / He, with a total flow rate of 10 sccm to 200 sccm, a ignition power of 15 W to 300 W, and an etching power of 500 W to 1500 W.

7. The method for fabricating a three-dimensional fin field-effect transistor using a thermal scanning probe according to claim 1, characterized in that, The directional assembly method is selected from dimensional confinement self-assembly, two-dimensional liquid crystal directional assembly, electrophoretic deposition, dip-coating or LB film transfer. The carbon nanotubes are semiconductor single-walled carbon nanotubes with a semiconductor purity of not less than 99.99% and a diameter of 1.2 nm to 2 nm.

8. The method for fabricating a three-dimensional fin field-effect transistor using a thermal scanning probe according to claim 1, characterized in that, The density of carbon nanotubes covering each fin is 300 to 1000 nanotubes per micrometer, and the deviation of the direction of the carbon nanotubes from the direction of the grooves is within 5°.

9. The method for fabricating a three-dimensional fin field-effect transistor using a thermal scanning probe according to claim 1, characterized in that, After defining the active region and source / drain electrode regions of the transistor, a polymer release layer and a thermosensitive polymer photosensitive layer are formed on the surface. Then, the active region is etched on the poly(p-phenylene terephthalamide) layer using a thermal scanning probe direct writing process. The polymer release layer and the thermosensitive polymer photosensitive layer are removed by development, and the source electrode and drain electrode metal layers are deposited.

10. The method for fabricating a three-dimensional fin field-effect transistor using a thermal scanning probe according to claim 1, characterized in that, The thickness of the gate dielectric layer is 1nm to 20nm, and the material of the gate dielectric layer is selected from hafnium oxide, zirconium oxide, aluminum oxide or yttrium oxide; the thickness of the gate electrode is 10nm to 100nm, and the material of the gate electrode is selected from palladium, platinum, gold, titanium, copper, aluminum, tungsten or scandium.

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