Method for manufacturing a semiconductor structure and semiconductor structure

Abstract

The application provides a semiconductor structure preparation method and a semiconductor structure, which comprises the following steps: providing a base including a substrate and a device isolation structure; the substrate is divided into a device region, the device isolation structure is located in the device region and forms a boundary of the device region; etching the device isolation structure and the substrate in the device region synchronously to form a first groove penetrating through the device isolation structure and a second groove on a surface layer of the substrate in the device region; filling a conductive material in the first groove and the second groove; forming a first injection region at a bottom of the substrate in the device region, the first injection region being in contact with the first groove; forming a drift region in the substrate above the first injection region; forming a body region around the second groove, a source region on a surface layer of the body region beside the second groove, a drain region in the drift region and a gate structure on the substrate between the source region and the drain region, so that the device area is reduced, the device withstand voltage is improved and the specific on-resistance is balanced.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and in particular to a method for preparing a semiconductor structure and the semiconductor structure thereof. Background Technology

[0002] Lateral double-diffused metal-oxide-semiconductor (LDMOS) devices are widely used in power management chips and other power integrated circuits due to their high voltage withstand capability, low on-resistance, and ease of compatibility with integrated circuit processes. Taking a mobile phone power management unit (PMU) as an example, a 5V N-type LDMOS is typically used as the basic power device for power switching, voltage regulation, and protection circuits. As PMUs develop towards higher integration, higher efficiency, and miniaturization, higher requirements are placed on the voltage withstand capability, conduction performance, and area utilization of LDMOS devices.

[0003] Existing LDMOS devices typically employ a planar layout for their source and body leads, with the body leads adjacent to the source, resulting in low hole collection efficiency and weak on-state breakdown voltage. Furthermore, the specific on-resistance of LDMOS devices is correlated with their on-state breakdown voltage, making it difficult to reduce conduction losses while simultaneously improving breakdown voltage. In addition, traditional LDMOS devices often utilize well regions as substrates or buried layers for their lead structures, occupying a large chip area and reducing device integration density. Therefore, how to reduce device area while improving breakdown voltage and balancing specific on-resistance has become one of the urgent technical challenges to be addressed.

[0004] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for preparing a semiconductor structure and a semiconductor structure, so as to solve the problem that LDMOS devices cannot improve the device voltage withstand and balance the specific on-resistance while miniaturizing them.

[0006] To achieve the above and other related objectives, the present invention provides a method for preparing a semiconductor structure, comprising:

[0007] A substrate is provided, the substrate including a substrate and a device isolation structure; wherein the device isolation structure is located on the upper surface of the substrate, the substrate is divided into device regions, and the device isolation structure is located within the device regions and forms the boundary of the device regions;

[0008] Simultaneously etch the device isolation structure and the substrate located in the device region to form a first trench penetrating the device isolation structure and a second trench located on the upper surface of the substrate in the device region, respectively;

[0009] The first trench and the second trench are filled with conductive material;

[0010] A first injection region is formed at the bottom of the substrate in the device region; the first injection region is in contact with the bottom of the first trench;

[0011] A drift region is formed in the substrate above the first implantation region in the device region; the drift region is of the opposite ion implantation type to the first implantation region;

[0012] A body region is formed around the second trench, a source region is formed on the upper surface of the body region next to the second trench, a drain region is formed on the side of the drift region away from the source region, and a gate structure is formed on the substrate between the source region and the drain region; wherein the body region is connected to the first implantation region and has the same ion implantation type; the ion implantation types of the source region and the drain region are opposite to those of the body region, and the depth of the source region is less than the depth of the second trench.

[0013] In one embodiment, the depth of the first trench is 0.5 micrometers to 1.5 micrometers, and the width of the first trench is 0.15 micrometers to 0.3 micrometers; the depth of the second trench is 0.5 micrometers to 1.5 micrometers, and the width of the second trench is 0.15 micrometers to 0.3 micrometers.

[0014] In one embodiment, before filling the first trench and the second trench with conductive material, the method further includes:

[0015] A second injection region is formed simultaneously on the periphery of the bottom of the first trench, and a third injection region is formed on the periphery of the bottom of the second trench; wherein the second injection region and the third injection region are of the same ion implantation type as the first injection region and the body region.

[0016] In one embodiment, a second injection area is formed on the periphery of the bottom of the first trench and a third injection area is formed on the periphery of the bottom of the second trench using an inclined injection method.

[0017] In one embodiment, the doping concentration of the third implantation region is greater than the doping concentration of the body region.

[0018] In one embodiment, the doping concentration of the third implantation region is 2e15. ~5e15 The doping concentration of the second implantation region is 2e15. ~5e15 The doping concentration of the body region is 2e12. ~2e13 .

[0019] In one embodiment, the substrate further includes a buried layer within a substrate below the device region and a well isolation structure located on the side of the device isolation structure opposite to the device region, the well isolation structure being spaced apart from the device isolation structure; after forming a drift region within the substrate above the first implantation region in the device region, the method further includes:

[0020] A first well region is formed in a substrate between the device isolation structure and the well region isolation structure, and a second well region is formed in a substrate on the side of the well region isolation structure away from the device region; wherein, the first well region is in contact with the buried layer, the first well region is spaced apart from the first implantation region, and the ion implantation types of the first well region and the buried layer are the same; and the ion implantation type of the second well region is opposite to that of the first well region.

[0021] Secondly, this application also provides a semiconductor structure, comprising:

[0022] A substrate includes a substrate and a device isolation structure; wherein the device isolation structure is located on the upper surface of the substrate, the substrate is divided into device regions, and the device isolation structure is located within the device regions and forms the boundary of the device regions;

[0023] The first trench penetrates the isolation structure of the device;

[0024] The second trench is located on the upper surface of the substrate in the device region; wherein the first trench and the second trench are formed simultaneously;

[0025] Conductive material is located in the first trench and the second trench;

[0026] The first injection region is located within the substrate at the bottom of the device region; the first injection region is in contact with the bottom of the first trench;

[0027] A body region is located within the substrate surrounding the second trench, and the body region is in communication with the first injection region;

[0028] The drift region is located within the substrate on both sides of the body region in the device region; the drift region is of the opposite ion implantation type to the first implantation region and the body region;

[0029] The source region is located on the upper surface of the body region beside the second trench;

[0030] The drain region is located on the side of the drift region away from the source region;

[0031] A gate structure is located on a substrate between the source region and the drain region; wherein the ion implantation types of the source region, the drain region and the body region are opposite, and the depth of the source region is less than the depth of the second trench.

[0032] In one embodiment, the depth of the first trench is 0.5 micrometers to 1.5 micrometers, and the width of the first trench is 0.15 micrometers to 0.3 micrometers; the depth of the second trench is 0.5 micrometers to 1.5 micrometers, and the width of the second trench is 0.15 micrometers to 0.3 micrometers.

[0033] In one embodiment, the semiconductor structure further includes:

[0034] The second injection area is located on the periphery of the bottom of the first trench;

[0035] The third injection zone is located on the periphery of the bottom of the second trench;

[0036] The second implantation region and the third implantation region are of the same ion implantation type as the first implantation region and the body region, and the second implantation region and the third implantation region are formed synchronously.

[0037] As described above, the semiconductor structure preparation method and semiconductor structure of the present invention have the following beneficial effects:

[0038] The present invention discloses a method for fabricating a semiconductor structure and the semiconductor structure thereof, comprising: providing a substrate, the substrate including a substrate and a device isolation structure; wherein the device isolation structure is located on the upper surface of the substrate, the substrate is divided into device regions, and the device isolation structure is located within the device regions and forms the boundary of the device regions; simultaneously etching the device isolation structure and the substrate located in the device regions to form a first trench penetrating the device isolation structure and a second trench located on the upper surface of the substrate in the device regions, respectively; filling the first trench and the second trench with conductive material; forming a first implantation region at the bottom of the substrate in the device regions; the first implantation region being in contact with the bottom of the first trench; forming a drift region in the substrate above the first implantation region in the device regions; the ion implantation type of the drift region being opposite to that of the first implantation region; forming a body region around the second trench, forming a source region on the upper surface of the body region next to the second trench, forming a drain region on the side of the drift region away from the source region, and forming a gate structure on the substrate between the source region and the drain region; wherein the body region is connected to the first implantation region and has the same ion implantation type; the ion implantation types of the source region and the drain region are opposite to those of the body region, and the depth of the source region is less than the depth of the second trench. This application simultaneously forms a first trench and a second trench, and fills the first trench and the second trench with conductive material. The first trench serves as the lead-out structure of the first injection region and is located within the device isolation structure, replacing the well region in the traditional process as the lead-out structure of the first injection region, thus reducing the device area. The second trench serves as the lead-out structure of the body region. While occupying a small area, its depth is greater than that of the source region, shortening the hole collection path and increasing the contact area between the lead-out structure and the body region, thereby increasing the area for collecting holes and improving the hole collection efficiency. While reducing the device area, it improves the device's withstand voltage and avoids increasing the device's specific on-resistance. In addition, the simultaneous formation of the first trench and the second trench improves the device fabrication efficiency. Attached Figure Description

[0039] The accompanying drawings, which form part of this specification, are used to provide a further understanding of the embodiments of this application and to illustrate the implementation of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application.

[0040] Figure 1 This is a schematic flowchart of a method for fabricating a semiconductor structure provided in one embodiment of this application;

[0041] Figure 2 This is a schematic diagram of the structure obtained in step S102 of the semiconductor structure fabrication method provided in an embodiment of this application;

[0042] Figure 3 , Figure 4 This is a schematic diagram of the structure obtained in step S104 of the semiconductor structure fabrication method provided in one embodiment of this application;

[0043] Figure 5 , Figure 6 This is a schematic diagram of the second injection region and the third injection region provided in one embodiment of this application;

[0044] Figure 7 This is a schematic diagram of the structure obtained in step S106 of the semiconductor structure fabrication method provided in an embodiment of this application;

[0045] Figure 8 This is a schematic diagram of the structure obtained in step S112 of the semiconductor structure fabrication method provided in one embodiment of this application.

[0046] Explanation of reference numerals in the attached figures: 102, substrate; 104, buried layer; 106, device isolation structure; 108, well isolation structure; 110, device region; 112, first window; 114, patterned mask; 116, patterned photoresist; 118, second window; 120, first trench; 122, second trench; 124, second implantation region; 126, third implantation region; 128, conductive material; 130, first implantation region; 132, drift region; 134, body region; 136, source region; 138, drain region; 142, gate oxide layer; 144, gate electrode; 146, gate sidewall; 152, first well region; 154, second well region. Detailed Implementation

[0047] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0048] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.

[0049] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0050] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0051] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0052] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0053] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0054] Please refer to Figure 1 The diagram shows a flow chart of a method for fabricating a semiconductor structure according to the present invention, which includes at least the following steps:

[0055] Step S102: Provide a substrate, the substrate including a substrate and a device isolation structure; wherein, the device isolation structure is located on the upper surface of the substrate, the substrate is divided into device regions, and the device isolation structure is located within the device regions and forms the boundary of the device regions;

[0056] Step S104: Simultaneously etch the device isolation structure and the substrate located in the device region to form a first trench penetrating the device isolation structure and a second trench located on the upper surface of the substrate in the device region, respectively.

[0057] Step S106: Fill the first trench and the second trench with conductive material;

[0058] Step S108: A first implantation region is formed at the bottom of the substrate in the device region; the first implantation region contacts the bottom of the first trench;

[0059] Step S110: A drift region is formed in the substrate above the first implantation region in the device region; the ion implantation type of the drift region is opposite to that of the first implantation region;

[0060] Step S112: A body region is formed around the second trench, a source region is formed on the upper surface of the body region next to the second trench, a drain region is formed on the side of the drift region away from the source region, and a gate structure is formed on the substrate between the source region and the drain region; wherein, the body region is connected to the first implantation region and the ion implantation type is the same; the ion implantation types of the source region, the drain region and the body region are opposite, and the depth of the source region is less than the depth of the second trench.

[0061] The following section, using a structural diagram, details the specific implementation methods for each of the above steps.

[0062] Please refer to Figure 2 Step S102: Provide a substrate, which includes a substrate 102 and a device isolation structure 106; wherein the device isolation structure 106 is located on the upper surface of the substrate 102, the substrate 102 is divided into device regions 110, and the device isolation structure 106 is located within the device regions 110 and forms the boundary of the device regions 110.

[0063] As an example, substrate 102 may be a P-type substrate, an N-type substrate, or an intrinsic material substrate. Substrate 102 may be constructed from semiconductor materials, insulating materials, conductive materials, or any combination thereof. Substrate 102 may be a single-layer structure or a multi-layer structure. For example, substrate 102 may be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V or II / VI semiconductor substrates. Alternatively, for example, substrate 102 may be a layered substrate comprising materials such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. Therefore, the type of substrate 102 should not limit the scope of this disclosure.

[0064] The device isolation structure 106 is used to isolate the device region 110 from other regions, preventing the device region 110 from being subjected to electrical interference. As an example, the device isolation structure 106 may include a shallow trench isolation structure.

[0065] Specifically, the width of the device isolation structure 106 is 0.6 micrometers to 5 micrometers, such as 0.6 micrometers, 1 micrometer, 1.5 micrometers, 2 micrometers, 2.5 micrometers, 3 micrometers, 3.5 micrometers, 4 micrometers, 4.5 micrometers, 5 micrometers, etc.

[0066] As an example, the substrate also includes a buried layer 104 in a substrate 102 located below the device region 110 and a well region isolation structure 108 located on the side of the device isolation structure 106 opposite to the device region 110, with the well region isolation structure 108 spaced apart from the device isolation structure 106.

[0067] Specifically, the buried layer 104 may be an N-type buried layer or a P-type buried layer. When the semiconductor device is an N-channel device, the buried layer 104 is an N-type buried layer; when the semiconductor device is a P-channel device, the buried layer 104 is a P-type buried layer. The doping concentration of the buried layer 104 is 2e15. ~5e15 For example, 2e15 2.75e15 3.5e15 4.25e15 5e15 wait.

[0068] Specifically, the well region isolation structure 108 is located on the side of the device isolation structure 106 opposite to the device region 110, and the well region isolation structure 108 is used to separate the first well region 152 and the second well region 154. The width of the well region isolation structure 108 is 0.2 micrometers to 2 micrometers, for example, 0.2 micrometers, 0.6 micrometers, 1 micrometer, 1.2 micrometers, 1.6 micrometers, 2 micrometers, etc. The well region isolation structure 108 may include a shallow trench isolation structure.

[0069] Please refer to Figure 3 , Figure 4 Step S104: Simultaneously etch the device isolation structure 106 and the substrate 102 located in the device region 110 to form a first trench 120 penetrating the device isolation structure 106 and a second trench 122 located on the upper surface of the substrate 102 in the device region 110, respectively.

[0070] As an example, a device isolation structure 106 and a substrate 102 located in the device region 110 are etched based on a patterned mask 114 to form a first trench 120 penetrating the device isolation structure 106 and a second trench 122 located on the upper surface of the substrate 102 in the device region 110, respectively. The patterned mask 114 includes a first window 112 exposing the first trench 120 and a second window 118 exposing the second trench 122. The patterned mask 114 is etched based on a patterned photoresist 116. The material of the patterned mask 114 may include silicon nitride or oxide.

[0071] As an example, the depth of the first trench 120 is 0.5 micrometers to 1.5 micrometers, such as 0.5 micrometers, 0.75 micrometers, 1 micrometer, 1.25 micrometers, 1.5 micrometers, etc. The width of the first trench 120 is 0.15 micrometers to 0.3 micrometers, such as 0.15 micrometers, 0.2 micrometers, 0.25 micrometers, 0.3 micrometers, etc. The depth of the second trench 122 is 0.5 micrometers to 1.5 micrometers, such as 0.5 micrometers, 0.75 micrometers, 1 micrometer, 1.25 micrometers, 1.5 micrometers, etc. The width of the second trench 122 is 0.15 micrometers to 0.3 micrometers, such as 0.15 micrometers, 0.2 micrometers, 0.25 micrometers, 0.3 micrometers, etc.

[0072] For example, please refer to Figure 5 , Figure 6 Before filling the first trench 120 and the second trench 122 with conductive material 128, the method further includes: simultaneously forming a second implantation region 124 on the bottom periphery of the first trench 120 and a third implantation region 126 on the bottom periphery of the second trench 122; wherein the second implantation region 124 and the third implantation region 126 are of the same ion implantation type as the first implantation region 130 and the body region 134.

[0073] Specifically, based on the patterned mask 114, a second injection area 124 can be formed on the bottom periphery of the first trench 120 and a third injection area 126 can be formed on the bottom periphery of the second trench 122 using an inclined injection method, thereby making the range of the second injection area 124 and the third injection area 126 at the bottom of the first trench 120 and the second trench 122 wider. After the second injection area 124 and the third injection area 126 are formed, the patterned mask 114 is removed.

[0074] Specifically, the doping concentration of the third implantation region 126 is greater than that of the body region 134, thereby increasing the doping concentration around the second trench 122, reducing the resistance around the second trench 122, and consequently reducing the voltage drop on the hole collection path, thus avoiding latch-up. The doping concentration of the third implantation region 126 is 2e15. ~5e15 For example, 2e15 2.75e15 3.5e15 4.25e15 5e15 etc.; the doping concentration of the second implantation region 124 is 2e15. ~5e15 For example, 2e15 2.75e15 3.5e15 4.25e15 5e15 The doping concentration of body region 134 is 2e12. ~2e13 For example, 2e12 6.5e12 1e13 1.55e13 2e13 wait.

[0075] Please refer to Figure 7 Step S106: Fill the first trench 120 and the second trench 122 with conductive material 128.

[0076] As an example, the conductive material 128 may be one or more of polycrystalline silicon, tungsten, copper, aluminum, cobalt, ruthenium, titanium, tantalum, titanium nitride, tantalum nitride, and tungsten nitride. Preferably, the conductive material 128 is doped polycrystalline silicon. The doping type of the polycrystalline silicon in the first trench 120 is the same as the ion implantation type of the first implantation region 130, and the doping type of the polycrystalline silicon in the second trench 122 is the same as the ion implantation type of the body region 134.

[0077] Step S108: A first implantation region 130 is formed at the bottom of the substrate 102 of the device region 110.

[0078] As an example, the first implantation region 130 may include an N-type first implantation region 130 or a P-type first implantation region 130. When the semiconductor device is an N-channel device, the first implantation region 130 is a P-type first implantation region 130, and when the semiconductor device is a P-channel device, the first implantation region 130 is an N-type first implantation region 130.

[0079] As an example, the doping concentration of the first implantation region 130 is 2e12. ~2e13 For example, 2e12 6.5e12 1e13 1.55e13 2e13 wait.

[0080] Step S110: A drift region 132 is formed in the substrate 102 above the first implantation region 130 in the device region 110; the ion implantation type of the drift region 132 is opposite to that of the first implantation region 130.

[0081] As an example, the first implantation region 130 and the drift region 132 can be implanted using the same mask. The doping concentration of the drift region 132 is 2e12. ~2e13 For example, 2e12 6.5e12 1e13 1.55e13 2e13 wait.

[0082] As an example, after forming a drift region 132 in the substrate 102 above the first implantation region 130 in the device region 110, the method further includes: forming a first well region 152 in the substrate 102 located between the device isolation structure 106 and the well region isolation structure 108, and a second well region 154 in the substrate 102 located on the side of the well region isolation structure 108 away from the device region 110; wherein, the first well region 152 is in contact with the buried layer 104, the first well region 152 is spaced from the first implantation region 130, and the ion implantation types of the first well region 152 and the buried layer 104 are the same; the ion implantation type of the second well region 154 is opposite to that of the first well region 152.

[0083] Specifically, the width of the first well region 152 is 4 micrometers to 7 micrometers, for example, 4 micrometers, 5 micrometers, 6 micrometers, 7 micrometers, etc. The width of the second well region 154 is 4 micrometers to 7 micrometers, for example, 4 micrometers, 5 micrometers, 6 micrometers, 7 micrometers, etc.

[0084] Please refer to Figure 8 Step S112 is executed as follows: a body region 134 is formed around the second trench 122; a source region 136 is formed on the upper surface of the body region 134 beside the second trench 122; a drain region 138 is formed on the side of the drift region 132 away from the source region 136; and a gate structure is formed on the substrate 102 between the source region 136 and the drain region 138; wherein the body region 134 is connected to the first implantation region 130 and has the same ion implantation type; the ion implantation types of the source region 136 and the drain region 138 are opposite to those of the body region 134, and the depth of the source region 136 is less than the depth of the second trench 122.

[0085] As an example, a body region 134 is formed within a drift region 132 surrounding the second trench 122. The body region 134 is connected to the first implantation region 130 and has the same ion implantation type as the first implantation region 130. Preferably, the body region 134 may include a first region and a second region, with the first region located above the second region. The width of the first region is greater than the width of the second region, thereby further shortening the hole collection path.

[0086] As an example, the self-aligned implantation formation region 134 can be based on the mask forming region 134 or on the gate structure.

[0087] Specifically, the doping concentration of body region 134 is 2e12. ~2e13 For example, 2e12 6.5e12 1e13 1.55e13 2e13 wait.

[0088] Specifically, the doping concentration of source region 136 is 2e15. -5e15 For example, 2e15 2.75e15 3.5e15 4.25e15 5e15 The doping concentration of drain region 138 is 2e15. ~5e15 For example, 2e15 2.75e15 3.5e15 4.25e15 5e15 wait.

[0089] Specifically, the gate structure includes a gate oxide layer 142 and a gate electrode 144 sequentially stacked on the substrate 102, and a gate sidewall 146 located on the sidewalls of the gate oxide layer 142 and the gate electrode 144.

[0090] Thus, a semiconductor structure is fabricated, comprising: a substrate, a first trench 120, a second trench 122, a conductive material 128, a first implantation region 130, a body region 134, a drift region 132, a source region 136, a drain region 138, and a gate structure; the substrate includes a substrate 102 and a device isolation structure 106; the device isolation structure 106 is located on the upper surface of the substrate 102, the substrate 102 is divided into device regions 110, and the device isolation structure 106 is located within the device regions 110 and forms the boundary of the device regions 110; the first trench 120 penetrates the device isolation structure 106; the second trench 122 is located on the upper surface of the substrate 102 of the device regions 110; wherein, the first trench 120 and the second trench 122 are formed simultaneously; the conductive material 128 is located within the first trench 120 and the second trench 122; the first implantation region 130, the body region 134, the drift region 132, the source region 136, the drain region 138, and the gate structure; the substrate includes a substrate 102 and a device isolation structure 106; the first trench 120 penetrates the device isolation structure 106; the second trench 122 is located on the upper surface of the substrate 102 of the device regions 110; wherein, the first trench 120 and the second trench 122 are formed simultaneously; the conductive material 128 is located within the first trench 120 and the second trench 122; the first implantation region 130, the body region 134, the drift region 135, the source region 136, the drain region 138, and the gate structure 136; the first trench 120, the body region 134, the drift region 135, the source region 136, 30 is located in the substrate 102 at the bottom of device region 110; the first implantation region 130 is in contact with the bottom of the first trench 120; the body region 134 is located in the substrate 102 surrounding the second trench 122, and the body region 134 is connected to the first implantation region 130; the drift region 132 is located in the substrate 102 on both sides of the body region 134 in device region 110; the ion implantation type of the drift region 132 is opposite to that of the first implantation region 130 and the body region 134; the source region 136 is located on the upper surface of the body region 134 beside the second trench 122; the drain region 138 is located on the side of the drift region 132 away from the source region 136; the gate structure is located on the substrate 102 between the source region 136 and the drain region 138; wherein, the ion implantation type of the source region 136 and the drain region 138 is opposite to that of the body region 134, and the depth of the source region 136 is less than the depth of the second trench 122.

[0091] As an example, the first trench 120 has a depth of 0.5 micrometers to 1.5 micrometers and a width of 0.15 micrometers to 0.3 micrometers; the second trench 122 has a depth of 0.5 micrometers to 1.5 micrometers and a width of 0.15 micrometers to 0.3 micrometers.

[0092] As an example, the semiconductor structure further includes a second implantation region 124 and a third implantation region 126; wherein the second implantation region 124 is located on the bottom periphery of the first trench 120; the third implantation region 126 is located on the bottom periphery of the second trench 122; the second implantation region 124 and the third implantation region 126 are of the same ion implantation type as the first implantation region 130 and the body region 134, and the second implantation region 124 and the third implantation region 126 are formed synchronously.

[0093] Specifically, the doping concentration of the third implantation region 126 is greater than that of the body region 134. The doping concentration of the third implantation region 126 is 2e15. ~5e15 The doping concentration of the second implantation region 124 is 2e15. ~5e15 The doping concentration of body region 134 is 2e12. ~2e13 .

[0094] As an example, the substrate also includes a buried layer 104 in a substrate 102 located below the device region 110 and a well region isolation structure 108 located on the side of the device isolation structure 106 facing away from the device region 110, with the well region isolation structure 108 spaced apart from the device isolation structure 106; the semiconductor structure also includes a first well region 152 and a second well region 154; the first well region 152 is located in the substrate 102 between the device isolation structure 106 and the well region isolation structure 108 and the second well region 154 is located in the substrate 102 on the side of the well region isolation structure 108 facing away from the device region 110; the first well region 152 is in contact with the buried layer 104 and is spaced apart from the first implantation region 130, and the ion implantation types of the first well region 152 and the buried layer 104 are the same; the ion implantation type of the second well region 154 is opposite to that of the first well region 152.

[0095] In summary, the semiconductor structure fabrication method and semiconductor structure of the present invention include: providing a substrate, the substrate including a substrate and a device isolation structure; wherein the substrate is divided into device regions, the device isolation structure is located on the upper surface of the substrate, the substrate is divided into device regions, and the device isolation structure is located within the device regions and forms the boundary of the device regions; simultaneously etching the device isolation structure and the substrate located in the device regions to respectively form a first trench penetrating the device isolation structure and a second trench located on the upper surface of the substrate in the device regions; filling the first trench and the second trench with conductive material; and etching the substrate in the device regions... A first implantation region is formed at the bottom of the first trench; the first implantation region is in contact with the bottom of the first trench; a drift region is formed in the substrate above the first implantation region in the device region; the ion implantation type of the drift region is opposite to that of the first implantation region; a body region is formed around the second trench, a source region is formed on the upper surface of the body region next to the second trench, a drain region is formed on the side of the drift region away from the source region, and a gate structure is formed on the substrate between the source region and the drain region; wherein the body region is connected to the first implantation region and the ion implantation type is the same; the ion implantation types of the source region, drain region and body region are opposite, and the depth of the source region is less than the depth of the second trench. This application simultaneously forms a first trench and a second trench, filling both with conductive material. The first trench serves as the lead-out structure for the first injection region, located within the device isolation structure. It replaces the well region in traditional processes as the lead-out structure for the first injection region, reducing the device area. The second trench serves as the lead-out structure for the body region. While occupying a small area, its depth is greater than that of the source region, shortening the hole collection path and increasing the contact area between the lead-out structure and the body region, thus increasing the hole collection area and improving hole collection efficiency. This reduces the device area while improving the device's withstand voltage and avoiding an increase in specific on-resistance. Furthermore, the simultaneous formation of the first and second trenches improves the device fabrication efficiency. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial applicability.

[0096] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, The method for preparing the semiconductor structure includes: A substrate is provided, the substrate including a substrate and a device isolation structure; wherein the device isolation structure is located on the upper surface of the substrate, the substrate is divided into device regions, and the device isolation structure is located within the device regions and forms the boundary of the device regions; Simultaneously etch the device isolation structure and the substrate located in the device region to form a first trench penetrating the device isolation structure and a second trench located on the upper surface of the substrate in the device region, respectively; The first trench and the second trench are filled with conductive material; A first injection region is formed at the bottom of the substrate in the device region; the first injection region is in contact with the bottom of the first trench; A drift region is formed in the substrate above the first implantation region in the device region; the drift region is of the opposite ion implantation type to the first implantation region; A body region is formed around the second trench, a source region is formed on the upper surface of the body region next to the second trench, a drain region is formed on the side of the drift region away from the source region, and a gate structure is formed on the substrate between the source region and the drain region; wherein the body region is connected to the first implantation region and has the same ion implantation type; the ion implantation types of the source region and the drain region are opposite to those of the body region, and the depth of the source region is less than the depth of the second trench.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The first trench has a depth of 0.5 micrometers to 1.5 micrometers and a width of 0.15 micrometers to 0.3 micrometers; the second trench has a depth of 0.5 micrometers to 1.5 micrometers and a width of 0.15 micrometers to 0.3 micrometers.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that, Before filling the first trench and the second trench with conductive material, the method further includes: A second injection region is formed simultaneously on the periphery of the bottom of the first trench, and a third injection region is formed on the periphery of the bottom of the second trench; wherein the second injection region and the third injection region are of the same ion implantation type as the first injection region and the body region.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that, A second injection area is formed on the periphery of the bottom of the first trench and a third injection area is formed on the periphery of the bottom of the second trench by means of inclined injection.

5. The method for preparing a semiconductor structure according to claim 3, characterized in that, The doping concentration of the third implantation region is greater than the doping concentration of the body region.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that, The doping concentration of the third implantation region is 2e15. ~5e15 The doping concentration of the second implantation region is 2e15. ~5e15 The doping concentration of the body region is 2e12. ~2e13 .

7. The method for preparing a semiconductor structure according to claim 1, characterized in that, The substrate further includes a buried layer within a substrate located below the device region and a well region isolation structure located on the side of the device isolation structure opposite to the device region, wherein the well region isolation structure is spaced apart from the device isolation structure; After forming a drift region in the substrate above the first implantation region in the device region, the method further includes: A first well region is formed in a substrate between the device isolation structure and the well region isolation structure, and a second well region is formed in a substrate on the side of the well region isolation structure away from the device region; wherein, the first well region is in contact with the buried layer, the first well region is spaced apart from the first implantation region, and the ion implantation types of the first well region and the buried layer are the same; the ion implantation type of the second well region is opposite to that of the first well region.

8. A semiconductor structure, characterized in that, include: A substrate includes a substrate and a device isolation structure; wherein the device isolation structure is located on the upper surface of the substrate, the substrate is divided into device regions, and the device isolation structure is located within the device regions and forms the boundary of the device regions; The first trench penetrates the isolation structure of the device; The second trench is located on the upper surface of the substrate in the device region; wherein the first trench and the second trench are formed simultaneously; Conductive material is located in the first trench and the second trench; The first injection region is located within the substrate at the bottom of the device region; the first injection region is in contact with the bottom of the first trench; A body region is located within the substrate surrounding the second trench, and the body region is in communication with the first injection region; The drift region is located within the substrate on both sides of the body region in the device region; the drift region is of the opposite ion implantation type to the first implantation region and the body region; The source region is located on the upper surface of the body region beside the second trench; The drain region is located on the side of the drift region away from the source region; A gate structure is located on a substrate between the source region and the drain region; wherein the ion implantation types of the source region, the drain region and the body region are opposite, and the depth of the source region is less than the depth of the second trench.

9. The semiconductor structure according to claim 8, characterized in that, The first trench has a depth of 0.5 micrometers to 1.5 micrometers and a width of 0.15 micrometers to 0.3 micrometers; the second trench has a depth of 0.5 micrometers to 1.5 micrometers and a width of 0.15 micrometers to 0.3 micrometers.

10. The semiconductor structure according to claim 8, characterized in that, The semiconductor structure also includes: The second injection area is located on the periphery of the bottom of the first trench; The third injection zone is located on the periphery of the bottom of the second trench; The second and third implantation regions are of the same ion implantation type as the first and body regions, and the second and third implantation regions are formed synchronously.

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