Semifloating gate transistor contact hole forming method, semifloating gate transistor and preparation method

Abstract

The application relates to the technical field of semiconductors, and discloses a method for forming a contact window of a semi-floating gate transistor, a semi-floating gate transistor and a preparation method, which comprises the following steps: providing an intermediate product, which comprises a semiconductor substrate and a pad oxide layer and a pad nitride layer which are sequentially stacked, a first groove is formed in the semiconductor substrate, a gate dielectric layer is formed on the sidewall and the bottom of the first groove, and a floating gate layer is filled in the first groove and has a top surface which is flush with the pad nitride layer; a second groove is formed by patterning the floating gate layer, the second groove exposes the sidewall of the pad nitride layer and has a bottom surface which is flush with the pad oxide layer; the pad nitride layer is laterally etched back to expose part of the pad oxide layer; and the exposed pad oxide layer is removed to form a contact window of the exposed semiconductor substrate at the bottom of the second groove. The application can relax the key size limit of the photolithography process to reduce the manufacturing cost, break through the resolution limit of photolithography to realize a super-small size contact window, eliminate the influence of overlay error on the size of the window, and improve the uniformity of the device performance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, specifically to a method for forming a contact window of a semi-floating gate transistor, a semi-floating gate transistor, and a fabrication method thereof. Background Technology

[0002] The floating gate of a semi-floating-gate transistor (SFGT) needs to be electrically connected to the semiconductor substrate through a specific contact window. This structure is the key path to achieve efficient charge injection and erasure.

[0003] In the fabrication of semi-floating gate transistors, the dimensional accuracy and morphological consistency of the contact window are key factors determining the uniformity of the device's erase and write speeds. Existing technologies typically employ the following process flow to form the contact window: [See details] Figures 1a to 1c As shown, the window area is defined by the photoresist layer 900; the floating gate polysilicon 910 and the underlying insulating layer 920 (such as SiO2) are etched to expose the semiconductor substrate 100 and form a contact window.

[0004] This solution has significant technical flaws:

[0005] 1. Lithography alignment errors cause window size fluctuations: Even with high-end ArF immersion lithography (ArFi) equipment, the overlay (OVL) control capability at the 40nm technology node is only ±6nm. This error will directly cause a 12nm fluctuation in the critical dimensions of the contact window, severely affecting the consistency of the window size. Size fluctuations will cause differences in erase and write speeds between devices, reducing chip yield and reliability.

[0006] 2. High equipment costs and technological barriers: ArF immersion lithography machines are expensive (over $100 million per unit) and the complexity of process control increases significantly, leading to a sharp rise in production costs, which is not conducive to the large-scale industrial application of the technology. Summary of the Invention

[0007] The purpose of this invention is to provide a method for forming a contact window of a semi-floating gate transistor, a semi-floating gate transistor and a fabrication method, which can relax the key size restrictions of the photolithography process to significantly reduce manufacturing costs, break through the photolithography resolution limit to achieve ultra-small contact windows, effectively eliminate the influence of overlay errors on window size, and greatly improve the consistency of contact window size and the uniformity of device performance.

[0008] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0009] In a first aspect, the present invention provides a method for forming a contact window of a semi-floating gate transistor, comprising:

[0010] An intermediate product is provided, the intermediate product including a semiconductor substrate, and a pad oxide layer and a pad nitride layer sequentially stacked on the surface of the semiconductor substrate in a vertical direction; a first trench is formed in the semiconductor substrate, a gate dielectric layer is formed on the sidewalls and bottom surface of the first trench, a floating gate layer is filled in the first trench, and the top surface of the floating gate layer is flush with the top surface of the pad nitride layer.

[0011] The floating grid layer is patterned, and a second trench is formed within the floating grid layer. The second trench extends downward and exposes the sidewalls of the pad nitride layer. The bottom surface of the second trench is flush with the top surface of the pad oxide layer.

[0012] The pad nitride layer is etched back laterally to expose a portion of the pad oxide layer on the surface of the semiconductor substrate;

[0013] Remove the exposed pad oxide layer to form a contact window at the bottom of the second trench that exposes the semiconductor substrate.

[0014] In one embodiment of the present invention, patterning the floating gate layer and forming a second trench within the floating gate layer specifically includes: forming a patterned photomask on the surfaces of the pad nitride layer and the floating gate layer, the photomask having an opening that exposes the top surface of the floating gate layer in the area to be etched, and covering the surface of the pad nitride layer in the non-etched area; using the photomask and the pad nitride layer together as an etching mask to etch the exposed floating gate layer to form the second trench; and removing the photomask.

[0015] In one embodiment of the present invention, the preparation of the intermediate product includes: forming a first conductivity type well region and a second conductivity type well region in a semiconductor substrate by ion implantation; sequentially depositing a pad oxide layer and a pad nitride layer on the surface of the semiconductor substrate; performing dry etching on the pad nitride layer, the pad oxide layer and the semiconductor substrate to form a first trench that penetrates the pad nitride layer and the pad oxide layer and extends into the semiconductor substrate; forming a gate dielectric layer on the sidewalls and bottom surface of the first trench; depositing a floating gate material in the first trench and performing chemical mechanical polishing to make the top surface of the floating gate layer flush with the top surface of the pad nitride layer.

[0016] In one embodiment of the present invention, the first conductivity type well region is a P-type well region, and the second conductivity type well region is an N-type well region.

[0017] In one embodiment of the present invention, the lateral etching of the pad nitride layer includes: isotropic etching of the pad nitride layer using a hot phosphoric acid wet etching process, so that the sidewall of the pad nitride layer is recessed inward relative to the sidewall of the pad oxide layer.

[0018] In one embodiment of the present invention, the removal of the exposed pad oxide layer includes: performing wet etching on the exposed pad oxide layer using a buffered oxide etching solution or a dilute hydrofluoric acid solution to completely remove the pad oxide layer at the bottom of the second trench and expose the surface of the semiconductor substrate.

[0019] In one embodiment of the present invention, after forming the contact window, the method further includes: depositing a conductive material layer in the second trench and the contact window, the conductive material layer filling the contact window and electrically connecting to the semiconductor substrate; and performing chemical mechanical polishing on the conductive material layer so that the top surface of the conductive material layer is flush with the top surface of the pad nitride layer.

[0020] In one embodiment of the present invention, the conductive material layer is made of the same material as the floating gate layer.

[0021] Secondly, the present invention provides a method for fabricating a semi-floating gate transistor, comprising:

[0022] Using the above-described method for forming the contact window of a semi-floating gate transistor, a contact window exposing the semiconductor substrate is formed at the bottom of the second trench;

[0023] A floating gate layer material is deposited again in the second trench, so that the floating gate layer material fills the contact window and is electrically connected to the semiconductor substrate;

[0024] The floating gate layer material is subjected to chemical mechanical polishing so that the top surface of the floating gate layer material is flush with the top surface of the pad nitride layer;

[0025] The pad nitride layer is removed using a wet etching process to expose the pad oxide layer;

[0026] A floating gate layer material is deposited again on the semiconductor substrate;

[0027] The re-deposited floating gate layer material is chemically and mechanically polished to ensure that the top surface of the floating gate layer material retains a predetermined height.

[0028] A tunneling dielectric layer and a control gate layer are sequentially deposited on top of the floating gate layer material;

[0029] A polysilicon photomask is used for exposure and development to etch away excess floating gate layer, tunneling dielectric layer and control gate layer, forming a semi-floating gate transistor.

[0030] Thirdly, the present invention provides a semi-floating gate transistor, which is prepared by the above-described preparation method.

[0031] The present invention has the following beneficial effects:

[0032] 1. This invention, through innovative process architecture design, significantly relaxes the critical photolithography dimensions used to define the contact window region. Compared to existing technologies that require shrinking the photolithography dimension CD to 60nm~80nm and rely on expensive ArF immersion lithography equipment, this invention only requires a mature and stable KrF lithography equipment to complete the exposure process. Because KrF lithography technology was developed earlier, its equipment, materials, and process systems are all very mature and stable, offering significant advantages such as low equipment and material costs, wide process tolerance, and high mass production yield.

[0033] 2. This invention uses a lateral etching-back process with a pad nitride layer to define the final size of the contact window, rather than directly relying on photolithography resolution. By precisely controlling the lateral removal thickness of the pad nitride layer, the critical size of the contact window can be reduced to the 10nm level. Compared to existing technologies that require upgrading to higher-end EUV lithography equipment or employing complex techniques such as ArF immersion lithography combined with multiple patterning to fabricate smaller contact windows, this invention achieves the fabrication of ultra-small windows through process optimization alone, without upgrading lithography equipment. This significantly lowers the technical threshold and manufacturing cost, providing a feasible process path for the continuous miniaturization of semi-floating gate transistors.

[0034] 3. This invention, through process decoupling design, completely eliminates the impact of overlay errors on the final critical dimensions of the contact window: photolithography overlay errors only affect the size and position of the etched window in the floating gate layer; the final critical dimensions of the contact window are entirely determined by the thickness of the lateral etching back of the pad nitride layer, and are only affected by the thickness control fluctuations of the etching process itself. Since the wet etching process has a much higher precision in controlling film thickness than photolithography overlay, this invention significantly narrows the fluctuation range of the critical dimensions of the contact window, significantly improving the consistency of contact window dimensions in the device array, thereby ensuring the uniformity of the erase / write speed of the semi-floating gate transistor and the reliability of the device.

[0035] 4. The contact window formation method of the present invention does not require the introduction of additional complex process steps. It only requires adding a wet lateral etching process to the existing process flow to achieve precise definition of the contact window. This wet etching process is a conventional and mature process in semiconductor manufacturing, which is fully compatible with existing CMOS production line equipment. No new dedicated equipment is required, which is conducive to the rapid introduction and industrialization of the technology. Attached Figure Description

[0036] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1a A schematic cross-sectional view of the contact window region defined in the prior art.

[0038] Figure 1b This is a schematic cross-sectional view of the etching of floating gate polysilicon in the prior art.

[0039] Figure 1c This is a schematic cross-sectional view of the contact window after it has been formed in the prior art.

[0040] Figure 2 This is a schematic flowchart of the method for forming a semi-floating gate transistor contact window disclosed in an embodiment of this application.

[0041] Figure 3a This is a schematic cross-sectional view of a patterned photomask formed on the surface of a floating grating layer, as disclosed in an embodiment of this application.

[0042] Figure 3b This is a schematic cross-sectional view of the etching of the floating gate layer to form a second trench as disclosed in the embodiments of this application.

[0043] Figure 3c This is a schematic cross-sectional view of the lateral etching of the pad nitride layer disclosed in the embodiments of this application.

[0044] Figure 3d This is a schematic cross-sectional view of the process of removing the exposed pad oxide layer to form a contact window, as disclosed in an embodiment of this application.

[0045] Figure 4a This is a schematic cross-sectional view of a semiconductor substrate disclosed in an embodiment of this application.

[0046] Figure 4b This is a schematic cross-sectional view of the formation of a first conductivity type well region and a second conductivity type well region as disclosed in the embodiments of this application.

[0047] Figure 4c This is a schematic cross-sectional view of the deposition of an oxide layer and a nitride layer and the formation of a photoresist layer as disclosed in the embodiments of this application.

[0048] Figure 4d This is a schematic cross-sectional view of the formation of the first trench as disclosed in an embodiment of this application.

[0049] Figure 4e This is a schematic cross-sectional view of the formation of the gate dielectric layer disclosed in the embodiments of this application.

[0050] Figure 4f This is a schematic cross-sectional view of the formation of a floating gate layer and chemical mechanical polishing as disclosed in an embodiment of this application.

[0051] Figure 5a This is a schematic cross-sectional view of the deposition of the floating grid layer material in the second trench and contact window as disclosed in the embodiments of this application.

[0052] Figure 5b This is a schematic cross-sectional view of the chemical mechanical polishing of the floating gate layer material disclosed in an embodiment of this application.

[0053] Figure 5c This is a schematic cross-sectional view of the removal of the nitride layer in the pad disclosed in an embodiment of this application.

[0054] Figure 5d This is a schematic cross-sectional view of the re-deposited floating gate layer material disclosed in an embodiment of this application.

[0055] Figure 5e This is a schematic cross-sectional view of the chemical mechanical polishing of the re-deposited floating gate layer material disclosed in an embodiment of this application.

[0056] Figure 5f This is a schematic cross-sectional view of the deposited tunneling medium layer and control gate layer disclosed in the embodiments of this application.

[0057] Figure 5g This is a schematic cross-sectional view of the photoresist coating layer disclosed in the embodiments of this application.

[0058] Figure 5h This is a schematic cross-sectional view of the formation of a semi-floating gate transistor as disclosed in an embodiment of this application.

[0059] In the above figures, the meanings of the reference numerals are as follows:

[0060] 100 - Semiconductor substrate, 110 - First trench, 120 - First conductivity type well region, 130 - Second conductivity type well region, 140 - Contact window, 200 - Pad oxide layer, 300 - Pad nitride layer, 400 - Gate dielectric layer, 500 - Floating gate layer, 510 - Second trench, 600 - Photomask, 700 - Tunneling dielectric layer, 800 - Control gate layer, 900 - Photoresist layer, 910 - Floating gate polysilicon, 920 - Insulating layer. Detailed Implementation

[0061] The embodiments of the present invention will be described below with reference to the accompanying drawings and preferred embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be understood that the preferred embodiments are only for illustrating the present invention and not for limiting the scope of protection of the present invention.

[0062] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the shape, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0063] See Figure 2 As shown, Figure 2 This is a schematic flowchart illustrating the method for forming a semi-floating gate transistor contact window disclosed in an embodiment of this application. This embodiment provides a method for forming a semi-floating gate transistor contact window, which includes the following steps:

[0064] Step S1: Provide an intermediate product. The intermediate product includes a semiconductor substrate 100, and a pad oxide layer 200 and a pad nitride layer 300 sequentially stacked on the surface of the semiconductor substrate 100 in a vertical direction. A first trench 110 is formed in the semiconductor substrate 100, and a gate dielectric layer 400 is formed on the sidewalls and bottom surface of the first trench 110. A floating gate layer 500 is filled in the first trench 110, and the top surface of the floating gate layer 500 is flush with the top surface of the pad nitride layer 300.

[0065] Step S2: Pattern the floating gate layer 500 and form a second trench 510 within the floating gate layer 500. The second trench 510 extends downward and exposes the sidewalls of the pad nitride layer 300, with the bottom surface of the second trench 510 flush with the top surface of the pad oxide layer 200.

[0066] Step S3: Pull-back the pad nitride layer 300 to expose a portion of the pad oxide layer 200 on the surface of the semiconductor substrate 100.

[0067] Step S4: Remove the exposed pad oxide layer 200 to form a contact window 140 at the bottom of the second trench 510 that exposes the semiconductor substrate 100.

[0068] The following detailed explanation of each step is provided in conjunction with the accompanying drawings.

[0069] Step S1: Provide intermediate products. See [link / reference] Figures 4a to 4f As shown, Figures 4a to 4f This is a schematic cross-sectional view of some stages in the formation process of the intermediate product disclosed in the embodiments of this application.

[0070] In this embodiment, the preparation process of the intermediate product is as follows:

[0071] First step, refer to Figure 4a and Figure 4bAs shown, a semiconductor substrate 100 is provided. The semiconductor substrate 100 can be a silicon substrate, a germanium-silicon substrate, a silicon-on-insulator (SOI) substrate, etc. This embodiment uses a silicon substrate as an example. A first conductivity type well region 120 and a second conductivity type well region 130 are formed within the semiconductor substrate 100 using an ion implantation process. In this embodiment, the first conductivity type well region 120 is a P-type well region (P-Well), and the second conductivity type well region 130 is an N-type well region (N-Well). The doping type, dosage, and energy of the ion implantation can be adjusted according to the device design requirements, and will not be elaborated here.

[0072] Step 2, see Figure 4c As shown, a pad oxide layer 200 and a pad nitride layer 300 are sequentially deposited on the surface of the semiconductor substrate 100. The pad oxide layer 200 can be made of silicon dioxide (SiO2) and can be formed by thermal oxidation or chemical vapor deposition (CVD) processes. Its thickness can be 5 nm to 20 nm, preferably 10 nm. The pad nitride layer 300 can be made of silicon nitride (SiN) and can be formed by low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD) processes. Its thickness can be 50 nm to 200 nm, preferably 100 nm. The pad oxide layer 200 serves as an etching stop layer during subsequent wet etching of the pad nitride layer 300, and also buffers stress and protects the surface of the semiconductor substrate 100.

[0073] Step 3, see Figure 4c As shown, dry etching is performed on the pad nitride layer 300, pad oxide layer 200, and semiconductor substrate 100 to form a first trench 110 that penetrates the pad nitride layer 300 and pad oxide layer 200 and extends into the semiconductor substrate 100. Specifically, a patterned photoresist layer 900 can be formed on the surface of the pad nitride layer 300 using photolithography. Then, using the photoresist layer 900 as a mask, an anisotropic dry etching process (such as reactive ion etching, RIE) is used to sequentially etch the pad nitride layer 300, pad oxide layer 200, and a portion of the semiconductor substrate 100 to form the first trench 110. (See also...) Figure 4d As shown, the depth of the first trench 110 can be set according to device design requirements, for example, it can extend to the first conductive type well region 120 under the semiconductor substrate 100. After etching is completed, the photoresist layer 900 is removed.

[0074] Step 4, refer to Figure 4e As shown, a gate dielectric layer 400 is formed on the sidewalls and bottom surface of the first trench 110. The gate dielectric layer 400 can be a silicon oxide layer, a high-k dielectric layer, or a combination thereof. In this embodiment, the gate dielectric layer 400 is a silicon dioxide layer formed by a thermal oxidation process, and its thickness can be 5 nm to 15 nm. The gate dielectric layer 400 is used to isolate the floating gate layer 500 from the semiconductor substrate 100 in subsequent processes to prevent charge leakage.

[0075] Step 5, refer to Figure 4f As shown, floating gate material is deposited within the first trench 110 to form a floating gate layer 500, and then chemical mechanical polishing (CMP) is performed to make the top surface of the floating gate layer 500 flush with the top surface of the pad nitride layer 300. The floating gate layer 500 can be made of polycrystalline silicon, which can be deposited using a chemical vapor deposition process. The deposited floating gate material fills the first trench 110 and covers the surface of the pad nitride layer 300. Subsequently, the excess floating gate material outside the first trench 110 is removed by a chemical mechanical polishing process, making the top surface of the floating gate layer 500 substantially flush with the top surface of the pad nitride layer 300, forming a flat surface morphology, which provides a good process foundation for subsequent photolithography and etching processes.

[0076] Step S2: Pattern the floating gate layer to form a second trench: See Figure 3a and Figure 3b As shown, Figures 3a to 3d This is a schematic cross-sectional view of some stages in the formation process of the semi-floating gate transistor contact window disclosed in the embodiments of this application.

[0077] In this embodiment, the specific process of patterning the floating gate layer 500 to form the second trench 510 within the floating gate layer 500 is as follows:

[0078] First step, refer to Figure 3a As shown, a patterned photomask 600 is formed on the surfaces of the pad nitride layer 300 and the floating gate layer 500. The photomask 600 (i.e., the patterned photoresist layer) has an opening that exposes the top surface of the floating gate layer 500 in the area to be etched, and covers the surface of the pad nitride layer 300 in the non-etched area.

[0079] It is important to note that, because this invention defines the contact window size through a subsequent lateral etch-back process using a pad nitride layer, the aperture size of the photomask 600 can be significantly increased. Taking the 40nm technology node as an example, the aperture size of the photomask 600 can be set in the range of 200nm to 400nm, far exceeding the 60nm to 80nm required in existing technologies. This size range can be fully achieved using a mature and low-cost KrF lithography machine (wavelength 248nm), eliminating the need for an expensive ArF immersion lithography machine (wavelength 193nm).

[0080] The photomask 600 can be a photoresist layer, formed through standard photolithography processes such as photoresist coating, pre-baking, exposure, development, and post-baking. In this embodiment, a KrF lithography machine is used in conjunction with a corresponding photomask to complete the exposure process.

[0081] Step 2, see Figure 3b As shown, the photomask 600 and the pad nitride layer 300 are used together as etching masks to etch the exposed floating gate layer 500, forming the second trench 510. Specifically, an anisotropic dry etching process, such as reactive ion etching (RIE), is employed, using the photomask 600 as a mask to etch the exposed floating gate layer 500. The etching extends downwards longitudinally (i.e., in the vertical direction) until the top surface of the gate dielectric layer 400 is exposed, forming the second trench 510. During this process, the second trench 510 simultaneously exposes the sidewalls of the pad nitride layer 300, meaning that the sidewalls of the pad nitride layer 300 at the second trench 510 are no longer covered by the floating gate layer 500. The bottom surface of the second trench 510 is flush with the top surface of the pad oxide layer 200.

[0082] During the etching process, the pad nitride layer 300 serves to protect the non-etched areas. Due to the difference in etching selectivity, the etching process has a higher etching rate for the floating gate layer 500 (polysilicon) and a lower etching rate for the gate dielectric layer 400 (SiO2). Therefore, the gate dielectric layer 400 can be used as an etching stop layer to ensure that the etching stops precisely on its top surface.

[0083] After etching is completed, the photomask 600 is removed, for example by ashing and / or wet stripping processes to remove the photoresist.

[0084] Step S3: Perform a lateral etchback of the pad nitride layer. (See reference...) Figure 3c As shown, the pad nitride layer 300 is etched back laterally to expose a portion of the pad oxide layer 200 on the surface of the semiconductor substrate 100.

[0085] In this embodiment, the lateral etching back is performed isotropically on the pad nitride layer 300 using a hot phosphoric acid (H3PO4) wet etching process. Hot phosphoric acid solution exhibits a high etching rate for silicon nitride, but an extremely low etching rate for silicon dioxide and polysilicon, thus providing excellent etching selectivity.

[0086] Specifically, the intermediate product is immersed in a hot phosphoric acid solution at a temperature of 140°C to 180°C (preferably 160°C) to isotropically etch the sidewalls of the pad nitride layer 300 exposed in the second trench 510. Due to the isotropic nature of wet etching, the pad nitride layer 300 is etched not only laterally but also to a certain extent longitudinally. The actual etching mainly occurs at the sidewalls of the pad nitride layer 300 exposed in the second trench 510, causing the sidewalls of the pad nitride layer 300 to be recessed inward relative to the sidewalls of the pad oxide layer 200, forming a lateral back-etching amount Δd, i.e., the depth of the inward recess of the sidewalls of the pad nitride layer 300.

[0087] The lateral back etching amount Δd can be precisely controlled by adjusting the etching time and etching solution temperature. By properly setting the lateral back etching amount Δd, the critical dimension of the final contact window 140 can be reduced to the 10nm level.

[0088] During this process, the pad oxide layer 200 serves as an etching stop layer and a protective layer to prevent the hot phosphoric acid solution from damaging the underlying semiconductor substrate 100. Simultaneously, due to the better uniformity and controllability of wet etching, the process fluctuation of the lateral etching depth Δd is much smaller than the photolithography overlay error, thus ensuring the consistency of the contact window size.

[0089] Step S4: Remove the exposed pad oxide layer. See [link / reference] Figure 3d As shown, the exposed pad oxide layer 200 is removed to form a contact window 140 at the bottom of the second trench 510 that exposes the semiconductor substrate 100.

[0090] In this embodiment, a buffered oxide etch (BOE) or dilute hydrofluoric acid (HF) solution is used to wet-etch the exposed pad oxide layer 200. Because the lateral etching in step S3 causes the sidewalls of the pad nitride layer 300 to recess inward, a portion of the pad oxide layer 200 at the bottom of the second trench 510 is no longer covered by the pad nitride layer 300 and is exposed. The wet etchant reaches the exposed pad oxide layer 200 through the bottom of the second trench 510 and removes it until the surface of the semiconductor substrate 100 is completely exposed, thereby forming the contact window 140.

[0091] The buffer oxide etching solution can be a mixed solution of NH4F and HF, and the concentration of the dilute hydrofluoric acid solution can be 100:1 to 500:1 (H2O:HF). The etching time is set according to the thickness of the pad oxide layer 200 and the etching rate to ensure complete removal of the pad oxide layer 200 at the bottom of the second trench 510.

[0092] At this point, the contact window 140 is complete. The final critical dimension of the contact window 140 is determined by the lateral back-etching amount Δd of the nitride layer 300 in step S3, rather than by the opening size of the photomask 600 in step S2, thus achieving decoupling between the photolithography process and the window size definition.

[0093] As an optional embodiment of this application, after forming the contact window 140, the following steps may also be included:

[0094] A conductive material layer is deposited within the second trench 510 and the contact window 140, filling the contact window 140 and electrically connecting it to the semiconductor substrate 100. The conductive material layer can be made of the same material as the floating gate layer 500, such as polysilicon. The deposition process can be chemical vapor deposition or atomic layer deposition. Due to the small size of the contact window 140, a deposition process with good conformal properties can be used to ensure sufficient filling of the conductive material. Subsequently, the conductive material layer is chemically mechanically polished to make its top surface flush with the top surface of the pad nitride layer 300, providing a smooth surface for subsequent processes.

[0095] See Figures 5a to 5h As shown, Figures 5a to 5h This is a schematic cross-sectional view of some stages in the formation process of the semi-floating gate transistor disclosed in the embodiments of this application.

[0096] This embodiment provides a method for fabricating a semi-floating gate transistor, which includes the following steps:

[0097] Step 1: Using the method described above for forming a semi-floating gate transistor contact window, a contact window 140 exposing the semiconductor substrate 100 is formed at the bottom of the second trench 510. For detailed process instructions, please refer to steps S1 to S4 above; they will not be repeated here.

[0098] Step two, refer to Figure 5aAs shown, a floating gate layer material is deposited again within the second trench 510, filling the contact window 140 and electrically connecting it to the semiconductor substrate 100. The floating gate layer material can be polycrystalline silicon, deposited using a chemical vapor deposition process. The deposited floating gate layer material fully fills the contact window 140, forming a good ohmic contact with the underlying semiconductor substrate 100, achieving an electrical connection between the floating gate and the substrate. This connection is a critical path for charge injection and erasure in a semi-floating gate transistor.

[0099] Step 3, refer to Figure 5b As shown, the floating gate layer material is chemically and mechanically polished until its top surface is flush with the top surface of the pad nitride layer 300. Excess floating gate layer material outside the second trench 510 is removed using a CMP process to form a smooth surface morphology.

[0100] Step 4, see reference Figure 5c As shown, the pad nitride layer 300 is removed using a wet etching process to expose the pad oxide layer 200. Specifically, the pad nitride layer 300 is selectively removed using a hot phosphoric acid wet etching process. Since the etching selectivity of hot phosphoric acid for SiN is much higher than that for SiO2 and polysilicon, this step can accurately remove the pad nitride layer 300 without damaging the underlying pad oxide layer 200 and floating gate layer 500.

[0101] Step 5, refer to Figure 5d As shown, a floating gate layer material is deposited again over the semiconductor substrate 100. The floating gate layer material covers the top surface of the floating gate layer 500 and the surface of the pad oxide layer 200. The deposited floating gate layer material is used to form an extension of the floating gate structure of the semi-floating gate transistor.

[0102] Step Six, see Figure 5e As shown, the re-deposited floating gate layer material is chemically and mechanically polished to retain a predetermined height on the top surface of the floating gate layer material. This predetermined height is determined according to device design requirements to form a floating gate structure that meets electrical performance requirements.

[0103] Step 7, see Figure 5f As shown, a tunneling dielectric layer 700 and a control gate layer 800 are sequentially deposited above the floating gate layer material. The tunneling dielectric layer 700 can be a silicon oxide layer, a silicon nitride layer, a silicon oxide / silicon nitride / silicon oxide (ONO) stack, or a high dielectric constant dielectric layer, etc., used to form a tunneling barrier between the control gate and the floating gate, realizing charge storage and retention. The control gate layer 800 can be a polysilicon layer or a metal layer, used to apply a control voltage to regulate the charge state in the floating gate.

[0104] Step 8, see Figure 5g and Figure 5h As shown, a polysilicon photomask is used for exposure and development to etch away excess floating gate layer, tunneling dielectric layer 700, and control gate layer 800, forming a semi-floating gate transistor. Specifically, a photoresist layer 900 is coated on the surface of the control gate layer 800, and a patterned photoresist mask is formed using a photolithography process. Then, using the photoresist mask as a mask, the control gate layer 800, tunneling dielectric layer 700, and floating gate layer material are sequentially dry etched to form the gate stack structure of the semi-floating gate transistor. After etching, the photoresist is removed.

[0105] At this point, the fabrication of the semi-floating gate transistor is complete.

[0106] This embodiment also provides a semi-floating gate transistor, which is fabricated using the above-described method for fabricating a semi-floating gate transistor. The semi-floating gate transistor includes a semiconductor substrate 100, a first trench 110 formed within the semiconductor substrate 100, a gate dielectric layer 400 formed on the sidewalls and bottom of the first trench 110, a floating gate layer 500 filling the first trench 110, and a conductive structure electrically connected to the semiconductor substrate 100 through a contact window 140. The critical dimensions of the contact window 140 are defined by the lateral etching process of the pad nitride layer, and can be reduced to the 10nm scale, unaffected by photolithography overlay errors, exhibiting excellent dimensional consistency.

[0107] Since the semi-floating gate transistor is prepared by the above-described method, it has good consistency in contact window size, uniform erase and write speed between devices, high yield, and low manufacturing cost, making it suitable for large-scale industrial applications.

[0108] To verify the technical effects of the present invention, the present invention is compared with the prior art in conjunction with specific parameters below:

[0109] Comparative Example (Prior Technology): At the 40nm technology node, ArF immersion lithography directly defines the contact window, with a critical lithographic dimension (CD) of approximately 60nm~80nm. Because the overlay error control capability of the ArF immersion lithography machine is approximately ±6nm, the critical dimension of the contact window exhibits a fluctuation range of approximately 12nm. Furthermore, the equipment procurement cost of the ArF immersion lithography machine exceeds $100 million, and the cost of consumables such as photoresist and masks is significantly higher than that of the KrF process, resulting in a persistently high total cost of ownership (COO).

[0110] In this embodiment of the invention, at the 40nm technology node, a KrF lithography machine is used to define the etching window of the floating gate layer, with the critical lithography dimensions set to 200nm~400nm. The final size of the contact window 140 is precisely controlled by a lateral etching process using a nitride layer 300 pad, allowing the critical size of the contact window 140 to be reduced to the 10nm range. Since the final size of the contact window 140 is determined by the lateral etching amount, it is not affected by lithography overlay errors, significantly narrowing the fluctuation range of the window size. Simultaneously, the equipment cost, photoresist cost, and gas consumption of the KrF lithography machine are significantly lower than those of the ArF immersion process, resulting in an overall cost of ownership reduction of over 60%.

[0111] In summary, this application provides a method for forming a contact window of a semi-floating gate transistor, a semi-floating gate transistor and its fabrication method. The core innovation lies in the decoupling design of the process by defining the etching window through large-size photolithography and precisely defining the contact window by lateral etching back of the pad nitride layer. This completely breaks the technical bottleneck in traditional processes where the size of the contact window is directly limited by photolithography resolution and overlay error.

[0112] On the one hand, this process architecture allows the use of mature, low-cost KrF lithography equipment to replace expensive ArF immersion or EUV lithography equipment. While significantly reducing the total cost of ownership and process complexity, it breaks through the physical limits of lithography resolution and achieves ultra-small contact windows on the order of 10nm. On the other hand, the final critical size of the contact window is entirely determined by the thickness of the wet lateral etching, completely eliminating the influence of lithography overlay errors on the window size. Combined with the high-precision control capability of wet etching, it significantly improves the consistency of contact window size in the device array, fundamentally ensuring the uniformity and high reliability of the erase and write speed of the semi-floating gate transistor.

[0113] Furthermore, this invention eliminates the need for complex process steps such as multiple exposures or self-aligned dual patterning. It achieves precise definition of the contact window simply by adding a conventional wet lateral etching process, making it fully compatible with existing CMOS production line equipment. This invention not only provides a feasible process path for the continued miniaturization of semi-floating gate transistors and novel memory devices in the post-Moore era, but also offers a highly competitive manufacturing solution for their low-cost, high-yield, large-scale industrial mass production.

[0114] The embodiments of the present invention disclosed above are merely illustrative of the invention. The embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method for forming a contact window of a semi-floating gate transistor, characterized in that, include: An intermediate product is provided, the intermediate product including a semiconductor substrate, and a pad oxide layer and a pad nitride layer sequentially stacked on the surface of the semiconductor substrate in a vertical direction; a first trench is formed in the semiconductor substrate, a gate dielectric layer is formed on the sidewalls and bottom surface of the first trench, a floating gate layer is filled in the first trench, and the top surface of the floating gate layer is flush with the top surface of the pad nitride layer. The floating grid layer is patterned, and a second trench is formed within the floating grid layer. The second trench extends downward and exposes the sidewalls of the pad nitride layer. The bottom surface of the second trench is flush with the top surface of the pad oxide layer. The pad nitride layer is etched back laterally to expose a portion of the pad oxide layer on the surface of the semiconductor substrate; Remove the exposed pad oxide layer to form a contact window at the bottom of the second trench that exposes the semiconductor substrate.

2. The method for forming a semi-floating gate transistor contact window according to claim 1, characterized in that: Patterning the floating grid layer and forming a second trench within the floating grid layer specifically includes: A patterned photomask is formed on the surfaces of the pad nitride layer and the floating gate layer. The photomask has an opening that exposes the top surface of the floating gate layer in the area to be etched and covers the surface of the pad nitride layer in the non-etched area. Using the photomask and the pad nitride layer together as an etching mask, the exposed floating gate layer is etched to form the second trench; Remove the photomask.

3. The method for forming a semi-floating gate transistor contact window according to claim 1, characterized in that: The preparation of the intermediate product includes: A first conductivity type well region and a second conductivity type well region are formed in a semiconductor substrate by ion implantation. A pad oxide layer and a pad nitride layer are sequentially deposited on the surface of the semiconductor substrate; Dry etching is performed on the pad nitride layer, the pad oxide layer and the semiconductor substrate to form a first trench that penetrates the pad nitride layer and the pad oxide layer and extends into the semiconductor substrate; A gate dielectric layer is formed on the sidewalls and bottom surface of the first trench; Floating grid material is deposited in the first trench and chemically mechanically polished so that the top surface of the floating grid layer is flush with the top surface of the pad nitride layer.

4. The method for forming a semi-floating gate transistor contact window according to claim 3, characterized in that: The first conductivity type well region is a P-type well region, and the second conductivity type well region is an N-type well region.

5. The method for forming a semi-floating gate transistor contact window according to claim 1, characterized in that: The lateral etching of the pad nitride layer includes: isotropic etching of the pad nitride layer using a hot phosphoric acid wet etching process, so that the sidewall of the pad nitride layer is recessed inward relative to the sidewall of the pad oxide layer.

6. The method for forming a semi-floating gate transistor contact window according to claim 1, characterized in that: The removal of the exposed pad oxide layer includes: performing wet etching on the exposed pad oxide layer using a buffered oxide etchant or a dilute hydrofluoric acid solution to completely remove the pad oxide layer at the bottom of the second trench and expose the surface of the semiconductor substrate.

7. The method for forming a semi-floating gate transistor contact window according to claim 1, characterized in that: After forming the contact window, the method further includes: depositing a conductive material layer in the second trench and in the contact window, the conductive material layer filling the contact window and being electrically connected to the semiconductor substrate; The conductive material layer is chemically and mechanically polished so that the top surface of the conductive material layer is flush with the top surface of the pad nitride layer.

8. The method for forming a semi-floating gate transistor contact window according to claim 7, characterized in that: The conductive material layer is made of the same material as the floating gate layer.

9. A method for fabricating a semi-floating gate transistor, characterized in that, include: Using the semi-floating gate transistor contact window formation method as described in any one of claims 1 to 8, a contact window exposing the semiconductor substrate is formed at the bottom of the second trench; A floating gate layer material is deposited again in the second trench, so that the floating gate layer material fills the contact window and is electrically connected to the semiconductor substrate; The floating gate layer material is subjected to chemical mechanical polishing so that the top surface of the floating gate layer material is flush with the top surface of the pad nitride layer; The pad nitride layer is removed using a wet etching process to expose the pad oxide layer; A floating gate layer material is deposited again on the semiconductor substrate; The re-deposited floating gate layer material is chemically and mechanically polished to ensure that the top surface of the floating gate layer material retains a predetermined height. A tunneling dielectric layer and a control gate layer are sequentially deposited on top of the floating gate layer material; A polysilicon photomask is used for exposure and development to etch away excess floating gate layer, tunneling dielectric layer and control gate layer, forming a semi-floating gate transistor.

10. A semi-floating gate transistor, characterized in that, It was prepared by the method described in claim 9.

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