Group iii nitride semiconductor device

Abstract

In one embodiment, a Group III nitride semiconductor device is provided that includes a substrate having a first major surface capable of supporting epitaxial growth of at least one Group III nitride layer, a Group III nitride superlattice disposed on the first major surface of the substrate, a Group III nitride buffer structure disposed on the Group III nitride superlattice, a Group III nitride device layer disposed on the Group III nitride buffer structure. The Group III nitride device layer includes a power device for switching a load. The Group III nitride superlattice includes alternating first and second Group III nitride layers that include different bandgaps. The first Group III nitride layers of the superlattice are n-type and the second Group III nitride layers of the superlattice are p-type.

Description

Background Technology

[0001] Group III nitride semiconductor devices (such as gallium nitride (GaN) devices) are emerging as attractive candidates for carrying high currents, supporting high voltages, and providing very low on-resistance and fast switching times. Group III nitride semiconductor devices can be formed in an epitaxial group III nitride body on a base substrate formed of a non-group III nitride material (such as Si, sapphire, or SiC). The group III nitride body may include a buffer structure disposed on the base substrate and a device layer disposed on the buffer structure.

[0002] For example, the device layer for HEMT (High Electron Mobility Transistor) may include a GaN channel layer and an AlGaN barrier layer disposed on the GaN channel layer. A heterojunction is formed at the interface between the AlGaN barrier layer and the GaN channel layer, which can support a two-dimensional charge carrier gas (e.g., a two-dimensional electron gas). The two-dimensional charge carrier gas provides the channel for the transistor device.

[0003] The buffer structure compensates for the lattice mismatch between the base substrate and the group III nitride host epitaxially grown on the base substrate, and also reduces cracking. By compensating for the lattice mismatch, the epitaxially grown group III nitride layer on the group III nitride host exhibits reduced crystallization defects (e.g., a reduced number of dislocations) and improved epitaxial quality. This leads to improved performance of the device formed in the device layer.

[0004] US 2018 / 047813 A discloses a substrate structure including a supporting substrate and a buffer structure disposed on the supporting substrate. The buffer structure includes an intentionally doped superlattice stack, an unintentionally doped first group III nitride layer disposed on the buffer structure, a second group III nitride layer disposed on the first group III nitride layer and forming a heterojunction therebetween, and a barrier layer disposed between the heterojunction and the buffer structure. The barrier layer is configured to block charge from entering the buffer structure.

[0005] To improve device performance and / or simplify the fabrication of group III nitride semiconductor devices, further improvements to the buffer structure of group III nitride semiconductor devices are desirable. Summary of the Invention

[0006] In one embodiment, a group III nitride semiconductor device is provided, comprising a substrate having a first main surface capable of supporting epitaxial growth of at least one group III nitride layer, a group III nitride superlattice disposed on the first main surface of the substrate, a group III nitride buffer structure disposed on the group III nitride superlattice, and a group III nitride device layer disposed on the group III nitride buffer structure. The group III nitride device layer includes power devices for switching loads. The group III nitride superlattice includes alternating first group III nitride layers and second group III nitride layers, the alternating first group III nitride layers and second group III nitride layers comprising different band gaps. The first group III nitride layer of the superlattice is n-type, and the second group III nitride layer of the superlattice is p-type.

[0007] Those skilled in the art will recognize the additional features and advantages upon reading the following detailed description and viewing the accompanying drawings. Attached Figure Description

[0008] The elements in the accompanying drawings are not necessarily proportional to each other. Similar reference numerals designate corresponding similar parts. Features of the various illustrated embodiments can be combined unless they are mutually exclusive. Exemplary embodiments are depicted in the accompanying drawings and described in detail below.

[0009] Figure 1 A schematic cross-sectional view of a group III nitride semiconductor device according to an embodiment is shown.

[0010] Figure 2 A schematic cross-sectional view of a group III nitride semiconductor device according to an embodiment is shown.

[0011] Figure 3 A schematic cross-sectional view of a group III nitride semiconductor device according to an embodiment is shown, and an exemplary device layer according to an embodiment is shown.

[0012] Figure 4 A schematic cross-sectional view of a group III nitride semiconductor device according to an embodiment is shown, and an exemplary device layer according to an embodiment is shown.

[0013] Figure 5 A schematic cross-sectional view of a group III nitride semiconductor device according to an embodiment is shown, and an exemplary device layer according to an embodiment is shown.

[0014] Figure 6 A schematic cross-sectional view of a group III nitride semiconductor device according to an embodiment is shown, and an exemplary device layer according to an embodiment is shown. Detailed Implementation

[0015] In the following detailed description, reference is made to the accompanying drawings, which form part of the detailed description and illustrate, by way of illustration, specific embodiments in which the invention may be practiced. In this regard, directional terms (such as “top,” “bottom,” “front,” “rear,” “head,” “tail,” etc.) are used with reference to the orientation of the described figures(s). Because components of the embodiments can be positioned in several different orientations, directional terms are used for illustrative purposes and are by no means limiting. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the invention. Therefore, the following detailed description is not to be construed as limiting, and the scope of the invention is defined by the appended claims.

[0016] Several exemplary embodiments will now be explained. In this context, the same structural features are identified by the same or similar reference numerals in the figures. In the context of this description, “lateral” or “lateral direction” should be understood to mean a direction or range that generally extends parallel to the lateral extent of the semiconductor material or semiconductor carrier. Thus, the lateral direction extends substantially parallel to these surfaces or sides. In contrast, the term “vertical” or “vertical direction” is understood to mean a direction that is generally perpendicular to these surfaces or sides, and therefore perpendicular to the lateral direction. Thus, the vertical direction extends in the thickness direction of the semiconductor material or semiconductor carrier.

[0017] As used in this specification, when an element such as a layer, region, or substrate is referred to as "on" or "extending" to another element, it may be directly on or directly extended to the other element, or there may be an intermediate element. In contrast, when an element is referred to as "directly on" or "directly extended" to another element, there is no intermediate element.

[0018] As used in this specification, when an element is referred to as "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be an intermediate element. In contrast, when an element is referred to as "directly connected" or "directly coupled" to another element, there is no intermediate element.

[0019] Depletion-type devices (such as high-voltage depletion-type transistors) have a negative threshold voltage, meaning they can conduct current at zero gate voltage. These devices are typically on. Enhancement-type devices, such as low-voltage enhancement-type transistors, have a positive threshold voltage, meaning they cannot conduct current at zero gate voltage and are typically off. Enhancement-type devices are not limited to low voltage and can also be high-voltage devices.

[0020] As used herein, the phrase “group III nitride” refers to a compound semiconductor comprising nitrogen (N) and at least one group III element, including aluminum (Al), gallium (Ga), indium (In), and boron (B), and including but not limited to any alloys thereof, such as aluminum gallium nitride (Al). x Ga (1-x) N), Indium gallium nitride (In) y Ga (1-y) N), aluminum indium gallium nitride (Al) x In y Ga (1-x-y) N), gallium arsenide phosphide nitride (GaAs) a P b N (1-a-b) ), and aluminum indium gallium arsenide phosphide nitride (Al x In y Ga (1-x-y) As a P b N (1-a-b) The terms "aluminum gallium nitride" and "AlGaN" are used herein to refer to aluminum gallium nitride made of the chemical formula Al. x Ga (1-x) N describes the alloy, where 0 <x<1。

[0021] This disclosure proposes a combination of modulation doping and superlattices in buffer layers for group III nitride devices, such as GaN-based devices on Si substrates, e.g., GaN-based HEMTs (high electron mobility transistors) on Si substrates, to reduce vertical leakage. For example, p-type / n-type modulation doping is introduced into AlGaN / AlN superlattices and / or into the C-(Al)GaN layer of the buffer structure to add an additional layer with bandgap engineering.

[0022] This bandgap-engineered layer structure exhibits a bandgap shift between alternating p-type and n-type layers, creating additional multiple barriers for charge carrier passage. The alternating p-doping and n-doping in the superlattice stack further enhances / increases the charge carrier potential barrier by further offsetting the AlGaN and AlN bands of the superlattice. This bandgap engineering increases the device's vertical resistance, reduces vertical leakage at the same vertical voltage, and thus improves the device's vertical lifetime under load conditions.

[0023] The use of p-type / n-type modulation doping also allows for a reduction in the thickness of the buffer structure, which in turn reduces epitaxial processing time. This results in reduced CO2 emissions due to less power consumed by the epitaxial tools. The reduced epitaxial thickness also reduces material consumption, thereby further reducing CO2 emissions in the supply chain.

[0024] The proposed structure allows for a reduction in epitaxial thickness, resulting in reduced stress in the wafer, a lower risk of wafer breakage, and lower epitaxial costs. Alternatively, thickness can be maintained while improving epitaxial vertical lifetime.

[0025] In some embodiments, the simple carbon-doped superlattice is modified to replace the continuous carbon doping with p-doped / n-doped layers. Examples of p-type dopants are Fe, C, and Mg, and examples of n-type dopants are S and Ge. Additional buffer layers, which can be continuously p-doped, can be disposed on the modified superlattice. In some embodiments, the continuously doped superlattice is combined with a modified C-(Al)GaN layer on a superlattice comprising alternating p-doped / n-doped sublayers. In some embodiments, both the superlattice and the C-(Al)GaN layer on the superlattice comprise alternating p-doped / n-doped sublayers.

[0026] In addition to the AlGaN / AlN superlattice, the introduction of alternating p-type / n-type doping into the C-(Al)GaN layer creates a two-bandgap engineered layer structure with a bandgap shift between the p-type and n-type layers, thus generating additional multiple barriers for charge carriers to pass through. This bandgap engineering increases the device's vertical resistance, thereby reducing vertical leakage at the same vertical voltage and thus improving vertical lifetime under load conditions. Combining these two methods can further reduce vertical leakage.

[0027] In some embodiments, only a portion of the superlattice and / or (Al)GaN includes a p / n alternating doped superlattice structure and / or includes p / n alternating doped regions in the (Al)GaN layer.

[0028] Figure 1 A schematic cross-sectional view of a group III nitride semiconductor device 10 according to one embodiment is shown. The group III nitride device 10 includes a substrate 11 having a first main surface 12 capable of supporting the epitaxial growth of at least one group III nitride layer. A group III nitride superlattice 13 is disposed on the first main surface 12 of the substrate 11, a group III nitride-based buffer structure 14 is disposed on the group III nitride superlattice 13, and a group III nitride device layer 15 is disposed on the group III nitride buffer structure 14. The group III nitride device layer 15 includes one or more power devices 16 suitable for switching loads. For example, the power devices 16 may be transistor devices such as HEMTs (high electron mobility transistors), diodes, or bidirectional switches.

[0029] In one embodiment, the group III-nitride based buffer structure 14 is disposed directly on the group III-nitride superlattice 13, and the group III-nitride device layer 15 is disposed directly on the group III-nitride buffer structure 14. The group III-nitride device layer 15 may include two or more sublayers and have a multilayer structure.

[0030] The group III-nitride superlattice 13 includes a plurality of first group III-nitride layers 17 and a plurality of second group III-nitride layers 17 alternately stacked on the first main surface 12 to form a first, second, first, second arrangement in the stack. The stack has a stacking direction extending perpendicular to the first main surface 12 of the substrate 11.

[0031] The first and second group III-nitride layers 17, 18 include different band gaps and different group III-nitride compositions. For example, the first group III-nitride layer 17 may be formed of aluminum nitride (AlN). And the second group III-nitride layer 18 may be formed of AlGaN (Al x Ga (1-x) N, where 0<x<1). In addition, the first and second group III-nitride layers 17, 18 also contain dopants of opposite conductivity. The first group III-nitride layer 17 includes an n-type dopant and n-type conductivity, and the second group III-nitride layer 18 includes a p-type dopant and p-type conductivity. Therefore, a stack of pn junctions is formed by the superlattice 13 on the substrate 11.

[0032] The n-type first group III-nitride layer 17 may include one or more selected from the group consisting of Si and Ge dopants, and the p-type second group III-nitride layer may include one or more selected from the group consisting of C, Mg and Fe dopants. In one embodiment, the first group III-nitride layer 17 includes a Si dopant, and the second group III-nitride layer 18 includes a C dopant. Secondary ion mass spectrometry (SIMS) may be used to determine the presence and levels of n-type (e.g., Si, Ge) and p-type (e.g., C, Fe, Mg) dopants.

[0033] Accordingly, the group III-nitride superlattice 13 includes a plurality of pairs 19, each pair including one of the n-type first group III-nitride layers 17 and one of the second p-type group III-nitride layers 18 (heterojunction), since the first and second group III-nitride layers 17, 18 include different band gaps, and a pn junction is formed between the n-type first group III-nitride layer 17 and the p-type group III-nitride layer 18 of each pair 19 as well as between these pairs. Depending on the desired breakdown voltage, the superlattice 13 may include between 20 and 100 pairs. In some embodiments, the bottommost layer and the topmost layer of the superlattice 13 are n-type first group III-nitride layers 17. The n-type first group III-nitride layer 17 may have a smaller thickness than the p-type group III-nitride layer 18.

[0034] In this embodiment, the group III-nitride buffer structure 14 arranged between the group III-nitride superlattice 13 and the group III-nitride device layers 1, 5 comprises a single layer comprising AlGaN. In one embodiment, the group III-nitride buffer structure 14 is unintentionally doped. Alternatively, the single layer of AlGaN may comprise a p-type dopant, whereby the doping level over the height of the buffer layer 14 is substantially uniform. This single layer of AlGaN does not have any n-type layer. The group III-nitride device layer 15 is unintentionally doped.

[0035] The substrate 11 may comprise materials other than group III-nitrides, and may be referred to as a heterogeneous substrate. The substrate 11 may comprise silicon or sapphire. The group III-nitride layers constituting the superlattice 13, the buffer structure 14 and the device layer 15 are epitaxially grown on the first main surface 12 of the substrate 11. The superlattice 13 and the buffer structure 14 provide a buffer between the substrate 11 and the device layer 15, which serves to compensate for the lattice mismatch between the substrate 11 (particularly the first main surface 12 of the substrate 11) and the device layer 15. This reduces crystalline defects in the group III device layer 15, thereby improving the quality of epitaxy and the performance of the device 16 formed in the group III-nitride device layer 15. The total height of the buffer in conventional devices may be at least 1 µm. This thickness can be reduced due to the use of modulation doping of the superlattice 13, i.e. the alternately arranged n-type first group III-nitride layer 17 and p-type second group III-nitride layer 18.

[0036] The superlattice 13 comprises a bandgap offset between adjacent p-type and n-type layers, i.e. a bandgap offset between the first and second group III-nitride layers 17, 18, thus creating additional multiple barriers for charge carriers to traverse. This bandgap engineering increases the vertical resistance of the device, thus reducing vertical leakage at the same vertical voltage, and thereby improving the vertical lifetime under load conditions.

[0037] Different compositions may be used for the first and second group III-nitride layers 17, 18 of the superlattice 13. In one embodiment, the n-type first group III-nitride layer 17 is formed of AlN, and the p-type second group III-nitride layer 18 is formed of Al x Ga (1-x) N, where 0<x<1. In another embodiment, the n-type first group III-nitride layer 17 is formed of AlN, and the p-type second group III-nitride layer 18 is formed of GaN. In yet another embodiment, the n-type first group III-nitride layer 17 is formed of Al x Ga (1-x) N, where 0<x<1, and the p-type second group III-nitride layer 18 is formed of Al y Ga (1-y)N is formed, where 0<y<1 and x ≠ y.

[0038] The concentrations of the dopants in the first and second group III-nitride layers 17, 18 of the superlattice 13 may be selected to be within a certain range. In one embodiment, the n-type first group III-nitride layer 17 comprises an n-type dopant at a concentration of 5 e 19 cm -3 to 5e 17 cm -3 , and / or the p-type second group III-nitride layer 18 comprises a p-type dopant at a concentration of 5 e 20 cm -3 to 1 e 18 cm -3 .

[0039] In one embodiment, the n-type first group III-nitride layer 17 comprises Si dopant at a concentration of 5 e 19 cm -3 to 5 e 17 cm -3 , preferably about 1 e 18 cm -3 , and the p-type second group III-nitride layer 18 comprises C dopant at a concentration of 5 e 20 cm -3 to 1 e 18 cm -3 , preferably about 2 e 19 cm -3 .

[0040] The thicknesses of the first and second group III-nitride layers 17, 18 of the superlattice 13 may be selected to be within a certain range. In one embodiment, the n-type first group III-nitride layer 17 has a thickness t sn , and the p-type second group III-nitride layer 18 has a thickness t sp , where 2 nm ≤ t sn ≤ 8 nm and 10 nm ≤ t sp ≤ 45 nm.

[0041] In one embodiment, the first and second group III-nitride layers 17, 18 of the superlattice 13 of the group III-nitride semiconductor device 10 comprise a combination of the following features. The n-type first group III-nitride layer 17 is formed of AlN, has a thickness t sn , where 2nm ≤ t sn ≤ 8 nm, and comprises a dopant at a concentration of 5 e 19 cm -3 to 5 e 17 cm -3 , preferably about 1 e18 cm -3 Si dopant, and the p-type second group III-nitride layer 18 is formed of Al x Ga (1-x) N, where 0<x<1, has a thickness t sp , where 10 nm ≤ t sp ≤45 nm, and contains C dopant at a concentration of 5 e 20 cm -3 to 1 e 18 cm -3 , preferably about 2 e 19 cm -3 .

[0042] Figure 2 shows a schematic cross-sectional view of a group III-nitride semiconductor device 10, which is similar to the device described with reference Figure 1 , comprising a base substrate 11, a group III-nitride superlattice 13 arranged on the first main surface 12 of the substrate 11, a group III-nitride buffer structure 14 arranged on the group III-nitride superlattice 13, and a group III-nitride device layer 15 arranged on the conventional nitride buffer layer 14. One or more power devices 16 suitable for switching a load are formed in the group III-nitride device layer 15.

[0043] In the Figure 2 illustrated embodiment, the group III-nitride buffer layer 14 comprises alternately stacked n-doped layer regions 20 and p-doped layer regions 21. Compared with the superlattice 13 of the device shown in Figure 1 , the n-doped layer regions 20 and the p-doped layer regions 21 of the buffer structure 14 have the same group III-nitride composition, such as AlGaN or GaN. In this embodiment, the buffer structure alone provides a stack of pn junctions. In this embodiment, the group III-nitride buffer structure 14 comprises a group III-nitride buffer layer arranged directly on the superlattice 13.

[0044] The n-doped layer regions 20 may comprise one or more selected from the group consisting of Si and Ge dopants, and the p-doped layer regions 21 may comprise one or more selected from the group consisting of C, Mg and Fe dopants.

[0045] The n-type layer regions 20 may comprise n-type dopant at a concentration of 5 e 19 cm -3 to 5 e 17 cm -3 , and the p-type layer regions 21 may comprise p-type dopant at a concentration of 5 e 20 cm -3 to 1 e 18 cm -3p-type dopant. In one embodiment, the n-type layer region 20 comprises a concentration of about 1 e 18 cm -3 of Si dopant, and the p-type layer region 21 comprises a concentration of about 5 e 19 cm -3 of C dopant.

[0046] The individual n-type layer regions 20 may have a smaller thickness than the individual p-type layer regions 21. For example, the n-type layer regions each have a thickness t bn , and the p-type layer regions each have a thickness t bp , where 20 nm ≤ t bn ≤ 50 nm and 5 nm ≤ t bp ≤ 20 nm. In one embodiment, 20 nm ≤ t bn ≤ 50 nm, and 5 nm ≤ t bp ≤ 20 nm, and t bn <t bp .

[0047] In Figure 2 the embodiment, and compared with Figure 1 the embodiment, the first and second group III nitride layers 17, 18 of the superlattice 13 have no pn junction therebetween. The first and second group III nitride layers 17, 18 of the superlattice 13 have the same conductivity type (e.g., p-type), or may be unintentionally doped. However, the first and second group III nitride layers 17, 18 of the superlattice 13 have different group III nitride compositions and band gaps, for example, the first group III nitride layer 17 is formed of AlN and the second group III nitride layer 18 is formed of Al x Ga (1-x) N, where 0<x<1. Both the first and second group III nitride layers 17, 18 of the superlattice 13 may be unintentionally doped or both p-doped, including, for example, carbon dopant. The group III nitride device layer 15 is unintentionally doped.

[0048] Figure 3 shows a schematic cross-sectional view of a semiconductor device 10 according to another embodiment, the semiconductor device 10 comprising Figure 1 the combination of the superlattice 13 and Figure 2 the buffer structure 14. The superlattice 13 includes alternating first and second group III nitride layers 17, 18 of opposite conductivity types, which are stacked such that a pn junction is formed between the first and second group III nitride layers 17, 18, and which include different group III nitride compositions such that a heterojunction is formed between the first and second group III nitride layers 17, 18. The group III nitride device layer 15 is unintentionally doped.

[0049] The buffer structure 14 includes alternating first and second layer regions 20, 21, which include alternating doping types, and a pn junction is formed between the first and second layer regions 20, 21, but a homojunction is formed between the first and second lateral layer regions 20, 21 because they include the same group III nitride composition. The buffer structure 14 has alternating n-type layer regions 20 and p-type layer regions 21.

[0050] In addition to the n-type and p-type doping of layers 17 and 18 of the superlattice 13, the combination of alternating p-type / n-type doped layer regions 20 and 21 in the buffer layer 14 creates a bandgap shift between the p-type and n-type layers, as well as additional multiple barriers for charge carriers to pass through. This band-engineered structure further increases the vertical resistance of the device, thereby reducing vertical leakage at the same vertical voltage and thus improving vertical lifetime under load conditions.

[0051] This embodiment can be used to increase the number of pn junctions arranged in the stack between device layer 15 and substrate 11. The same n-type and p-type dopants can be used in both superlattice 13 and buffer structure 14.

[0052] The concentration of dopants in the first and second group III nitride layers 17, 18 of the superlattice 13 can be selected to be within a certain range. In one embodiment, the n-type first group III nitride layer 17 comprises a concentration of 5 e 19 cm -3 up to 5e 17 cm -3 The n-type dopant and / or p-type group III nitride layer 18 includes a concentration of 5 e 20 cm -3 up to 1 e 18 cm -3 p-type dopant.

[0053] In one embodiment, the n-type group III nitride layer 17 comprises a concentration of 5 e 19 cm -3 up to 5 e 17 cm -3 , preferably about 1 e 18 cm -3 The Si dopant, and the p-type group II III nitride layer 18 includes a concentration of 5 e 20 cm -3 up to 1 e 18 cm -3 , preferably about 2 e 19 cm -3 C dopant.

[0054] The thicknesses of the first and second group III-nitride layers 17, 18 of the superlattice 13 may be selected to fall within a certain range. In one embodiment, the n-type first group III-nitride layer 17 has a thickness t sn , and the p-type second group III-nitride layer 18 has a thickness t sp , where 2 nm ≤ t sn ≤ 8 nm and 10 nm ≤ t sp ≤ 45 nm.

[0055] In one embodiment, the first and second group III-nitride layers 17, 18 of the superlattice 13 of the group III-nitride semiconductor device 10 comprise a combination of the following features. The n-type first group III-nitride layer 17 is formed of AlN, and has a thickness t sn , where 2 nm ≤ t sn ≤ 8 nm, and includes Si dopant at a concentration of 5 e 19 cm -3 to 5 e 17 cm -3 , preferably about 1 e 18 cm -3 , and the p-type second group III-nitride layer 18 is formed of Al x Ga (1-x) N, where 0<x<1, has a thickness t sp , where 10 nm ≤ t sp ≤45 nm, and includes C dopant at a concentration of 5 e 20 cm -3 to 1 e 18 cm -3 , preferably about 2 e 19 cm -3 .

[0056] Different compositions may be used for the first and second group III-nitride layers 17, 18 of the superlattice 13. In one embodiment, the n-type first group III-nitride layer 17 is formed of AlN, and the p-type second group III-nitride layer 18 is formed of Al x Ga (1-x) N, where 0<x<1. In another embodiment, the n-type first group III-nitride layer 17 is formed of AlN, and the p-type second group III-nitride layer 18 is formed of GaN. In yet another embodiment, the n-type first group III-nitride layer 17 is formed of Al x Ga (1-x) N, where 0<x<1, and the p-type second group III-nitride layer 18 is formed of Al y Ga (1-y) N, where 0<y<1 and x ≠ y.

[0057] In the buffer structure 14, the n-type layer region 20 may include a concentration of 5 e 19 cm -3 up to 5 e 17 cm -3 The n-type dopant, and the p-type layer region 21 may include an n-type dopant with a concentration of 5 e 20 cm -3 up to 1 e 18 cm -3 The p-type dopant. Individual n-type layer regions 20 can have a smaller thickness than individual p-type layer regions 21. For example, each n-type layer region has a thickness t. bn Furthermore, each of the p-type layer regions has a thickness t. bp Where 20 nm ≤ t bn ≤ 50 nm and 5 nm ≤ t bp ≤ 20 nm. In one embodiment, 20 nm ≤ t bn ≤ 50 nm and 5 nm ≤ t bp ≤ 20 nm and t bn <t bp .

[0058] In one embodiment, the n-type layer region 20 includes a concentration of approximately 1 e 18 cm -3 The Si dopant, and the p-type layer region 21 includes a concentration of approximately 5 e 19 cm -3 C dopant.

[0059] Figure 4 A semiconductor device 10 according to another embodiment is shown, which includes Figure 3 The structure of the superlattice 13 and buffer structure 14 is shown. The group III nitride device layer 15 is unintentionally doped. In this embodiment, the semiconductor device 10 also includes a nucleation layer 22 formed on a first main surface 12 of the substrate 11, and the nucleation layer 22 is located between the first main surface 11 and the superlattice 13 and is in direct contact with the first main surface 11 and the superlattice 13. For example, if the substrate 11 is formed of silicon (e.g., single-crystal silicon or an epitaxial silicon layer), the nucleation layer 22 can be formed of aluminum nitride. The nucleation layer 22 can be used to improve the epitaxy of the bottommost layer of the superlattice 13, and thus improve the epitaxy of the subsequently grown group III nitride layers 17, 18, buffer structure 14, and device layer 15 of the superlattice 13. The nucleation layer 22 can also be used as a reference. Figures 1 to 3 In the semiconductor device 10 shown and described.

[0060] Figure 4A schematic cross-sectional view of an exemplary structure of the device layer 15 is also shown. In this embodiment, the device layer 15 includes a group III-nitride channel layer 23 and a group III-nitride barrier layer 24, and the group III-nitride channel layer 23 is arranged on the buffer structure 14. The group III-nitride barrier layer 24 is arranged on the group III-nitride channel layer 23, and a heterojunction is formed therebetween, which can support a two-dimensional charge carrier gas, such as 2DEG (two-dimensional electron gas), as schematically depicted by the dashed line in the accompanying drawings. The group III-nitride channel layer 23 may be formed of GaN, and the group III-nitride barrier layer 24 may be formed of AlGaN (Al x Ga (1-x) N, where 0<x<1).

[0061] In this embodiment, the group III-nitride device layer 15 further includes an optional group III-nitride back barrier layer 25 arranged between the group III-nitride buffer structure 14 and the group III-nitride channel layer 23. The group III-nitride back barrier layer 25 forms a heterojunction with the group III-nitride channel layer 23 capable of supporting a two-dimensional charge gas. For example, the group III-nitride back barrier layer may be formed of AlGaN and have a composition different from that of the AlGaN barrier layer 24, for example, the group III-nitride back barrier layer may have Al y Ga (1-y) N composition, where 0<y<1 and x ≠ y. The group III-nitride back barrier layer 25, the group III-nitride channel layer 23, and the group III-nitride barrier layer 24 are unintentionally doped.

[0062] In Figure 4 the embodiment shown in, the device formed in the group III-nitride device layer 15 is a transistor device, which is a HEMT in this embodiment. The group III-nitride device layer 15 further includes a first power electrode 26, a second power electrode 27, and a gate 28 arranged on the upper surface 32 of the group III-nitride device layer 15, and the group III-nitride device layer 15 is formed by the upper surface 32 of the group III-nitride barrier layer 24 in this embodiment. The first power electrode 26 may be a source electrode, and the second power electrode 27 may be a drain electrode. The gate 28 is laterally arranged between the source electrode 26 and the drain electrode 27 to form a lateral transistor structure.

[0063] The transistor device 16 may be a depletion-mode device or an enhancement-mode device. Figure 4The HEMT shown is an enhancement-mode device and includes a gate structure 28 comprising a recess 29 formed in an AlGaN barrier layer 24, a p-doped group III nitride layer 30 located in the recess and adjacent to the first main surface 12, and a metal gate 31 located on the p-doped group III nitride layer 30. The p-doped group III nitride layer 30 may have a T-shaped cross-section. In some embodiments, a second AlGaN barrier layer may be provided lining the recess 29. The p-doped group III nitride layer 30 may comprise p-doped GaN or p-doped AlGaN. A Mg dopant may be used to form the p-doped group III nitride layer 30. The source electrode 26 and drain electrode 27 may be formed of an ohmic metal (e.g., Al) or a multilayer structure (e.g., Ti, Al, and a covering metal such as Ti). The gate metal layer 31 may be formed of an ohmic metal (e.g., Al) for forming an ohmic gate or a Schottky metal for forming a Schottky gate. Schottky metals can be TiN, Ti, W, or WSi. x One or more of Ta, TaN, Ni, Pd, Pt and Ir.

[0064] Figure 5 A schematic cross-sectional view of an exemplary power device 16 according to another embodiment is shown, which can be used for Figures 1 to 3 In the device layer 15 of the embodiment shown, device layer 15 includes a group III nitride channel layer 23 and a group III nitride barrier layer 24 disposed on the group III nitride channel layer 23 (as shown in...). Figure 4 (In the embodiments). However, in Figure 5 In the embodiment shown, the back barrier layer is omitted, so that the group III nitride channel layer 23 is in direct contact with the buffer structure 14, especially with the uppermost n-band layer region 20 of the buffer structure 14.

[0065] In this embodiment, the power device 16 is a diode 40 with a gate-controlled diode structure. Similar to... Figure 4 In the HEMT shown, a first power electrode 26, a second power electrode 27, a gate 28 with a recess 29, a p-doped group III nitride layer 30, and a gate metal 31 are disposed on a first main surface 32, such that the gate 28 is laterally disposed between the first power contact 26 and the second power contact 27. The gate 28 is electrically connected to the first power contact 26, for example, through a conductive layer 33. The first power electrode 26 provides the anode of the diode, and the second power electrode 28 provides the cathode of the diode.

[0066] Figure 6 A schematic cross-sectional view of an exemplary power device 15 according to another embodiment is shown, which can be used for Figures 1 to 3In the embodiment shown, device layer 15 includes a back barrier layer 25 disposed on buffer structure 14, a group III nitride channel layer 23 disposed on back barrier layer 25, and a group III nitride barrier layer 24 disposed on group III nitride channel layer 23 (as shown in...). Figure 4 (as in the embodiment). However, the back barrier layer 25 can be omitted.

[0067] In this embodiment, the power device is a bidirectional switch 41. The bidirectional switch 41 includes a first power electrode 26, a second power electrode 27, a first gate 28, and a second gate 28' disposed on the upper surface 32 of the group III nitride device layer 15. The first and second gates 28 and 28' are laterally disposed between the first power electrode 26 and the second power electrode 27, and are laterally adjacent to each other. (See reference...) Figure 4 Each of the gates 28 and 28' includes a recess 29, a p-doped group III nitride layer 31, and a gate metal 32.

[0068] In another embodiment, not shown, the bidirectional switch 41 includes a single gate.

[0069] In summary, a group III nitride semiconductor device is provided which includes alternating p-type / n-type doped layer regions 20, 21 in one or both of the buffer layer 14 and the superlattice 13. These alternating doped regions provide a bandgap shift between the p-type and n-type layers and provide additional multiple barriers for charge carriers to pass through. This bandgap engineering structure increases the vertical resistance of the device, thereby reducing vertical leakage at the same vertical voltage and thus improving vertical lifetime under load conditions.

[0070] The proposed structure can help reduce vertical leakage in Si-based group III nitride epitaxial stacks, which in turn helps improve epitaxial vertical lifetime. This is useful for forming highly reliable GaN-based devices. While maintaining the same vertical leakage (and vertical blocking voltage), the reduction in epitaxial thickness leads to a reduction in epitaxial processing time and cost.

[0071] Although this disclosure is not limited thereto, the examples numbered below illustrate one or more aspects of this disclosure.

[0072] Example 1. A group III nitride semiconductor device, comprising: A substrate having a first primary surface capable of supporting the epitaxial growth of at least one group III nitride layer; A group III nitride superlattice arranged on the first main surface of the substrate; A group III nitride buffer structure arranged on a group III nitride superlattice; Group III nitride device layer, which is arranged on the Group III nitride buffer structure and includes a power device for switching a load; wherein the Group III nitride superlattice comprises alternating first Group III nitride layers and second Group III nitride layers, the alternating first Group III nitride layers and second Group III nitride layers have different band gaps, wherein the first Group III nitride layers are n-type and the second Group III nitride layers are p-type.

[0073] 2. The Group III nitride semiconductor device according to Example 1, wherein the Group III nitride superlattice comprises a plurality of pairs, each pair comprising an n-type Group III nitride layer and a p-type Group III nitride layer, wherein a heterojunction and a pn junction are formed between the n-type Group III nitride layer and the p-type Group III nitride layer of each pair and between pairs in the plurality of pairs.

[0074] 3. The Group III nitride semiconductor device according to Example 1 or Example 2, wherein the first Group III nitride layers and the second Group III nitride layers are arranged alternately in a stack.

[0075] 4. The Group III nitride semiconductor device according to any one of Examples 1 to 3, wherein the n-type first Group III nitride layers and the p-type Group III nitride layers have different band gaps.

[0076] 5. The Group III nitride semiconductor device according to any one of Examples 1 to 3, wherein the n-type first Group III nitride layer is formed of AlN, and the p-type second Group III nitride layer is formed of Al x Ga (1-x) N, where 0<x<1, or the n-type first Group III nitride layer is formed of AlN, and the p-type second Group III nitride layer is formed of GaN, or the n-type first Group III nitride layer is formed of Al x Ga (1-x) N, where 0<x<1, and the p-type second Group III nitride layer is formed of Al y Ga (1-y) N, where 0<y<1 and x ≠ y.

[0077] 6. The Group III nitride semiconductor device according to any one of Examples 1 to 5, wherein the n-type first Group III nitride layer comprises Si or Ge dopant, and the p-type second Group III nitride layer comprises C or Mg or Fe dopant.

[0078] 7. The group III nitride semiconductor device according to any one of Examples 1 to 6, wherein the n-type first group III nitride layer comprises a concentration of 5 e 19 cm -3 up to 5 e 17 cm -3 The n-type dopant and / or p-type group III nitride layer includes a concentration of 5 e 20 cm -3 up to 1 e 18 cm -3 p-type dopant.

[0079] 8. The group III nitride semiconductor device according to any one of Examples 1 to 7, wherein the n-type first group III nitride layer comprises a concentration of 5 e 19 cm -3 up to 5 e 17 cm -3 , preferably about 1 e 18 cm -3 The Si dopant, and the p-type group II III nitride layer contains a concentration of 5 e 20 cm -3 up to 1 e 18 cm -3 , preferably about 2 e 19 cm -3 C dopant.

[0080] 9. The group III nitride semiconductor device according to any one of Examples 1 to 8, wherein the n-type first group III nitride layer has a thickness t sn Furthermore, the p-type group II III nitride layer has a thickness of t. sp Where 2 nm ≤ t sn ≤ 8 nm and 10 nm ≤ t sp ≤ 45 nm.

[0081] 9. The group III nitride semiconductor device according to any one of Examples 1 to 8, wherein The n-type Group III nitride layer is formed of AlN, and the p-type Group III nitride layer is formed of Al x Ga (1-x) N forms, where 0 <x<1, The n-type group IIII nitride layer has a thickness of t. sn Furthermore, the p-type group II III nitride layer has a thickness of t. sp Where 2 nm ≤ t sn ≤ 8 nm and 10 nm ≤ t sp ≤ 45 nm, and The n-type first group III nitride layer comprises Si dopant at a concentration of 5 e 19 cm -3 to 5 e 17 cm -3 , preferably about 1 e 18 cm -3 , and the p-type second group III nitride layer comprises C dopant at a concentration of 5 e 20 cm -3 to 1 e 18 cm -3 , preferably about 2 e 19 cm -3 .

[0082] 10. The group III nitride semiconductor device according to any one of examples 1 to 9, wherein the group III nitride buffer structure comprises a group III nitride buffer layer disposed directly on the superlattice, the group III nitride buffer layer is formed of Al x Ga (1-x) N, where 0<x<1 or is GaN, and the group III nitride buffer layer is unintentionally doped.

[0083] 11. The group III nitride semiconductor device according to any one of examples 1 to 9, wherein the group III nitride buffer structure comprises a group III nitride buffer layer disposed directly on the superlattice, the group III nitride buffer layer is formed of Al x Ga (1-x) N, where 0<x<1 or is GaN, and the group III nitride buffer layer comprises alternately stacked n-doped layer regions and p-doped layer regions.

[0084] 12. The group III nitride semiconductor device according to example 11, wherein the n-type layer regions comprise an n-type dopant at a concentration of 5 e 19 cm -3 to 5 e 17 cm -3 , and / or the p-type layer regions comprise a p-type dopant at a concentration of 5 e 20 cm -3 to 1 e 18 cm -3 , and / or wherein the n-type layer regions each have a thickness t bn and the p-type layer regions each have a thickness t bp , where 20 nm ≤ t bn ≤ 50 nm and 5 nm ≤ t bp ≤ 20 nm.

[0085] 13. The group III nitride semiconductor device according to Example 11 or Example 12, wherein the n-type layer region comprises a concentration of approximately 1 e 18 cm -3 The Si dopant, and the p-type layer region includes a concentration of approximately 5 e 19 cm -3 C dopant.

[0086] 14. A group III nitride semiconductor device according to any one of Examples 1 to 13, wherein the power device comprises a transistor device or a bidirectional switch or a diode.

[0087] 15. The group III nitride semiconductor device according to Example 14, wherein the power device includes a HEMT (high electron mobility transistor).

[0088] 16. The group III nitride semiconductor device according to any one of Examples 1 to 15, wherein the group III nitride device layer further includes a first power electrode, a second power electrode, and a gate disposed on the upper surface of the group III nitride device layer.

[0089] 17. The group III nitride semiconductor device according to any one of Examples 1 to 16, wherein the group III nitride device layer includes a group III nitride channel layer disposed on a group III nitride buffer structure and a group III nitride barrier layer disposed on the group III nitride channel layer, wherein a heterojunction capable of supporting a two-dimensional charge carrier gas is formed therebetween.

[0090] 18. The group III nitride semiconductor device according to any one of Examples 1 to 17, wherein the group III nitride device layer further comprises a group III nitride back barrier layer disposed between the group III nitride buffer structure and the group III nitride channel layer, and forming a heterojunction with the group III nitride channel layer capable of supporting a two-dimensional charge carrier gas.

[0091] 19. The group III nitride semiconductor device according to any one of Examples 1 to 17, wherein the group III nitride back barrier layer, the group III nitride channel layer and the group III nitride barrier layer are unintentionally doped.

[0092] 20. A group III nitride semiconductor device according to any one of Examples 1 to 19, wherein the substrate is formed of silicon.

[0093] 21. The group III nitride semiconductor device according to Example 20, wherein the substrate is formed of monocrystalline silicon or an epitaxial silicon layer.

[0094] 22. The group III nitride semiconductor device according to Example 20 or Example 21 further includes an AlN nucleation layer formed on a first main surface of a silicon substrate.

[0095] For ease of description, spatially relative terms (such as "below," "under," "below," "above," "upper," and the like) are used to explain the positioning of one element relative to a second element. These terms are also intended to cover different orientations of the device, in addition to orientations different from those depicted in the figures. Furthermore, terms such as "first," "second," and the like are used to describe various elements, regions, segments, etc., and are not intended to be limiting. Throughout this description, similar terms refer to similar elements.

[0096] As used herein, the terms “having,” “containing,” “comprising,” “including,” and the like are open-ended terms that indicate the presence of a stated element or feature but do not exclude additional elements or features. The articles “a,” “an,” and “the” are intended to include both plural and singular forms unless the context clearly indicates otherwise. It should be understood that features of the various embodiments described herein can be combined with each other unless specifically indicated otherwise.

[0097] Although specific embodiments have been illustrated and described herein, those skilled in the art will appreciate that various alternatives and / or equivalent implementations can be used instead of the illustrated and described embodiments without departing from the scope of the invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that the invention be limited only to the claims and their equivalents.

Claims

1. A group III nitride semiconductor device, comprising: A substrate having a first primary surface capable of supporting the epitaxial growth of at least one group III nitride layer; A group III nitride superlattice disposed on the first main surface of the substrate; A group III nitride buffer structure arranged on the group III nitride superlattice; A group III nitride device layer is disposed on the group III nitride buffer structure and includes power devices for switching loads. The group III nitride superlattice comprises alternating group III nitride layers and group III nitride layers, the alternating group III nitride layers and group III nitride layers comprising different band gaps, wherein the group III nitride layers are n-type and the group III nitride layers are p-type.

2. The group III nitride semiconductor device according to claim 1, wherein... The n-type Group III nitride layer is formed of AlN, and the p-type Group III nitride layer is formed of Al x Ga (1-x) N is formed, where 0 < x < 1, or The n-type Group III nitride layer is formed of AlN, and the p-type Group III nitride layer is formed of GaN, or n-type group IIII nitride layer is composed of Al x Ga (1-x) N is formed, where 0 < x < 1, and the p-type group II III nitride layer is composed of Al. y Ga (1-y) N is formed, where 0 < y < 1 and x ≠ y.

3. The group III nitride semiconductor device according to claim 1 or 2, wherein the n-type first group III nitride layer comprises Si or Ge dopant, and the p-type second group III nitride layer comprises C, Mg, or Fe dopant.

4. The group III nitride semiconductor device according to any one of claims 1 to 3, wherein the n-type first group III nitride layer comprises a concentration of 5 e 19 cm -3 up to 5 e 17 cm -3 The n-type dopant and / or p-type group III nitride layer includes a concentration of 5 e 20 cm -3 up to 1 e 18 cm -3 p-type dopant.

5. The group III nitride semiconductor device according to any one of claims 1 to 4, wherein the n-type first group III nitride layer comprises a concentration of 5 e 19 cm -3 up to 5 e 17 cm -3 , preferably about 1 e 18 cm -3 The Si dopant, and the p-type group II III nitride layer contains a concentration of 5 e 20 cm -3 up to 1 e 18 cm -3 , preferably about 2 e 19 cm -3 C dopant.

6. The group III nitride semiconductor device according to any one of claims 1 to 5, wherein the n-type first group III nitride layer has a thickness t sn Furthermore, the p-type group II III nitride layer has a thickness of t. sp Where 2 nm ≤ t sn ≤ 8 nm and 10 nm ≤ t sp ≤ 45 nm.

7. The group III nitride semiconductor device according to any one of claims 1 to 6, wherein the group III nitride buffer structure comprises a group III nitride buffer layer directly disposed on a superlattice, wherein the group III nitride buffer layer is made of Al x Ga (1-x) N is formed, where 0 < x < 1 or GaN, and the group III nitride buffer layer comprises alternately stacked n-doped layer regions and p-doped layer regions.

8. The group III nitride semiconductor device according to claim 7, The n-type layer region includes a concentration of 5 e 19 cm -3 up to 5 e 17 cm -3 The n-type dopant and / or p-type layer region include a concentration of 5 e 20 cm -3 up to 1 e 18 cm -3 p-type dopants, and / or Each of the n-type layer regions has a thickness t. bn Furthermore, each p-type layer region has a thickness t. bp Where 20 nm ≤ t bn ≤ 50 nm and 5 nm ≤ t bp ≤ 20 nm.

9. The group III nitride semiconductor device according to claim 7 or 8, wherein the n-type layer region comprises a concentration of approximately 1e 18 cm -3 The Si dopant, and the p-type layer region includes a concentration of approximately 5 e 19 cm -3 C dopant.

10. The group III nitride semiconductor device according to any one of claims 1 to 9, wherein the power device comprises a transistor device or a bidirectional switch or a diode.

11. The group III nitride semiconductor device according to any one of claims 1 to 10, wherein the group III nitride device layer further comprises a first power electrode, a second power electrode, and a gate disposed on the upper surface of the group III nitride device layer.

12. The group III nitride semiconductor device according to any one of claims 1 to 11, wherein the group III nitride device layer comprises a group III nitride channel layer disposed on a group III nitride buffer structure and a group III nitride barrier layer disposed on the group III nitride channel layer, wherein a heterojunction capable of supporting a two-dimensional charge carrier gas is formed therebetween.

13. The group III nitride semiconductor device according to any one of claims 1 to 12, wherein the group III nitride device layer further comprises a group III nitride back barrier layer, the group III nitride back barrier layer being disposed between the group III nitride buffer structure and the group III nitride channel layer, and forming a heterojunction with the group III nitride channel layer capable of supporting a two-dimensional charge carrier gas.

14. The group III nitride semiconductor device according to any one of claims 1 to 13, wherein the substrate is formed of silicon.

15. The group III nitride semiconductor device of claim 14, further comprising an AlN nucleation layer formed on a first main surface of a silicon substrate.

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