An N-polar radio frequency switch device and a method of fabricating the same

Abstract

The application discloses an N-polarity radio frequency switch device, which comprises a substrate, an N-polarity buffer layer superposed on the substrate, a Fin structure superposed on the N-polarity buffer layer, a source electrode, a drain electrode, a gate medium and a gate electrode; the N-polarity buffer layer is provided with the source electrode at one end of the surface and the drain electrode at the other end; the Fin structure is located between the source electrode and the drain electrode; the Fin structure comprises N-polarity barrier layers and N-polarity channel layers which are alternately stacked and an N-polarity cap layer superposed on the uppermost layer; the Fin structure is provided with a plurality of inter-fin grooves; the surface and the inter-fin grooves are provided with the gate medium, and the gate electrode is embedded in the inter-fin grooves; the N-polarity channel layer and the N-polarity barrier layer are both nitride semiconductor materials grown along the N-polarity direction. The application controls the closing and opening of the multilayer N-polarity channel through the Fin structure, significantly improves the isolation degree of the device, reduces the on-resistance, and provides a technical scheme with high isolation degree and low loss for a millimeter wave radio frequency switch circuit.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, specifically relating to an N-polarity radio frequency switch device and its fabrication method. Background Technology

[0002] With the rapid development of 5G / 6G millimeter-wave communication, high-resolution phased array radar, and satellite communication systems, radio frequency (RF) front-end systems are placing higher demands on the performance of high-frequency RF switches. The core function of an RF switch is to achieve low-loss signal transmission and high-isolation signal cutoff under high-frequency, high-signal conditions. The core performance indicator for RF switches is the figure of merit (FoM), which is defined as the on-resistance (…). R ON ) and the off capacitor ( C off The product of () and (). The smaller the FoM value, the better the overall switching performance of the device at high frequencies.

[0003] Traditional single-channel AlGaN / GaN high electron mobility transistors (HEMTs) face density is limited by the physical constraints of polarization intensity, making it difficult to further reduce the two-dimensional electron gas (2DEG) areal density. To achieve the extremely low on-resistance required by RF systems, the conventional approach is to significantly increase the physical gate width of the device. However, this directly leads to a sharp increase in parasitic turn-off capacitance, severely degrading high-frequency isolation.

[0004] In recent years, multi-channel epitaxial structures have become the preferred epitaxial structure for high-performance RF switches. As a 2022 study by L. Nela et al. from the Swiss Federal Institute of Lausanne pointed out, multi-channel technology can effectively overcome the carrier concentration limit of single-channel devices, significantly improving the intrinsic current driving capability and reducing sheet resistance. However, existing multi-channel RF devices are mainly based on Ga polar epitaxial materials. As devices evolve towards millimeter waves and even higher frequencies, the short-channel effect of Ga polar materials gradually becomes apparent, hindering performance improvement. When RF switches operate under high voltage conditions, extremely high peak electric fields are generated near the gate edge of the input terminal. Although field plate technology is often used in power amplifiers to alleviate electric field congestion, in millimeter-wave RF switches, traditional field plates introduce huge parasitic capacitances, disrupting high-frequency FOM. Furthermore, to suppress gate leakage current in RF switches, insulating gate dielectrics are typically introduced. The introduction of conventional gate dielectrics introduces positive series dielectric capacitance, leading to severe degradation of the device's subthreshold swing, reducing switching efficiency, and hindering further miniaturization of the device's gate length and width to reduce leakage current. C off .

[0005] In summary, there is currently a lack of RF switch devices in the field of millimeter-wave RF switches that can effectively suppress short-channel effects, simultaneously reduce contact resistance, and possess both high isolation and low loss characteristics. Summary of the Invention

[0006] To address the aforementioned problems in the prior art, this invention provides an N-polarity radio frequency switch device and its manufacturing method. The technical problem to be solved by this invention is achieved through the following technical solution: An N-polar radio frequency switch device includes a substrate, an N-polar buffer layer superimposed on the substrate, a Fin structure superimposed on the N-polar buffer layer, and a source, a drain, a gate dielectric, and a gate.

[0007] The source electrode is located at one end of the surface of the N-polar buffer layer, and the drain electrode is located at the other end; the Fin structure is located between the source electrode and the drain electrode.

[0008] The Fin structure includes alternating stacked N-polar barrier layers and N-polar channel layers, and an N-polar cap layer superimposed on the topmost layer; the Fin structure has multiple inter-fin trenches; the gate dielectric is disposed on the surface and between the multiple inter-fin trenches, and the gate is embedded in and between the multiple inter-fin trenches; the N-polar channel layer and the N-polar barrier layer are both nitride semiconductor materials grown along the N-polar direction.

[0009] Preferably, the angle between the sidewall of the interfin groove and the N-polarity buffer layer is 50~80°.

[0010] Preferably, the N-polar radio frequency switch device further includes a passivation layer, which is superimposed on the surfaces of the N-polar cap layer, the source, the drain, and the gate.

[0011] Preferably, the material of the N-polar barrier layer is any one of N-polar AlGaN, InAlN, and InAlGaN.

[0012] Preferably, the material of the N-polar channel layer is N-polar GaN.

[0013] Preferably, the material of the N-polar buffer layer is a semi-insulating GaN doped with N-polar Fe or C elements.

[0014] Preferably, in the alternately stacked N-polar barrier layer and N-polar channel layer, the thickness of the N-polar barrier layer is 1~20nm, and the thickness of the N-polar channel layer is 5~50nm.

[0015] Preferably, the gate dielectric is a material with intrinsic ferroelectric properties.

[0016] A method for fabricating an N-polarity radio frequency switch device includes the following steps: Step 1: Epitaxially grow an N-polarity buffer layer on a substrate; alternately grow multiple N-polarity barrier layers and N-polarity channel layers on the N-polarity buffer layer, and grow an N-polarity cap layer on top to form an N-polarity multi-channel epitaxial wafer; the N-polarity channel layer and the N-polarity barrier layer are both nitride semiconductor materials grown along the N-polarity direction. Step 2: Define source and drain patterns on the N-polar cap layer of the epitaxial wafer, etch the N-polar cap layer and the N-polar barrier layer and N-polar channel layer below the source and drain patterns, with the etching endpoint located on the upper surface of the N-polar buffer layer, forming source and drain regions; fabricate source and drain electrodes on the source and drain regions respectively, and perform active region isolation; Step 3: Define an arrayed groove pattern on the N-polar cap layer between the source and drain. Etch the N-polar cap layer and the N-polar barrier layer and N-polar channel layer below it within the arrayed groove pattern. The etching endpoint is located on the upper surface of the N-polar buffer layer, forming a Fin structure with multiple interfin trenches. The multiple interfin trenches correspond to the arrayed groove pattern. Step 4: Prepare a gate dielectric on and between the plurality of interfin trenches, and prepare a gate based on the plurality of interfin trenches with the gate dielectric covering the inner surface of the trenches; the gate is fitted into and between the plurality of interfin trenches.

[0017] Preferably, the process further includes step five: depositing a passivation layer on the surface of the wafer obtained after step four, and then creating holes in the passivation layer to fabricate the interconnect metal for the source and drain electrodes. Compared with the prior art, the beneficial effects of the present invention are: This invention employs N-polarity nitride semiconductor material as the carrier for multi-channel devices. Utilizing the back barrier formed by the polarization reversal of the N-polarity nitride semiconductor material, the confinement capability of carriers within the channel is enhanced, thereby suppressing the short-channel effect caused by size reduction. The polarization characteristics of the N-polarity nitride semiconductor material can also reduce the contact resistance in the source and drain regions. Furthermore, the N-polarity RF switch device provided by this invention includes a Fin structure, formed by periodically cutting multiple heterojunctions. This Fin structure allows the gate electric field to directly enter the multi-layer channel laterally from both sides of the Fin structure, thereby achieving unified control of all multi-layer channels. This Fin structure also reduces the sheet resistance in the on-state and improves the isolation in the off-state. Thus, this invention, through the Fin structure, enables the gate to effectively control the on and off of multiple N-polarity channels, significantly improving the device's isolation and reducing on-resistance. R ON This provides a technical solution for millimeter-wave radio frequency switching circuits that combines high isolation with low loss characteristics.

[0018] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0019] Figure 1 It is a comparison of the polarity and performance band structure of Ga and N poles; Figure 2 This is the N-polar multi-channel bandgap structure provided in the embodiments of the present invention; Figure 3 This is a structural diagram of an N-polarity radio frequency switch device provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the structure of an N-polar radio frequency switch device with a V-shaped tilted gate morphology provided in an embodiment of the present invention; Figure 5 This is a comparison diagram of the electric field distribution at the gate pin near the input terminal of an N-polarity RF switch device with a conventional gate and a V-shaped tilted gate provided in an embodiment of the present invention under high operating voltage. Figure 6 This is a schematic diagram of the structure of an N-polar radio frequency switch device with a negative capacitance effect, which uses ferroelectric material as the gate dielectric, according to an embodiment of the present invention. Figure 7 This is a comparison of the subthreshold characteristics of N-polar radio frequency switching devices using conventional materials as gate dielectrics and ferroelectric materials as gate dielectrics provided in the embodiments of the present invention. Figure 8 This is a process flow diagram of the fabrication process of an N-polarity radio frequency switch device provided in an embodiment of the present invention; Figures 9(a)-9(l) This is a schematic diagram of the steps in a method for fabricating an N-polarity radio frequency switch device according to an embodiment of the present invention; Figure 10 This is a cross-sectional schematic diagram in step three of a method for fabricating an N-polarity radio frequency switch device provided in an embodiment of the present invention, wherein the radio frequency switch device has a V-shaped inclined gate sidewall morphology. Detailed Implementation

[0020] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0021] Currently, multi-channel RF switching devices are mainly fabricated using Ga polar epitaxial materials. Multilayer two-dimensional electron gases (2DEGs) help reduce... R ONHowever, planar gate structures struggle to exhaust multiple 2DEG layers, thus deteriorating the isolation in the off-state. By etching, a three-dimensional fin structure is formed by periodically cutting multiple heterojunctions, using the sidewalls and top to control the multi-layer channel and improve the isolation in the off-state. However, due to the intrinsic physical limitations of Ga's polarization characteristics, its conduction band structure lacks a natural back barrier. When RF switches aim to meet millimeter-wave ultra-low voltage requirements... C off When gate length is reduced to meet the requirements, Ga polar devices will face severe short-channel effects, resulting in deep charge penetration, increased leakage current, and a sharp deterioration in high-frequency isolation in the off state.

[0022] Please see Figure 1 , Figure 1 This is a schematic diagram comparing the band structures of Ga and N polar materials. Physically, Ga polar materials consist of a buffer layer, a channel layer, and a barrier layer from bottom to top; N polar materials consist of a buffer layer and a back barrier layer from bottom to top. In terms of band structure, Ga polar materials exhibit a conduction band (…). E c ) and price band ( E v At the heterojunction interface, it bends downwards as a whole, and its core function is to form a surface potential well through polarization effect, so that the Fermi level ( E F The electron density is higher than the conduction band bottom, thus accumulating electrons at the interface and inducing a 2DEG channel. In contrast, N-polar materials exhibit a steep upward bulge of the energy band at the back barrier. Its fundamental function is to construct a strong electron confinement barrier, effectively preventing electron leakage to the buffer layer by increasing the barrier height for carrier migration downwards. This forcibly confines the two-dimensional electron gas to the conduction band after the steep rise of the back barrier. E c The relatively concave channel region. Compared to traditional Ga polar materials, N polar nitrides, due to their reverse polarization characteristics, have a natural back barrier effect and excellent electron confinement capability. Therefore, N polar nitrides are the optimal platform for suppressing short-channel effects in the millimeter-wave band and realizing device miniaturization from a physical source.

[0023] The primary objective of this invention is to fully utilize the advantages of N-polar materials in terms of low on-resistance and high electronic confinement, while overcoming their bottlenecks in device structure and manufacturing processes.

[0024] Therefore, in a first aspect of the present invention, an N-polar radio frequency switch device is provided, which includes an N-polar buffer layer, an N-polar barrier layer, an N-polar channel layer and an N-polar cap layer, thereby utilizing an N-polar multi-channel bandgap structure to significantly reduce on-resistance and increase saturation current.

[0025] Please see Figure 2, Figure 2 This is an N-polar multi-channel bandgap structure provided in an embodiment of the present invention. This bandgap design utilizes the characteristic of polarization direction reversal in N-polar nitride materials to form multiple conduction band bottoms at the interface of the multi-channel bandgap. E c Below the Fermi level ( E F The quantum wells are composed of multiple parallel conductive channels. Each quantum well independently accumulates a high concentration of two-dimensional electron gas (2DEG). The core advantage of this N-polar multi-channel bandgap structure lies in the fact that the resistances of each channel are connected in parallel, resulting in a low total on-resistance. R ON The current is reduced by several times; at the same time, the saturation current is significantly increased, providing an ideal band structure basis for millimeter-wave RF switches with low loss and high current handling capability.

[0026] Please see Figure 3 , Figure 3 This is a structural diagram of an N-polarity radio frequency switch device provided in an embodiment of the present invention. The radio frequency switch device includes a substrate, an N-polarity buffer layer superimposed on the substrate, a Fin structure superimposed on the N-polarity buffer layer, and a source, drain, gate dielectric, and gate. A source is located at one end of the surface of the N-polarity buffer layer, and a drain is located at the other end; the Fin structure is located between the source and drain. The Fin structure includes alternately stacked N-polarity barrier layers and N-polarity channel layers, and an N-polarity cap layer superimposed on the topmost layer; the Fin structure has multiple inter-fin trenches; gate dielectrics are provided on the surfaces and between the multiple inter-fin trenches, and the gate is embedded within and between the multiple inter-fin trenches; both the N-polarity channel layer and the N-polarity barrier layer are nitride semiconductor materials grown along the N-polarity direction.

[0027] This invention employs N-polarity nitride semiconductor material as the carrier for multi-channel devices. The back barrier formed by the polarization reversal of the N-polarity nitride semiconductor material enhances the confinement capability of carriers within the channels, thereby suppressing short-channel effects caused by size reduction. The polarization characteristics of the N-polarity nitride semiconductor material also reduce the contact resistance in the source / drain regions. Furthermore, the N-polarity RF switch device provided by this invention includes a Fin structure, formed by periodically cutting multiple heterojunctions. This Fin structure allows the gate electric field to directly enter the multi-channel channels laterally from both sides of the Fin structure, thereby achieving unified control of all multi-channel channels. This Fin structure also reduces the sheet resistance in the on-state and improves the isolation in the off-state. Thus, this invention, through the Fin structure, enables the gate to effectively control the switching on and off of multiple N-polarity channels, significantly improving the device's isolation and reducing on-resistance. R ON This provides a technical solution for millimeter-wave radio frequency switching circuits that combines high isolation with low loss characteristics.

[0028] Preferably, the substrate can be SiC, Al2O3, Si, or GaN, with a thickness of 300~1000 μm, but it is not limited to this. SiC, Al2O3, or Si are used to form heteroepitaxial growth, while GaN is used to form homoepitaxial growth.

[0029] Preferably, the N-polar buffer layer is a semi-insulating GaN doped with N-polar elements such as Fe or C, and its thickness is 1~2μm, but it is not limited to this.

[0030] Preferably, the N-polar barrier layer is at least one of N-polar AlGaN, InAlN, and InAlGaN, with a thickness of 1-20 nm; the N-polar channel layer is N-polar GaN, with a thickness of 5-50 nm; the number n of alternating N-polar barrier layers and N-polar channel layers should be greater than or equal to 2, preferably 2-5 layers, but is not limited thereto.

[0031] In one embodiment, the angle between the sidewall of the interfin groove in the Fin structure and the buffer layer is 50-80°. Thus, as... Figure 4 As shown, the gate structure exhibits a V-shaped morphology.

[0032] Understandably, traditional metal field plate structures parallel to the surface of the epitaxial structure form huge parallel-plate parasitic capacitances with the underlying channel or epitaxial layer. This directly leads to a sharp increase in the total parasitic capacitance of the RF switch, severely degrading the FoM value of the RF switch device. To avoid this problem, this invention does not use a gate-extended field plate, but instead utilizes the depletion effect of the sidewalls of the three-dimensional Fin structure to suppress the peak electric field at the gate edge. Therefore, this invention fundamentally eliminates the parasitic capacitance path introduced by the metal field plate while ensuring a high breakdown voltage, avoiding the degradation of the RF switch FoM value caused by traditional field plates.

[0033] In addition, in order to reduce the electric field peak near the gate pin of the input terminal under high operating voltage, without deteriorating the performance of the circuit, the following measures are taken: C off Under the premise of achieving excellent withstand voltage characteristics and dynamic on-resistance stability, the embodiments of the present invention have optimized the gate morphology by electric field engineering, replacing the gate structure from a straight I-type gate structure to a continuously sloping V-type gate structure, which achieves an electric field homogenization effect similar to that of an electric field plate.

[0034] Thus, in this embodiment of the invention, the vertical distance between the gate and the channel is continuously and gradually changed by tilting the sidewalls, thereby uniformly dispersing and smoothing the electric field near the gate pin near the input end along the slope, reducing the electric field peak, overcoming the electric field accumulation under high operating voltage, thereby improving the breakdown level of the device and enabling the device to adapt to higher operating voltages.

[0035] Please see Figure 5 , Figure 5 This is a comparison diagram of the electric field distribution near the gate pin of the N-polar RF switch device with a conventional gate and a V-shaped tilted gate provided in the embodiments of the present invention under high operating voltage. Figure 5 In the diagram, the horizontal axis represents the physical spatial location of the device near the input gate edge, and the vertical axis represents the local electric field intensity (E). The solid and dashed lines correspond to the electric field distribution curves of a conventional I-type gate and a V-type tilted gate, respectively. It can be seen that the V-type tilted gate disperses the sharp high electric field peaks, originally concentrated at the edge of a conventional gate, laterally in space, reducing the peak value and effectively improving the device's breakdown voltage threshold. Furthermore, by significantly reducing high field stress, it suppresses the current collapse effect commonly seen in RF switches at high operating voltages, ultimately ensuring the long-term reliability of the device in high-power, high-voltage applications.

[0036] Preferably, the source electrode can be a multilayer metal such as Ti / Au / Ti that can serve as an ohmic metal, with a thickness of 200~300nm.

[0037] Preferably, the drain electrode can be a multilayer metal such as Ti / Au / Ti that can serve as an ohmic metal, with a thickness of 200~300nm.

[0038] In one implementation, the gate dielectric material can be a conventional dielectric material (such as Al2O3) or a high-K dielectric material (such as HfO2), with a thickness of 2~5nm, but it is not limited to these.

[0039] In another implementation, the gate dielectric material can be a ferroelectric material with a thickness of 2-5 nm, but it is not limited to this.

[0040] Specifically, in existing metal-insulator-semiconductor (MIS) structures, the introduction of a conventional gate dielectric is equivalent to adding a positive capacitor in series with the gate circuit. This leads to a decrease in the gate-to-channel coupling efficiency, severely degrading the device's subthreshold swing (SS). This forces the device to employ an extremely large gate voltage swing or a larger physical device size to improve the SS. The introduction of a conventional insulating dielectric is equivalent to adding a positive capacitor to the original gate capacitance... C g A positive capacitor was connected in series. C d According to the principle of capacitor series connection, a decrease in the equivalent capacitance value weakens the gate control force and leads to a deterioration in the subthreshold swing. To mitigate the subthreshold swing deterioration caused by conventional insulating dielectrics, this invention introduces a ferroelectric material as the gate dielectric.

[0041] Ferroelectric materials exhibit negative capacitance, enabling them to overcome the Boltzmann theoretical limit of no less than 60 mV / dec for the subthreshold swing of traditional MOSFETs at room temperature. This allows for a steeper subthreshold slope, resulting in more efficient channel turn-on and turn-off at the same gate voltage swing. For example... Figure 6 As shown, introducing a ferroelectric material as the gate dielectric is equivalent to adding a ferroelectric material to the original gate capacitance. C g A negative capacitor was connected in series. C d Its advantages are specifically reflected in the following aspects: First, the reduction in subthreshold swing means that the gate voltage swing required for switching is smaller, and the dynamic power consumption is significantly reduced; second, the steeper subthreshold slope ensures that the channel can be quickly and completely depleted in the off state, effectively suppressing the leakage current between the source and drain. Especially in RF switch applications, it can avoid the stepped change in channel resistance caused by gate voltage disturbances or process fluctuations, thereby improving the stability of off-state isolation; third, the synergistic effect of the ferroelectric gate dielectric, the sidewall depletion of the three-dimensional Fin structure, and the N-polarity back barrier forms a triple carrier confinement mechanism, further enhancing the suppression of short-channel effects. Therefore, the embodiments of the present invention can not only improve the subthreshold swing, but also achieve lower insertion loss and higher isolation in the millimeter-wave band, providing a feasible material and structural solution for high-performance RF switches.

[0042] Preferably, the ferroelectric material used here can be ScAlN, but it is not limited to this.

[0043] In one specific embodiment of the present invention, when the gate dielectric is a ScAlN gate dielectric, the proportion of Sc component is 15% to 20%.

[0044] This embodiment utilizes the extremely high remanent polarization intensity of ScAlN and, through precise control of the Sc component ratio and film thickness, enables the ScAlN gate dielectric layer to exhibit negative capacitance (NC) characteristics, i.e. C g A negative capacitor is connected in series. C d The equivalent capacitance is increased, improving gate control and enhancing the device's subthreshold characteristics, such as... Figure 10 As shown. This embodiment of the invention introduces a negative capacitance effect through ferroelectric materials, which improves the subthreshold swing, enhances gate control capability, and improves switching characteristics. This allows N-polar devices to be miniaturized to a deeper level in terms of physical size while maintaining high RF switching performance, greatly reducing the total parasitic capacitance and breaking through the FoM of higher frequency RF switches.

[0045] Please see Figure 7 , Figure 7This is a comparison of the subthreshold characteristics of N-polar radio frequency switching devices using conventional materials as the gate dielectric and ferroelectric materials as the gate dielectric provided in the embodiments of the present invention. Figure 7 In the graph, the horizontal axis represents the gate voltage, and the vertical axis represents the drain current of the device. The solid line represents the typical subthreshold characteristic curve of an RF switch device using conventional materials as the gate dielectric, where the current rises gradually with the gate voltage. The dashed line represents the subthreshold characteristic curve of an RF switch device using ferroelectric materials as the gate dielectric. It can be seen that ferroelectric materials utilize a unique negative capacitance effect to make the subthreshold swing of the device steeper, exhibiting a near-step-like rapid turn-on characteristic at a specific gate voltage. Simultaneously, in the off state, its leakage current is significantly lower than that of conventional devices. This not only greatly improves the switching current ratio but also enables the device to achieve extremely fast RF switching with a smaller gate voltage swing, thus effectively balancing the requirements of low power consumption control, high linearity, and low signal leakage in RF switching.

[0046] Preferably, the gate is a multilayer metal such as Ni / Au or other metals that can be used to make the gate, and its thickness is 400~600nm, but it is not limited to this.

[0047] Secondly, embodiments of the present invention provide a method for fabricating an N-polarity radio frequency switch device, such as... Figure 8 As shown, it includes the following steps: Step 1: Epitaxially grow an N-polar buffer layer on the substrate; alternately grow multiple N-polar barrier layers and N-polar channel layers on the N-polar buffer layer, and grow an N-polar cap layer on top to form an N-polar multi-channel epitaxial wafer; both the N-polar channel layer and the N-polar barrier layer are nitride semiconductor materials grown along the N-polar direction. Specifically, an N-polar buffer layer is epitaxially grown on a substrate using MOCVD technology. Multiple N-polar barrier layers and N-polar channel layers are alternately grown on the N-polar buffer layer, and an N-polar cap layer is grown on top.

[0048] For example, an epitaxial wafer was fabricated on a Si substrate using a metal-organic chemical vapor deposition (MOCVD) system, as shown in Figure 9(a). The epitaxial growth sequence was as follows: first, an N-polarity buffer layer was epitaxially grown on the substrate; then, an n-layer N-polarity barrier layer and an N-polarity channel layer were stacked on the N-polarity buffer layer, where n is greater than or equal to 2, i.e., a structure with at least two channels; finally, an N-polarity cap layer was epitaxially grown on the topmost N-polarity channel layer to obtain the epitaxial wafer.

[0049] Step 2: Define source and drain patterns on the N-polar cap layer of the epitaxial wafer, etch the N-polar cap layer and the N-polar barrier layer and N-polar channel layer below the source and drain patterns, with the etching endpoint located on the upper surface of the N-polar buffer layer to form the source and drain regions; fabricate source and drain electrodes on the source and drain regions respectively, and perform active region isolation.

[0050] Specifically, photolithography is used to define the source and drain patterns. Inductively coupled plasma etching (ICP) is used to etch the N-polar cap layer and the N-polar barrier layer and N-polar channel layer below the source and drain patterns to expose the surface of the N-polar buffer layer. Then, the source and drain are formed using a regrowth method, and ion implantation is performed in the non-active region to achieve active region isolation.

[0051] For example, step two specifically includes: (2.1) SiO2 is deposited on the wafer as a mask using a plasma-enhanced chemical vapor deposition (PECVD) system.

[0052] (2.2) Define the source and drain ohmic regrowth regions on the wafer using photolithography.

[0053] (2.3) Using an ICP etching device, the source and drain ohmic regrowth regions are etched to form regrowth regions. First, the SiO2 in the source and drain ohmic regrowth regions is etched using an F-based ICP device to expose the underlying N-polar cap layer. Then, the N-polar cap layer in the source and drain ohmic regrowth regions and the underlying N-polar barrier layer and N-polar channel layer are etched using a Cl-based ICP device.

[0054] (2.4) Using an MOCVD system or a molecular beam epitaxy (MBE) system to grow n in the source regrowth region + InGaN or n + In GaN, the drain regrowth region is the same as the source, and then hydrofluoric acid is used to remove SiO2 and n outside the ohmic regions of the source and drain. + InGaN or n + GaN.

[0055] (2.5) Define the source and drain metal evaporation regions using photolithography, and use electron beam evaporation equipment to grow the n-ohmic regrowth regions of the source and drain. + InGaN or n + Evaporation of Ti / Au / Ti on GaN can serve as a stacked metal for ohmic metals, and the ohmic electrode can be fabricated after stripping.

[0056] (2.6) Photolithography is used to define the active region, which is covered with photoresist, while the non-active region is not covered with photoresist. The active region includes the source surface, the drain surface, and the surface between the source and drain electrodes; the non-active region includes the surface outside the source and drain electrodes. Subsequently, an ion implantation process is performed, where the non-active region without photoresist is implanted to form a high-resistivity region, isolating it from the active region. After photoresist removal, the wafer undergoes annealing to improve the isolation effect.

[0057] At this point, the device structure is shown in Figure 9(b).

[0058] Step 3: Define an arrayed groove pattern on the N-polar cap layer between the source and drain. Etch the N-polar cap layer and the N-polar barrier layer and N-polar channel layer below it within the arrayed groove pattern. The etching endpoint is located on the upper surface of the N-polar buffer layer, forming a Fin structure with multiple interfin trenches. The multiple interfin trenches correspond to the arrayed groove pattern.

[0059] Specifically, firstly, SiO2 is deposited on the wafer using PECVD process as a hard mask for subsequent etching; then, electron beam resist is spin-coated on the wafer to define an arrayed groove pattern, and the N-polar cap layer and the N-polar barrier layer and N-polar channel layer below it are etched using Cl-based etching.

[0060] For example, in step three, SiO2 is deposited using a PECVD process as a hard mask for subsequent etching, including: (3.1) A 100 nm SiO2 layer was deposited on the wafer using a PECVD system as a hard mask for subsequent etching, as shown in Figure 9(c).

[0061] For example, spin-coating an electron beam resist defines an array of groove patterns. The N-polar cap layer and the underlying N-polar barrier layer and N-polar channel layer within the array of groove patterns are etched using a Cl-based etching process, including: (3.2) Electron beam resist is spin-coated onto the wafer to define an array of groove patterns, as shown in Figure 9(d). To more intuitively demonstrate the resist shape at different locations after exposure and development, three cross-sections, AA', BB', and CC', are defined in Figure 9(d), as shown in Figure 9(e). The cross-section AA' shows that the electron beam resist in this area has not been exposed; the cross-section BB' shows that the electron beam resist in this area has been exposed. The length of the groove pattern along the source-drain direction is Fin ( L Fin The CC' section shows the array exposure of the electron beam resist along the gate width direction, with a groove pattern length of [missing information]. W t The width between the groove pattern and the next groove pattern is Fin ( W FinSubsequently, F-based etching was used to remove the SiO2 beneath the arrayed gate trench pattern, as shown in Figure 9(f).

[0062] For example, in step three, spin-coating the electron beam resist includes: (3.2.1) First, pre-bake the sample on a hot plate at 200°C for 5 min to remove moisture. Then, spin-coat the electron beam resist. The electron beam resist can be ZEP 520 or CSAR 62 series electron beam photoresist. In this embodiment, CSAR 62 series 6200.13 resist is used as an example. The spin speed is 3500 rpm for 40 s. After uniform spin coating, the wafer is placed on a hot plate for pre-baking at 150°C for 1 min.

[0063] For example, in step three, the arrayed groove pattern is defined, including: (3.2.2a) First, the electron beam resist on the wafer is exposed. Then, the exposed sample is placed in the electron beam developer AR 600-546 to remove the photoresist in the groove area. The sample is placed on a hot plate at 130°C for 1 min to harden the film and complete the electron beam resist development.

[0064] (3.2.2b) First, using an F-based ICP etching apparatus, the SiO2 beneath the groove pattern is removed, and the arrayed groove pattern is transferred to the hard mask SiO2 beneath the electron beam resist. Then, using an electron beam resist remover AR 600-71, the remaining electron beam resist on the wafer surface is removed, completing the definition of the arrayed groove pattern.

[0065] Optionally, in one implementation, in step three, an I-type gate groove is formed by using the N-polar cap layer and the underlying N-polar barrier layer and N-polar channel layer within the Cl-based etched array groove pattern, as shown in Figure 9(g), including: (3.3a) Using a Cl-based ICP etching system, the N-polar cap layer without a SiO2 hard mask, as well as the stacked n-layer N-polar barrier layer and N-polar channel layer, were etched down to the N-polar buffer layer. During the etching process, the gas flow rate ratio of Cl2 to BCl3 was 4:1, with Cl2 at 20 sccm and BCl3 at 5 sccm. The chamber pressure of the ICP etching system was 10 mT, the upper electrode power was 500 W, and the lower electrode power was 100 W. During this process, the areas with the SiO2 hard mask were not etched using Cl-based etching, while the areas without the SiO2 hard mask were etched down to the N-polar buffer layer. The structures of different cross-sections are shown in Figure 9(g). At this point, the angle between the sidewall of the interfin trench in the Fin structure and the N-polar buffer layer is a right angle. Finally, hydrofluoric acid was used to remove the SiO2 hard mask, completing the fabrication of the Fin structure.

[0066] Alternatively, in another implementation, in step three, a V-shaped gate groove is formed by using the N-polar cap layer and the underlying N-polar barrier layer and N-polar channel layer within the Cl-based etched array groove pattern, such as... Figure 10 As shown, it includes: (3.3b) Controllable tilted sidewalls were achieved using low-pressure Cl-based ICP etching. During the etching process, the gas flow ratio of Cl2 and BCl3 was 1:1, with Cl2 at 15 sccm and BCl3 at 15 sccm. The chamber pressure of the ICP etching system was 5 mT, the upper electrode power was 150 W, and the lower electrode power was 50 W. The effect of the BB' section after etching is shown in the figure. Figure 6 As shown, a V-shaped gate trench with a continuous, gently sloping design is formed, and then the gate metal is fabricated to obtain a gate with an inclined morphology. At this point, the angle between the sidewall of the interfin trench in the Fin structure and the surface of the N-polarity buffer layer is 50~60°.

[0067] Step 4: Prepare a gate dielectric on the surface and between multiple interfin trenches, and prepare a gate based on the multiple interfin trenches covering the inner surface of the trenches with the gate dielectric; the gate is fitted into and between the multiple interfin trenches.

[0068] Specifically, the gate dielectric is fabricated using ALD technology, and the gate electrode is fabricated using electron beam lithography and lift-off processes.

[0069] Optionally, in one embodiment, step four involves using an ALD process to fabricate a gate dielectric of conventional or high-k materials, including: (4.1a) Using an atomic layer deposition (ALD) system, a gate dielectric is deposited to reduce gate leakage current. The deposited material can be a conventional material such as Al2O3 or a high-K dielectric such as HfO2. The effects of different cross sections are shown in Figure 9(h).

[0070] Alternatively, in another embodiment, step four involves fabricating the gate dielectric of the ferroelectric material using an ALD process, including: (4.1b) Using an atomic layer deposition (ALD) system, a gate dielectric is deposited, and the deposited material may be a ferroelectric material. For example, using an atomic layer deposition (ALD) system, ScAlN ferroelectric material is deposited.

[0071] For example, in step four, the gate is fabricated using electron beam lithography and lift-off processes, including: (4.2.1) Spin-coating electron beam resist and using electron beam lithography to define the top grid pattern. The effects of different cross-sections are shown in Figure 9(i).

[0072] (4.2.2) Place the wafer in an electron beam evaporation stage and evaporate the gate metal. The gate metal can be a multilayer metal such as Ni / Au or other metals that can be used to make the gate.

[0073] (4.2.3) After stripping away the electron beam resist, the gate is prepared. The effects of different cross-sections are shown in Figure 9 (j).

[0074] Preferably, the method for fabricating an N-polarity radio frequency switch device provided by the present invention further includes step five: depositing a passivation layer on the surface of the wafer obtained after step four, and then opening holes in the passivation layer to prepare the interconnect metal of the source and drain.

[0075] Specifically, a passivation layer is deposited using PECVD, the passivation layer is etched using ICP, and interconnect metals are prepared using electron beam evaporation.

[0076] For example, step five specifically includes: (5.1) Using a PECVD system, a passivation layer is deposited on the surface of the wafer. The material of the passivation layer can be SiO2, SiN or other materials that can be used as passivation layers. The effects of different cross sections are shown in Figure 9 (k).

[0077] (5.2) Define the opening area on the wafer using photolithography, and remove the passivation layer material and gate dielectric material in the opening area using F-based ICP etching equipment to ensure that the evaporated interconnect metal can make electrode contact.

[0078] (5.3) Place the wafer in an electron beam evaporation stage and evaporate the interconnect metal. The interconnect metal can be a stacked metal such as Ti / Au / Ti. The effect of the BB' section is shown in Figure 9(l).

[0079] Thus, the fabrication of the N-polarity radio frequency switch device is completed.

[0080] In the fabrication method of the N-polar RF switch device provided by this invention, an N-polar nitride multilayer heterojunction is grown epitaxially via MOCVD. The N-polar nitride semiconductor material provides a natural back barrier, suppressing short-channel effects and reducing contact resistance in the source-drain region. Secondly, an I-type gate with a three-dimensional Fin array is formed by Cl-based ICP etching, achieving three-dimensional lateral electrostatic control, reducing sheet resistance in the on-state, and improving isolation in the off-state. Low-voltage Cl-based ICP etching achieves controllable tilted sidewalls, thereby uniformly dispersing and smoothing the electric field near the gate pin near the input end along the slope, reducing electric field peaks, overcoming electric field accumulation under high operating voltages, and thus improving the device's breakdown level, enabling the device to adapt to higher operating voltages. Using ALD to deposit a ferroelectric gate dielectric enhances gate control capability and improves switching characteristics, allowing the device to be miniaturized to a deeper level in physical dimensions, significantly reducing total parasitic capacitance, and breaking through the FoM (Form Factor) limitations of higher frequency RF switches.

[0081] The method for fabricating N-polar radio frequency switching devices provided by this invention is simple, compatible with standard semiconductor processes, suitable for mass production, and has good prospects for industrial applications.

[0082] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. An N-polarity radio frequency switch device, characterized in that, It includes a substrate, an N-polarity buffer layer superimposed on the substrate, a Fin structure superimposed on the N-polarity buffer layer, and a source, drain, gate dielectric, and gate. The source electrode is located at one end of the surface of the N-polarity buffer layer, and the drain electrode is located at the other end; the Fin structure is located between the source electrode and the drain electrode. The Fin structure includes alternating stacked N-polar barrier layers and N-polar channel layers, and an N-polar cap layer superimposed on the topmost layer; the Fin structure has multiple inter-fin trenches; the gate dielectric is disposed on the surface and between the multiple inter-fin trenches, and the gate is embedded in and between the multiple inter-fin trenches; the N-polar channel layer and the N-polar barrier layer are both nitride semiconductor materials grown along the N-polar direction.

2. The N-polarity radio frequency switch device according to claim 1, characterized in that, The angle between the sidewall of the interfin groove and the N-polarity buffer layer is 50~80°.

3. The N-polarity radio frequency switch device according to claim 1, characterized in that, It also includes a passivation layer, which is superimposed on the surfaces of the N-polarity cap layer, the source, the drain, and the gate.

4. The N-polarity radio frequency switch device according to claim 1, characterized in that, The material of the N-polar barrier layer is any one of N-polar AlGaN, InAlN, and InAlGaN.

5. The N-polarity radio frequency switch device according to claim 1, characterized in that, The material of the N-polar channel layer is N-polar GaN.

6. The N-polarity radio frequency switch device according to claim 1, characterized in that, The material of the N-polar buffer layer is a semi-insulating GaN doped with N-polar Fe or C elements.

7. The N-polarity radio frequency switch device according to claim 1, characterized in that, In the alternating stacked N-polar barrier layer and N-polar channel layer, the thickness of the N-polar barrier layer is 1~20nm, and the thickness of the N-polar channel layer is 5~50nm.

8. The N-polarity radio frequency switch device according to claim 1, characterized in that, The gate dielectric is a material with intrinsic ferroelectric properties.

9. A method for fabricating an N-polarity radio frequency switch device, characterized in that, Includes the following steps: Step 1: Epitaxially grow an N-polarity buffer layer on a substrate; alternately grow multiple N-polarity barrier layers and N-polarity channel layers on the N-polarity buffer layer, and grow an N-polarity cap layer on top to form an N-polarity multi-channel epitaxial wafer; the N-polarity channel layer and the N-polarity barrier layer are both nitride semiconductor materials grown along the N-polarity direction. Step 2: Define source and drain patterns on the N-polar cap layer of the epitaxial wafer, etch the N-polar cap layer and the N-polar barrier layer and N-polar channel layer below the source and drain patterns, with the etching endpoint located on the upper surface of the N-polar buffer layer, to form source and drain regions. Source and drain electrodes are fabricated on the source and drain regions respectively, and active region isolation is performed; Step 3: Define an arrayed groove pattern on the N-polar cap layer between the source and drain. Etch the N-polar cap layer and the N-polar barrier layer and N-polar channel layer below it within the arrayed groove pattern. The etching endpoint is located on the upper surface of the N-polar buffer layer, forming a Fin structure with multiple interfin trenches. The multiple interfin trenches correspond to the arrayed groove pattern. Step 4: Prepare a gate dielectric on and between the plurality of interfin trenches, and prepare a gate based on the plurality of interfin trenches with the gate dielectric covering the inner surface of the trenches; the gate is fitted into and between the plurality of interfin trenches.

10. The method for fabricating an N-polarity radio frequency switch device according to claim 9, characterized in that, Also includes: Step 5: Deposit a passivation layer on the surface of the wafer obtained after step 4, and then create holes in the passivation layer to prepare the interconnect metal of the source and drain.

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