Semiconductor device and method for manufacturing semiconductor device

Abstract

The purpose of this disclosure is to provide a semiconductor device capable of suppressing on-resistance and reducing parasitic capacitance. The semiconductor device (101) includes: a gate oxide film (8) formed in an area sandwiched between multiple p-type well regions (4) when viewed from above, i.e., the JFET region (7) containing n... ＋ The region sandwiched between the JFET region (7) and the source region (5) in the surface layer of the p-type well region (3) and the p-type well region (4) is above the channel region; and the gate electrode (9) is formed above the channel region through the gate oxide film (8). The gate oxide film (8) has a deep oxide portion (8A) formed in the JFET region (7) at a depth greater than the gate oxide film (8) above the channel region. The deep oxide portion (8A) has a pointed shape that becomes narrower as it goes deeper.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices. Background Technology

[0002] Patent document 1 discloses a technique for reducing parasitic capacitance by forming a trench between adjacent p-type base layers and burying a portion of the gate oxide film covering the gate electrode into the trench.

[0003] Patent Document 1: Japanese Patent Application Publication No. 2009-259861

[0004] In the structure of Patent Document 1, the on-resistance is higher than that of a typical planar MOS because the gate oxide film buried in the trench restricts the current path. Summary of the Invention

[0005] This disclosure was made to address the aforementioned problems, and its purpose is to provide a semiconductor device capable of suppressing on-resistance and reducing parasitic capacitance.

[0006] The semiconductor device disclosed herein comprises: a drift layer of a first conductivity type formed on a semiconductor substrate of the first conductivity type; a first well region formed on the drift layer, wherein the impurity concentration of the first conductivity type is higher than that of the drift layer; a plurality of second well regions of a second conductivity type discretely formed on the surface of the first well regions; an impurity region of the first conductivity type formed on the surface of each of the plurality of second well regions; a gate oxide film formed on the surface of the first well region and the second well region of the JFET region, which are sandwiched by the plurality of second well regions when viewed from above, i.e., the region sandwiched by the JFET region and the impurity region, i.e., the channel region; and a gate electrode formed on the channel region through the gate oxide film, wherein the gate oxide film has a deep oxide portion formed in the JFET region at a depth greater than that of the gate oxide film on the channel region, and the deep oxide portion has a pointed shape that becomes narrower as it goes deeper.

[0007] In the semiconductor device disclosed herein, parasitic capacitance is reduced by embedding the gate oxide film, i.e., the deep portion of the oxide film, into the first well region of the JFET region. Furthermore, by making the deep portion of the oxide film tapered, the increase in on-resistance is suppressed so as not to obstruct the forward current path. Attached Figure Description

[0008] Figure 1 This is a top view of the semiconductor device according to Embodiment 1.

[0009] Figure 2 This is a cross-sectional view of the semiconductor device according to Embodiment 1.

[0010] Figure 3This is a cross-sectional view of the semiconductor device involved in the first variation of Embodiment 1.

[0011] Figure 4 This is a cross-sectional view of a semiconductor device according to a second variation of Embodiment 1.

[0012] Figure 5 This is a cross-sectional view of the semiconductor device involved in the third variation of Embodiment 1.

[0013] Figure 6 This is a top view of the semiconductor device according to Embodiment 1.

[0014] Figure 7 This is a flowchart illustrating the manufacturing method of the semiconductor device according to Embodiment 1.

[0015] Figure 8 This is a cross-sectional view of the semiconductor device involved in the fourth variation of Embodiment 1.

[0016] Figure 9 This is a cross-sectional view of the semiconductor device involved in the comparative example.

[0017] Figure 10 It is a diagram showing the capacitance waveform of a semiconductor device.

[0018] Figure 11 This is a cross-sectional view of the semiconductor device involved in Embodiment 2.

[0019] Figure 12 This is a flowchart illustrating the manufacturing method of the semiconductor device according to Embodiment 2.

[0020] Explanation of reference numerals in the attached figures

[0021] 1…n type semiconductor substrate; 2…n － Type-3 drift layer; 3…n ＋ 3A… deep well region; 4… p-type well region; 5… source region; 6… p… ＋ Type contact area; 7…JFET region; 8…Gate oxide film; 8A…Deep oxide film; 9…Gate electrode; 9A…Deep gate electrode; 10…Interlayer insulating film; 11…Source electrode; 12…Drain electrode; 100, 101, 101A, 101B, 101C, 101D, 102…Semiconductor device. Detailed Implementation

[0022] In the following explanation, the first conductivity type of the semiconductor layer is designated as n-type, and the second conductivity type as p-type. However, the conductivity types can also be reversed. That is, the first conductivity type can be designated as p-type, and the second conductivity type as n-type. Furthermore, n... ＋ This means that the concentration of n-type impurities is higher than that of n.－ This means that the concentration of n-type impurities is lower than that of n-type impurities. The same applies to p-type impurities; p-type impurities... ＋ This means that the concentration of p-type impurities is higher than that of p-type impurities. － This means that the concentration of p-type impurities is lower than that of p-type impurities.

[0023] <A. Implementation Method 1>

[0024] <A-1. Structure>

[0025] Figure 1 This is a top view of a unit region of the semiconductor device 101 according to Embodiment 1. Figure 2 yes Figure 1 A cross-sectional view of the semiconductor device 101 at line AA. Figure 1 For ease of explanation, the portion above the semiconductor layer and p are omitted. ＋ Type 6 contact area.

[0026] A cell region refers to a region where a semiconductor element structure is formed and operates as a semiconductor element. In the case where the semiconductor device 101 is a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), a MOSFET structure is formed in the cell region and operates as a MOSFET.

[0027] Although Figure 1 and Figure 2 Not shown, but the semiconductor device 101 includes a pad area and a termination area. The pad area is a control pad for controlling the MOSFET. The termination area is the area surrounding the cell area and the pad area.

[0028] Semiconductor device 101 includes, for example, a current sensing pad or a gate pad as a control pad. The current sensing pad is a control pad that detects the current flowing in the cell region. The current sensing pad is electrically connected to a portion of the cell region. Thus, when current flows in the cell region, a fraction to a few ten-thousandths of the current flowing throughout the cell region flows through the current sensing pad. Multiple current sensing pads can be provided, or only one can be provided. The current sensing pad is also referred to as sensing the cell region. On the other hand, the gate pad is connected to the gate electrode 9 of the cell region and controls the current flowing in the cell region. The region where the gate pad is formed is also referred to as the gate pad region. Furthermore, the cross-sectional view of the current sensing pad is also... Figure 2 The diagram shown is the same. That is, the cell area and the current sensing pad have the same cross-sectional structure.

[0029] like Figure 2 As shown, the semiconductor device 101 includes: an n-type semiconductor substrate 1, an n-type semiconductor substrate 2, and an n-type semiconductor substrate 3.－ Type drift layer 2, n ＋ p-type well region 3, p-type well region 4, source region 5, p ＋ The electrode consists of a contact region 6, a gate oxide film 8, a gate electrode 9, an interlayer insulating film 10, a source electrode 11, and a drain electrode 12.

[0030] The n-type semiconductor substrate 1 is, for example, made of silicon carbide (SiC), which is a wide-bandgap semiconductor. Hereinafter, the semiconductor device 101 will be described as a MOSFET, but the semiconductor device 101 may also be an IGBT (Insulated Gate Bipolar Transistor) or the like, in addition to a MOSFET.

[0031] n-type semiconductor substrate 1 is formed on n-type semiconductor substrate 1. － Type 2 drift layer. In n － n is formed on top of drift layer 2 ＋ Type-3 trap region. In n ＋ Multiple p-type well regions 4 are discretely formed on the surface of the p-type well region 3. In this specification, n ＋ The p-type well region 3 is also called the first well region, and the p-type well region 4 is also called the second well region. A source region 5, serving as an impurity region, and a p-type well region 4 are formed on the surface of each p-type well region 4. ＋ Type 6 contact area.

[0032] n ＋ Type-shaped trap region 3, n － The n-type drift layer 2 and source region 5 are regions that have undergone n-type doping. The p-type well region 4 and p... ＋ P-type contact region 6 is the region that has undergone p-type doping. ＋ The carrier concentration in trap region 3 is higher than n. － Type drift layer 2, the carrier concentration in source region 5 is higher than n ＋ Trap region 3.

[0033] The region between two adjacent p-type well regions 4 when viewed from above is called the JFET region 7. It is located between the source region 5 and the n-type well region 4. ＋ The surface layer of the p-type well region 4, sandwiched by the p-type well region 3, forms the channel region. In the JFET region 7, n... ＋ A gate oxide film 8 is formed over the well region 3 and the channel region. A gate electrode 9 is formed over the gate oxide film 8. The gate electrode 9 is formed at a position opposite to the channel region, separated by the gate oxide film 8. An interlayer insulating film 10 is formed to cover the gate electrode 9.

[0034] Through the contact holes of the interlayer insulating film 10, it interacts with the source region 5 and p. ＋An active electrode 11 is formed by contacting the n-type contact region 6. This active electrode 11 is formed in the n-type semiconductor substrate 1 with the n-type contact region 6. － A drain electrode 12 is formed on the main surface of the opposite side of the drift layer 2.

[0035] The gate oxide film 8 is formed thicker in the JFET region 7 than in the channel region. That is, the gate oxide film 8 is formed deeper in the JFET region 7 than in the channel region. The gate oxide film 8 formed at this depth is referred to as the oxide depth 8A.

[0036] exist Figure 1 In this example, the p-type well region 4 and the source region 5 are formed in a stripe pattern. The deep oxide layer 8A is also configured in a stripe pattern at the center of the JFET region 7.

[0037] The horizontal dimension of the oxide film depth 8A is defined as the width of the oxide film depth 8A, and the vertical dimension of the oxide film depth 8A is defined as the thickness of the oxide film depth 8A. The oxide film depth 8A has a pointed shape that becomes narrower towards the drain electrode 12, i.e., deeper into the oxide film. Since the gate oxide film 8 is formed thicker in the JFET region 7 than in the channel region, parasitic capacitance can be reduced. In addition, the pointed shape of the oxide film depth 8A does not obstruct the forward current path, thus avoiding an increase in on-resistance. That is, according to the semiconductor device 101, parasitic capacitance can be reduced without increasing resistance.

[0038] <A-2. Variations>

[0039] For the deep 8A oxide film, any shape that decreases in width with increasing depth is acceptable; it is not limited to any particular shape. Figure 2 The shape shown.

[0040] Figure 3 This is a cross-sectional view of the semiconductor device 101A according to the first variation of Embodiment 1. Figure 3 As shown, the deep oxide film 8A can also be as follows Figure 3 It appears as a triangular shape when viewed in cross-section.

[0041] Figure 4 This is a cross-sectional view of the semiconductor device 101B according to the second variation of Embodiment 1. Figure 4 As shown, the deep oxide film 8A can also be as follows Figure 4 The outline shown is a curve when viewed in cross-section at depth 8A of the oxide film.

[0042] Figure 5 This is a cross-sectional view of the semiconductor device 101C according to the third variation of Embodiment 1. Figure 5As shown, the gate electrode 9 is formed over the channel region and the JFET region 7, separated by the gate oxide film 8, and may also have a gate electrode depth 9A buried deep into the oxide film depth 8A. The gate electrode depth 9A is a portion formed on the oxide film depth 8A at a depth deeper than the surface of the channel region. The gate electrode depth 9A may also be a pointed shape that becomes narrower towards the depth.

[0043] exist Figure 1 In the example, the deep oxide layer 8A is configured as stripes in the center of the JFET region 7. However, as... Figure 6 As shown, the oxide depth 8A can also be periodically arranged in the center of the JFET region 7. This allows for adjustment of parasitic capacitance. Furthermore, if multiple oxide depths 8A are discretely formed within a JFET region 7, their arrangement does not need to be periodic.

[0044] exist Figure 1 and Figure 6 The image shows an example of a MOSFET configured in a striped pattern, but MOSFETs can also be configured in other shapes such as a lattice or hexagon. Regardless of the shape, a deep oxide film 8A is formed within the JFET region 7.

[0045] <A-3. Manufacturing Process>

[0046] The manufacturing method of the semiconductor device 101 will be described. First, in step S101, an n-type semiconductor substrate 1 is prepared.

[0047] Next, in step S102, for example, an n-type semiconductor substrate 1 is formed on its main surface by epitaxial growth via chemical vapor deposition (CVD). － Type 2 drift layer.

[0048] Subsequently, in step S103, an injection mask is formed using a photoresist or the like, and the material is injected into n. － The surface of the n-type drift layer 2 is ion-implanted, for example, with N-type ions. Subsequently, the implantation mask is removed. Through this process, the region ion-implanted with n-type ions becomes n... ＋ Trap region 3.

[0049] In addition, an injection mask is formed using photoresist or similar agents to inject n ＋ Ions are implanted into the p-type well region 3 with, for example, Al, as a p-type impurity. The implantation mask is then removed. Through this process, the region implanted with p-type ions becomes the p-type well region 4.

[0050] Next, an implantation mask is formed using a photoresist or similar agent, and ions such as N, an n-type impurity, are implanted into the p-type well region 4. The implantation mask is then removed. Through this process, the region implanted with n-type ions becomes the source region 5.

[0051] Next, in step S104, annealing is performed in an inert gas atmosphere such as argon (Ar) using a heat treatment apparatus. The annealing temperature is above 1300°C and below 1900°C, and the annealing time is above 30 seconds and below 1 hour. This annealing electroactivates the N and Al that have undergone ion implantation.

[0052] Subsequently, in step S105, a trench is formed, for example, by dry etching, in a manner located at the center of the JFET region 7.

[0053] Next, in step S106, a gate oxide film 8 of the desired thickness is formed on the semiconductor surface, for example, by thermal oxidation. At this time, due to the characteristics of the n-type semiconductor substrate 1, the oxidation rate of the trench portion is faster, and as a result, the gate oxide film 8 of the trench portion, that is, the depth 8A of the oxide film, is formed to be thicker than that of other portions.

[0054] Subsequently, in step S107, a conductive polycrystalline silicon film is formed on the gate oxide film 8 by depressurized CVD, and patterned to form the gate electrode 9. Next, an interlayer insulating film 10 is formed by depressurized CVD. Then, a source region 5 and p-type region 5 are formed that penetrate the interlayer insulating film 10 and the gate oxide film 8 and reach the unit cell. ＋ Contact hole in contact area 6.

[0055] Next, in step S108, after forming a Ni-based metal film by sputtering or the like, a heat treatment at a temperature of 600°C to 1100°C is performed, causing the Ni-based metal film to react with the semiconductor layer within the contact hole, forming silicide between the semiconductor layer and the metal film. Next, wet etching is used to remove the metal film remaining on the interlayer insulating film 10, excluding the silicide formed during the reaction. Thus, an ohmic electrode is formed.

[0056] Furthermore, in the n-type semiconductor substrate 1 and n － On the opposite side of the drift layer 2, i.e. the back side, a metal with Ni as the main component is formed and heat-treated to form an ohmic electrode.

[0057] Subsequently, in step S109, wiring metal such as Al is formed on the surface of the n-type semiconductor substrate 1 processed up to this point by sputtering or vapor deposition, and then processed into a predetermined shape by photolithography, thereby forming a source electrode 11 that contacts the ohmic electrode and a gate wiring that contacts the gate electrode 9. Furthermore, a drain electrode 12, which is a metal film, is formed on the surface of the ohmic electrode formed on the back side of the semiconductor substrate.

[0058] <A-4. Effects>

[0059] Figure 8 This is a cross-sectional view of the semiconductor device 101D according to the fourth variation of Embodiment 1. The semiconductor device 101D differs from the semiconductor device 101C according to the third variation of Embodiment 1 in that it does not possess p... ＋ Type 6 contact area. Furthermore, in Figure 8 The diagrams of the n-type semiconductor substrate 1, source electrode 11, and drain electrode 12 are omitted.

[0060] In semiconductor device 101D, the distance between the uppermost part of the oxide film depth 8A and the p-type well region 4 is 0.2 μm. The width of the uppermost part of the oxide film depth 8A is 0.6 μm. The width of the deepest part of the oxide film depth 8A is 0.1 μm. The height of the oxide film depth 8A is 0.5 μm.

[0061] Figure 9 This is a cross-sectional view of a comparative example semiconductor device 100. The difference between semiconductor device 100 and semiconductor device 101 according to Embodiment 1 is that the gate oxide film 8 does not have an oxide film depth 8A in the JFET region 7.

[0062] Figure 10 The capacitance waveforms of the semiconductor device 101D (hereinafter, "this configuration") according to the fourth variation of Embodiment 1 and the semiconductor device 100 (hereinafter, "existing configuration") of the comparative example are shown. Figure 10 The horizontal axis represents Vd / V, and the vertical axis shows the input capacitance Ciss, the output capacitance Coss, and the reverse transfer capacitance Crss. Vd / V is a value obtained by normalizing the drain voltage using a reference voltage V.

[0063] according to Figure 10 As can be seen, in this configuration, the reverse transfer capacitance Crss is reduced by approximately 25% compared to the existing configuration. That is, in this configuration, since the gate oxide film 8 is formed thicker in the JFET region 7 than in the channel region, the parasitic capacitance can be reduced compared to the existing configuration. Furthermore, in this configuration, since the deep portion 8A of the oxide film has a pointed shape that narrows towards the depth, it does not affect the on-resistance, and the on-resistance of this configuration is the same as that of the comparative example.

[0064] exist Figure 2 In sections -5 and -8, the bottom surface of the deep oxide film 8A is positioned above the bottom surface of the p-type well region 4. This reduces the on-resistance.

[0065] However, the bottom surface of the oxide film depth 8A can also be located lower than the bottom surface of the p-type well region 4. The lower the bottom surface of the oxide film depth 8A is located, the lower the parasitic capacitance and the better the switching characteristics. As compensation, the on-resistance will increase, but by making the oxide film depth 8A a narrow, pointed shape that becomes narrower towards the depth, the increase in on-resistance can be minimized.

[0066] <B. Implementation Method 2>

[0067] <B-1. Structure>

[0068] Figure 11 This is a cross-sectional view of the semiconductor device 102 according to Embodiment 2. The top view of the semiconductor device 102 is also shown. Figure 1 or Figure 6 The top view of the semiconductor device 101 involved in Embodiment 1 shown is the same.

[0069] The difference between semiconductor device 102 and semiconductor device 101 according to Embodiment 1 is that n ＋ The trap region 3 has a deep trap region 3A directly below the oxide depth 8A of the gate oxide film 8. The trap region depth 3A is formed in a region other than that formed directly below the oxide depth 8A. ＋ The location of the trap region at depth 3.

[0070] According to the semiconductor device 102, the on-resistance can be reduced by the depth 3A of the well region compared to the semiconductor device 101 according to Embodiment 1.

[0071] like Figure 11 As shown, the deep portion 3A of the trap region, like the deep portion 8A of the oxide film, has a pointed shape that becomes narrower as it goes deeper.

[0072] <B-2. Manufacturing Process>

[0073] Figure 12 This is a flowchart illustrating a method for manufacturing the semiconductor device 102 according to Embodiment 2. Steps S201, S202, and... Figure 7 Steps S101 and S102 are the same.

[0074] In forming n － After the drift layer 2 and before ion implantation, in step S203, in n － The drift layer 2 should become the region forming groove of the JFET region 7.

[0075] After the groove is formed, in step S204, an injection mask is formed using a photoresist or the like, and the groove is injected into n. － The surface of the n-type drift layer 2 is implanted with N-type ions, for example. Then, the implantation mask is removed. Through this process, the region implanted with n-type ions becomes n... ＋ Trap region 3. In this process, by also performing ion implantation on the part where the groove is formed, ions are implanted deep below the groove, and the region where the implantation is deep becomes the deep part of the trap region 3A.

[0076] The subsequent steps S205, S206, S207, S208, S209 and Figure 7 Steps S104, S106, S107, S108, and S109 are the same.

[0077] <B-3. Effects>

[0078] Similar to the semiconductor device 101 according to Embodiment 1, the semiconductor device 102 includes a gate oxide film 8, i.e., an oxide film depth 8A, which is deeper than the gate oxide film 8 above the channel region within the JFET region 7. The oxide film depth 8A has a pointed shape that becomes narrower towards the depth. Therefore, according to the semiconductor device 102, the on-resistance and parasitic capacitance can be reduced in the same way as in the semiconductor device 101.

[0079] The preferred embodiments have been described in detail above, but are not limited to the embodiments described above. Various modifications and substitutions can be made to the embodiments described above without departing from the scope of the technical solution.

[0080] The various methods disclosed herein will be recorded hereafter as appendices.

[0081] (Note 1)

[0082] A semiconductor device, characterized in that,

[0083] have:

[0084] A drift layer of the first conductivity type is formed on a semiconductor substrate of the first conductivity type;

[0085] The first well region is formed on the drift layer, and the impurity concentration of the first conductivity type is higher than that of the drift layer.

[0086] Multiple second well regions of the second conductivity type are discretely formed on the surface of the first well region.

[0087] Impurity regions of a first conductivity type are formed on the surface of each of the plurality of second well regions;

[0088] A gate oxide film is formed on the surface of the first well region within the JFET region and the second well region, which are sandwiched by the JFET region and the impurity region when viewed from above; and on the channel region within the surface layer of the second well region.

[0089] The gate electrode is formed on the channel region, with respect to the aforementioned gate oxide film.

[0090] The aforementioned gate oxide film has a depth portion formed in the JFET region at a location deeper than the gate oxide film above the channel region.

[0091] The oxide film described above has a pointed shape that becomes narrower as it goes deeper.

[0092] (Note 2)

[0093] The semiconductor device according to Appendix 1 is characterized in that,

[0094] The aforementioned gate electrode is formed over the aforementioned channel region and the aforementioned JFET region, separated by the aforementioned gate oxide film.

[0095] The aforementioned gate electrode has a portion formed above the aforementioned oxide film at a depth greater than the surface of the aforementioned channel region, i.e., the gate electrode depth.

[0096] The aforementioned gate electrode has a pointed shape that becomes narrower as it goes deeper.

[0097] (Note 3)

[0098] The semiconductor device according to Appendix 1 or 2 is characterized in that,

[0099] The aforementioned first well region has a deep portion formed directly below the aforementioned JFET region at a depth greater than other portions.

[0100] The deep part of the first trap region has a pointed shape that becomes narrower as you go deeper.

[0101] (Note 4)

[0102] The semiconductor device according to any one of Appendices 1 to 3 is characterized in that,

[0103] The bottom surface of the aforementioned oxide film is located above the bottom surface of the aforementioned second well region.

[0104] (Note 5)

[0105] The semiconductor device according to any one of Appendices 1 to 3 is characterized in that,

[0106] The bottom surface of the deep part of the oxide film is located below the bottom surface of the second well region.

[0107] (Note 6)

[0108] The semiconductor device according to any one of Appendices 1 to 5 is characterized in that,

[0109] The aforementioned oxide film is discretely formed in multiple deep regions relative to one of the aforementioned JFET regions.

[0110] (Note 7)

[0111] The semiconductor device according to any one of Appendices 1 to 6 is characterized in that,

[0112] The aforementioned semiconductor substrate is a silicon carbide semiconductor substrate.

[0113] (Note 8)

[0114] A method for manufacturing a semiconductor device, characterized in that,

[0115] The aforementioned drift layer of the first conductivity type is formed on a semiconductor substrate of the first conductivity type.

[0116] A first well region with a higher impurity concentration of the first conductivity type than the drift layer is formed on the surface of the drift layer.

[0117] Multiple second well regions of the second conductivity type are discretely formed on the surface layer of the aforementioned first well region.

[0118] Impurity regions of a first conductivity type are formed on the surface of each of the aforementioned multiple second well regions.

[0119] When viewed from above in the first well region, the area sandwiched by the multiple second well regions, i.e., the JFET region, and the area on the surface of the second well region sandwiched by the JFET region and the impurity region, i.e., the channel region, are formed with a gate oxide film.

[0120] A gate electrode is formed over the channel region, separated from the aforementioned gate oxide film.

[0121] Before forming the aforementioned gate oxide film, a trench is formed in the aforementioned JFET region.

[0122] The gate oxide film is formed inside the trench in the JFET region.

[0123] (Note 9)

[0124] According to the method for manufacturing a semiconductor device described in Appendix 8, the characteristic is that...

[0125] The width of the groove decreases as it becomes deeper.

[0126] (Postscript 10)

[0127] The method for manufacturing a semiconductor device according to Appendix 8 or 9 is characterized in that,

[0128] The bottom surface of the aforementioned groove is positioned above the bottom surface of the aforementioned second well region.

[0129] (Postscript 11)

[0130] The method for manufacturing a semiconductor device according to Appendix 8 or 9 is characterized in that,

[0131] The bottom surface of the aforementioned groove is located below the bottom surface of the aforementioned second well region.

[0132] (Postscript 12)

[0133] The method for manufacturing a semiconductor device according to any one of Appendices 8 to 11 is characterized in that,

[0134] The aforementioned groove was formed before the aforementioned first well region.

[0135] (Postscript 13)

[0136] The method for manufacturing a semiconductor device according to any one of Appendices 8 to 11 is characterized in that,

[0137] The aforementioned groove is formed after the aforementioned first well region.

Claims

1. A semiconductor device, characterized in that, have: A drift layer of the first conductivity type is formed on a semiconductor substrate of the first conductivity type; A first well region is formed on the drift layer, wherein the impurity concentration of the first conductivity type is higher than that of the drift layer; Multiple second well regions of the second conductivity type are discretely formed on the surface of the first well region; Impurity regions of a first conductivity type are formed on the surface of each of the plurality of second well regions; A gate oxide film is formed on the surface of the first well region and the second well region of the JFET region, which are sandwiched by multiple second well regions when viewed from above, i.e., the channel region, which is sandwiched by the JFET region and the impurity region. as well as A gate electrode is formed on the channel region, with the gate oxide film in between. The gate oxide film has a depth portion formed in the JFET region at a location deeper than the gate oxide film above the channel region. The oxide film has a pointed shape that becomes narrower as it goes deeper.

2. The semiconductor device according to claim 1, characterized in that, The gate electrode is formed over the channel region and the JFET region, separated by the gate oxide film. The gate electrode has a portion formed above the depth of the oxide film at a location deeper than the surface of the channel region, i.e., the gate electrode depth. The gate electrode has a pointed shape that becomes narrower as it goes deeper.

3. The semiconductor device according to claim 1 or 2, characterized in that, The first well region has a deep portion formed directly below the JFET region at a location deeper than other portions. The first well region has a narrow, pointed shape that becomes narrower as it goes deeper.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that, The bottom surface of the deep oxide film is located above the bottom surface of the second well region.

5. The semiconductor device according to any one of claims 1 to 3, characterized in that, The bottom surface of the deep oxide film is located below the bottom surface of the second well region.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that, The oxide film is discretely formed in multiple deep portions relative to one of the JFET regions.

7. The semiconductor device according to any one of claims 1 to 6, characterized in that, The semiconductor substrate is a silicon carbide semiconductor substrate.

8. A method for manufacturing a semiconductor device, characterized in that, A drift layer of the first conductivity type is formed on a semiconductor substrate of the first conductivity type. A first well region is formed on the surface of the drift layer where the impurity concentration of the first conductivity type is higher than that of the drift layer. Multiple second well regions of a second conductivity type are discretely formed on the surface layer of the first well region. Impurity regions of a first conductivity type are formed on the surface of each of the plurality of second well regions. When viewed from above in the first well region, a gate oxide film is formed on the area sandwiched by multiple second well regions, i.e., the JFET region, and on the surface layer of the second well region, on the area sandwiched by the JFET region and the impurity region, i.e., the channel region. A gate electrode is formed over the channel region, separated from the gate oxide film. Before forming the gate oxide film, a trench is formed in the JFET region. The gate oxide film is formed inside the trench in the JFET region.

9. The method for manufacturing a semiconductor device according to claim 8, characterized in that, The groove becomes narrower as it becomes deeper.

10. The method of manufacturing a semiconductor device according to claim 8 or 9, characterized in that, The bottom surface of the groove is positioned above the bottom surface of the second well region.

11. The method of manufacturing a semiconductor device according to claim 8 or 9, characterized in that, The bottom surface of the groove is located below the bottom surface of the second well region.

12. The method for manufacturing a semiconductor device according to any one of claims 8 to 11, characterized in that, The groove was formed before the first well region.

13. The method for manufacturing a semiconductor device according to any one of claims 8 to 11, characterized in that, The groove is formed after the first well region.

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