Semiconductor device and method of manufacturing the same

Abstract

Provided are a semiconductor device and a method for manufacturing the same. The semiconductor device includes: a semiconductor layer (10) in which a gate trench (GTR) and a dummy trench (DTR) are formed in a first main surface (10a); a trench gate (30) having a gate electrode (34) buried in the gate trench; an interlayer insulating film (50) disposed on the gate electrode and buried in the gate trench; a dummy trench gate (40) having a dummy electrode (44) buried in the dummy trench; and a source electrode (24) in contact with the first main surface of the semiconductor layer and in contact with the dummy electrode buried in the dummy trench. An upper surface of the dummy electrode is located at a position higher than an upper surface of the gate electrode. Thus, a semiconductor device capable of improving the degree of freedom of layout of the trench gate and the dummy trench gate can be provided.

Description

Technical Field

[0001] The technology disclosed in this specification relates to semiconductor devices and methods of manufacturing them. Background Technology

[0002] Patent Documents 1 and 2 disclose semiconductor devices in which an active trench is formed between adjacent trench gates. A source electrode is disposed in the source trench. In a semiconductor device having such a structure, the channel resistance and the gate input capacitance can be adjusted. Furthermore, in this specification, the source trench is referred to as a dummy trench, the electrode disposed in the dummy trench is referred to as a dummy electrode, and the structure including the dummy electrode is referred to as a dummy trench gate.

[0003] Existing technical documents Patent documents Patent Document 1: Japanese Patent Application Publication No. 2024-107497 Patent Document 2: Japanese Patent Application Publication No. 2023-027360 Summary of the Invention

[0004] In semiconductor devices, contacts electrically connected to surface electrodes are required in the region between adjacent trench gates. In the semiconductor devices described in Patent Documents 1 and 2, dummy trench gates are used as contacts. Therefore, in the semiconductor devices described in Patent Documents 1 and 2, dummy trench gates must be arranged in each region between adjacent trench gates, resulting in low layout freedom. This specification provides a technique that can improve the layout freedom of trench gates and dummy trench gates.

[0005] According to one aspect of this disclosure, a semiconductor device may include: a semiconductor layer having a first main surface and a second main surface, and having a gate trench and a dummy trench formed on the first main surface; a trench gate having a gate electrode buried in the gate trench; an interlayer insulating film disposed on the gate electrode and buried in the gate trench; a dummy trench gate having a dummy electrode buried in the dummy trench; and a surface electrode connected to the first main surface of the semiconductor layer and to the dummy electrode buried in the dummy trench. The upper surface of the dummy electrode may be located above the upper surface of the gate electrode. In this semiconductor device, the interlayer insulating film is buried in the trench gate. Therefore, the region between adjacent trench gates in the first main surface of the semiconductor layer can be directly connected to the surface electrode. Thus, the dummy trench gate does not need to be disposed in every region between adjacent trench gates and can be appropriately configured according to specifications. The trench gate and the dummy trench gate of the aforementioned semiconductor device have a high degree of freedom in their layout.

[0006] According to one aspect of this disclosure, a method for manufacturing a semiconductor device may include: a trench forming step, forming a gate trench and a dummy trench on the first main surface of a semiconductor layer having a first main surface and a second main surface; an electrode embedding step, embedding a gate electrode in the gate trench and a dummy electrode in the dummy trench, such that the upper surface of the dummy electrode is located above the upper surface of the gate electrode; and an interlayer insulating film embedding step, embedding an interlayer insulating film in the gate trench. This manufacturing method can produce a semiconductor device with a high degree of freedom in the layout of the trench gate and the dummy trench gate. Attached Figure Description

[0007] Figure 1 It is a schematic representation of the longitudinal sectional view of the main parts of a semiconductor device, and is related to... Figure 2 The longitudinal section view corresponding to line II.

[0008] Figure 2 It is a schematic representation of the cross-sectional view of the main parts of a semiconductor device, and is related to... Figure 1 The cross section view corresponding to line II-II.

[0009] Figure 3 This is a longitudinal sectional view of the main parts of a semiconductor device in a modified example where the layout of the trench gate and the dummy trench gate has been changed. Figure 4 The longitudinal section view corresponding to line III-III.

[0010] Figure 4 This is a cross-sectional view of the main parts of a semiconductor device in a modified example where the layout of the trench gate and the dummy trench gate has been changed. Figure 3 The cross section view corresponding to line IV-IV.

[0011] Figure 5 This is a longitudinal sectional view of the main parts of a semiconductor device in a modified example where the layout of the trench gate and the dummy trench gate has been changed. Figure 6 The longitudinal section view corresponding to the VV line.

[0012] Figure 6 This is a cross-sectional view of the main parts of a semiconductor device in a modified example where the layout of the trench gate and the dummy trench gate has been changed. Figure 5 The cross section view corresponding to line VI-VI.

[0013] Figure 7 Manufacturing Figure 1 and Figure 2 A schematic diagram showing a longitudinal sectional view of the main part of the semiconductor layer in a process of manufacturing a semiconductor device.

[0014] Figure 8 Manufacturing Figure 1 and Figure 2 A schematic diagram showing a longitudinal sectional view of the main part of the semiconductor layer in a process of manufacturing a semiconductor device.

[0015] Figure 9 Manufacturing Figure 1 and Figure 2 A schematic diagram showing a longitudinal sectional view of the main part of the semiconductor layer in a process of manufacturing a semiconductor device.

[0016] Figure 10 Manufacturing Figure 1 and Figure 2 A schematic diagram showing a longitudinal sectional view of the main part of the semiconductor layer in a process of manufacturing a semiconductor device.

[0017] Figure 11 Manufacturing Figure 1 and Figure 2 A schematic diagram showing a longitudinal sectional view of the main part of the semiconductor layer in a process of manufacturing a semiconductor device.

[0018] Figure 12 Manufacturing Figure 1 and Figure 2 A schematic diagram showing a longitudinal sectional view of the main part of the semiconductor layer in a process of manufacturing a semiconductor device.

[0019] Figure 13 Manufacturing Figure 1 and Figure 2 A schematic diagram showing a longitudinal sectional view of the main part of the semiconductor layer in a process of manufacturing a semiconductor device.

[0020] Figure 14 Manufacturing Figure 1 and Figure 2 A schematic diagram showing a longitudinal sectional view of the main part of the semiconductor layer in a process of manufacturing a semiconductor device.

[0021] Figure 15 Manufacturing Figure 1 and Figure 2 A schematic diagram showing a longitudinal sectional view of the main part of the semiconductor layer in a process of manufacturing a semiconductor device.

[0022] Figure 16 This is a schematic diagram showing a longitudinal sectional view of the main parts of a semiconductor device with a modified example of altered trench width of a dummy trench.

[0023] Figure 17This is a schematic diagram showing a longitudinal sectional view of the main parts of a semiconductor device with a modified example of altered trench width of a dummy trench.

[0024] Figure 18 This is a schematic diagram showing a longitudinal sectional view of the main parts of a semiconductor device with a modified example of altered trench depth of a dummy trench.

[0025] Figure 19 This is a schematic diagram showing a longitudinal sectional view of the main parts of a semiconductor device with a modified example of altered trench depth of a dummy trench.

[0026] Figure 20 This is a schematic diagram showing a longitudinal sectional view of the main parts of a semiconductor device with a modified source electrode structure.

[0027] Figure 21 It is a schematic representation of the main parts of a semiconductor device in three dimensions, and is a three-dimensional view with the source electrode removed. Detailed Implementation

[0028] The semiconductor device disclosed in this specification will now be described with reference to the accompanying drawings. Furthermore, for the purpose of clarity, only a portion of the repeatedly arranged components are labeled with reference numerals. Additionally, for the same components in semiconductor devices of different embodiments, the same reference numerals are used, and their descriptions are omitted.

[0029] like Figure 1 and Figure 2 As shown, semiconductor device 1 is an n-channel type power device called a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and includes a semiconductor layer 10 having a first main surface 10a and a second main surface 10b. The material of semiconductor layer 10 can be, for example, silicon carbide (SiC). Here, the first main surface 10a and the second main surface 10b are two opposite surfaces extending in a parallel relationship on the surface of semiconductor layer 10, and are surfaces perpendicular to the thickness direction of semiconductor layer 10. Hereinafter, the structure of semiconductor device 1 will be described with the first main surface 10a as the upper surface, the second main surface 10b as the lower surface, and the thickness direction of semiconductor layer 10 as the vertical direction.

[0030] The semiconductor device 1 further includes a drain electrode 22 covering a second main surface 10b of the semiconductor layer 10, a source electrode 24 covering a first main surface 10a of the semiconductor layer 10, a plurality of trench gates 30 disposed on the first main surface 10a of the semiconductor layer 10, and a plurality of dummy trench gates 40 disposed on the first main surface 10a of the semiconductor layer 10. The semiconductor layer 10 has n+ 12. Drain region of type n, 14. Drift region of type n, 16. Body region of type p, p + Type 17 and n body contact areas + Type 18 source region.

[0031] Drain region 12 is a region formed in the lower portion of semiconductor layer 10, positioned at the location exposed on the second main surface 10b of semiconductor layer 10. Drain region 12 contains a high concentration of n-type impurities and is in ohmic contact with drain electrode 22. As described in the manufacturing method described later, drain region 12 can be a silicon carbide substrate used for epitaxial growth of drift region 14.

[0032] The drift region 14 is a region formed in contact with the upper surface of the drain region 12 and is disposed between the drain region 12 and the body region 16. The concentration of n-type impurities contained in the drift region 14 is lower than the concentration of n-type impurities contained in the drain region 12. The drift region 14 can be formed, for example, by epitaxial growth from the upper surface of the drain region 12.

[0033] Body region 16 is a region formed in contact with the upper surface of drift region 14, disposed between drift region 14 and body contact region 17 and between drift region 14 and source region 18. Body region 16 is in contact with the side surfaces of trench gate 30 and dummy trench gate 40. Body region 16 can be formed, for example, by ion implantation of p-type impurities (e.g., aluminum) from the first main surface 10a of semiconductor layer 10.

[0034] Body contact region 17 is a region formed on the upper part of semiconductor layer 10, adjacent to the upper surface of body region 16, and positioned at the exposed location on the first main surface 10a of semiconductor layer 10. Body contact region 17 contains a high concentration of p-type impurities and has an ohmic contact with source electrode 24. The configuration of body contact region 17 formed on the first main surface 10a of semiconductor layer 10 is appropriately designed according to specifications. Body contact region 17 may, for example, be configured to be adjacent to the upper side of dummy trench gate 40. Body contact region 17 may, for example, be formed by ion implantation of p-type impurities (e.g., aluminum) from the first main surface 10a of semiconductor layer 10.

[0035] Source region 18 is a region formed on the upper part of semiconductor layer 10, adjacent to the upper surface of body region 16, and positioned at the exposed location on the first main surface 10a of semiconductor layer 10. Source region 18 contains a high concentration of n-type impurities and is in ohmic contact with source electrode 24. The configuration of source region 18 formed on the first main surface 10a of semiconductor layer 10 is appropriately designed according to specifications. Source region 18 may, for example, be configured to be adjacent to the upper side of trench gate 30. Source region 18 may, for example, be formed by ion implantation of n-type impurities (e.g., nitrogen) from the first main surface 10a of semiconductor layer 10.

[0036] A trench gate 30 is disposed in a gate trench GTR that extends from the first main surface 10a of the semiconductor layer 10 through the source region 18 and the body region 16 to the drift region 14. When viewed from above, the plurality of trench gates 30 can be configured, for example, in a strip shape. That is, when viewed from above, the plurality of trench gates 30 can extend along one direction (hereinafter referred to as the length direction of the trench gate 30) and be arranged at intervals from each other in a direction orthogonal to its length direction. Alternatively, a portion of the trench gate 30 may be truncated in the length direction, and a dummy trench gate 40 may be disposed in the region between the truncated trench gates 30.

[0037] The trench gate 30 includes a gate insulating film 32 and a gate electrode 34. The gate insulating film 32 is in contact with the side and bottom surfaces of the gate trench GTR. The gate electrode 34 is disposed in the gate trench GTR, and its side and bottom surfaces are covered by the gate insulating film 32. The gate electrode 34 is insulated from the semiconductor layer 10 through the gate insulating film 32. The gate electrode 34 may be, for example, polysilicon doped with a high concentration of n-type impurities.

[0038] The gate electrode 34 is disposed in a portion of the gate trench GTR such that its upper surface is located below the horizontal level of the first main surface 10a of the semiconductor layer 10. In other words, the gate electrode 34 is buried in the gate trench GTR. An interlayer insulating film 50 is disposed in the gate trench GTR on the gate electrode 34. The interlayer insulating film 50 is disposed on the upper part of the gate trench GTR such that its upper surface is flush with the first main surface 10a of the semiconductor layer 10 or its upper surface is located below the horizontal level of the first main surface 10a of the semiconductor layer 10. In other words, the interlayer insulating film 50 is buried in the gate trench GTR. The gate electrode 34 is insulated from the source electrode 24 by the interlayer insulating film 50. The structure in which the interlayer insulating film 50 is buried in the gate trench GTR is called a self-aligned contact structure.

[0039] A dummy trench gate 40 is disposed in a dummy trench DTR extending from the first main surface 10a of the semiconductor layer 10 through the body contact region 17 and the body region 16 to the drift region 14. When viewed from above, the plurality of dummy trench gates 40 can be configured, for example, in a strip shape. That is, when viewed from above, the plurality of dummy trench gates 40 can extend along one direction (hereinafter referred to as the length direction of the dummy trench gate 40) and be arranged at intervals from each other in a direction orthogonal to its length direction. Alternatively, a portion of the dummy trench gate 40 may be truncated in the length direction, and a trench gate 30 may be disposed in the region between the truncated dummy trench gates 40.

[0040] The dummy trench gate 40 includes a dummy insulating film 42 and a dummy electrode 44. The dummy insulating film 42 is in contact with the side and bottom surfaces of the dummy trench DTR. The dummy electrode 44 is disposed in the dummy trench DTR, and its side and bottom surfaces are covered by the dummy insulating film 42. The dummy electrode 44 is separated from the semiconductor layer 10 by the dummy insulating film 42. The dummy electrode 44 may be, for example, polysilicon doped with a high concentration of n-type impurities.

[0041] The dummy electrode 44 is disposed in the dummy trench DTR such that its upper surface is coplanar with the first main surface 10a of the semiconductor layer 10, or its upper surface is located below the horizontal level of the first main surface 10a of the semiconductor layer 10. In other words, the dummy electrode 44 is buried in the dummy trench DTR. The dummy electrode 44 also has its upper surface located above the horizontal level of the upper surface of the gate electrode 34. No interlayer insulating film 50 is disposed in the dummy trench DTR. Therefore, the upper surface of the dummy electrode 44 is in contact with the source electrode 24.

[0042] The source electrode 24 is disposed on the first main surface 10a of the semiconductor layer 10, and includes a silicide layer 24b and a metal electrode layer 24c. The silicide layer 24b may be a thinner layer than the metal electrode layer 24c. The source electrode 24 is an example of a surface electrode.

[0043] The silicide layer 24b is disposed such that it covers the first main surface 10a of the semiconductor layer 10. The silicide layer 24b is disposed at a position that is in contact with the first main surface 10a of the semiconductor layer 10 and the dummy electrode 44, respectively, and is in ohmic contact with them. The silicide layer 24b can be a single metal of titanium (Ti) or a silicide layer formed by silicided titanium-containing compounds such as titanium nitride (TiN).

[0044] The metal electrode layer 24c is configured to cover the first main surface 10a of the semiconductor layer 10 and functions as a metal pad. A recess 26 is formed on the upper surface of the metal electrode layer 24c, located above the gate trench GTR and the dummy trench DTR. As described later, the depth of the recess 26 (the maximum depth of the recess 26) differs between the recess 26 corresponding to the gate trench GTR and the recess 26 corresponding to the dummy trench DTR. The metal electrode layer 24c may also be, for example, aluminum silicon (AlSi).

[0045] Next, the operation of semiconductor device 1 will be explained. If a positive voltage higher than that of source electrode 24 is applied to drain electrode 22, and a positive voltage higher than that of threshold voltage is applied to gate electrode 34, semiconductor device 1 is turned on. At this time, a channel of inversion layer is formed in body region 16, which is connected to the side of trench gate 30. Electrons injected from source region 18 are injected into drift region 14 via inversion layer of body region 16, and further move from drift region 14 to drain region 12. Thus, semiconductor device 1 is turned on. If the positive voltage applied to gate electrode 34 is lower than threshold voltage, inversion layer of body region 16 disappears, and semiconductor device 1 is turned off. In this way, semiconductor device 1 can perform switching operation by controlling the current flowing through inversion layer according to the voltage applied to gate electrode 34.

[0046] As described above, the semiconductor device 1 has a self-aligned contact structure. Therefore, the interlayer insulating film 50 is buried in the gate trench GTR and is not disposed on the first main surface 10a of the semiconductor layer 10. Thus, the source electrode 24 can be directly connected to the first main surface 10a of the semiconductor layer 10. Unlike the prior art described in the background section, in the semiconductor device 1, the dummy trench gate 40 is not used as a contact portion for electrically connecting the semiconductor layer 10 and the source electrode 24. Therefore, the dummy trench gate 40 does not need to be configured for every region between adjacent trench gates 30, and can be appropriately configured according to specifications. For example, it can also be configured as follows: Figure 3 and Figure 4 As shown in semiconductor device 2, when viewed from above, a plurality of dummy trench gates 40 are arranged between adjacent trench gates 30. Alternatively, it can be like... Figure 5 and Figure 6 As shown in semiconductor device 3, when viewed from above, a plurality of trench gates 30 are arranged between dummy trench gates 40. Alternatively, when viewed from above, the trench gates 30 and dummy trench gates 40 can be arranged alternately. These are examples; the layout of the trench gates 30 and dummy trench gates 40 can be appropriately designed according to specifications. The technology disclosed in this specification increases the degree of freedom in the layout of the trench gates 30 and dummy trench gates 40.

[0047] In the above embodiment, the source electrode 24 has a titanium-containing silicide layer 24b in contact with the dummy electrode 44. In the prior art, nickel is often used as the material for the silicide layer. In this case, there is a concern that dust generation may occur due to an abnormal reaction between the polysilicon material of the dummy electrode 44 and nickel. On the other hand, in the semiconductor device 1, since a titanium-containing silicide layer 24b is disposed on the dummy electrode 44, such dust generation is suppressed.

[0048] In the above embodiment, the upper surface of the dummy electrode 44 is located above the horizontal plane of the upper surface of the gate electrode 34. For example, if the upper surface of the dummy electrode 44 is at the same depth as or deeper than the upper surface of the gate electrode 34, since no interlayer insulating film 50 is buried in the dummy trench DTR, the amount of recess 26 above the dummy trench DTR in the upper surface of the source electrode 24 becomes larger, raising concerns about deterioration of the flatness of the source electrode 24. Furthermore, if the upper surface of the dummy electrode 44 is at the same depth as or deeper than the upper surface of the gate electrode 34, since no interlayer insulating film 50 is buried in the dummy trench DTR, the step between the first main surface of the semiconductor layer 10 and the upper surface of the dummy electrode 44 becomes larger, raising concerns about splitting during the deposition of the silicide layer 24b. In the above embodiment, by positioning the upper surface of the dummy electrode 44 above the horizontal level of the upper surface of the gate electrode 34, the increase in the amount of recess 26 corresponding to the dummy trench DTR is suppressed, and the generation of splitting during the formation of the silicide layer 24b is also suppressed. In the above embodiment, the position of the upper surface of the dummy electrode 44 is further adjusted so that the amount of recess 26 corresponding to the dummy trench DTR is less than the amount of recess 26 corresponding to the gate trench GTR. Therefore, the source electrode 24 in the above embodiment can have high flatness and good film formation properties of the silicide layer 24b.

[0049] (Manufacturing method of semiconductor device 1) Next, refer to Figures 7-15 The manufacturing method of semiconductor device 1 will be described.

[0050] First, such as Figure 7 As shown, a semiconductor layer 10 is prepared by stacking a drain region 12, a drift region 14, a body region 16, a body contact region 17, and a source region 18. This semiconductor layer 10 can be prepared, for example, by growing an epitaxial layer with a low concentration of n-type impurities on the upper surface of the drain region 12, which serves as a silicon carbide substrate, and then ion implanting n-type and p-type impurities into the upper part of the epitaxial layer to form the body region 16, the body contact region 17, and the source region 18.

[0051] Next, as Figure 8 As shown, for example, a gate trench (GTR) and a dummy trench (DTR) are formed from the first main surface 10a of the semiconductor layer 10 through the body region 16 to the drift region 14 using a dry etching technique. The gate trench (GTR) can be formed such that at least a portion of its side surface is connected to the source region 18. The dummy trench (DTR) can be formed such that at least a portion of its side surface is connected to the body contact region 17.

[0052] Next, as Figure 9As shown, for example, a silicon oxide film is formed by CVD covering the first main surface 10a of the semiconductor layer 10. The silicon oxide film is also formed on the inner walls of the gate trench GTR and the dummy trench DTR. Thus, a gate insulating film 32 is formed on the side and bottom surfaces of the gate trench GTR, and a dummy insulating film 42 is formed on the side and bottom surfaces of the dummy trench DTR.

[0053] Next, as Figure 10 As shown, for example, a polysilicon film doped with n-type impurities is formed by CVD over the first main surface 10a of the semiconductor layer 10. The polysilicon film is filled in the gate trench GTR and the dummy trench DTR. Next, using an etching technique, unwanted polysilicon film formed above the first main surface 10a of the semiconductor layer 10 is removed by etching back. As a result, the gate electrode 34 is buried in the gate trench GTR, and the dummy electrode 44 is buried in the dummy trench DTR.

[0054] Next, as Figure 11 As shown, for example, a mask 62 is formed on the first main surface 10a of the semiconductor layer 10 using photolithography. The mask 62 is patterned in such a way that it covers the dummy electrode 44 and exposes the gate electrode 34.

[0055] Next, as Figure 12 As shown, for example, a portion of the gate electrode 34 buried in the gate trench GTR is removed using a wet etching technique. After removing a portion of the gate electrode 34, the mask 62 is removed. Through this process, the upper surface of the dummy electrode 44 is positioned above the horizontal level of the upper surface of the gate electrode 34.

[0056] Next, as Figure 13 As shown, for example, an interlayer insulating film 50 is formed by CVD in a manner that covers the first main surface 10a of the semiconductor layer 10. A portion of the interlayer insulating film 50 is buried in the gate trench GTR.

[0057] Next, as Figure 14 As shown, for example, dry etching is used to etch back the interlayer insulating film 50 and insulating films 32 and 42 until the first main surface 10a of the semiconductor layer 10 is exposed. In this etch-back process, the interlayer insulating film 50 and insulating films 32 and 42 can be over-etched to reliably expose the first main surface 10a of the semiconductor layer 10. In this case, the interlayer insulating film 50 and insulating films 32 and 42 after the etch-back process are located below the horizontal level of the first main surface 10a of the semiconductor layer 10.

[0058] Next, as Figure 15As shown, for example, a titanium-containing metal layer is formed by sputtering to cover the first main surface 10a of the semiconductor layer 10. Then, by annealing at a specified temperature, the titanium contained in the metal layer reacts with the silicon contained in the semiconductor layer 10 and the dummy electrode 44 to form a silicide layer 24b.

[0059] Next, for example, a metal electrode layer 24c is formed by sputtering to cover the first main surface 10a of the semiconductor layer 10. This forms a source electrode 24 comprising a silicide layer 24b and the metal electrode layer 24c. Finally, a drain electrode 22 is formed on the second main surface 10b of the semiconductor layer 10, thereby completing the semiconductor device 1.

[0060] In the above manufacturing method, before the step of forming the interlayer insulating film 50, by positioning the upper surface of the gate electrode 34 at a position lower than the horizontal level of the upper surface of the dummy electrode 44, the interlayer insulating film 50 can be selectively buried in the upper part of the gate trench GTR. In the above manufacturing method, the dummy trench gate 40 can be incorporated into a semiconductor device having a self-aligned contact structure.

[0061] In the above embodiment, the trench widths in the short-side direction of the trench gate 30 and the dummy trench gate 40 are the same. Alternatively, it could be like this... Figure 16 As shown in semiconductor device 4, the trench width of the dummy trench gate 40 is made smaller than the trench width of the trench gate 30. Alternatively, it can be like... Figure 17 The trench width of the dummy trench gate 40 is made larger than the trench width of the trench gate 30, as shown in semiconductor device 5. The relative relationship between the trench widths of the trench gate 30 and the dummy trench gate 40 can be appropriately designed according to specifications. Furthermore, in Figure 16 In the case of semiconductor device 4, it can be omitted Figure 11 The mask forming process is shown. Generally, components buried in trenches with small trench widths have low etching rates. Therefore, when the trench width of the dummy trench gate 40 is smaller than the trench width of the trench gate 30, in Figure 12 In the etching process shown, even without the formation of mask 62, the etching rate of the dummy electrode 44 embedded in the dummy trench DTR is low. Therefore, in Figure 12 In the etching process shown, even without forming the mask 62, the upper surface of the dummy electrode 44 can be positioned above the upper surface of the gate electrode 34. Figure 16 The semiconductor device 4 shown has a structure that allows it to be manufactured with fewer steps.

[0062] In the above embodiment, the trench gate 30 and the dummy trench gate 40 have the same trench depth. Alternatively, it could be like this... Figure 18As shown in semiconductor device 6, the trench depth of the dummy trench gate 40 is made deeper than the trench depth of the trench gate 30. Alternatively, it can be like... Figure 19 The trench depth of the dummy trench gate 40 is made shallower than the trench depth of the trench gate 30, as shown in semiconductor device 7. The relative relationship between the trench depths of the trench gate 30 and the dummy trench gate 40 can be appropriately designed according to specifications.

[0063] In the above embodiment, a certain type of silicide layer 24b is used to improve the ohmic characteristics of the source electrode 24. Alternatively, a layer like... Figure 20 The semiconductor device 8, as shown, comprises a silicide layer consisting of a first silicide layer 124a and a second silicide layer 124b. The first silicide layer 124a is selectively disposed at a position adjacent to the first main surface 10a of the semiconductor layer 10, making ohmic contact with the body contact region 17 and the source region 18. More specifically, the first silicide layer 124a is adjacent to the upper surface of the upper portion of the semiconductor layer 10, excluding the gate trench GTR and the dummy trench DTR, i.e., the mesa defined between the trenches GTR and DTR. The first silicide layer 124a is disposed between the first main surface 10a of the semiconductor layer 10 and the metal electrode layer 24c. The first silicide layer 124a can be, for example, a nickel silicide (NiSi) formed by nickel (Ni) silicide. Alternatively, the first silicide layer 124a can also be, for example, a metal silicide formed by tantalum (Ta), tungsten (W), or molybdenum (Mo) silicide. The second silicide layer 124b is made of the same material as the titanium-containing silicide layer 24b described in the above embodiment, and is selectively disposed at the position in contact with the dummy electrode 44. In the semiconductor device 8, since the titanium-containing second silicide layer 124b is disposed at the portion in contact with the dummy electrode 44, dust generation is also suppressed. Furthermore, in the semiconductor device 8, since the nickel-containing first silicide layer 124a is disposed at the portion in contact with the mesa of the semiconductor layer 10, the contact resistance between the source electrode 24 and the semiconductor layer 10 is low. These silicide layers can be fabricated separately, for example, using sputtering and etching techniques.

[0064] Figure 21 A semiconductor device 9 applying the technology disclosed in this specification is shown. In addition to the constituent elements of semiconductor devices in other embodiments, the semiconductor device 9 also includes a superjunction layer 110, an electric field mitigation layer 120, a connection layer 130, and a current dispersing layer 140.

[0065] The superjunction layer 110 is a layer formed in contact with the upper surface of the drift region 14 and disposed between the drift region 14 and the electric field mitigation layer 120. The superjunction layer 110 has a plurality of n-type pillars 112 containing n-type impurities and a plurality of p-type pillars 114 containing p-type impurities. The concentration of n-type impurities in the n-type pillars 112 is higher than the concentration of n-type impurities in the drift region 14.

[0066] The n-type pillar 112 and p-type pillar 114 each have a generally flat plate shape and extend along the thickness direction of the semiconductor layer 10 between the drift region 14 and the electric field mitigation layer 120. The n-type pillar 112 and p-type pillar 114 can each be alternately and repeatedly arranged along the length direction of the trench gate 30 and the dummy trench gate 40, for example. Alternatively, the n-type pillar 112 and p-type pillar 114 can each be repeatedly arranged in any direction. In the semiconductor device 9 equipped with the superjunction layer 110, the on-resistance and breakdown voltage are improved.

[0067] The electric field mitigation layer 120 is formed in contact with the upper surface of the superjunction layer 110 and is disposed between the superjunction layer 110 and the current dispersing layer 140. The electric field mitigation layer 120 includes multiple low-concentration electric field mitigation regions 122 containing p-type impurities, multiple JFET regions 124 containing n-type impurities, and multiple high-concentration electric field mitigation regions 126 containing p-type impurities. The concentration of p-type impurities in the high-concentration electric field mitigation regions 126 is higher than the concentration of p-type impurities in the low-concentration electric field mitigation regions 122. Furthermore, in... Figure 21 The accompanying drawings only show one of the multiple high-concentration electric field mitigation regions 126.

[0068] The low-concentration electric field mitigation regions 122 and JFET regions 124 can each be alternately arranged along a direction different from the repeating direction of the superjunction layer 110, for example, a direction orthogonal to the repeating direction of the superjunction layer 110. Furthermore, the plurality of low-concentration electric field mitigation regions 122 can each be arranged below a corresponding trench in the plurality of trench gates 30 and the plurality of dummy trench gates 40. The plurality of high-concentration electric field mitigation regions 126 can be formed in contact with the upper surfaces of the low-concentration electric field mitigation regions 122 and JFET regions 124, and are spaced apart from each other in a direction different from the repeating direction of the low-concentration electric field mitigation regions 122 and JFET regions 124, for example, a direction orthogonal to the repeating direction of the low-concentration electric field mitigation regions 122 and JFET regions 124. That is, when viewed from above, the plurality of low-concentration electric field mitigation regions 122 and the plurality of high-concentration electric field mitigation regions 126 can be arranged in a lattice pattern. As described above, multiple high-concentration electric field mitigation regions 126 are dispersed in the planar direction of the semiconductor layer 10. Therefore, the multiple high-concentration electric field mitigation regions 126 are not separated from the current dispersing layer 140 by the JFET region 124 in the thickness direction of the semiconductor layer 10. The JFET region 124 and the current dispersing layer 140 are connected in the thickness direction of the semiconductor layer 10 via the region between the high-concentration electric field mitigation regions 126. Thus, the JFET region 124 connects the n-type pillars 112 of the superjunction layer 110 to the current dispersing layer 140 in the thickness direction of the semiconductor layer 10. In the semiconductor device 9 equipped with the electric field mitigation layer 120, the electric field on the bottom surface of the trench gate 30 and the dummy trench gate 40 is mitigated.

[0069] The interconnect layer 130 is a region formed in contact with the side and bottom surfaces of the dummy trench gate 40, and is configured to extend from the first main surface 10a of the semiconductor layer 10 through the body region 16 and the current dispersing layer 140 to the electric field mitigation layer 120. The interconnect layer 130 is a region containing a high concentration of p-type impurities. The upper end of the interconnect layer 130 is in contact with the source electrode 24 and makes an ohmic contact with the source electrode 24. Alternatively, the upper end of the interconnect layer 130 may also be electrically connected to the source electrode 24 via the body contact region 17. The lower end of the interconnect layer 130 is in contact with the low-concentration electric field mitigation region 122 and the high-concentration electric field mitigation region 126 of the electric field mitigation layer 120. In this way, the low-concentration electric field mitigation region 122 and the high-concentration electric field mitigation region 126 of the electric field mitigation layer 120 are fixed at the source potential via the interconnect layer 130.

[0070] The current dispersing layer 140 is a region formed in contact with the upper surface of the electric field mitigation layer 120, disposed between the electric field mitigation layer 120 and the body region 16. The current dispersing layer 140 is contacted with the lower side surface and bottom surface of the trench gate 30, and extends in the planar direction of the semiconductor layer 10. The current dispersing layer 140 is a region containing a high concentration of n-type impurities. The n-type impurity concentration in the current dispersing layer 140 is higher than that in the drift region 14, the n-type pillar 112, and the JFET region 124. Therefore, the current flowing through the semiconductor layer 10 can be spread in the planar direction of the semiconductor layer 10 through the current dispersing layer 140. In the semiconductor device 9 equipped with the current dispersing layer 140, the on-resistance is improved.

[0071] Similar to other implementations, the semiconductor device 9 also has a self-aligned contact structure. Therefore, the trench gate 30 and the dummy trench gate 40 can be freely arranged in the semiconductor device 9.

[0072] The specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes technologies obtained by various modifications and alterations to the specific examples illustrated above. In the above embodiments, a MOSFET is illustrated, but the technology disclosed in this specification can also be applied to other types of semiconductor devices having trench gates, such as IGBTs (Insulated Gate Bipolar Transistors). Furthermore, in the above embodiments, an n-channel semiconductor device is described, but the technology disclosed in this specification can also be applied to p-channel semiconductor devices. Additionally, the technical elements described in this specification or drawings, individually or in various combinations, contribute to the technical utility and are not limited to the combinations described in the claims at the time of application. Furthermore, the technology illustrated in this specification or drawings can achieve multiple objectives simultaneously, and achieving one of these objectives is itself technically practical.

Claims

1. A semiconductor device, characterized in that, have: A semiconductor layer having a first main surface and a second main surface, and having a gate trench and a dummy trench formed on the first main surface; A trench gate having a gate electrode embedded in the gate trench; An interlayer insulating film is disposed on the gate electrode and embedded in the gate trench; A dummy trench gate having a dummy electrode embedded in the dummy trench; as well as A surface electrode, which is connected to the first main surface of the semiconductor layer and to the dummy electrode buried in the dummy trench; The upper surface of the dummy electrode is located above the upper surface of the gate electrode.

2. The semiconductor device according to claim 1, characterized in that, Multiple trench gates are formed on the first main surface of the semiconductor layer. When viewed from above, the semiconductor layer shows that each of the plurality of trench gates extends along a first direction and is spaced apart from each other in a second direction orthogonal to the first direction. Multiple dummy trench gates are formed on the first main surface of the semiconductor layer. When viewed from above, the semiconductor layer shows that each of the plurality of dummy trench gates extends along the first direction and is spaced apart from each other in the second direction. A plurality of dummy trench gates are disposed between adjacent trench gates along the second direction.

3. The semiconductor device according to claim 1, characterized in that, Multiple trench gates are formed on the first main surface of the semiconductor layer. When viewed from above, the semiconductor layer shows that each of the plurality of trench gates extends along a first direction and is spaced apart from each other in a second direction orthogonal to the first direction. Multiple dummy trench gates are formed on the first main surface of the semiconductor layer. When viewed from above, the semiconductor layer shows that each of the plurality of dummy trench gates extends along the first direction and is spaced apart from each other in the second direction. A plurality of the trench gates are disposed between adjacent dummy trench gates along the second direction.

4. The semiconductor device according to claim 1, characterized in that, A recess is formed on the upper surface of the surface electrode, located above the gate trench and the dummy trench. The amount of recess in the recess corresponding to the dummy trench is less than the amount of recess in the recess corresponding to the gate trench.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that, The dummy electrode is polycrystalline silicon. The surface electrode has a titanium-containing silicide layer in the portion that is in contact with the dummy electrode.

6. A manufacturing method for a semiconductor device, characterized in that, have: The trench forming process forms a gate trench and a dummy trench on the first main surface of a semiconductor layer having a first main surface and a second main surface; In the electrode embedding process, a gate electrode is embedded in the gate trench, and a dummy electrode is embedded in the dummy trench, such that the upper surface of the dummy electrode is located above the upper surface of the gate electrode. as well as The interlayer insulating film embedding process involves embedding an interlayer insulating film in the gate trench.

7. The manufacturing method according to claim 6, characterized in that, The electrode embedding process includes: A gate electrode is embedded in the gate trench, and a dummy electrode is embedded in the dummy trench. A mask is formed that covers the dummy electrode and exposes the gate electrode; as well as A portion of the gate electrode buried in the gate trench is removed.

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