Semiconductor device, method of manufacture, power module, conversion circuit and vehicle

Abstract

The application discloses a semiconductor device, a preparation method, a power module, a conversion circuit and a vehicle. The semiconductor device comprises a semiconductor body further comprising a well region and a source region, the source region is located at a first surface, and the well region is arranged to be of a second conductivity type and is located at a side of the source region away from the first surface; the first surface is provided with a groove, and the groove extends from the first surface into the well region; the semiconductor body further comprises a first region, a second region and a third region, and the third region is located at the first surface; the first region is located at a side of the third region adjacent to a second surface, and the first region is in contact with at least the third region and the well region; the second region is located at a side of the groove adjacent to the second surface, and the second region extends from a bottom of the groove to a side of the well region away from the first surface; a vertical projection of the groove on the second surface is located in a vertical projection of the second region on the second surface. The application can reduce the on-resistance of the device and effectively inhibit the degradation of the on-resistance of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and more particularly to a semiconductor device, a fabrication method, a power module, a conversion circuit, and a vehicle. Background Technology

[0002] Silicon carbide metal-oxide-semiconductor field-effect transistors (SiC MOSFETs) have evolved from planar to trench types. By improving the gate structure, the direction of current flow on the gate has changed from planar to vertical. However, existing devices have relatively high on-resistance and low operating efficiency; moreover, the source-drain voltage (Vds) may overshoot or oscillate, causing degradation of the device's on-resistance. Summary of the Invention

[0003] This invention provides a semiconductor device, a fabrication method, a power module, a conversion circuit, and a vehicle, which can reduce the on-resistance of the device and effectively suppress the degradation of the on-resistance.

[0004] According to one aspect of the present invention, a semiconductor device is provided, comprising: The semiconductor body includes a first surface and a second surface disposed opposite to each other; the semiconductor body also includes a well region and a source region, the source region being configured with a first conductivity type and located on the first surface, and the well region being configured with a second conductivity type and located on the side of the source region away from the first surface; the first conductivity type and the second conductivity type are different; a trench is provided on the first surface, the trench extending from the first surface into the well region; the semiconductor body also includes a first region, a second region and a third region, the third region being configured with a second conductivity type and located on the first surface; both the first region and the second region are configured with the first conductivity type; the first region is located on the side of the third region adjacent to the second surface, and the first region is in contact with at least the third region and the well region; the second region is located on the side of the trench adjacent to the second surface, and the second region extends from the bottom of the trench to the side of the well region away from the first surface; The gate is located within the trench; The drain electrode is located on the second surface; The source pole is located on the first surface.

[0005] Based on the above embodiments, optionally, along the first direction, at least two third regions are located on both sides of the trench; each third region corresponds to at least one first region; and adjacent first regions are spaced apart.

[0006] Based on the above embodiments, optionally, the semiconductor device further includes: The fourth region is configured with a second conductivity type and is located on the side of the well region away from the first surface; the second region extends from the bottom of the trench to the side of the fourth region away from the first surface.

[0007] Optionally, based on the above embodiments, the first region and the fourth region are in contact.

[0008] Based on the above embodiments, optionally, the ion concentration in the fourth region is greater than the ion concentration in the well region; The minimum width of the second region in contact with the fourth region is less than the width of the second region in contact with the first surface of the fourth region and the width of the second region in contact with the second surface of the fourth region, respectively; wherein, the first surface is the surface of the fourth region adjacent to the first surface, and the second surface is the surface of the fourth region adjacent to the second surface.

[0009] Based on the above embodiments, optionally, the semiconductor body includes a substrate and an epitaxial layer, and the surface of the substrate away from the epitaxial layer is a second surface; The semiconductor body also includes a fifth region configured as a second conductivity type; the fifth region is located on the side of the fourth region adjacent to the second surface; the vertical projection of the fifth region on the second surface at least partially overlaps with the vertical projection of the third region on the second surface. The fifth region is used to form a semi-superjunction structure or a superjunction structure.

[0010] Based on the above embodiments, optionally, the semiconductor device further includes: A gate insulating layer is located inside the trench and covers the bottom and sidewalls of the trench. An interlayer dielectric layer is located on the side of the first surface away from the second surface; the interlayer dielectric layer is used to isolate the gate and the source; the source is located on the side of the interlayer dielectric layer away from the second surface.

[0011] According to another aspect of the present invention, a method for fabricating a semiconductor device is provided, comprising: A semiconductor body is provided; the semiconductor body includes a first surface and a second surface disposed opposite to each other; the semiconductor body also includes a well region and a source region, the source region being configured with a first conductivity type and located on the first surface, and the well region being configured with a second conductivity type and located on the side of the source region away from the first surface; the first conductivity type and the second conductivity type are different; a trench is provided on the first surface, the trench extending from the first surface into the well region; the semiconductor body also includes a first region, a second region and a third region, the third region being configured with a second conductivity type and located on the first surface; both the first region and the second region are configured with the first conductivity type; the first region is located on the side of the third region adjacent to the second surface, and the first region is in contact with at least the third region and the well region; the second region is located on the side of the trench adjacent to the second surface, and the second region extends from the bottom of the trench to the side of the well region away from the first surface; A gate is formed within the trench; A source electrode is formed on the first surface; A drain electrode is formed on the second surface.

[0012] Based on the above embodiments, optionally, a semiconductor body is provided, including: An epitaxial layer is formed on one side of the substrate; the surface of the substrate away from the epitaxial layer is the second surface; A fourth intermediate region is formed on the side of the epitaxial layer away from the substrate; the fourth intermediate region is configured as a second conductivity type; A well region intermediate region is formed on the side of the fourth region intermediate region away from the second surface; the well region intermediate region is set to the second conductivity type, and the ion concentration of the fourth region intermediate region is greater than the ion concentration of the well region intermediate region; the surface of the well region intermediate region away from the substrate is the first surface; A first mask layer is formed on the side of the epitaxial layer away from the substrate, and the first mask layer is patterned. The patterned first mask layer includes a first opening; the first opening exposes a portion of the first surface. A third region is formed in the first surface based on the first opening; A first region is formed; along a first direction, at least two third regions are located on both sides of the trench; each third region corresponds to at least one first region; adjacent first regions are spaced apart. Remove the first mask layer; A source region is formed on the first surface; Grooves are formed on the first surface; A second region, a trap region, and a fourth region are formed; the second region extends from the bottom of the trench to the side of the fourth region away from the first surface; the minimum width of the second region in contact with the fourth region is less than the width of the second region in contact with the first surface of the fourth region and the width of the second region in contact with the second surface of the fourth region, respectively; wherein, the first surface is the surface of the fourth region adjacent to the first surface, and the second surface is the surface of the fourth region adjacent to the second surface.

[0013] Based on the above embodiments, optionally, forming a first region includes: A second mask layer is formed on the sidewall of the first opening to form a second opening; the width of the second opening is smaller than the width of the first opening. Based on the second opening, a first region is formed in the middle region of the trap region, such that each first region corresponds to a first region. Removing the first mask layer includes: Remove the first mask layer and the second mask layer.

[0014] Based on the above embodiments, optionally, forming a first region includes: A second mask layer is formed on the sidewall of the first opening to form a second opening; the width of the second opening is smaller than the width of the first opening. A third mask layer is formed inside the second opening; the third mask layer fills the second opening; the first mask layer and the third mask layer are made of the same material, and the first mask layer and the second mask layer are made of different materials. Remove the second mask layer to form a third opening; each third region corresponds to two third openings. Based on the third opening, a first region is formed in the middle region of the trap region, such that each first region corresponds to two first regions; Removing the first mask layer includes: Remove the first and third mask layers.

[0015] Based on the above embodiments, optionally, a second region is formed, including: A fourth mask layer is formed on the sidewall of the trench, forming a fourth opening; the width of the fourth opening is smaller than the width of the trench. Based on the fourth opening, a second region is formed at the bottom of the trench; Remove the fourth mask layer.

[0016] According to another aspect of this application, a power module is provided, including a substrate and a semiconductor device as described in any embodiment of this application, wherein the substrate is used to support the semiconductor device.

[0017] According to another aspect of this application, a power conversion circuit is provided, which is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device as described in any embodiment of this application, with the power device electrically connected to the circuit board.

[0018] According to another aspect of this application, a vehicle is provided, including a load and a power conversion circuit as described in any embodiment of this application, the power conversion circuit being used to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input it to the load.

[0019] The technical solution of this application embodiment includes: a semiconductor body, the semiconductor body including a first surface and a second surface disposed opposite to each other; the semiconductor body also includes a well region and a source region, the first surface is provided with a trench, the trench extends from the first surface into the well region; the semiconductor body also includes a first region, a second region and a third region, the third region is configured with a second conductivity type and is located on the first surface; the first region and the second region are both configured with a first conductivity type; the first region is located on the side of the third region adjacent to the second surface, and the first region is in contact with at least the third region and the well region; the second region is located on the side of the trench adjacent to the second surface, and the second region extends from the bottom of the trench to the side of the well region away from the first surface. In this embodiment, the first region is in contact with at least the third region and the well region, forming a carrier discharge path. The first region and the third region form a low-resistance channel, which can form a discharge path for avalanche current or surge current, so that carriers are quickly discharged and current flows quickly, which can effectively suppress overshoot and oscillation problems caused by source-drain voltage (Vds). The PN junction formed by the first region and the well region affects the electric field at the trench sidewalls, allowing for a smoother carrier extraction and preventing electric field impacts at the interfaces of different materials on the trench sidewalls. This improves the electric field distribution, protects the trench interface, prevents electric field accumulation at the interface, and effectively suppresses the degradation of the device's on-resistance. Setting a second region at the bottom of the trench further reduces the device's on-resistance, thereby improving its operating efficiency.

[0020] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application.

[0023] Figure 2 This is a cross-sectional schematic diagram of a semiconductor device provided in an embodiment of this application.

[0024] Figure 3 This is a cross-sectional schematic diagram of another semiconductor device provided in the embodiments of this application.

[0025] Figure 4 This is a cross-sectional schematic diagram of another semiconductor device provided in the embodiments of this application.

[0026] Figure 5 This is a cross-sectional schematic diagram of another semiconductor device provided in the embodiments of this application.

[0027] Figure 6 This is a cross-sectional schematic diagram of another semiconductor device provided in the embodiments of this application.

[0028] Figure 7 This is a flowchart of a method for fabricating a semiconductor device provided in an embodiment of this application.

[0029] Figures 8-19 This is a schematic diagram of the intermediate structure of a semiconductor device provided in an embodiment of this application. Detailed Implementation

[0030] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0031] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0032] This application provides a semiconductor device. Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application. Figure 2 This is a cross-sectional schematic diagram of a semiconductor device provided in an embodiment of this application, with reference to... Figure 1 and Figure 2 Semiconductor devices include: The semiconductor body 1 includes a first surface 01 and a second surface 02 disposed opposite to each other. The semiconductor body 1 also includes a well region 30 and a source region 40. The source region 40 is configured with a first conductivity type and is located on the first surface 01. The well region 30 is configured with a second conductivity type and is located on the side of the source region 40 away from the first surface 01. The first conductivity type and the second conductivity type are different. A trench 50 is provided on the first surface 01, extending from the first surface 01 into the well region 30. The semiconductor body 1 also includes a first region 11, a second region 12, and a third region 13. The third region 13 is configured with a second conductivity type and is located on the first surface 01. Both the first region 11 and the second region 12 are configured with the first conductivity type. The first region 11 is located on the side of the third region 13 adjacent to the second surface 02, and the first region 11 is in contact with at least the third region 13 and the well region 30. The second region 12 is located on the side of the trench 50 adjacent to the second surface 02, extending from the bottom of the trench 50 to the side of the well region 30 away from the first surface 01. Gate G is located within trench 50; Drain electrode D is located on the second surface O2; The source electrode S is located on the first surface O1.

[0033] In this embodiment, the semiconductor device includes, but is not limited to, MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), JFET (Junction Field-Effect Transistor), IGBT (Insulated Gate Bipolar Transistor), and HEMT (High Electron Mobility Transistor). The semiconductor body may include wide-bandgap or ultra-wide-bandgap semiconductor materials such as silicon carbide semiconductor body and gallium nitride semiconductor body. Exemplarily, the MOSFET includes an N-type MOSFET or a P-type MOSFET. For an N-type MOSFET, the first conductivity type is N-type, and the second conductivity type is P-type. For a P-type MOSFET, the first conductivity type is P-type, and the second conductivity type is N-type. For regions with N-type conductivity, N-type doping can be used, where the dopant ions can be phosphorus (P) ions or nitrogen (N) ions; for regions with P-type conductivity, P-type doping can be used, where the dopant ions can be aluminum (Al) ions or boron (B) ions. If the device is an N-type device, the well region 30 can be a P-type well region, the source region 40 can be an N+ source region, the first region 11 and the second region 12 can be N-type regions, and the third region 13 can be a P-type source region. The material of the semiconductor body 1 may include silicon carbide (SiC), and the semiconductor device in the embodiments of this application can be a SiC MOSFET device.

[0034] Specifically, the semiconductor body 1 includes a substrate 10 and an epitaxial layer 20 stacked sequentially; both the substrate 10 and the epitaxial layer 20 are configured with a first conductivity type; only the doping ion concentrations differ. The surface of the substrate 10 away from the epitaxial layer 20 is a second surface 02, and the surface of the source region 40 away from the substrate 10 is a first surface 01. The semiconductor body 1 can be formed by a single epitaxial layer or by multiple epitaxial layers. That is, the semiconductor body 1 can be a single epitaxial layer or a stacked structure formed by multiple epitaxial layers. The material of the substrate 10 and the material of the epitaxial layer 20 can be the same, or the material of the substrate 10 and the material of the epitaxial layer 20 can be different. For example, the material of the epitaxial layer 20 and the material of the substrate 10 can both be SiC.

[0035] In this embodiment, the first region 11 and the third region 13 can be formed by ion implantation or by first etching a groove and then depositing within it. For example, if ion implantation is used, the third region 13 and the first region 11 will form an ion scattering region. The ion scattering region of the third region 13 is a light red region surrounding a dark red region, and the ion scattering region of the first region 11 is a light blue region surrounding a blue region. The first region 11 is in contact with at least the well region 30 and the third region 13. During reverse blocking, the interface between the first region 11 and the well region 30 forms a PN junction, meaning that some holes in the well region 30 are stored in the first region 11. During reverse recovery of the body diode, the first region 11 and the third region 13 contact, forming a carrier discharge path. The first region 11 and the third region 13 form a low-resistance channel, thus creating a discharge path for avalanche current or surge current, allowing carriers to be quickly discharged and current to flow rapidly, effectively suppressing overshoot and oscillation problems caused by source-drain voltage (Vds). The PN junction formed by the first region 11 and the well region 30 will affect the electric field at the sidewall of the trench 50, so that the charge carriers can be extracted smoothly, avoiding the electric field impact at the interface of different materials on the sidewall of the trench 50, which can improve the electric field distribution, protect the trench interface, avoid the electric field accumulation at the interface, and effectively suppress the degradation of the on-resistance of the device.

[0036] For example, the vertical projection of the groove 50 onto the second surface 02 is located within the vertical projection of the second region 12 onto the second surface 02.

[0037] The second region 12 is located at the bottom of the trench 50. The second region 12 serves as a current conduction path, enabling the device to conduct. Since the second region 12 is only located at the bottom of the trench 50, its concentration can be set relatively high, resulting in lower on-resistance and improved device efficiency. However, if the entire lateral region of the device under the trench is composed of a high concentration of the second region 12, the second region 12 will deplete the charge carriers in the shielding area during subsequent shielding formation, leading to a decrease in shielding effectiveness and increased susceptibility to device breakdown.

[0038] The technical solution of this application embodiment includes: a semiconductor body 1, which includes a first surface 01 and a second surface 02 disposed opposite to each other; the semiconductor body 1 also includes a well region 30 and a source region 40, the first surface 01 is provided with a trench 50, the trench 50 extends from the first surface 01 into the well region 30; the semiconductor body 1 also includes a first region 11, a second region 12 and a third region 13, the third region 13 is configured as a second conductivity type and is located on the first surface 01; the first region 11 and the second region 12 are both configured as first conductivity type; the first region 11 is located on the side of the third region 13 adjacent to the second surface 02, and the first region 11 is in contact with at least the third region 13 and the well region 30; the second region 12 is located on the side of the trench 50 adjacent to the second surface 02, and the second region 12 extends from the bottom of the trench 50 to the side of the well region 30 away from the first surface 01. In this embodiment, the first region 11 is in contact with at least the third region 13 and the well region 30, forming a discharge path for charge carriers. The first region 11 and the third region 13 form a low-resistance channel, which can form a discharge path for avalanche current or surge current, allowing charge carriers to be quickly discharged and current to pass through rapidly, effectively suppressing overshoot and oscillation problems caused by source-drain voltage (Vds). The PN junction formed by the first region 11 and the well region 30 affects the electric field at the sidewall of the trench 50, allowing charge carriers to be extracted smoothly, avoiding electric field impacts at the interfaces of different materials on the sidewall of the trench 50, improving the electric field distribution, protecting the trench interface, preventing electric field accumulation at the interface, and effectively suppressing the degradation of the device's on-resistance. Setting the second region 12 at the bottom of the trench 50 can reduce the on-resistance of the device, thereby improving the device's operating efficiency.

[0039] Based on the above embodiments, Figure 3 This is a cross-sectional schematic diagram of another semiconductor device provided in the embodiments of this application, referred to... Figures 2-3 Optionally, along the first direction X, at least two third regions 13 are located on both sides of the trench 50; each third region 13 corresponds to at least one first region 11; adjacent first regions 11 are spaced apart.

[0040] In this design, both the first direction X and the second direction Y are perpendicular to the third direction Z. The second direction Y is the direction from the second surface O2 to the first surface O1, and it is also the depth direction of the trench 50. The third direction Z is the inward extension direction of the trench 50.

[0041] For details, please refer to Figure 2 Each third region 13 corresponds to a first region 11, see reference. Figure 3Each third region corresponds to two first regions 11. The more first regions 11 there are, the more discharge paths there are for charge carriers, allowing them to be quickly discharged and current to flow through rapidly. This can more effectively suppress overshoot and oscillation problems caused by source-drain voltage (Vds). The more first regions 11 there are, the larger the contact area between the first region 11 and the well region 30, the larger the depletion region formed, and the greater the influence of the electric field. This can avoid electric field impacts at the interfaces of different materials on the sidewalls of the trench 50, further improve the electric field distribution, protect the trench interface, prevent electric field accumulation at the interface, and effectively suppress the degradation of the device's on-resistance.

[0042] Based on the above embodiments, optionally, refer to Figures 1-3 The semiconductor device further includes: a fourth region 14, which is configured as a second conductivity type and is located on the side of the well region 30 away from the first surface 01; and a second region 12 extending from the bottom of the trench 50 to the side of the fourth region 14 away from the first surface 01.

[0043] Based on the above embodiments, optionally, refer to Figure 1 and Figure 3 The first region 11 comes into contact with the fourth region 14.

[0044] Based on the above embodiments, optionally, Figure 4 This is a cross-sectional schematic diagram of another semiconductor device provided in the embodiments of this application, referred to... Figure 4 The first area 11 and the fourth area 14 do not come into contact.

[0045] The third region 13 serves to reduce ohmic contact. The third region 13 is electrically connected to the fourth region 14 and is grounded. The first region 11 is in contact with the third region 13, and the third region 13 and the fourth region 14 are at the same potential. Whether the first region 11 is in contact with the fourth region 14 or not, the first region 11 provides a discharge path with a significant barrier and impedance for holes in the fourth region 14, thus forming a discharge path for avalanche current or surge current. This allows for rapid conduction of charge carriers and rapid current flow, effectively suppressing oscillations caused by excessive current. Furthermore, the fourth region 14 provides electric field shielding for the trench corners of the trench 50, protecting the gate insulating layer 51 and preventing its breakdown within the trench 50, thereby improving the reliability of the semiconductor device. When the first region 11 and the fourth region 14 are in direct contact, charge carriers are discharged more rapidly, further suppressing oscillations caused by excessive current.

[0046] Based on the above embodiments, refer to Figures 1-4Optionally, the ion concentration of the fourth region 14 is greater than the ion concentration of the trap region 30; the minimum width of the second region 12 in contact with the fourth region 14 is less than the width of the second region 12 in contact with the first surface of the fourth region 14 and the width of the second region 12 in contact with the second surface of the fourth region 14, respectively; wherein, the first surface is the surface of the fourth region 14 adjacent to the first surface 01, and the second surface is the surface of the fourth region 14 adjacent to the second surface 02.

[0047] The second region 12 extends from the bottom of the trench 50 to the side of the fourth region 14 away from the first surface 01. The fourth region 14 has a higher ion concentration, enabling it to shield the trench corners of the trench 50 from the electric field. The second region 12 is located within the well region 30, the fourth region 14, and the epitaxial layer 20. Because the ion concentration in the fourth region 14 is greater than that in the well region 30, when the second region 12 is formed by ion implantation, the fourth region 14 consumes more ions than the well region 30 when using the same ion implantation concentration. Therefore, the width of the second region 12 in contact with the fourth region 14 is smaller than the width of the second region 12 in contact with the well region 30. The epitaxial layer 20 and the second region 12 have the same conductivity type, therefore the second region 12 in contact with the epitaxial layer 20 is the widest, meaning the width of the second region in contact with the epitaxial layer 20 is greater than the width of the second region 12 in contact with the well region 30. The first surface of the fourth region 14 is the surface that contacts the well region 30, and the second surface of the fourth region 14 is the surface that contacts the epitaxial layer 20. In the second region 12 that contacts the fourth region 14, the minimum width of the second region 12 is located in the middle region of the fourth region 14 along the second direction Y. The minimum width of the second region 12 is smaller than both the width of the second region 12 that contacts the first surface and the width of the second region 12 that contacts the second surface, thus forming a second region 12 with curved edges on both sides along the first direction X. All width dimensions are dimensions along the first direction X.

[0048] Based on the above embodiments, optionally, Figure 5 This is a cross-sectional schematic diagram of another semiconductor device provided in the embodiments of this application. Figure 6 This is a cross-sectional schematic diagram of another semiconductor device provided in the embodiments of this application, referred to... Figure 5 and Figure 6 The semiconductor body 1 includes a substrate 10 and an epitaxial layer 20. The surface of the substrate 10 away from the epitaxial layer 20 is a second surface 02. The semiconductor body 1 also includes a fifth region 15, which is configured as a second conductivity type. The fifth region 15 is located on the side of the fourth region 14 adjacent to the second surface 02. The vertical projection of the fifth region 15 on the second surface 02 at least partially overlaps with the vertical projection of the third region 13 on the second surface 02. The fifth region 15 is used to form a semi-superjunction structure or a superjunction structure.

[0049] in, Figure 5 The fifth region 15 is used to form a semi-superjunction structure. The surface of the fifth region 15 away from the first surface 01 does not contact the substrate. The epitaxial layer 20 is between the fifth region 15 and the substrate 10. Figure 6 The fifth region 15 is used to form a superjunction structure, and the surface of the fifth region 15 away from the first surface 01 is in contact with the substrate 10. The fifth region 15 can be a heavily doped P+ region. By forming a semi-superjunction structure or a superjunction structure in the epitaxial layer 20, the breakdown voltage of the semiconductor device can be further improved.

[0050] Based on the above embodiments, optionally, refer to Figure 1 The semiconductor device further includes: a gate insulating layer 51 located within a trench 50, covering the bottom and sidewalls of the trench 50; an interlayer dielectric layer 60 located on the side of the first surface 01 away from the second surface 02; the interlayer dielectric layer 60 is used to isolate the gate G and the source S; the source S is located on the side of the interlayer dielectric layer 60 away from the second surface 02.

[0051] The gate G can be made of polysilicon; the gate insulating layer 51 can be made of silicon oxide. The source S and drain D can be made of metal, for example, aluminum. The interlayer dielectric layer 60 covers the gate G, the gate insulating layer 51, and a portion of the source region 40, exposing a portion of the source region 40, such that the source S contacts the portion of the source region 40 and the third region 13. The interlayer dielectric layer 60 can also be made of silicon oxide or silicon nitride.

[0052] Based on the above embodiments, this invention also provides a method for fabricating a semiconductor device, used to fabricate the aforementioned semiconductor device. Figure 7 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of this application, see reference. Figure 7 The preparation methods include: S100. A semiconductor body is provided; the semiconductor body includes a first surface and a second surface disposed opposite to each other; the semiconductor body also includes a well region and a source region, the source region being configured with a first conductivity type and located on the first surface, and the well region being configured with a second conductivity type and located on the side of the source region away from the first surface; the first conductivity type and the second conductivity type are different; a trench is provided on the first surface, the trench extending from the first surface into the well region; the semiconductor body also includes a first region, a second region and a third region, the third region being configured with a second conductivity type and located on the first surface; both the first region and the second region are configured with the first conductivity type; the first region is located on the side of the third region adjacent to the second surface, and the first region is in contact with at least the third region and the well region; the second region is located on the side of the trench adjacent to the second surface, and the second region extends from the bottom of the trench to the side of the well region away from the first surface.

[0053] S200, A gate is formed in the trench.

[0054] The gate is formed through a deposition process.

[0055] S300, the source electrode is formed on the first surface.

[0056] The source electrode can be formed through sputtering.

[0057] S400, a drain electrode is formed on the second surface.

[0058] The drain electrode can be formed through sputtering.

[0059] This application provides a method for fabricating a semiconductor device. By setting a first region to contact at least a third region and a well region, a carrier discharge path is formed. The first and third regions form a low-resistance channel, which can form a discharge path for avalanche current or surge current, allowing carriers to be quickly discharged and current to flow through rapidly. This effectively suppresses overshoot and oscillation problems caused by source-drain voltage (Vds). The PN junction formed by the first region and the well region affects the electric field at the trench sidewall, allowing carriers to be extracted smoothly and avoiding electric field impacts at the interfaces of different materials on the trench sidewall. This improves the electric field distribution, protects the trench interface, prevents electric field accumulation at the interface, and effectively suppresses the degradation of the device's on-resistance. Setting a second region at the bottom of the trench can reduce the on-resistance of the device, thereby improving the device's operating efficiency.

[0060] Based on the above embodiments, optionally, the present invention provides a specific method for fabricating a semiconductor device. Figures 8-19 This is a schematic diagram of an intermediate structure of a semiconductor device provided in an embodiment of this application, with reference to... Figures 8-19 Specifically, it includes: S110. An epitaxial layer is formed on one side of the substrate. The surface of the substrate away from the epitaxial layer is the second surface.

[0061] Among them, reference Figure 8 An epitaxial layer 20 can be grown on a substrate 10, which can be an N-type substrate and the epitaxial layer 20 can be an N-type epitaxial layer. The surface of the substrate 10 away from the epitaxial layer 20 is the second surface O2.

[0062] After the epitaxial layer is formed, a fifth region can be formed by low-energy ion implantation.

[0063] S120, A fourth region intermediate area is formed on the side of the epitaxial layer away from the substrate; the fourth region intermediate area is set to the second conductivity type.

[0064] Among them, reference Figure 9 The fourth region intermediate region 141 can be formed by epitaxial process, and the fourth region intermediate region 141 is P+ epitaxial.

[0065] S130, A well region intermediate region is formed on the side of the fourth region intermediate region away from the second surface; the well region intermediate region is set to the second conductivity type, and the ion concentration of the fourth region intermediate region is greater than the ion concentration of the well region intermediate region; the surface of the well region intermediate region away from the substrate is the first surface.

[0066] Among them, reference Figure 10 The intermediate region 31 of the well region can be formed by epitaxial process, and the intermediate region 31 of the well region is P-epitaxy.

[0067] S140. A first mask layer is formed on the side of the epitaxial layer away from the substrate, and the first mask layer is patterned. The patterned first mask layer includes a first opening; the first opening exposes a portion of the first surface.

[0068] Among them, reference Figure 11 A first mask layer 71 can be formed by deposition, and a first opening K1 can be etched into the first mask layer 71 in a patterned manner. The extension direction of the first opening K1 is the same as the extension direction of the subsequent trench. The first mask layer 71 can be a silicon oxide mask.

[0069] S150, Based on the first opening, a third region is formed in the first surface.

[0070] Among them, reference Figure 11 A third region 13 can be formed by low-energy ion implantation at the first opening K1. The third region 13 is the source P+ region, and the implanted ions can be P-type ions, which can make the third region 13 form a good ohmic contact.

[0071] S160, A first region is formed; along a first direction, at least two third regions are located on both sides of the trench respectively; each third region corresponds to at least one first region; adjacent first regions are spaced apart.

[0072] Specifically, S161-S162 below describes the preparation method of one first region corresponding to each third region, and S163-S166 below describes the preparation method of two first regions corresponding to each third region.

[0073] S170, Remove the first mask layer.

[0074] Among them, reference Figure 15 All mask layers are removed by wet etching.

[0075] S180, a source region is formed on the first surface.

[0076] Among them, reference Figure 15 A source region 40 is formed on the surface of the intermediate region 31 of the well region away from the substrate 10. The first conductive ion can be doped on the intermediate region 31 of the well region to form the source region, which is the source N+ region.

[0077] S190, forming a groove on the first surface.

[0078] Among them, reference Figure 16 A fifth mask layer 75 is formed through a deposition process. The fifth mask layer 75 is then dry-etched to form a trench pattern. Trench 50 is then etched out, and the fifth mask layer 75 is removed. The material of the fifth mask layer 75 includes silicon oxide.

[0079] S191, forming a second region, a trap region, and a fourth region; the second region extends from the bottom of the trench to the side of the fourth region away from the first surface; the minimum width of the second region in contact with the fourth region is less than the width of the second region in contact with the first surface of the fourth region and the width of the second region in contact with the second surface of the fourth region, respectively; wherein, the first surface is the surface of the fourth region adjacent to the first surface, and the second surface is the surface of the fourth region adjacent to the second surface.

[0080] Among them, reference Figure 17 A fourth mask layer 74 is formed on the sidewall of trench 50, forming a fourth opening K4. The width of the fourth opening K4 is smaller than the width of trench 50. Based on the fourth opening K4, a second region 12 is formed at the bottom of trench 50. The material of the fourth mask layer 74 includes silicon oxide. The fourth mask layer 74 covers the sidewalls of trench 50 and the sidewalls of the fifth mask layer 75. During ion implantation to form the second region 12, the sidewalls of trench 50 are prevented from being implanted. The fourth mask layer 74 can protect the trench sidewalls and improve the reliability of the device. The fourth mask layer 74 and the fifth mask layer 75 are then removed.

[0081] After the formation of the second region, the trap region, and the fourth region, refer to Figure 18 A gate insulating layer 51 is formed within the trench 50; the gate insulating layer 51 is located within the trench 50 and covers the bottom and sidewalls of the trench 50. A gate G is formed on the side of the gate insulating layer 51 away from the second surface 02; the gate G covers the gate insulating layer 51. (Reference) Figure 19 An interlayer dielectric layer 60 is formed on the side of the first surface 01 away from the second surface 02; formed by deposition and etching processes, the interlayer dielectric layer 60 is used to isolate the gate G and the source S. The source S is formed on the side of the interlayer dielectric layer 60 away from the second surface 02. The drain D is formed on the second surface 02.

[0082] The following is a first specific preparation method for forming the first region 11, namely, each third region corresponds to a first region.

[0083] The first region is formed, including: S161. A second mask layer is formed on the sidewall of the first opening to form a second opening; the width of the second opening is smaller than the width of the first opening.

[0084] Among them, reference Figure 12 The second mask layer 72 is made of silicon nitride. The second mask layer 72 covers the sidewall of the first opening K1 but does not completely fill it. The second mask layer 72 is formed through deposition and etching processes, thereby forming the second opening K2. The width of each mask layer is along the first direction X.

[0085] S162. Based on the second opening, a first region is formed in the middle region of the trap region, such that each first region corresponds to a first region.

[0086] Among them, reference Figure 12 Ions of the first conductivity type are vertically injected directly into the second opening to form the first region.

[0087] Removing the first mask layer includes: Remove the first mask layer and the second mask layer.

[0088] Wet etching can be used to remove the first and second mask layers.

[0089] The following is a second specific preparation method for forming the first region 11, namely, two first regions are set for each third region.

[0090] S163. A second mask layer is formed on the sidewall of the first opening to form a second opening; the width of the second opening is smaller than the width of the first opening.

[0091] Among them, reference Figure 13The second mask layer 72 is made of silicon nitride. The second mask layer 72 covers the sidewall of the first opening K1 but does not completely fill it. The second mask layer 72 is formed through deposition and etching processes, thereby forming the second opening K2. The width of each mask layer is along the first direction X.

[0092] S164. A third mask layer is formed inside the second opening; the third mask layer fills the second opening, the first mask layer and the third mask layer are made of the same material, and the first mask layer and the second mask layer are made of different materials.

[0093] Among them, reference Figure 13 The third mask layer 73 is formed by deposition and etching processes, and the material of the third mask layer 73 is silicon oxide.

[0094] S165. Remove the second mask layer to form a third opening; each third region corresponds to two third openings.

[0095] Among them, reference Figure 14 The second mask layer 72 is removed by wet etching, while the first mask layer 71 and the third mask layer 73 are retained, so that two third openings K3 are formed in each first opening K1.

[0096] S166. Based on the third opening, a first region is formed in the middle region of the trap region, such that each first region corresponds to two first regions.

[0097] Among them, reference Figure 14 At the third opening K3, ions of the first conductivity type are vertically injected to form the first region 11.

[0098] If each third region corresponds to multiple first regions, multiple third openings can be set in the first opening, and ions of the first conductivity type can be vertically injected into the third openings to form multiple first regions.

[0099] Removing the first mask layer includes removing both the first mask layer and the third mask layer.

[0100] The first and third mask layers are removed by wet etching.

[0101] By controlling the energy of ion implantation, the formed first region can be made to contact the intermediate region of the fourth region, or the formed first region can be made to not contact the intermediate region of the fourth region.

[0102] The semiconductor device fabrication method provided in this application embodiment belongs to the same inventive concept, has the same structure, and has the same beneficial effects as the semiconductor device in any embodiment of this application.

[0103] Based on the above embodiments, this application also provides a power module, including a substrate and the semiconductor device described in any embodiment of this application, wherein the substrate is used to support the semiconductor device.

[0104] The power module provided in the embodiments of this application and the semiconductor device described in any embodiment of this application belong to the same inventive concept and have the same beneficial effects.

[0105] Based on the above embodiments, this application also provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction. The power conversion circuit includes a circuit board and the semiconductor device described in any embodiment of this application, and the semiconductor device is electrically connected to the circuit board.

[0106] The power conversion circuit provided in the embodiments of this application and the semiconductor device described in any embodiment of this application belong to the same inventive concept and have the same beneficial effects.

[0107] Based on the above embodiments, this application also provides a vehicle, including a load and the power conversion circuit described in any embodiment of this application. The power conversion circuit is used to convert AC power to DC power, convert AC power to AC power, convert DC power to DC power, or convert DC power to AC power and then input it to the load.

[0108] The vehicles provided in the embodiments of this application and the semiconductor devices described in any embodiment of this application belong to the same inventive concept and have the same beneficial effects.

[0109] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0110] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A semiconductor device, characterized in that, include: A semiconductor body includes a first surface and a second surface disposed opposite to each other; the semiconductor body also includes a well region and a source region, the source region being configured with a first conductivity type and located on the first surface, and the well region being configured with a second conductivity type and located on the side of the source region away from the first surface; the first conductivity type and the second conductivity type are different; a trench is provided on the first surface, the trench extending from the first surface into the well region; the semiconductor body also includes a first region, a second region, and a third region, the third region being configured with a second conductivity type and located on the first surface; both the first region and the second region are configured with a first conductivity type; the first region is located on the side of the third region adjacent to the second surface, and the first region is in contact with at least the third region and the well region; the second region is located on the side of the trench adjacent to the second surface, and the second region extends from the bottom of the trench to the side of the well region away from the first surface; The gate is located within the trench; The drain electrode is located on the second surface; The source electrode is located on the first surface.

2. The semiconductor device according to claim 1, characterized in that, Along the first direction, at least two of the third regions are located on both sides of the trench; each of the third regions corresponds to at least one of the first regions; and adjacent first regions are spaced apart.

3. The semiconductor device according to claim 1, characterized in that, Also includes: A fourth region, configured as a second conductivity type and located on the side of the well region away from the first surface; the second region extends from the bottom of the trench to the side of the fourth region away from the first surface.

4. The semiconductor device according to claim 3, characterized in that, The first region is in contact with the fourth region.

5. The semiconductor device according to claim 3, characterized in that, The ion concentration in the fourth region is greater than the ion concentration in the well region; The minimum width of the second region in contact with the fourth region is less than the width of the second region in contact with the first surface of the fourth region and the width of the second region in contact with the second surface of the fourth region, respectively; wherein, the first surface is the surface of the fourth region adjacent to the first surface, and the second surface is the surface of the fourth region adjacent to the second surface.

6. The semiconductor device according to claim 3, characterized in that, The semiconductor body includes a substrate and an epitaxial layer, wherein the surface of the substrate away from the epitaxial layer is a second surface; The semiconductor body further includes a fifth region configured with a second conductivity type; the fifth region is located on the side of the fourth region adjacent to the second surface; the vertical projection of the fifth region on the second surface at least partially overlaps with the vertical projection of the third region on the second surface; The fifth region is used to form a semi-superjunction structure or a superjunction structure.

7. The semiconductor device according to claim 1, characterized in that, Also includes: A gate insulating layer is located within the trench and covers the bottom and sidewalls of the trench. An interlayer dielectric layer is located on the side of the first surface away from the second surface; The interlayer dielectric layer is used to isolate the gate and the source. The source electrode is located on the side of the interlayer dielectric layer away from the second surface.

8. A method for fabricating a semiconductor device, characterized in that, include: A semiconductor body is provided; the semiconductor body includes a first surface and a second surface disposed opposite to each other; the semiconductor body further includes a well region and a source region, the source region being configured with a first conductivity type and located on the first surface, and the well region being configured with a second conductivity type and located on the side of the source region away from the first surface; the first conductivity type and the second conductivity type are different; a trench is provided on the first surface, the trench extending from the first surface into the well region; the semiconductor body further includes a first region, a second region, and a third region, the third region being configured with a second conductivity type and located on the first surface; both the first region and the second region are configured with a first conductivity type; the first region is located on the side of the third region adjacent to the second surface, and the first region is in contact with at least the third region and the well region; the second region is located on the side of the trench adjacent to the second surface, and the second region extends from the bottom of the trench to the side of the well region away from the first surface; A gate is formed within the trench; A source electrode is formed on the first surface; A drain electrode is formed on the second surface.

9. The preparation method according to claim 8, characterized in that, Provide semiconductor bodies, including: An epitaxial layer is formed on one side of the substrate; the surface of the substrate away from the epitaxial layer is the second surface; A fourth intermediate region is formed on the side of the epitaxial layer away from the substrate; the fourth intermediate region is configured with a second conductivity type. A well region intermediate region is formed on the side of the fourth region intermediate region away from the second surface; the well region intermediate region is configured with a second conductivity type, and the ion concentration in the fourth region intermediate region is greater than the ion concentration in the well region intermediate region; the surface of the well region intermediate region away from the substrate is the first surface. A first mask layer is formed on the side of the epitaxial layer away from the substrate, and the first mask layer is patterned, wherein the patterned first mask layer includes a first opening; the first opening exposes a portion of the first surface; A third region is formed in the first surface based on the first opening; A first region is formed; along a first direction, at least two third regions are respectively located on both sides of the trench; each third region corresponds to at least one first region; adjacent first regions are spaced apart; Remove the first mask layer; A source region is formed on the first surface; A groove is formed on the first surface; A second region, a trap region, and a fourth region are formed; the second region extends from the bottom of the trench to the side of the fourth region away from the first surface; the minimum width of the second region in contact with the fourth region is less than the width of the second region in contact with the first surface of the fourth region and the width of the second region in contact with the second surface of the fourth region, respectively; wherein, the first surface is the surface of the fourth region adjacent to the first surface, and the second surface is the surface of the fourth region adjacent to the second surface.

10. The preparation method according to claim 9, characterized in that, The first region is formed, including: A second mask layer is formed on the sidewall of the first opening to form a second opening; the width of the second opening is smaller than the width of the first opening; Based on the second opening, the first region is formed in the middle region of the trap region, such that each first region corresponds to a first region. Removing the first mask layer includes: Remove the first mask layer and the second mask layer.

11. The preparation method according to claim 9, characterized in that, The first region is formed, including: A second mask layer is formed on the sidewall of the first opening to form a second opening; the width of the second opening is smaller than the width of the first opening; A third mask layer is formed within the second opening; the third mask layer fills the second opening, the first mask layer and the third mask layer are made of the same material, and the first mask layer and the second mask layer are made of different materials; Remove the second mask layer to form a third opening; each of the third regions corresponds to two third openings; Based on the third opening, the first region is formed in the middle region of the trap region, such that each first region corresponds to two first regions. Removing the first mask layer includes: Remove the first mask layer and the third mask layer.

12. The preparation method according to claim 9, characterized in that, The second region is formed, including: A fourth mask layer is formed on the sidewall of the trench, forming a fourth opening; the width of the fourth opening is smaller than the width of the trench. Based on the fourth opening, a second region is formed at the bottom of the trench; Remove the fourth mask layer.

13. A power module, characterized in that, It includes a substrate and at least one semiconductor device as described in any one of claims 1-7, wherein the substrate is used to support the semiconductor device.

14. A power conversion circuit, characterized in that, The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device as described in any one of claims 1-7, wherein the semiconductor device is electrically connected to the circuit board.

15. A vehicle, characterized in that, The device includes a load and a power conversion circuit as described in claim 14, the power conversion circuit being used to convert AC power to DC power, convert AC power to AC power, convert DC power to DC power, or convert DC power to AC power and then input it to the load.

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