A trench type semiconductor device and a method of fabricating the same
Patent Information
- Application Number
- CN202510489357.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-16
- Publication Date
- 2026-10-23
AI Technical Summary
[0003]对于线宽(Pitch)小的器件或者台面区(Mesa)小的器件，为了维持正常的工艺窗口，需要将沟槽的特征尺寸缩小0.1～0.25μm左右，以平衡修复损伤层吃掉的工艺窗口，例如，对于特征尺寸为0.5μm、深度为3μm的沟槽，在光刻站点需要将尺寸做小到0.25～0.4μm，对光刻工艺能力需求提高，并且也挑战深沟槽刻蚀机台能力，特征尺寸减小，刻蚀的深宽比能力由6:1需提升到7:1～12:1，可能会出现刻蚀停止(Etch Stop)现象，同时由于特征尺寸缩小，对沟槽内缺陷的清洗能力也有影响，挑战成熟Fab的机台能力
[0026]如上所述，本发明的沟槽型半导体器件及其制作方法中，先逐步调低NF3的流量，增加O2的流量，形成开口大底部小的沟槽形貌，最后一步降低刻蚀功率，以及降低NF3的流量，增加O2的流量进行沟槽形貌修正，让整体形貌更圆滑，且吃掉一部分刻蚀损伤，一方面利于后续栅氧层和多晶硅层的填充，另一方面能够降低IDSS漏电，提高产品良率；另外，无需为了维持沟槽CD而减小光刻站点CD，降低光刻工艺难度，降低器件Ron敏感性，适用于低电压小线宽的功率器件。
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Figure CN122970967A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor technology and relates to a trench semiconductor device and its fabrication method. Background Technology
[0002] With continuous technological innovation, semiconductor devices are evolving towards higher performance, lower power consumption, and smaller size. In the production of trench semiconductor devices, the silicon surface damaged after trench etching needs to be addressed. Whether using furnace oxidation to repair etching damage or soft etching to remove it, both methods increase the trench size and reduce the process window. For example, for SGT (Shielded Gate Trench) devices, the trench depth typically exceeds 2.5 μm, reaching up to 7 μm. The etching time is long, and the etching process causes relatively severe damage to the silicon substrate. Therefore, furnace oxidation is required to oxidize the damaged layer into a sacrificial oxide layer before removal. The sacrificial oxide layer typically... The trench size will increase by about 0.1-0.25μm. Similarly, using a Soft Etch machine for isotropic dry etching to remove the damage layer will also increase the trench size.
[0003] For devices with small linewidths (Pitch) or small mesa areas, in order to maintain a normal process window, the feature size of the trench needs to be reduced by about 0.1 to 0.25 μm to balance the process window consumed by the repair damage layer. For example, for a trench with a feature size of 0.5 μm and a depth of 3 μm, the size needs to be reduced to 0.25 to 0.4 μm at the lithography station, which increases the requirements for lithography process capabilities and also challenges the capabilities of deep trench etching equipment. With the feature size reduced, the etching aspect ratio capability needs to be increased from 6:1 to 7:1 to 12:1, which may lead to etching stop phenomenon. At the same time, due to the reduction in feature size, the ability to clean defects in the trench is also affected, which challenges the equipment capabilities of mature fabs.
[0004] If the sacrificial oxide layer is removed directly, the etching damage will cause excessive leakage current in the IDSS or even lead to breakdown, resulting in a loss of yield. Summary of the Invention
[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a trench semiconductor device and its fabrication method, which solves the problem of the contradiction between reducing trench size and reducing IDSS leakage current in the prior art.
[0006] To achieve the above and other related objectives, the present invention provides a method for fabricating a trench semiconductor device, comprising the following steps:
[0007] S1: Provide a substrate on which a hard mask layer with an etching window is formed;
[0008] S2: Using the hard mask layer as a mask, the substrate is etched in stages to form the target trench. The etching conditions include etching power and etching gas. The etching gas includes HBr, NF3, and O2. The staged etching includes:
[0009] S20: Perform a first etching step on the substrate to form a trench of the first depth;
[0010] S21: Perform a second etching step on the substrate to form a trench of a second depth, wherein the etching power of the second etching step is the same as that of the first etching step, the NF3 flow rate of the second etching step is less than that of the first etching step, the O2 flow rate of the second etching step is greater than that of the first etching step, and the inclination of the trench sidewall of the second etching step is greater than that of the trench sidewall of the first etching step.
[0011] S22: Perform a third etching step on the substrate to form the target trench, wherein the etching power of the third etching step is less than that of the second etching step, the NF3 flow rate of the third etching step is less than that of the second etching step, the O2 flow rate of the third etching step is greater than that of the second etching step, and the third etching step corrects the trench morphology and reduces etching damage.
[0012] S3: A gate oxide layer is formed on the sidewalls and bottom of the target trench.
[0013] Optionally, in the first etching step, the etching power ranges from 600 to 900 W, the HBr flow rate ranges from 120 to 160 sccm, the NF3 flow rate ranges from 100 to 150 sccm, and the O2 flow rate ranges from 5 to 8 sccm.
[0014] In the second etching step, the etching power range is 600-900W, the HBr flow rate range is 120-160sccm, the NF3 flow rate range is 90-130sccm, and the O2 flow rate range is 6-9sccm.
[0015] In the third etching step, the etching power ranges from 300 to 700 W, the HBr flow rate ranges from 120 to 160 sccm, the NF3 flow rate ranges from 80 to 110 sccm, and the O2 flow rate ranges from 8 to 11 sccm.
[0016] Optionally, the depth of the target trench is not less than 3 μm.
[0017] Optionally, the ratio between the depth of the first depth trench and the depth of the second depth trench is in the range of 1 / 4 to 1 / 3.
[0018] Optionally, the hard mask layer includes a silicon oxide layer, a silicon nitride layer, or a stacked silicon oxide / silicon nitride / silicon oxide layer.
[0019] Optionally, the step of forming the etched window in the hard mask layer includes:
[0020] S10: A photoresist layer is formed and patterned on the hard mask layer, and the patterned photoresist layer defines the position of the etching window;
[0021] S11: Using the patterned photoresist layer as a mask, etch the hard mask layer to form the etching window.
[0022] Optionally, the substrate includes a silicon substrate.
[0023] Optionally, the gate oxide layer may be made of silicon oxide.
[0024] Optionally, before forming the gate oxide layer, the step of removing the hard mask layer is further included.
[0025] The present invention also provides a trench semiconductor device, which is fabricated by the trench semiconductor device fabrication method described in any one of the above claims.
[0026] As described above, in the trench semiconductor device and its fabrication method of the present invention, the flow rate of NF3 is gradually reduced and the flow rate of O2 is increased to form a trench morphology with a large opening and a small bottom. In the final step, the etching power is reduced and the flow rate of NF3 is reduced while the flow rate of O2 is increased to correct the trench morphology, making the overall morphology smoother and absorbing some of the etching damage. This is beneficial for the subsequent filling of the gate oxide layer and polysilicon layer, and can reduce IDSS leakage current and improve product yield. In addition, there is no need to reduce the CD of the photolithography station in order to maintain the trench CD, which reduces the difficulty of the photolithography process and reduces the device Ron sensitivity, making it suitable for low-voltage and small-linewidth power devices. Attached Figure Description
[0027] Figure 1 The diagram shown is a flowchart of the fabrication method of a trench semiconductor device in an embodiment of the present invention.
[0028] Figure 2 The diagram shown is a schematic diagram of a substrate provided in an embodiment of the present invention, on which a hard mask layer is formed.
[0029] Figure 3 The diagram shown is a schematic representation of a photoresist layer formed on a hard mask layer in an embodiment of the present invention.
[0030] Figure 4 The diagram shown is a schematic diagram of forming an etching window in an embodiment of the present invention.
[0031] Figure 5 The image shown is a schematic diagram after the first etching step in an embodiment of the present invention.
[0032] Figure 6 The image shown is a schematic diagram after the second etching step in an embodiment of the present invention.
[0033] Figure 7 The image shown is a schematic diagram after the third step of etching in an embodiment of the present invention.
[0034] Figure 8 The diagram shown is a schematic diagram of the formation of the gate oxide layer in an embodiment of the present invention.
[0035] Figure 9 The image shown is an electron microscope image of the trench in an embodiment of the present invention.
[0036] Figure 10 The image shown is an electron microscope image of the groove in the comparative example.
[0037] Figure 11 The diagram shows a comparison of IDSS leakage current between embodiments and comparative examples of the present invention.
[0038] Component designation explanation
[0039] 1 Substrate
[0040] 2 Hard mask layer
[0041] 20 Etched Window
[0042] 3 Photoresist layer
[0043] 30 Photoresist opening
[0044] 4 First Depth Trench
[0045] 5 Second Depth Trench
[0046] 6. Target trench
[0047] 7. Gate oxide layer Detailed Implementation
[0048] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0049] Please see Figures 1 to 11It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0050] This embodiment provides a method for fabricating a trench semiconductor device. Please refer to [link to relevant documentation]. Figure 1 This includes the following steps:
[0051] S1: Provide a substrate on which a hard mask layer with an etching window is formed;
[0052] S2: Using the hard mask layer as a mask, the substrate is etched in stages to form the target trench. The etching conditions include etching power and etching gas. The etching gas includes HBr, NF3, and O2. The staged etching includes:
[0053] S20: Perform a first etching step on the substrate to form a trench of the first depth;
[0054] S21: Perform a second etching step on the substrate to form a trench of a second depth, wherein the etching power of the second etching step is the same as that of the first etching step, the NF3 flow rate of the second etching step is less than that of the first etching step, the O2 flow rate of the second etching step is greater than that of the first etching step, and the inclination of the trench sidewall of the second etching step is greater than that of the trench sidewall of the first etching step.
[0055] S22: Perform a third etching step on the substrate to form the target trench, wherein the etching power of the third etching step is less than that of the second etching step, the NF3 flow rate of the third etching step is less than that of the second etching step, the O2 flow rate of the third etching step is greater than that of the second etching step, and the third etching step corrects the trench morphology and reduces etching damage.
[0056] S3: A gate oxide layer is formed on the sidewalls and bottom of the target trench.
[0057] The fabrication method of the trench semiconductor device in this embodiment will be described in detail below with reference to the specific accompanying drawings.
[0058] First, please refer to Figures 2 to 4 Step S1: Provide a substrate 1, on which a hard mask layer 2 with an etching window 20 is formed.
[0059] As an example, the substrate 1 can be any suitable semiconductor substrate, such as a silicon substrate, a gallium arsenide substrate, a gallium nitride substrate, a silicon carbide substrate, etc.; specifically, in this embodiment, the substrate 1 is a silicon substrate.
[0060] As an example, the hard mask layer 2 includes a silicon oxide layer, a silicon nitride layer, or a stacked silicon oxide / silicon nitride / silicon oxide (ONO) layer; preferably, in this embodiment, the hard mask layer 2 adopts an ONO structure. The silicon nitride in the ONO structure has high etching selectivity and can effectively protect the underlying silicon substrate during the etching process. The silicon oxide can serve as a stress buffer layer to reduce the impact of stress generated during the etching process on the silicon substrate.
[0061] As an example, the step of forming the etched window 20 in the hard mask layer 2 includes:
[0062] S10: As Figure 3 As shown, a photoresist layer 3 is formed and patterned on the hard mask layer 2, and the patterned photoresist layer 3 defines the position of the etching window 20;
[0063] S11: As Figure 4 As shown, the patterned photoresist layer 3 is used as a mask to etch the hard mask layer 2, forming the etching window 20.
[0064] As an example, when the photoresist layer 3 is patterned, the feature size of the photoresist opening 30 is the feature size of the device trench. For example, for a trench with a feature size of 0.5 μm, the feature size of the photoresist opening 30 can also be made 0.5 μm at the lithography station. There is no need to reduce the feature size of the lithography, and there is no need to increase the requirements for feature size and alignment accuracy at the lithography station. There is no need to invest in lithography equipment with higher process capabilities.
[0065] Next, please refer to Figures 5 to 7 Step S2: Using the hard mask layer 2 as a mask, the substrate 1 is etched in stages to form the target trench 6. The etching conditions include etching power and etching gas, and the etching gas includes HBr, NF3 and O2.
[0066] As an example, in this embodiment, the target trench 6 is a deep trench, and the trench depth of the target trench 6 is not less than 3μm. For example, it can be 3μm, 4μm, 5μm, 6μm, 7μm, etc. In this embodiment, the trench depth of the target trench 6 is 3μm.
[0067] As an example, the step-by-step etching includes:
[0068] S20: As Figure 5As shown, the substrate 1 is etched in the first step to form a trench 4 of the first depth. In the first step of etching, the etching power ranges from 600 to 900 W, the flow rate of HBr ranges from 120 to 160 sccm, the flow rate of NF3 ranges from 100 to 150 sccm, and the flow rate of O2 ranges from 5 to 8 sccm.
[0069] S21: As Figure 6 As shown, a second etching step is performed on the substrate 1 to form a second depth trench 5. The etching power of the second etching step is the same as that of the first etching step. The NF3 flow rate of the second etching step is less than that of the first etching step. The O2 flow rate of the second etching step is greater than that of the first etching step. The sidewall inclination of the trench in the second etching step is greater than that of the trench in the first etching step. In the second etching step, the etching power ranges from 600 to 900 W, the HBr flow rate ranges from 120 to 160 sccm, the NF3 flow rate ranges from 90 to 130 sccm, and the O2 flow rate ranges from 6 to 9 sccm.
[0070] S22: As Figure 7 As shown, a third etching step is performed on the substrate 1 to form the target trench 6. The etching power of the third etching step is lower than that of the second etching step, the NF3 flow rate of the third etching step is lower than that of the second etching step, and the O2 flow rate of the third etching step is higher than that of the second etching step. The third etching step corrects the trench morphology and reduces etching damage. In the third etching step, the etching power ranges from 300 to 700 W, the HBr flow rate ranges from 120 to 160 sccm, the NF3 flow rate ranges from 80 to 110 sccm, and the O2 flow rate ranges from 8 to 11 sccm.
[0071] As an example, during the etching process, the etching power controls the plasma density. The plasma density determines the number of ions and active groups, as well as the reaction rate on the material surface and the bombardment energy of ions on the material surface. The Br radicals in HBr can react chemically with silicon to generate volatile SiBr4. At the same time, HBr also has the effect of sidewall protection, forming straighter sidewalls, which is beneficial for deep trench etching and can also improve the etching selectivity. The fluorine-containing active groups in NF3 can break the chemical bonds in silicon to generate volatile SiF4. O2 can synergistically react with NF3 to generate more free radicals with strong oxidizing and reactive properties, thereby accelerating the etching rate. However, excessive O2 flow rate will cause oxidation of the silicon material surface, which will reduce the etching rate. That is, O2 can adjust the selectivity and affect the morphology of the trench sidewalls.
[0072] In this embodiment, the target trench 6 is formed by step etching. First, a first etching step with relatively high etching power is used to form the trench opening (the first depth trench 4). Then, without changing the etching power, the NF3 flow rate is reduced and the O2 flow rate is increased to perform the second etching step to reach the required trench depth (3 μm in this embodiment). The flow rate ratio of NF3 to O2 is adjusted so that the inclination of the trench sidewall produced by the second etching step is greater than that produced by the first etching step. Then, the etching power is reduced, the NF3 flow rate is further reduced, and the O2 flow rate is increased to perform the third etching step. The third etching step corrects the morphology, making the overall morphology smoother. Due to the reduced etching power and the further adjustment of the NF3 to O2 flow rate ratio, the third etching step will not cause more etching damage and can absorb some of the damage layer produced by the first two etching steps.
[0073] As an example, the ratio between the depth of the first depth trench 4 and the depth of the second depth trench 5 is in the range of 1 / 4 to 1 / 3. The depth of the first depth trench 4 is the height difference between the bottom of the trench and the upper surface of the substrate after the first etching step, and the depth of the second depth trench 5 is the height difference between the bottom of the trench and the upper surface of the substrate after the second etching step.
[0074] Next, please refer to Figure 8 Step S3: Form a gate oxide layer 7 on the sidewall and bottom of the target trench 6.
[0075] As an example, after the target trench 6 is formed by step etching, it is not necessary to form a sacrificial oxide layer and then remove it, or to use a Soft Etch machine to remove the etched damage layer, thus reducing equipment investment costs.
[0076] As an example, in this embodiment, the trench gate semiconductor device is a shielded gate trench (SGT) device, and the gate oxide layer 7 serves as the gate dielectric layer of the shielded gate.
[0077] As an example, after forming the gate oxide layer 7, the process further includes forming a shielding gate polysilicon layer, an isolation oxide layer, a control gate gate oxide layer, and a control gate polysilicon layer. The processes for forming the shielding gate polysilicon layer, the isolation oxide layer, the control gate gate oxide layer, and the control gate polysilicon layer are well known in the art and will not be described in detail here.
[0078] As an example, taking the one-step etching process to form deep trenches in the existing process as a comparative example, the etching process is as follows: the etching power ranges from 600 to 900 W, the gas flow rate of HBr ranges from 120 to 160 sccm, the gas flow rate of NF3 ranges from 100 to 150 sccm, and the flow rate of O2 ranges from 5 to 8 sccm. Specifically, in the comparative example, samples were prepared with an etching power of 750 W, an HBr flow rate of 140 sccm, an NF3 flow rate of 125 sccm, and an O2 flow rate of 7 sccm. In this embodiment, samples were prepared with the following etching parameters: first step etching power of 750 W, HBr flow rate of 140 sccm, NF3 flow rate of 125 sccm, and O2 flow rate of 7 sccm; second step etching power of 750 W, HBr flow rate of 140 sccm, NF3 flow rate of 110 sccm, and O2 flow rate of 8 sccm; and third step etching power of 500 W, HBr flow rate of 140 sccm, NF3 flow rate of 95 sccm, and O2 flow rate of 9 sccm. Please refer to [link to relevant documentation]. Figure 9 and Figure 10 The images shown are electron microscope (EM) images of the trenches in the embodiments and comparative examples of the present invention. In the embodiments of the present invention, the trench angle is 88°–89°, and in the comparative examples, the trench angle is 89°–90°. In the embodiments of the present invention, the trench opening size L1 is equal to the trench opening size L4 in the comparative examples. In the embodiments of the present invention, the trench middle size L2 is 87% of the opening size L1. In the embodiments of the present invention, the trench bottom size L3 is 75% of the opening size L1. In the comparative examples, the trench middle size L5 is 90% of the opening size L4, and the trench bottom size L6 is 80% of the opening size L4. That is, the bottom size of the trench in the present invention is reduced by about 30–40 nm, which increases the tilt angle of the trench, which is beneficial for the subsequent filling of the gate oxide layer and polysilicon layer and avoids the formation of filling gaps (seam).
[0079] For example, please refer to Figure 11 The figure shows a comparison of IDSS leakage current between the embodiments and the comparative examples of the present invention. In the comparative example, the IDSS leakage current is about 0.03 μA, while in the present invention, the IDSS leakage current is about 0.02 μA, which reduces the IDSS leakage current by 10 to 20 nA.
[0080] As an example, this application eliminates the need to reduce the CD of the lithography site in order to maintain the CD of the trench, which can significantly reduce the difficulty of the lithography process. In addition, the on-resistance Ron of the device is directly related to the CD of the lithography, the alignment accuracy, and the CD of the trench. This application can reduce the Ron sensitivity of the device. At the same time, this application improves etching damage, reduces and stabilizes the leakage current IDSS of the product, improves the product yield, and reduces the bottom size of the trench in this application, which is beneficial to the subsequent filling of the gate oxide layer and polysilicon layer and avoids the appearance of filling gaps.
[0081] As an example, conventional processes are suitable for SGT devices with voltages greater than 60V and linewidths greater than 2μm. This application is suitable for SGT devices with low voltage and small linewidths, voltages less than 60V, linewidths less than 2μm, and photolithographic alignment accuracy requirements less than 60nm.
[0082] As an example, this embodiment only lists the trench semiconductor device as an SGT device, but it is also applicable to other trench power devices without sacrificial oxide layer processes, and is not limited to this embodiment.
[0083] This embodiment also provides a trench semiconductor device, which is fabricated by the above-described method for fabricating trench semiconductor devices.
[0084] In summary, the trench semiconductor device and its fabrication method of the present invention first gradually reduce the flow rate of NF3 and increase the flow rate of O2 to form a trench morphology with a large opening and a small bottom. The final step involves reducing the etching power and the flow rate of NF3 while increasing the flow rate of O2 to correct the trench morphology, resulting in a smoother overall morphology and absorbing some etching damage. This facilitates subsequent filling of the gate oxide layer and polysilicon layer, reduces IDSS leakage current, and improves product yield. Furthermore, it eliminates the need to reduce the lithography station CD to maintain the trench CD, reducing the difficulty of the lithography process and the device's Ron sensitivity, making it suitable for low-voltage, small-linewidth power devices. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.
[0085] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A method for fabricating a trench-type semiconductor device, characterized in that, Includes the following steps: S1: Provide a substrate on which a hard mask layer with an etching window is formed; S2: Using the hard mask layer as a mask, the substrate is etched in stages to form the target trench. The etching conditions include etching power and etching gas. The etching gas includes HBr, NF3, and O2. The staged etching includes: S20: Perform a first etching step on the substrate to form a trench of the first depth; S21: Perform a second etching step on the substrate to form a trench of a second depth, wherein the etching power of the second etching step is the same as that of the first etching step, the NF3 flow rate of the second etching step is less than that of the first etching step, the O2 flow rate of the second etching step is greater than that of the first etching step, and the inclination of the trench sidewall of the second etching step is greater than that of the trench sidewall of the first etching step. S22: Perform a third etching step on the substrate to form the target trench, wherein the etching power of the third etching step is less than that of the second etching step, the NF3 flow rate of the third etching step is less than that of the second etching step, the O2 flow rate of the third etching step is greater than that of the second etching step, and the third etching step corrects the trench morphology and reduces etching damage. S3: A gate oxide layer is formed on the sidewalls and bottom of the target trench.
2. The method for fabricating a trench-type semiconductor device according to claim 1, characterized in that: In the first etching step, the etching power ranges from 600 to 900 W, and the HBr flow rate ranges from 120 to 160 sccm. The flow rate range for NF3 is 100–150 sccm, and the flow rate range for O2 is 5–8 sccm. In the second etching step, the etching power ranges from 600 to 900 W, and the HBr flow rate ranges from 120 to 160 sccm. The flow rate range for NF3 is 90–130 sccm, and the flow rate range for O2 is 6–9 sccm. In the third etching step, the etching power ranges from 300 to 700 W, and the HBr flow rate ranges from 120 to 160 sccm. The flow rate range for NF3 is 80–110 sccm, and the flow rate range for O2 is 8–11 sccm.
3. The method for fabricating a trench-type semiconductor device according to claim 1, characterized in that: The depth of the target trench is not less than 3μm.
4. The method for fabricating a trench-type semiconductor device according to claim 1, characterized in that: The ratio between the depth of the first depth trench and the depth of the second depth trench is in the range of 1 / 4 to 1 / 3.
5. The method for fabricating a trench-type semiconductor device according to claim 1, characterized in that: The hard mask layer includes a silicon oxide layer, a silicon nitride layer, or a stack of silicon oxide / silicon nitride / silicon oxide layers.
6. The method for fabricating a trench-type semiconductor device according to claim 1, characterized in that, The step of forming the etched window in the hard mask layer includes: S10: A photoresist layer is formed and patterned on the hard mask layer, and the patterned photoresist layer defines the position of the etching window; S11: Using the patterned photoresist layer as a mask, etch the hard mask layer to form the etching window.
7. The method for fabricating a trench-type semiconductor device according to claim 1, characterized in that: The substrate includes a silicon substrate.
8. The method for fabricating a trench-type semiconductor device according to claim 1, characterized in that: The gate oxide layer is made of silicon oxide.
9. The method for fabricating a trench-type semiconductor device according to claim 1, characterized in that: Before forming the gate oxide layer, the process also includes a step of removing the hard mask layer.
10. A trench-type semiconductor device, characterized in that: The trench semiconductor device is manufactured by the method for manufacturing a trench semiconductor device according to any one of claims 1-9.