Semiconductor device and method of manufacturing the same

Abstract

The application relates to the technical field of semiconductors, in particular to a semiconductor device and a preparation method thereof. The method comprises the following steps: providing a substrate; forming an interface layer on the substrate, the interface layer comprising at least one of silicon oxide, silicon oxynitride; forming a dielectric layer on the interface layer, the dielectric layer comprising at least one of HfO a , ZrO b , HfZrO c , HfAlO, HfSiO, HfLaO; performing element doping treatment and annealing treatment on the dielectric layer to obtain a high dielectric medium layer, a stress gradient varying along the thickness direction of the high dielectric medium layer is formed in the high dielectric medium layer, the stress gradient is used for improving the dielectric constant of the high dielectric medium layer, and the dielectric constant of the high dielectric medium layer is at least 60. The method of the embodiment of the application improves the dielectric constant by inducing the crystallization of the high dielectric medium layer, and further improves the defects of the semiconductor device and suppresses the leakage current.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for fabricating the same. Background Technology

[0002] Complementary field-effect transistors (CFETs), with their vertically stacked structure of n-type and p-type field-effect transistors, represent a significant direction for improving integration density. Continuous reduction in equivalent oxide thickness (EOT) is crucial for enhancing CMOS device performance. However, when the EOT falls below 1 nm, traditional high-dielectric-layer-based EOT miniaturization techniques have stalled due to the exponential increase in gate leakage current and a sharp degradation in reliability.

[0003] EOT miniaturization techniques mainly include SiO2 interface layer elimination (IL scavenging) and gate dielectric material κ value enhancement. Interface layer elimination can be achieved by directly depositing high-κ materials or inserting oxygen-removing metal layers. However, SiO2 interface layer elimination leads to a significant increase in interface defects, resulting in severe carrier mobility degradation. Enhancing the κ value of the gate dielectric material is the most direct and efficient method to reduce EOT, avoiding mobility and leakage current degradation. Next-generation high-κ gate dielectric materials need to possess suitable band gaps, good interface characteristics, and device compatibility. Composite materials formed by doping HfO2 gate dielectrics with elements such as Ti, Ta, and Bi have higher κ values, but these higher-κ materials often have lower band gaps (Eg ~κ-0.65), leading to increased tunneling current and making it difficult to meet the leakage current requirements of small-size semiconductor devices.

[0004] It should be noted that the above content is not necessarily prior art, nor is it intended to limit the scope of protection of this application. Summary of the Invention

[0005] This application provides a semiconductor device and a method for fabricating the same, in order to solve or alleviate one or more of the technical problems mentioned above.

[0006] A first aspect of this application provides a method for fabricating a semiconductor device. The method includes the following steps: Provide substrate; An interface layer is formed on the substrate, the interface layer comprising at least one of silicon oxide and silicon oxynitride; A dielectric layer is formed on the interface layer, the dielectric layer comprising HfO. a ZrO b HfZrOc At least one of HfAlO, HfSiO, and HfLaO; The dielectric layer is subjected to elemental doping and annealing to obtain a high-dielectric dielectric layer. A stress gradient varying along the thickness direction is formed within the high-dielectric dielectric layer. The stress gradient is used to increase the dielectric constant of the high-dielectric dielectric layer, and the dielectric constant of the high-dielectric dielectric layer is at least 60.

[0007] The method in this application induces the crystallization of a high-dielectric layer, increases the dielectric constant, and thereby improves the defects of semiconductor devices and suppresses leakage current. Specifically, the interface layer can ensure the thermal stability between the channel and the high-dielectric layer and reduce interface states. A stress gradient varying along its thickness direction is formed in the high-dielectric layer, maintaining high crystal quality in the region near the channel and further inducing high-quality crystallization of the entire film. The dielectric constant of the high-dielectric layer is at least 60, which can significantly reduce the equivalent oxide layer thickness and further promote gate stacking miniaturization. The replacement of defects such as oxygen vacancies by doping elements reduces the low oxygen vacancy defect concentration in the dielectric film and suppresses leakage current.

[0008] According to an embodiment of this application, in the direction from the substrate to the high dielectric layer, the slope Δ1 of the stress gradient varies from 0.01 to 0.1, so that the stress of the high dielectric layer gradually decreases.

[0009] According to embodiments of this application, the doping element includes at least one selected from nitrogen, hydrogen, oxygen, argon, rare earth elements, and halogen elements; the element doping treatment method includes one of plasma treatment and free radical treatment. This further improves the defect reduction and suppresses leakage current in semiconductor devices.

[0010] According to an embodiment of this application, the thickness of the high dielectric layer is less than 2.5 nm.

[0011] According to an embodiment of this application, the conditions for plasma treatment include: a power of 600W-1000W and a time of 10s-300s.

[0012] According to an embodiment of this application, the annealing temperature is 700℃-1000℃, and the time is 3s-80s. This further increases the grain size.

[0013] According to an embodiment of this application, in the direction from the substrate to the high-dielectric layer, the concentration of doped elements in the high-dielectric layer varies in a gradient. The slope of the concentration gradient change is Δ2, and Δ2 is greater than 0.5.

[0014] According to an embodiment of this application, the size of the grains in the high-dielectric layer is not less than 20 nm.

[0015] According to an embodiment of this application, the equivalent oxide layer thickness in the high dielectric layer is no greater than 0.5 nm.

[0016] A second aspect of this application provides a semiconductor device fabricated using the fabrication method described in the first aspect. The semiconductor device includes a channel layer, a gate electrode, and a high-dielectric layer and an interface layer stacked between the channel layer and the gate electrode, wherein the interface layer is close to the channel, and the high-dielectric layer has a stress gradient that varies along its thickness direction. Attached Figure Description

[0017] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments disclosed in this application and should not be construed as limiting the scope of this application.

[0018] Figure 1 These are process flow diagrams of semiconductor devices according to some embodiments; Figure 2 These are process flow diagrams of semiconductor devices according to other embodiments; Figure 3 These are process flow diagrams of semiconductor devices according to some embodiments; Figure 4 These are scanning electron microscope images of the semiconductor devices in Examples 1-3.

[0019] Explanation of reference numerals in the attached figures: 100: Substrate; 200: Interface layer; 300: Dielectric layer; 400: High dielectric dielectric layer. Detailed Implementation

[0020] The embodiments of this application are described in detail below, examples of which are illustrated in the accompanying drawings. In the drawings, for clarity, the dimensions of layers, regions, and elements, as well as their relative dimensions, may be exaggerated. Throughout, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.

[0021] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0022] It should be noted that the terms "first," "second," etc., used in this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that the embodiments of this application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0023] In this application, when numerical intervals (i.e., numerical ranges) are involved, unless otherwise specified, the distribution of selectable numerical values ​​within the numerical interval is considered continuous, and includes the two endpoints of the numerical interval (i.e., the minimum and maximum values), as well as every numerical value between these two endpoints. Unless otherwise specified, when a numerical interval refers only to integers within that numerical interval, it includes the two endpoint integers of the numerical range, as well as every integer between the two endpoints, which is equivalent to directly listing every integer. When multiple numerical ranges are provided to describe features or characteristics, these numerical ranges can be merged. In other words, unless otherwise specified, the numerical ranges disclosed in this application should be understood to include any and all subranges included therein. The "numerical value" in the numerical interval can be any quantitative value, such as a number, percentage, ratio, etc. The term "numerical interval" can be broadly included to include percentage intervals, ratio intervals, proportion intervals, etc.

[0024] A first aspect of this application provides a method for fabricating a semiconductor device. The method includes the following steps: (1) providing a substrate; (2) forming an interface layer on the substrate, the interface layer comprising at least one of silicon oxide and silicon oxynitride; and (3) forming a dielectric layer on the interface layer, the dielectric layer comprising HfO. a ZrO b HfZrO c (3) At least one of HfAlO, HfSiO, and HfLaO; (4) The dielectric layer is subjected to element doping and annealing to obtain a high dielectric layer, wherein a stress gradient is formed in the high dielectric layer along its thickness direction, the stress gradient is used to increase the dielectric constant of the high dielectric layer, and the dielectric constant of the high dielectric layer is at least 60.

[0025] The method in this application induces the crystallization of a high-dielectric layer and constructs a controllable stress gradient inside the high-dielectric layer, thereby achieving a synergistic effect of ultra-high dielectric constant, low leakage current, and good interface characteristics, and thus improving the performance of the device.

[0026] Specifically, the interface layer ensures thermal stability between the channel and the high-dielectric layer and reduces interface states. A stress gradient varying along the thickness direction is formed in the high-dielectric layer, maintaining high crystallinity near the channel region and further inducing high-quality overall film crystallization. The dielectric constant of the high-dielectric layer is at least 60, which can significantly reduce the equivalent oxide layer thickness, thereby further promoting gate stack miniaturization. The replacement of defects such as oxygen vacancies by doping elements reduces the concentration of low-oxygen vacancy defects in the dielectric film, suppressing leakage current.

[0027] In the aforementioned stress gradient formed within the high-dielectric layer that varies along its thickness direction, the thickness direction refers to the direction from the substrate to the high-dielectric layer.

[0028] In the above, the element doping process is used to introduce elements into the dielectric layer, and the annealing process is used to activate and drive the doped elements to migrate within the dielectric layer, thereby forming a stress gradient that varies continuously along its thickness direction in the high dielectric layer; the stress gradient is used to induce and lock the high crystallinity of the high dielectric layer to improve the dielectric constant of the high dielectric layer.

[0029] According to an embodiment of this application, step (1) provides a substrate. The substrate may be at least one of single-crystal silicon, SiGe, and silicon-on-insulator.

[0030] According to an embodiment of this application, step (2) involves forming an interface layer on the substrate, the interface layer comprising at least one of silicon oxide and silicon oxynitride.

[0031] In some embodiments, the interface layer is formed using processes such as ALD and PECVD. During the deposition of the interface layer, the process parameters can be fine-tuned according to its thickness.

[0032] Furthermore, the thickness of the interface layer is controlled between 0.5nm and 1.5nm. Its function is to act as a buffer layer between the channel and the subsequent high-dielectric layer, ensuring thermal stability and reducing the interface state density.

[0033] According to an embodiment of this application, step (3) involves elemental doping and annealing of the dielectric layer to obtain a high-dielectric dielectric layer. A stress gradient varying along the thickness direction is formed within the high-dielectric dielectric layer. The stress gradient is used to increase the dielectric constant of the high-dielectric dielectric layer, and the dielectric constant of the high-dielectric dielectric layer is at least 60.

[0034] In some embodiments, the slope Δ1 of the stress gradient in the direction from the substrate to the high-dielectric layer varies from 0.01 to 0.1, so that the stress gradually decreases. This change in the stress gradient, in turn, affects the stress change, thereby improving the quality of the high-dielectric layer.

[0035] Furthermore, the slope Δ1 of the stress gradient gradually decreases, meaning that the slope of the stress gradient in the region near the interface layer is greater than that in the region near the interface layer. This creates a rapid suppression of interface defects in the region near the substrate, and forms a high-dielectric-constant crystalline phase on the side near the gate electrode.

[0036] As a specific example, the stress gradually decreases in the direction from the substrate towards the high dielectric layer. The elemental doping concentration corresponds to the change in stress.

[0037] In some embodiments, the doping element includes at least one selected from nitrogen, hydrogen, oxygen, argon, rare earth elements, and halogen elements. During the element doping process, these doping elements enter vacancies, inducing lattice strain within the dielectric layer, forming a controllable stress gradient along the thickness direction, reducing defect density, suppressing leakage current, reducing surface energy and grain boundary energy, promoting grain nucleation and growth, forming high crystallinity, and improving phase uniformity.

[0038] Furthermore, the element doping treatment method includes one of plasma treatment and free radical treatment. When plasma treatment is used for element doping, the power of the plasma daughter body can be selected from 600W to 1000W.

[0039] Optionally, the plasma treatment time is 10s-300s.

[0040] In some embodiments, the annealing process can further promote the diffusion of free ions into the dielectric layer of the element doping product, forming non-uniform doping and inducing gradient stress inside the dielectric layer; the gradient stress further forms a high-dielectric dielectric layer with high-quality crystals.

[0041] As a concrete example, see reference Figure 1 After forming the dielectric layer, it undergoes elemental doping and annealing to form a high-dielectric dielectric layer. Specifically, (a) shows the formation of an interface layer 200 on the substrate 100, and a dielectric layer 300 on the interface layer 200, wherein the dielectric layer contains vacancies, represented by hollow circles in the figure. (b) shows the elemental doping and annealing processes, with doping elements (shaded circles in the figure), where the shaded circles represent the migration of elements into the dielectric layer. (c) refers to the formation of a high-dielectric dielectric layer 400, i.e., the doping elements enter the dielectric layer to form a high-dielectric dielectric layer.

[0042] Furthermore, the annealing temperature is 700℃-1000℃, and the time is 3s-80s. The higher temperature causes the dopant elements to migrate along the thickness direction, forming a controllable concentration distribution, such as forming a non-uniform doping concentration distribution, thereby locking the stress gradient; through high-temperature grain growth, a quasi-single crystal structure with a large grain size (>100nm) is formed, reducing the grain boundary density; defects such as oxygen vacancies are repaired, reducing the gate leakage current; and the interface layer regrowth is suppressed under a controlled atmosphere, maintaining ultra-low EOT.

[0043] In some embodiments, in the direction from the substrate to the high-dielectric-constant dielectric layer, the concentration of doped elements in the high-dielectric-constant dielectric layer varies in a gradient, the slope of which is Δ2, and Δ2 is greater than 0.5, for example, it can be 0.51, 0.53, 0.7, 0.9, 1, etc. This further promotes the formation of a dielectric layer with a high dielectric constant and reduces EOT.

[0044] Specifically, the stress gradient lowers the nucleation barrier of the high-K phase, guiding the orderly growth of grains from the interface layer to form a large-sized, low-grain-boundary-density columnar crystal structure. Grain boundaries are the main pathways for leakage current, and large grain size (≥20nm) significantly reduces lateral leakage paths.

[0045] Furthermore, the grain size in the high-dielectric layer is not less than 20 nm. This is achieved by elemental doping and annealing the dielectric layer. For example, a grain size of 20 nm-200 nm and extremely low grain boundary density significantly reduce leakage paths and lower gate leakage current.

[0046] Furthermore, the equivalent oxide layer thickness in the high-dielectric layer is no greater than 0.5 nm. This further enhances the gate's electrostatic control capability over the channel and effectively suppresses the short-channel effect.

[0047] Optionally, the equivalent oxide layer thickness is 0.3 nm to 0.5 nm.

[0048] In some embodiments, after the element doping process and before the annealing process, the method further includes depositing a capping layer comprising titanium oxide. This prevents the doped elements from escaping during the annealing process.

[0049] Furthermore, after the annealing process, the process also includes removing the capping layer. Removing the capping layer eliminates its influence on the device.

[0050] As a concrete example, see reference Figure 2 and 3 An interface layer is deposited on a substrate, a dielectric layer is deposited on the resulting material with the interface layer, and the dielectric layer is then subjected to elemental doping and annealing to obtain a high-dielectric dielectric layer. Figure 2 This is a device fabrication process according to one embodiment, wherein Figure 2 (a) Includes forming an interface layer 200 on the substrate 100, Figure 2 (b) A dielectric layer 300 is wrapped around the interface layer 200. Figure 2 (c) represents the element doping and annealing processes. Figure 2 (d) is a high-dielectric dielectric layer obtained by element doping and annealing of the dielectric layer.

[0051] Figure 3 In other embodiments, the device fabrication process, wherein Figure 3 (a) Includes forming an interface layer 200 on the substrate 100, Figure 3 (b) A dielectric layer 300 is wrapped around the interface layer 200. Figure 3 (c) represents the element doping and annealing processes. Figure 3 (d) is a high-dielectric dielectric layer obtained by element doping and annealing of the dielectric layer.

[0052] A second aspect of this application provides a semiconductor device formed using the fabrication method described in the first aspect. The semiconductor device includes a channel layer, a gate electrode, and a high-dielectric layer and an interface layer stacked between the channel layer and the gate electrode, wherein the interface layer is close to the channel, and the high-dielectric layer has a stress gradient that varies along its thickness direction.

[0053] Exemplary embodiments according to this application will now be described in more detail with reference to the accompanying drawings. It should be understood that these exemplary embodiments may be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein.

[0054] Example 1 An interface layer is formed on the substrate using an ALD process. The material of the interface layer is selected from silicon oxide, and the thickness of the interface layer is 1 nm.

[0055] A dielectric layer containing HfO was grown on the interface layer using ALD, with the temperature controlled at 300℃. a The dielectric layer is selected with a thickness of 2 nm.

[0056] Nitrogen elements are introduced into the dielectric layer using a plasma nitriding process with a power of 800W and a duration of 60s.

[0057] The product obtained from the plasma nitriding process was annealed at 700°C for 12 seconds to obtain a semiconductor device.

[0058] Examples 2 and 3 Semiconductor devices were prepared in accordance with the method of Example 1, except that the heat treatment temperatures were 500°C and 600°C, respectively.

[0059] Figure 4 These are scanning electron microscope images of the devices obtained in Examples 1-3. Figure 4 Image (a) is a scanning electron microscope image of the device in Example 2. Figure 4 Image (b) is a scanning electron microscope image of the device in Example 3. Figure 4 Image (c) is a scanning electron microscope image of the device in Example 1. As can be seen from the image, elemental doping and annealing can significantly increase the grain size of the high dielectric layer and reduce the grain boundary density, thereby increasing the dielectric constant of the high dielectric layer and significantly reducing the leakage path, thus reducing the gate leakage current.

[0060] It should also be noted that the terms "some embodiments," "other embodiments," and "embodiments" used in this application refer to specific features, structures, or characteristics described in connection with those embodiments, which are included in at least one embodiment described in the general description of this application. The appearance of the same expression in multiple places in the specification does not necessarily refer to the same embodiment. Furthermore, when a specific feature, structure, or characteristic is described in connection with any embodiment, the intention is to suggest that implementing such a feature, structure, or characteristic in conjunction with other embodiments also falls within the scope of this application.

[0061] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0062] It should also be noted that the above are merely preferred embodiments of this application and do not limit the scope of protection of this application. Any equivalent structural or procedural transformations made using the content of this application's specification, or direct or indirect applications in other related technical fields, are similarly included within the scope of protection of this application.

Claims

1. A method for fabricating a semiconductor device, characterized in that, Includes the following steps: Provide substrate; An interface layer is formed on the substrate, the interface layer comprising at least one of silicon oxide and silicon oxynitride; A dielectric layer is formed on the interface layer, the dielectric layer comprising HfO. a ZrO b HfZrO c At least one of HfAlO, HfSiO, and HfLaO; The dielectric layer is subjected to elemental doping and annealing to obtain a high-dielectric dielectric layer. A stress gradient varying along the thickness direction is formed within the high-dielectric dielectric layer. The stress gradient is used to increase the dielectric constant of the high-dielectric dielectric layer, and the dielectric constant of the high-dielectric dielectric layer is at least 60.

2. The preparation method according to claim 1, characterized in that, In the direction from the substrate to the high dielectric layer, the slope Δ1 of the stress gradient varies from 0.01 to 0.1, so that the stress in the high dielectric layer gradually decreases.

3. The preparation method according to claim 1, characterized in that, The doped elements include at least one of nitrogen, hydrogen, oxygen, argon, rare earth elements, and halogen elements. The element doping treatment methods include one of plasma treatment and free radical treatment.

4. The preparation method according to any one of claims 1-3, characterized in that, The thickness of the high dielectric layer is less than 2.5 nm.

5. The preparation method according to claim 3, characterized in that, The conditions for plasma treatment include: power of 600W-1000W and time of 10s-300s.

6. The preparation method according to any one of claims 1-3, characterized in that, The annealing temperature is 700℃-1000℃, and the time is 3s-80s.

7. The preparation method according to any one of claims 1-3, characterized in that, In the direction from the substrate to the high-dielectric layer, the concentration of doped elements in the high-dielectric layer varies in a gradient. The slope of the concentration gradient change is Δ2, where Δ2 is greater than 0.

5.

8. The preparation method according to any one of claims 1-3, characterized in that, The size of the grains in the high-dielectric layer is not less than 20 nm.

9. The preparation method according to any one of claims 1-3, characterized in that, The thickness of the equivalent oxide layer in the high dielectric layer is no greater than 0.5 nm.

10. A semiconductor device, characterized in that, Prepared by the preparation method according to any one of claims 1-9 The semiconductor device includes a channel layer, a gate electrode, and a high-dielectric layer and an interface layer stacked between the channel layer and the gate electrode, wherein the interface layer is close to the channel, and the high-dielectric layer has a stress gradient that varies along its thickness direction.

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