Method of forming metal gate
Patent Information
- Application Number
- CN202611167035.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-08-03
- Publication Date
- 2026-10-23
AI Technical Summary
[0004]本发明的目的在于提供一种金属栅的形成方法，以解决干法刻蚀工艺窗口较小的问题
[0025]本发明提供的金属栅的形成方法，包括提供在晶圆表面绝缘介质层内形成有栅凹槽的晶圆；在所述栅凹槽内依次沉积高K栅介质层、功函数层和阻挡层；在形成有所述阻挡层的栅凹槽内填充金属层，使得所述金属层高出所述绝缘介质层表面预设厚度；采用化学机械研磨的方式，去除所述绝缘介质层表面的所述高K栅介质层以及所述高K栅介质层上的其他介质层，使得所述金属层与所述绝缘介质层表面大致齐平；至少再进行一次化学机械研磨，使得金属栅的厚度到第一预设厚度；再沉积第二预设厚度的所述绝缘介质层；在所述绝缘介质层上形成对应于所述栅凹槽图案的掩模层；以所述掩模层图案，去除所述金属栅上的所述绝缘介质层；去除所述掩模层，形成低于所述绝缘介质层所述第二预设厚度的金属栅。通过采用CMP工艺替代干法刻蚀工艺，对金属栅的高度进行调节，再沉积绝缘介质补足后通过干法刻蚀打开金属栅区域，消除干法刻蚀等离子体对金属栅的损伤，后续的绝缘介质刻蚀损伤更小，残留在后续清洗工艺中更容易去除，降低短路风险，更易于控制一片晶圆上所有芯片的电学性质均一性。
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Figure CN122970970A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a method for forming a metal gate. Background Technology
[0002] With the iteration of semiconductor technology nodes, metal gates have become the most effective way to solve gate depletion and are widely used by major manufacturers. The most common metal material used for metal gates is tungsten (W). To adjust the electrical properties of the device, after removing excess surface metal using CMP (Chemical Metallurgy), the metal gate height needs to be precisely adjusted using dry etching, known as W Etch Back. This process requires that the plasma etching process not damage the metal gate device, but also etch to a certain depth to achieve the purpose of adjusting the gate height, while avoiding threshold voltage deviation or causing short circuits. Therefore, the process window and parameter control of dry etching have very high requirements. Even a slight drift in etching parameters can lead to a decrease in device yield or even scrap. With the continuous iteration of process nodes, the process window of dry etching has gradually become unable to cover all situations, thus requiring a new method to adjust the gate height to meet the needs of new processes.
[0003] It should be noted that the information disclosed in the background section of this invention is intended only to enhance the understanding of the general background of this invention, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention
[0004] The purpose of this invention is to provide a method for forming a metal gate to solve the problem of small window size in dry etching processes.
[0005] To solve the above-mentioned technical problems, the present invention provides a method for forming a metal grid, comprising the following steps:
[0006] Step S1: Provide a wafer with gate grooves formed in the insulating dielectric layer on the wafer surface;
[0007] Step S2: Sequentially deposit a high-K gate dielectric layer, a work function layer, and a barrier layer within the gate groove;
[0008] Step S3: Fill the gate groove where the barrier layer is formed with a metal layer, such that the metal layer is higher than the surface of the insulating dielectric layer by a predetermined thickness;
[0009] Step S4: Use chemical mechanical polishing to remove the high-K gate dielectric layer and other dielectric layers on the surface of the insulating dielectric layer, so that the metal layer is approximately flush with the surface of the insulating dielectric layer;
[0010] Step S5: Based on step S4, perform at least one more chemical mechanical polishing to bring the thickness of the metal grid to the first preset thickness;
[0011] Step S6: Deposit a second predetermined thickness of the insulating dielectric layer on top of step S5;
[0012] Step S7: Form a mask layer corresponding to the gate groove pattern on the insulating dielectric layer in step S6;
[0013] Step S8: Remove the insulating dielectric layer on the metal gate using the mask layer pattern described in step S7;
[0014] Step S9: After step S8, the mask layer is removed to form a metal gate with a thickness lower than the second preset thickness of the insulating dielectric layer.
[0015] Preferably, in step S1, a source region and a drain region are also formed on the wafer surface, respectively disposed on both sides of the bottom of the gate groove.
[0016] Preferably, in step S6, the second preset thickness is equal to the thickness reduced during chemical mechanical polishing in step S5.
[0017] Preferably, in step S7, forming the mask layer includes:
[0018] An organic planarization layer and a photoresist layer are sequentially formed on the insulating dielectric layer;
[0019] The organic planarization layer and the photoresist layer are patterned using a photolithography process to open the top region of the gate recess.
[0020] Preferably, the insulating dielectric layer is made of silicon oxide.
[0021] Preferably, the metal layer is made of tungsten.
[0022] Preferably, the insulating dielectric layer on the metal gate is removed by dry etching with a fluorine-containing gas using the mask layer in step S7.
[0023] Preferably, the high-k gate dielectric layer is made of HfSiO2.
[0024] Preferably, the material of the barrier layer includes TiN and Ti.
[0025] The present invention provides a method for forming a metal gate, comprising: providing a wafer in which gate grooves are formed within an insulating dielectric layer on the wafer surface; sequentially depositing a high-k gate dielectric layer, a work function layer, and a barrier layer within the gate grooves; filling the gate grooves in which the barrier layer is formed with a metal layer such that the metal layer is higher than the surface of the insulating dielectric layer by a predetermined thickness; removing the high-k gate dielectric layer and other dielectric layers on the surface of the insulating dielectric layer by chemical mechanical polishing, such that the metal layer is approximately flush with the surface of the insulating dielectric layer; performing at least one more chemical mechanical polishing to reduce the thickness of the metal gate to a first predetermined thickness; depositing the insulating dielectric layer to a second predetermined thickness; forming a mask layer on the insulating dielectric layer corresponding to the gate groove pattern; removing the insulating dielectric layer on the metal gate using the mask layer pattern; and removing the mask layer to form a metal gate with a thickness lower than the second predetermined thickness of the insulating dielectric layer. By using CMP (Continuous Metal Processing) to replace dry etching, the height of the metal gate is adjusted, and after replenishing with insulating dielectric, the metal gate area is opened by dry etching. This eliminates the damage to the metal gate caused by the dry etching plasma, resulting in less damage from subsequent insulating dielectric etching. The residue is also easier to remove in subsequent cleaning processes, reducing the risk of short circuits and making it easier to control the uniformity of electrical properties of all chips on a wafer. Attached Figure Description
[0026] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:
[0027] Figure 1 This is a schematic diagram of a stacked structure in the prior art;
[0028] Figure 2 This is a schematic diagram of the metal layer structure in the prior art;
[0029] Figure 3 This is a schematic diagram of the structure after CMP process in the prior art;
[0030] Figure 4 This is a schematic diagram of the structure after back etching using existing technology;
[0031] Figure 5 This is a flowchart of an embodiment of the present invention;
[0032] Figure 6 This is a schematic diagram of a stacked structure according to an embodiment of the present invention;
[0033] Figure 7 This is a schematic diagram of a metal layer structure according to an embodiment of the present invention;
[0034] Figure 8 This is a schematic diagram of the structure after the first thinning process according to an embodiment of the present invention;
[0035] Figure 9 This is a schematic diagram of the structure after the second thinning process according to an embodiment of the present invention;
[0036] Figure 10 This is a schematic diagram of the structure after depositing an insulating dielectric layer according to an embodiment of the present invention;
[0037] Figure 11 This is a schematic diagram of the structure after forming an organic planarization layer and a photoresist layer according to an embodiment of the present invention;
[0038] Figure 12 This is a schematic diagram of the structure after removing the high-k gate dielectric layer, work function layer, barrier layer and silicon oxide above the metal layer according to an embodiment of the present invention;
[0039] Figure 13 This is a schematic diagram of the structure after removing the organic planarization layer and the photoresist layer according to an embodiment of the present invention.
[0040] In the attached image:
[0041] 10. Substrate; 11. Source region; 12. Drain region; 20. Insulating dielectric layer; 30. High-k gate dielectric layer; 40. Work function layer; 50. Barrier layer; 60. Metal layer; 70. Organic planarization layer; 80. Photoresist layer. Detailed Implementation
[0042] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in more detail below with reference to the accompanying drawings. Embodiments of this disclosure are illustrated in the accompanying drawings. However, this disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the content of this disclosure thorough and complete.
[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. The terminology used in this disclosure is for describing particular embodiments only and is not intended to limit the scope of this disclosure.
[0044] It should be understood that when an element or layer is referred to as being "in," "near," "connected to," or "coupled to" another element or layer, it can be directly in, near, connected to, or coupled to that other element or layer, or there may be intermediate elements or layers. Conversely, when an element is referred to as being "directly in," "directly near," "directly connected to," or "directly coupled to" another element or layer, there are no intermediate elements or layers. It should be understood that although the terms "first," "second," "third," etc., can be used to describe various elements, parts, regions, layers, doping types, and / or portions, they should not be limiting of these elements, parts, regions, layers, doping types, and / or portions. These terms are used only to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this disclosure, the first element, part, region, layer, doping type, or portion discussed below may be referred to as the second element, part, region, layer, doping type, or portion. For example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type. The first doping type and the second doping type are different doping types. For example, the first doping type can be P-type and the second doping type can be N-type, or the first doping type can be N-type and the second doping type can be P-type.
[0045] This document uses spatial relation terms such as “below,” “under,” “lower,” “above,” or “upper” to describe the relationship of one element or feature to another element or feature shown in the figures. It should be understood that, in addition to the orientations shown in the figures, spatial relation terms also include different orientations of the device during use and operation. For example, if the device in the figures is flipped, the element described as “below” or “under” another element or feature would be facing “above” that other element or feature. Therefore, the exemplary terms “below” and “under” can include upward and downward directions. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein should be interpreted accordingly.
[0046] As used herein, the singular forms “a,” “an,” “an,” and “the” may include the plural forms unless the context clearly indicates otherwise. It should also be understood that terms such as “comprising / including” or “having” specify the presence of the stated feature, integral, step, operation, component, part, or combination thereof, but do not preclude the possibility of the presence or addition of one or more other features, integrals, steps, operations, components, parts, or combinations thereof. Additionally, in the specification, the term “and / or” includes any and all combinations of the associated listed items.
[0047] Embodiments of this disclosure are described herein with reference to schematic cross-sectional views of preferred embodiments (and intermediate structures) of this disclosure; therefore, it is expected that the shapes shown will vary due to manufacturing techniques and / or tolerances, etc. Consequently, embodiments of this disclosure should not be limited to the specific shapes of the regions shown herein, but should include shape variations, for example, due to manufacturing techniques. For instance, injection regions shown as rectangular typically have rounded or curved features at their edges and / or injection concentration gradients, rather than a binary variation from the injection region to the non-injection region. Furthermore, the embedded region formed by injection may result in some injection in the area between the embedded region and the surface where the injection is performed. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of the device regions, nor do they limit the scope of this disclosure.
[0048] The existing techniques for etching back metal gates include the following steps: Figure 1 As shown, a metal gate region is dry-etched onto the front insulating dielectric layer 20, followed by the deposition of a high-K gate dielectric layer 30, a work function layer 40, and a barrier layer 50; as Figure 2 As shown, a metal layer 60 is deposited on the surface to fill the metal gate region using PVD (Physical Vapor Deposition); as... Figure 3 As shown, the excess metal layer 60 and work function layer 40 on the surface are removed by CMP process, leaving the remaining film on the surface of the insulating dielectric layer 20; Figure 4 As shown, the height of the metal gate is adjusted by dry etching of a portion of the metal layer 60, the high-K gate dielectric layer 30, the work function layer 40, the barrier layer 50, etc., according to the required electrical parameters.
[0049] The study found that the dry etching method described above requires precise control of parameters such as time and endpoint during the etching process to regulate the metal gate height, resulting in a narrow process window. Furthermore, this process requires etching the metal layer 60 to a certain depth, and the plasma etching process may damage the surface of the metal gate, i.e., the metal layer 60, leading to device electrical instability or yield issues. When the metal layer 60 is made of tungsten, the tungsten back-etching process generates byproducts. If these byproducts are not thoroughly cleaned, they can connect the metal gate and the contact hole in the subsequent contact hole process, causing short circuits. The plasma used in dry etching (usually a gas containing C and F) contains F ions, whose strong penetrating power allows them to easily penetrate the channel region, causing channel failure. Dry etching also introduces loading on different areas of the wafer or metal gates of different lengths. Under the loading effect, the overall electrical properties of all chips will differ.
[0050] Based on this, the core idea of the present invention is to precisely adjust the metal gate height by using CMP process, thereby eliminating the damage to the metal gate caused by dry etching plasma. Subsequent etching damage is smaller, and the residue is easier to remove in subsequent cleaning processes, reducing the risk of short circuits and making it easier to control the uniformity of electrical properties of all chips on a wafer.
[0051] For details, please refer to Figures 5-13 This is a schematic diagram of an embodiment of the present invention. Figure 5 As shown, a method for forming a metal grid includes:
[0052] Step S1: Provide a wafer with gate grooves formed in the insulating dielectric layer on the wafer surface;
[0053] Step S2: Sequentially deposit a high-K gate dielectric layer 30, a work function layer 40, and a barrier layer 50 within the gate groove;
[0054] Step S3: Fill the gate groove where the barrier layer 50 is formed with a metal layer 60, such that the metal layer 60 is higher than the surface of the insulating dielectric layer 20 by a predetermined thickness.
[0055] Step S4: Use chemical mechanical polishing to remove the high-K gate dielectric layer 30 and other dielectric layers on the surface of the insulating dielectric layer 20, so that the metal layer 60 is approximately flush with the surface of the insulating dielectric layer 20.
[0056] Step S5: Based on step S4, perform at least one more chemical mechanical polishing to bring the thickness of the metal grid to the first preset thickness;
[0057] Step S6: Deposit the insulating dielectric layer 20 of a second predetermined thickness on top of the layer in step S5;
[0058] Step S7: Form a mask layer corresponding to the gate groove pattern on the insulating dielectric layer 20 of step S6;
[0059] Step S8: Using the mask layer pattern from step S7, remove the insulating dielectric layer 20 on the metal gate;
[0060] Step S9: After step S8, the mask layer is removed to form a metal gate with a thickness lower than the second preset thickness of the insulating dielectric layer 20.
[0061] To address the issues of a small process window and material damage associated with dry etching, CNC machining (CMP) was adopted to replace the previous dry etching method. First, CMP does not involve plasma, thus directly avoiding the influence of fluorine ions on the channel. Second, CMP allows for control of the polishing rate by adjusting the polishing pressure and polishing slurry formulation, thereby increasing the process window. Finally, CMP has a lower loading rate than dry etching, making it easier to control the electrical property uniformity of all chips on a wafer.
[0062] The metal layer 60 is thinned to the desired target height using CMP process, and oxide is re-covered on the metal layer 60. The oxide on the top of the metal layer 60 is removed by etching separately to form the desired structure. This method can precisely adjust the height of the metal gate, or metal layer 60, and reduce damage to the top surface of the metal layer 60. Residues are easy to remove.
[0063] First, provide wafers, such as... Figure 6 In step S1, the substrate 10 of the wafer shown further includes source regions 11 and drain regions 12 correspondingly disposed on both sides of the bottom of the gate recess. It is understood that the region between the source region 11 and the drain region 12 is a channel region, and the gate recess is located above the channel region. It is understood that the substrate 10 referred to herein can include any type of substrate, typically a semiconductor substrate, such as a bulk single-crystal silicon wafer, a binary compound substrate (e.g., a GaAs silicon wafer), a ternary compound substrate (e.g., an AlGaAs silicon wafer), or a higher-order compound silicon wafer, on which additional insulating or conductive layers may or may not be formed. When a semiconductor substrate is used, it may also include non-semiconductor materials, such as oxides in a half-silicon insulator (SOI), partially SOI substrates, polycrystalline silicon, insulators, oxides, metals, amorphous silicon, or organic materials. In some embodiments, the substrate 10 may also include multiple wafers or dies stacked together or otherwise bonded together. The substrate 10 may include a wafer cut from a silicon ingot, and / or any other type of semiconductor / non-semiconductor and / or deposited or grown layer (such as an epitaxial layer) formed on the underlying sub-substrate.
[0064] The high-k gate dielectric layer 30 is made of HfSiO2. The barrier layer 50 is made of TiN or Ti, and it effectively prevents the migration of metal atoms, reducing the risk of short circuits and leakage current. The insulating dielectric layer 20 is made of silicon oxide. For NMOS transistors, TiAl is commonly used as the work function layer 40, while for PMOS transistors, TiN is commonly used.
[0065] like Figure 7 As shown, a metal layer 60 is filled in the gate recess region. The material of the metal layer 60 includes tungsten.
[0066] Next, the metal layer 60 is thinned using a two-step CMP process. Specifically, the CMP process for thinning the metal layer 60 includes:
[0067] like Figure 8 As shown, the metal layer 60 is thinned using a CMP process until the high-K gate dielectric layer 30, work function layer 40, and barrier layer 50 on the top surface of the insulating dielectric layer 20 are removed.
[0068] like Figure 9 As shown, the metal layer 60 and the insulating dielectric layer 20 are further thinned using a CMP process to form a metal gate, exposing the top surfaces of the high-K gate dielectric layer 30, the work function layer 40, and the barrier layer 50 on both sides of the metal gate.
[0069] First, the film layer on the surface of the insulating dielectric layer 20 is completely removed. Then, the metal layer 60 is ground down to the target height required for the metal gate. CMP (Continuous Polishing) is used instead of traditional dry etching to continue grinding downwards. A polishing slurry specifically for tungsten (such as Fujimi's dedicated polishing slurry) and cerium-based abrasives can be used to control the grinding rate of the tungsten and the interlayer dielectric layer (ILD), which is the insulating dielectric layer 20. The height of the remaining metal layer 60, or metal gate, is precisely adjusted by the grinding time.
[0070] like Figure 10 As shown, FCVD (Flowable CVD) or PECVD (Plasma Enhanced CVD) is used on the metal layer 60 and the insulating dielectric layer 20 to re-deposit and replenish the insulating dielectric layer 20 that was worn away in the previous CMP process.
[0071] Understandably, in step S6, the second preset thickness is equal to the thickness reduced in the chemical mechanical polishing process in step S5, and the thickness of the deposited silicon oxide corresponds to the thickness of the insulating dielectric layer 20 reduced by the CMP process.
[0072] like Figure 11 As shown, in step S7, forming the mask layer includes:
[0073] An organic planarization layer 70 and a photoresist layer 80 are sequentially formed on the insulating dielectric layer 20;
[0074] The organic planarization layer 70 and the photoresist layer 80 are patterned using a photolithography process to open the top region of the gate groove.
[0075] Next, the insulating dielectric layer 20 on the metal gate is removed by dry etching with a fluorine-containing gas using the mask layer from step S7.
[0076] For example, photolithography, exposure, and development processes are first performed on the photoresist layer 80 to form a pattern exposing the gate recess region. The patterned photoresist layer 80 is then used to etch the organic planarization layer 70, forming the organic planarization layer 70 and photoresist layer 80 that expose the high-k gate dielectric layer 30, the work function layer 40, the barrier layer 50, and the oxide on top of the metal layer 60. By defining the metal gate region to be opened through photolithography, it is easier to adjust the CD (Critical Dimension) size, increase the adjustable process window, and provide a feasible solution to the short-circuit risk of subsequent contact hole connections.
[0077] The redeposited silicon oxide is etched away using a dry etching method, such as... Figure 12 Because of the high selectivity between tungsten and silicon oxide, etching can be precisely stopped on the tungsten surface, opening the metal gate area and etching the oxide without consuming the metal layer 60. Therefore, there is no problem of fluoride ions penetrating the tungsten metal layer 60 and causing channel failure.
[0078] Specifically, after etching away the high-k gate dielectric layer 30, the work function layer 40, the barrier layer 50, and the oxide on top of the metal gate, the organic planarization layer 70 and the photoresist layer 80 are also removed to form a metal gate with a thickness lower than the second preset thickness of silicon oxide, such as... Figure 13 .
[0079] Furthermore, etching, such as wet etching, is used to remove the organic planarization layer (OPL) 70 and the photoresist layer 80. The photoresist layer 80 is an adhesive photoresist film used in semiconductor chip packaging or printed circuit board manufacturing. It is typically a photosensitive polymer material, such as polyimide (PI), bis-benzocyclobutene (BCB), or poly(p-phenylene-2,6-benzobisOxazole) (PBO).
[0080] The method for forming a metal gate provided by the present invention includes: step S1: providing a wafer in which a gate groove is formed in an insulating dielectric layer on the wafer surface; step S2: sequentially depositing a high-K gate dielectric layer 30, a work function layer 40, and a barrier layer 50 in the gate groove; step S3: filling the gate groove in which the barrier layer 50 is formed with a metal layer 60, such that the metal layer 60 is higher than a predetermined thickness above the surface of the insulating dielectric layer 20; step S4: removing the high-K gate dielectric layer 30 and other dielectric layers on the high-K gate dielectric layer 30 from the surface of the insulating dielectric layer 20 by chemical mechanical polishing, such that the metal layer 60 and the insulating dielectric layer 20 are separated. The surface of dielectric layer 20 is approximately flush; Step S5: Based on step S4, perform at least one more chemical mechanical polishing (CMP) to bring the metal gate thickness to a first preset thickness; Step S6: Deposit the insulating dielectric layer 20 with a second preset thickness on top of step S5; Step S7: Form a mask layer corresponding to the gate groove pattern on the insulating dielectric layer 20 of step S6; Step S8: Remove the insulating dielectric layer 20 on the metal gate using the mask layer pattern from step S7; Step S9: After step S8, remove the mask layer to form a metal gate with a thickness lower than the second preset thickness of the insulating dielectric layer 20. Using CMP technology instead of dry etching to adjust the metal gate height provides more precise height adjustment, eliminates plasma damage to the metal gate during dry etching, and improves device yield stability. Subsequent oxide etching causes less damage compared to tungsten etching, and residues are easier to remove in subsequent cleaning processes, reducing the risk of short circuits. Compared to dry etching, CMP process has a smaller load, making it easier to control the electrical properties uniformity of all chips on a wafer. There are no F ions in CMP process, and there is basically no subsequent dry etching process for the tungsten metal layer 60, so it will not damage the channel area and cause short circuits in the device.
[0081] The above description is only a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present invention.
Claims
1. A method for forming a metal grid, characterized in that, Includes the following steps: Step S1: Provide a wafer with gate grooves formed in the insulating dielectric layer on the wafer surface; Step S2: Sequentially deposit a high-K gate dielectric layer, a work function layer, and a barrier layer within the gate groove; Step S3: Fill the gate groove where the barrier layer is formed with a metal layer, such that the metal layer is higher than the surface of the insulating dielectric layer by a predetermined thickness; Step S4: Use chemical mechanical polishing to remove the high-K gate dielectric layer and other dielectric layers on the surface of the insulating dielectric layer, so that the metal layer is approximately flush with the surface of the insulating dielectric layer; Step S5: Based on step S4, perform at least one more chemical mechanical polishing to bring the thickness of the metal grid to the first preset thickness; Step S6: Deposit a second predetermined thickness of the insulating dielectric layer on top of step S5; Step S7: Form a mask layer corresponding to the gate groove pattern on the insulating dielectric layer in step S6; Step S8: Remove the insulating dielectric layer on the metal gate using the mask layer pattern described in step S7; Step S9: After step S8, the mask layer is removed to form a metal gate with a thickness lower than the second preset thickness of the insulating dielectric layer.
2. The method for forming a metal grid according to claim 1, characterized in that, In step S1, source and drain regions are also formed on the wafer surface, respectively located on both sides of the bottom of the gate groove.
3. The method for forming a metal grid according to claim 1, characterized in that, In step S6, the second preset thickness is equal to the thickness reduced during chemical mechanical polishing in step S5.
4. The method for forming a metal grid according to claim 1, characterized in that, In step S7, forming the mask layer includes: An organic planarization layer and a photoresist layer are sequentially formed on the insulating dielectric layer; The organic planarization layer and the photoresist layer are patterned using a photolithography process to open the top region of the gate recess.
5. The method for forming a metal grid according to claim 1, characterized in that, The insulating dielectric layer is made of silicon oxide.
6. The method for forming a metal grid according to claim 5, characterized in that, The metal layer is made of tungsten.
7. The method for forming a metal grid according to claim 6, characterized in that, Using the mask layer from step S7, the insulating dielectric layer on the metal gate is removed by dry etching with a fluorine-containing gas.
8. The method for forming a metal grid according to claim 1, characterized in that, The high-K gate dielectric layer is made of HfSiO2.
9. The method for forming a metal grid according to claim 1, characterized in that, The barrier layer is made of materials including TiN and Ti.