Semiconductor element and method for manufacturing the same

Abstract

A semiconductor device and a method of fabricating the same are disclosed. The method includes providing a substrate including a core region and an input / output (I / O) region, forming a first gate structure in the core region and a second gate structure in the I / O region, forming a first spacer next to the first gate structure and a second spacer next to the second gate structure, the first spacer and the second spacer including different widths, and forming a first source / drain region next to the first spacer and a second source / drain region next to the second spacer.

Description

Technical Field

[0001] This invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming spacer walls of different thicknesses in the core region and the input / output (I / O) region, respectively. Background Technology

[0002] In the current semiconductor industry, polysilicon is widely used in semiconductor devices such as metal-oxide-semiconductor (MOS) transistors as the standard gate fill material. However, as the size of MOS transistors continues to shrink, traditional polysilicon gates suffer from problems such as reduced device performance due to the boron penetration effect and the unavoidable depletion effect. This leads to an increase in the equivalent gate dielectric layer thickness, a decrease in gate capacitance, and consequently, a decline in device drive capability. Therefore, the semiconductor industry is also exploring new gate fill materials, such as work function metals, to replace traditional polysilicon gates as control electrodes to match high-k gate dielectric layers.

[0003] However, in current metal gate transistor fabrication processes, particularly in the input / output (I / O) region and core region, the electrical performance is suboptimal due to the pre-defined gate dielectric layer thickness. Therefore, improving current metal gate fabrication processes to address this issue is a crucial research topic. Summary of the Invention

[0004] An embodiment of the present invention discloses a method for fabricating a semiconductor device, which mainly involves first providing a substrate including a core region and an input / output (I / O) region, then forming a first gate structure in the core region and a second gate structure in the I / O region, forming a first gap wall next to the first gate structure and a second gap wall next to the second gate structure, wherein the first gap wall and the second gap wall have different widths, and then forming a first source / drain region next to the first gap wall and a second source / drain region next to the second gap wall.

[0005] Another embodiment of the present invention discloses a semiconductor device, which mainly includes a substrate comprising a core region and an input / output (I / O) region, a first gate structure disposed in the core region and a second gate structure disposed in the I / O region, a first gap wall disposed next to the first gate structure and a second gap wall disposed next to the second gate structure, a first source / drain region disposed next to the first gap wall and a second source / drain region disposed next to the second gap wall, wherein the first gap wall and the second gap wall have different widths. Attached Figure Description

[0006] Figures 1 to 7 This is a schematic diagram of a method for fabricating a semiconductor device according to an embodiment of the present invention;

[0007] Figures 8 to 10 This is a schematic diagram of a method for fabricating a semiconductor device according to an embodiment of the present invention.

[0008] Symbol explanation:

[0009] 12: Base

[0010] 14: Core Area

[0011] 16:I / O area

[0012] 20: Fin-like structure

[0013] 22: Gate Structure

[0014] 24: Gate dielectric layer

[0015] 26: Gate material layer

[0016] 28: Spacer wall

[0017] 30: Source / Drain Region

[0018] 32: Epitaxial layer

[0019] 34: Contact hole etching stop layer

[0020] 36: Interlayer dielectric layer

[0021] 38: Groove

[0022] 50: Gate dielectric layer

[0023] 52: High dielectric constant dielectric layer

[0024] 54: Work function metal layer

[0025] 56: Low-resistivity metal layer

[0026] 58: Metal gate

[0027] 58: Hard Mask

[0028] 62: Metal gate

[0029] 64: Contact plug

[0030] 66: Stop Layer

[0031] 72: Processing and manufacturing techniques

[0032] 74: Patterned Mask

[0033] 78: Interstitial wall Detailed Implementation

[0034] Please refer to Figures 1 to 7 , Figures 1 to 7 This is a schematic diagram illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention. Figure 1 As shown, a substrate 12 is first provided, such as a silicon substrate or a silicon-on-insulator (SOI) substrate, and a core region 14 and an input / output (I / O) region 16 are defined on the substrate. In this embodiment, the core region 14 and the I / O region 16 are preferably transistor regions of the same conductivity type, such as both PMOS transistor regions or both NMOS transistor regions. Each core region 14 and I / O region 16 on the substrate 12 has at least one fin structure 20, wherein the bottom of the fin structure 20 is covered by an insulating material such as silicon oxide to form a shallow trench isolation (not shown). It should be noted that although this embodiment takes the fabrication of a non-planar field-effect transistor such as a fin structure as an example, it is not limited to this. The present invention can also be applied to general planar field-effect transistors, and this embodiment is also within the scope of the present invention.

[0035] According to one embodiment of the present invention, the fin structure 20 can be fabricated using sidewall image transfer (SIT) technology. The procedure generally includes: providing a layout pattern to a computer system and performing appropriate calculations to define the corresponding pattern in a photomask. Subsequently, multiple equidistant and equally wide patterned sacrificial layers are formed on a substrate using photolithography and etching processes, giving each layer a strip-like appearance. Then, deposition and etching processes are sequentially performed to form spacers on the sidewalls of the patterned sacrificial layers. The patterned sacrificial layers are then removed, and etching is performed under the cover of the spacers, transferring the pattern formed by the spacers into the substrate. Finally, a fin cut process is performed to obtain the desired patterned structure, such as a strip-shaped patterned fin structure.

[0036] In addition, the formation of the fin structure 20 may also include first forming a patterned mask (not shown) on the substrate 12, and then transferring the pattern of the patterned mask to the substrate 12 through an etching process to form the fin structure 20. Alternatively, the fin structure 20 may be formed by first fabricating a patterned hard mask layer (not shown) on the substrate 12, and then using an epitaxial fabrication process to grow a semiconductor layer, such as silicon-germanium, on the substrate 12 exposed above the patterned hard mask layer. This semiconductor layer can then serve as the corresponding fin structure 20. These embodiments of forming the fin structure 20 are all within the scope of this invention.

[0037] Next, gate structures 22 or dummy gates can be formed on the substrate 12 of the core region 14 and the I / O region 16, respectively. In this embodiment, the gate structure 22 is preferably formed by sequentially forming a gate dielectric layer 24, a gate material layer 26, and a selective hard mask (not shown) on the substrate 12, and using a patterned photoresist (not shown) as a mask to perform a pattern transfer fabrication process. A single etching or sequential etching step is used to remove a portion of the gate material layer 26 and a portion of the gate dielectric layer 24, and then the patterned photoresist is stripped to form at least one gate structure 22 composed of a patterned gate dielectric layer 24 and a patterned gate material layer 26 on the fin structure 20 of the core region 14 and the I / O region 16, respectively. In this embodiment, the gate dielectric layer 24 may contain silicon oxide and the gate material layer 26 may contain polysilicon, but is not limited thereto.

[0038] Then, at least one spacer 28, such as an offset spacer, is formed on the sidewall of each gate structure 22. The spacer 28 located in the core region 14 and the spacer 28 in the I / O region 16 have the same thickness or width 'a'. The width 'a' of each spacer 28 is preferably greater than 20 angstroms, for example, between 20 and 25 angstroms. The spacer 28 is preferably selected from oxygen-free compounds or dielectric materials, such as, but not limited to, silicon nitride (SiN) or silicon carbide (SiC). In this embodiment, the thickness of the spacer 28 can be defined as the maximum width range of the spacer 28 extending along the horizontal or X-direction.

[0039] Then as Figure 2 As shown, a processing step 72 is performed to remove some of the gap walls 28 in the core region 14, but not any of the gap walls 28 in the I / O region 16. More specifically, in this stage, a patterned mask 74, such as a patterned photoresist, can be formed on the I / O region 16 first, and then a processing step 72 is performed, for example, using wet etching or dry etching with the patterned mask 74 as a mask to remove some of the gap walls 28 in the core region 14, so that the width a of each gap wall 28 in the core region 14 is slightly reduced to width b. Since the width a of the gap walls 28 in the I / O region 16 is not affected by etching during the etching process due to the masking of the patterned mask 74, the width b of each gap wall 28 in the core region 14 after processing step 72 is preferably slightly smaller than the width a of each gap wall 28 in the I / O region 16. According to one embodiment of the present invention, the width b of each gap wall 28 of the core region 14 is preferably less than 20 angstroms after being thinned by the processing manufacturing process 72, such as between 15 and 20 angstroms or more preferably about 15 angstroms, while the width a of the gap wall 28 of the I / O region 16 is maintained at more than 20 angstroms after the processing manufacturing process, such as between 20 and 25 angstroms or more preferably about 25 angstroms.

[0040] Subsequently, as Figure 3As shown, the patterned mask 74 is first removed, and then another gap wall 78, such as the main gap wall, is formed next to the gap wall 28. Preferably, the gap wall 78 in the core region 14 and the gap wall 78 in the I / O region 16 have the same thickness or width, and the thickness or width of each gap wall 78 is preferably greater than 70 angstroms, for example, between 75-85 angstroms or preferably about 80 angstroms. It is worth noting that the gap walls 28 and 78 located on the sidewalls of each gate structure 22 in this stage have three different widths. The inner gap walls 28 in the core region 14 have the smallest width b, the inner gap walls 28 in the I / O region 16 have an intermediate width a, and the outer gap walls 78 in the core region 14 and the I / O region 16 have the largest width c. Preferably, the width c of each gap wall 78 is more than one, such as two, three, four, or even five times or more, than the width a and / or b of the gap wall 28. These are all within the scope of this invention. Furthermore, the spacer wall 78 formed in this stage may contain the same or different materials as the aforementioned spacer wall 28. For example, the spacer wall 78 may contain silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbide nitride, or combinations thereof, but is not limited thereto.

[0041] like Figure 4 As shown, a source / drain region 30 and / or epitaxial layer 32 can then be formed in the fin-like structure 20 on both sides of the spacer wall 78 and / or in the substrate 12, and a metal silicide (not shown) can be selectively formed on the surface of the source / drain region 30 and / or epitaxial layer 32. In this embodiment, the source / drain region 30 and the epitaxial layer 32 may contain different dopants or different materials depending on the conductivity type of the transistor being disposed. For example, the source / drain region 30 may contain P-type dopants or N-type dopants, while the epitaxial layer 32 may contain silicon germanide, silicon carbide, or silicon phosphide.

[0042] Next, a contact etch stop layer (CESL) 34 made of silicon nitride is selectively formed on the substrate 12 and covers the gate structure 22. Then, an interlayer dielectric layer 36 is formed on the contact etch stop layer 34. Then, a planarization process is performed, for example, by chemical mechanical polishing (CMP) to remove part of the interlayer dielectric layer 36 and part of the contact etch stop layer 34 and expose the gate material layer 26 made of polysilicon, so that the upper surface of the gate material layer 26 of the core region 14 and the I / O region 16 is flush with the upper surface of the interlayer dielectric layer 36.

[0043] Subsequently, as Figure 5As shown, a metal gate replacement (RMG) fabrication process is performed to convert each gate structure 22 into a metal gate. For example, a selective dry etching or wet etching process can be performed first, such as using an etching solution such as ammonia hydroxide (NH4OH) or tetramethylammonium hydroxide (TMAH) to remove the gate material layer 26 and the gate dielectric layer 24 in the gate structure 22 of the core region 14 and the I / O region 16, so as to form a groove 38 in the interlayer dielectric layer 36.

[0044] like Figure 6 As shown, an oxide growth process, such as a rapid thermal oxidation (RTO) process or an in-situ steam generation (ISSG) process, is then performed to form a gate dielectric layer 50 made of silicon oxide in the recesses 38 of the core region 14 and the I / O region 16, respectively. It should be noted that, to accommodate the higher voltage of the I / O region 16, the thickness of the gate dielectric layer 50 in the I / O region 16 is preferably greater than the thickness of the gate dielectric layer 50 in the core region 14.

[0045] Subsequently, a high dielectric constant dielectric layer 52, a work function metal layer 54, and a low impedance metal layer 56 are sequentially formed in the groove. Then, a planarization process is performed, for example, CMP is used to remove part of the low impedance metal layer 56, part of the work function metal layer 54, and part of the high dielectric constant dielectric layer 52 to form a metal gate 62 or a gate electrode.

[0046] In this embodiment, the high dielectric constant dielectric layer 52 comprises a dielectric material with a dielectric constant greater than 4, such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), and strontium bismuth tantalum oxide (SrTiO3). SrBi₂Ta₂O₉, SBT, lead zirconate titanate, PbZr x Ti 1-x O3, PZT), barium strontium titanate (Ba x Sr 1-x The group consisting of TiO3, BST, or combinations thereof.

[0047] The work function metal layer 54 is preferably used to adjust the work function of the metal gate to make it suitable for N-type transistors (NMOS) or P-type transistors (PMOS). If the transistor is an N-type transistor, the work function metal layer 54 can be made of a metal material with a work function of 3.9 eV to 4.3 eV, such as titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), hafnium aluminide (HfAl), or TiAlC (titanium aluminum carbide), but is not limited thereto; if the transistor is a P-type transistor, the work function metal layer 54 can be made of a metal material with a work function of 4.8 eV to 5.2 eV, such as titanium nitride (TiN), tantalum nitride (TaN), or tantalum carbide (TaC), but is not limited thereto. Another barrier layer (not shown) may be included between the work function metal layer 54 and the low impedance metal layer 56. The material of the barrier layer may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc. The low impedance metal layer 56 may be selected from low resistance materials such as copper (Cu), aluminum (Al), tungsten (W), titanium-aluminum alloy (TiAl), cobalt-tungsten phosphide (CoWP), or combinations thereof.

[0048] Next, a portion of the high-dielectric-constant dielectric layer 52, a portion of the work function metal layer 54, and a portion of the low-resistivity metal layer 56 can be removed to form a groove (not shown). Then, a hard mask 58 is filled into the groove, making the hard mask 58 flush with the surface of the interlayer dielectric layer 36. The hard mask 58 can be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride. It should be noted that, in this stage, when etching away a portion of the high-dielectric-constant dielectric layer 52, a portion of the work function metal layer 54, and a portion of the low-resistivity metal layer 56 to form the groove, due to the different material selection ratios, the top surface of the low-resistivity metal layer 56 is preferably slightly higher than the top surfaces of the high-dielectric-constant dielectric layer 52 and the work function metal layer 54.

[0049] Subsequently, as Figure 7As shown, a contact plug fabrication process can be performed to form a contact plug 64 that electrically connects the source / drain regions 30 of the core region 14 and the I / O region 16, respectively, and then a stop layer 66 is formed on the interlayer dielectric layer 36. In this embodiment, the contact plug 64 can be formed by first removing part of the interlayer dielectric layer 36 and part of the contact hole, etching the stop layer 34 to form a contact hole (not shown), and then sequentially depositing a barrier layer (not shown) and a metal layer (not shown) on the substrate 12 to fill the contact hole. Next, a planarization process, such as CMP, is used to remove part of the metal layer, part of the barrier layer, and even part of the interlayer dielectric layer 36 to form the contact plug 64 in the contact hole, and the upper surface of the contact plug 64 is preferably flush with the upper surface of the interlayer dielectric layer 36. In this embodiment, the barrier layer is preferably selected from the group consisting of titanium, tantalum, titanium nitride, tantalum nitride, and tungsten nitride; the metal layer is preferably selected from the group consisting of aluminum, titanium, tantalum, tungsten, niobium, molybdenum, and copper; and the stop layer 66 preferably comprises an oxide such as tetraethyl orthosilicate (TES), but is not limited thereto. This completes the fabrication of a semiconductor device according to an embodiment of the present invention.

[0050] Please continue to refer to Figures 8 to 10 , Figures 8 to 10 This is a schematic diagram illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention. Figure 8 As shown, compared to the aforementioned embodiments where a portion of the spacer wall 28 in the core region 14 is removed by process 72 before the RMG fabrication process or before the gate material layer 26 is hollowed out to form the groove 38, thereby reducing its width, according to other embodiments of the present invention, the outer spacer wall 78 can be directly formed next to the spacer wall 28 without etching to remove part of the inner spacer wall 28, and then the source / drain region 30, the contact hole etch stop layer 34, and the interlayer dielectric layer 36 are formed sequentially. In other words, before the gate material layer 26 is hollowed out to form the groove 38, the spacer wall next to the gate structure 22 has only two widths, wherein the spacer wall 28 located inside the core region 14 and the I / O region 16 both have the same width a, while the outer spacer wall 78 both include a width c.

[0051] Subsequently, as Figure 9 As shown, firstly, etching is used to remove the gate material layer 26 and gate dielectric layer 24 in the gate structure 22 of the core region 14 and I / O region 16 to form a groove 38 in the interlayer dielectric layer 36, forming a patterned mask 74 such as patterned photoresist in the I / O region 16. Then, a processing technology 72 is performed, for example, using wet etching or dry etching with the patterned mask 74 as a mask to remove part of the gap walls 28 of the core region 14, so that the width a of each gap wall 28 of the core region 14 is slightly reduced to width b. From another perspective, although the width of each gap wall of the core region 14 is also reduced from width a to width b in this stage, compared with Figure 2The width of the gap wall 28 is reduced to width b by thinning the outer sidewall of the gap wall 28. In this embodiment, the width of the gap wall 28 is reduced to width b by thinning the inner sidewall of the gap wall 28.

[0052] Then as Figure 10 As shown, it can be compared with Figures 6 to 7 The fabrication process sequentially forms a gate dielectric layer 50, a high dielectric constant dielectric layer 52, a work function metal layer 54, a low impedance metal layer 56, and a hard mask 58 in the grooves 38 of the core region 14 and the I / O region 16. Contact plugs 64 are formed on both sides of the gate structure 22 to connect the source / drain regions 30. Then, a stop layer 66 is formed on the interlayer dielectric layer 36.

[0053] Generally, when fabricating fin-structured field-effect transistors (FETs) with core and I / O regions using current metal gate replacement processes, a thicker gate dielectric layer is formed in the I / O region to match the relatively high voltage of approximately 3.3V. Since both the gate dielectric layer and the innermost spacer walls contain oxygen-containing materials such as silicon oxide, as the thickness of the gate dielectric layer in the I / O region increases, the process of etching away the polysilicon layer during metal gate replacement to form grooves can easily affect the overall gate length (L) of the core region. g To improve this problem, the present invention preferably uses an oxygen-free dielectric material, such as silicon nitride, as the innermost spacer wall 28 closest to the gate electrode or gate structure, and then can be used according to... Figures 1 to 7 In this embodiment, before forming the groove 38, a portion of the gap wall 28 of the core region 14 is removed using a processing technique 72, thereby reducing its thickness or width, or as follows: Figures 8 to 10 In general, after the groove 38 is formed, a portion of the gap wall 28 of the core region 14 is removed using the processing technology 72, thereby adjusting the overall gate length of the subsequent core region. These variations are all within the scope of this invention.

[0054] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, Include: The base includes a core area and input / output areas; A first gate structure is formed in the core region and a second gate structure is formed in the input / output region; A first gap wall is formed next to the first gate structure and a second gap wall is formed next to the second gate structure, wherein the first gap wall and the second gap wall have different widths; as well as A first source / drain region is formed next to the first gap wall, and a second source / drain region is formed next to the second gap wall.

2. The method of claim 1, further comprising: A third gap wall is formed next to the first gap wall and a fourth gap wall is formed next to the second gap wall; An interlayer dielectric layer is formed surrounding the third spacer wall and the fourth spacer wall; Remove the first gate structure and the second gate structure to form a first recess and a second recess; and A first metal gate is formed in the first groove and a second metal gate is formed in the second groove.

3. The method of claim 2 further comprises performing a processing step to remove a portion of the first gap wall before forming the third gap wall and the fourth gap wall.

4. The method of claim 2 further comprises a processing step after forming the first groove and the second groove to remove a portion of the first gap wall.

5. The method of claim 2, wherein the third gap wall and the fourth gap wall have the same width.

6. The method of claim 2, wherein the width of the first gap wall is less than the width of the third gap wall.

7. The method of claim 2, wherein the width of the second gap wall is less than the width of the fourth gap wall.

8. The method of claim 1, wherein the width of the first gap wall is smaller than the width of the second gap wall.

9. The method of claim 1, wherein the first spacer wall and the second spacer wall comprise an oxygen-free compound.

10. A semiconductor element, characterized in that, Include: The base consists of the core area and the input / output area; A first gate structure is disposed in the core region and a second gate structure is disposed in the input / output region; A first gap wall is disposed next to the first gate structure and a second gap wall is disposed next to the second gate structure, wherein the first gap wall and the second gap wall have different widths; as well as The first source / drain region is located next to the first gap wall, and the second source / drain region is located next to the second gap wall.

11. The semiconductor device of claim 10, further comprising: A third gap wall is disposed beside the first gap wall, and a fourth gap wall is disposed beside the second gap wall; and An interlayer dielectric layer surrounds the third spacer wall and the fourth spacer wall.

12. The semiconductor element of claim 11, wherein the third spacer wall and the fourth spacer wall have the same width.

13. The semiconductor element of claim 11, wherein the width of the first gap wall is smaller than the width of the third gap wall.

14. The semiconductor element of claim 11, wherein the width of the second gap wall is smaller than the width of the fourth gap wall.

15. The semiconductor element of claim 10, wherein the width of the first gap wall is smaller than the width of the second gap wall.

16. The semiconductor device of claim 10, wherein the first spacer wall and the second spacer wall comprise an oxygen-free compound.

17. The semiconductor device of claim 10, wherein the first gate structure and the second gate structure comprise a metal gate.

Images