Semiconductor structure and method of forming the same

Abstract

Methods for forming a semiconductor structure are provided. The method includes forming a first transistor over a substrate. The first transistor includes a first plurality of nanostructures extending longitudinally over a first base portion, a first source / drain component located on the first base portion, and a first gate stack extending longitudinally across the first base portion and surrounding the first plurality of nanostructures. The method also includes forming a first contact structure on the first source / drain component, and forming a second contact structure on the first contact structure. The second contact structure extends beyond an edge of the first contact structure. The method also includes removing the substrate, forming a first opening through the first base portion to expose a backside surface of the first source / drain component, and forming a third contact structure in the first opening. Embodiments of the present application also relate to semiconductor structures and methods of forming the same.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor structures and methods of forming the same. Background Technology

[0002] The electronics industry is experiencing a growing demand for smaller and faster electronic devices capable of supporting a greater number of increasingly complex and sophisticated functions. Consequently, there is a persistent trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). To date, these goals have been largely achieved by shrinking the size of semiconductor ICs (e.g., the smallest component size), thereby improving production efficiency and reducing associated costs. However, such miniaturization introduces greater complexity into semiconductor manufacturing processes. Therefore, continued advancements in semiconductor ICs and devices require similar advancements in semiconductor manufacturing processes and technologies.

[0003] Recently, multi-gate devices have been introduced in an attempt to improve gate control by increasing gate-channel coupling, reducing off-state current, and mitigating short-channel effect (SCE). One such multi-gate device that has been introduced is the gate-all-around transistor (GAA). GAA devices are named for their gate structure, which extends around the channel region and provides access to the channel on both sides or all four sides. GAA devices are compatible with associated complementary metal-oxide-semiconductor (CMOS) processes, and their structure allows them to be significantly miniaturized while maintaining gate control and mitigating SCE. GAA devices provide the channel within silicon nanowires / nanosheets. However, fabricating GAA components integrated around nanowires / nanosheets can be challenging. For example, while current methods are satisfactory in many respects, further improvements are still needed. Summary of the Invention

[0004] Some embodiments of this application provide a method for forming a semiconductor structure, comprising: forming a first transistor over a substrate, wherein the first transistor includes a first plurality of nanostructures extending longitudinally over a first substrate portion along a first direction, a first source / drain component located on the first substrate portion, and a first gate stack extending longitudinally across the first substrate portion along a second direction and surrounding the first plurality of nanostructures, wherein the second direction is different from the first direction; forming a first contact structure on the first source / drain component, wherein the conductivity of the first contact structure is greater than the conductivity of the first source / drain component; forming a second contact structure on the first contact structure, wherein the second contact structure extends beyond the edge of the first contact structure; removing the substrate; forming a first opening through the first substrate portion to expose a back surface of the first source / drain component; and forming a third contact structure in the first opening, wherein, in a cross-sectional view, the third contact structure is narrower than the first contact structure.

[0005] Other embodiments of this application provide a method for forming a semiconductor structure, comprising: forming a plurality of active regions over a substrate, wherein each of the active regions includes a substrate portion and a nanostructure stacked over the substrate portion, and the plurality of active regions extend longitudinally along a first direction; forming an isolation structure adjacent to the substrate portion of the plurality of active regions; forming a plurality of source / drain components on the substrate portion of the active regions, wherein each source / drain component includes a portion suspended above the isolation structure; and forming a plurality of gate stacks across the substrate portion of the plurality of active regions to surround the nanostructure of the active regions; A plurality of front contact structures are formed on the source / drain components; an interlayer dielectric layer is formed above the contact structures; the interlayer dielectric layer is etched to form a trench, wherein the trench extends longitudinally along the first direction and is located between a first active region and a second active region in the plurality of active regions, and the trench exposes the first front contact structure and the second front contact structure in the plurality of front contact structures; a conductive material is formed in the trench; and a metal line is formed below the substrate portion of the first active region and the second active region, wherein the metal line is electrically connected to the first front contact structure, the second front contact structure and the conductive material.

[0006] Some embodiments of this application provide a semiconductor structure, including: a first plurality of nanostructures located above a first substrate portion; a gate stack enclosing the first plurality of nanostructures; a first source / drain component adjacent to a first side of the first plurality of nanostructures; a contact etch stop layer covering the first source / drain component; an interlayer dielectric layer located above the contact etch stop layer, wherein the dielectric constant of the contact etch stop layer is different from the dielectric constant of the interlayer dielectric layer; and a first first-level contact structure located on the front surface of the first source / drain component, wherein the first first-level contact structure is electrically coupled to the first source / drain component through a silicide layer. The device includes a source / drain component, wherein the conductivity of the silicide layer is between the conductivity of the first first-level contact structure and the conductivity of the first source / drain component; a first second-level contact structure located on the first first-level contact structure, wherein, in a top view, the first second-level contact structure includes a first portion located inside the first first-level contact structure and a second portion located outside the first first-level contact structure; and a first back-side contact structure located on the back-side surface of the first source / drain component, wherein the first back-side contact structure vertically overlaps the first first-level contact structure and the first second-level contact structure. Attached Figure Description

[0007] Various aspects of the embodiments of this disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] Figure 1 This is a perspective view of a semiconductor structure according to some embodiments of the present disclosure.

[0009] Figure 2A-1 , Figure 2A-2 and Figure 2A-3 This is a schematic diagram illustrating the formation of a semiconductor structure at various intermediate stages according to some embodiments of the present disclosure.

[0010] Figure 2B-1 , Figure 2B-2 and Figure 2B-3 This is a schematic diagram illustrating the formation of a semiconductor structure at various intermediate stages according to some embodiments of the present disclosure.

[0011] Figure 2C-1 , Figure 2C-2 , Figure 2C-3 and Figure 2C-4 This is a schematic diagram illustrating the formation of a semiconductor structure at various intermediate stages according to some embodiments of the present disclosure.

[0012] Figure 2D-1 , Figure 2D-2 and Figure 2D-3 This is a schematic diagram illustrating the formation of a semiconductor structure at various intermediate stages according to some embodiments of the present disclosure.

[0013] Figure 2E-1 , Figure 2E-2 and Figure 2E-3 This is a schematic diagram illustrating the formation of a semiconductor structure at various intermediate stages according to some embodiments of the present disclosure.

[0014] Figure 2F-1 and Figure 2F-2 This is a schematic diagram illustrating the formation of a semiconductor structure at various intermediate stages according to some embodiments of the present disclosure.

[0015] Figure 2G-1 , Figure 2G-2 and Figure 2G-3 This is a schematic diagram illustrating the formation of a semiconductor structure at various intermediate stages according to some embodiments of the present disclosure.

[0016] Figure 2H This is a schematic diagram illustrating the formation of a semiconductor structure at various intermediate stages according to some embodiments of the present disclosure.

[0017] Figure 2I This is a schematic diagram illustrating the formation of a semiconductor structure at various intermediate stages according to some embodiments of the present disclosure.

[0018] Figure 2J This is a schematic diagram illustrating the formation of a semiconductor structure at various intermediate stages according to some embodiments of the present disclosure.

[0019] Figure 2K This is a schematic diagram illustrating the formation of a semiconductor structure at various intermediate stages according to some embodiments of the present disclosure.

[0020] Figure 2L This is a schematic diagram illustrating the formation of a semiconductor structure at various intermediate stages according to some embodiments of the present disclosure.

[0021] Figure 2M This is a schematic diagram illustrating the formation of a semiconductor structure at various intermediate stages according to some embodiments of the present disclosure.

[0022] Figure 2N-1 , Figure 2N-2 , Figure 2N-3 , Figure 2N-4 and Figure 2N-5 This is a schematic diagram illustrating the formation of a semiconductor structure at various intermediate stages according to some embodiments of the present disclosure.

[0023] Figure 3-1 , Figure 3-2 and Figure 3-3 This is a schematic diagram illustrating a semiconductor structure according to some embodiments of the present disclosure.

[0024] Figure 4-1 and Figure 4-2 This is a schematic diagram illustrating a semiconductor structure according to some embodiments of the present disclosure.

[0025] Figure 5-1 , Figure 5-2 and Figure 5-3 This is a schematic diagram illustrating a semiconductor structure according to some embodiments of the present disclosure.

[0026] Figure 6 This is a schematic diagram illustrating a semiconductor structure according to some embodiments of the present disclosure.

[0027] Figure 7-1 , Figure 7-2 and Figure 7-3 This is a schematic diagram illustrating a semiconductor structure according to some embodiments of the present disclosure.

[0028] Figure 8-1 and Figure 8-2 This is a schematic diagram illustrating a semiconductor structure according to some embodiments of the present disclosure.

[0029] Figure 9 This is a schematic diagram illustrating a semiconductor structure according to some embodiments of the present disclosure.

[0030] Figure 10A This is a schematic diagram illustrating the formation of a semiconductor structure at various intermediate stages according to some embodiments of the present disclosure.

[0031] Figure 10B This is a schematic diagram illustrating the formation of a semiconductor structure at various intermediate stages according to some embodiments of the present disclosure.

[0032] Figure 10C This is a schematic diagram illustrating the formation of a semiconductor structure at various intermediate stages according to some embodiments of the present disclosure.

[0033] Figure 10D-1 and Figure 10D-2 This is a schematic diagram illustrating the formation of a semiconductor structure at various intermediate stages according to some embodiments of the present disclosure.

[0034] Figure 10E This is a schematic diagram illustrating the formation of a semiconductor structure at various intermediate stages according to some embodiments of the present disclosure.

[0035] Figure 10FThis is a schematic diagram illustrating the formation of a semiconductor structure at various intermediate stages according to some embodiments of the present disclosure.

[0036] Figure 10G This is a schematic diagram illustrating the formation of a semiconductor structure at various intermediate stages according to some embodiments of the present disclosure.

[0037] Figure 10H This is a schematic diagram illustrating the formation of a semiconductor structure at various intermediate stages according to some embodiments of the present disclosure.

[0038] Figure 10I-1 , Figure 10I-2 , Figure 10I-3 , Figure 10I-4 and Figure 10I-5 This is a schematic diagram illustrating the formation of a semiconductor structure at various intermediate stages according to some embodiments of the present disclosure.

[0039] Figure 11-1 and Figure 11-2 This is a schematic diagram illustrating a semiconductor structure according to some embodiments of the present disclosure.

[0040] Figure 12-1 , Figure 12-2 and Figure 12-3 This is a schematic diagram illustrating a semiconductor structure according to some embodiments of the present disclosure.

[0041] Figure 13 This is a schematic diagram illustrating a semiconductor structure according to some embodiments of the present disclosure. Detailed Implementation

[0042] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of embodiments of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0043] Some variations of the embodiments are described. Throughout the various views and illustrative embodiments, the same reference numerals are used to denote the same elements. It should be understood that additional operations may be provided before, during, and after the method, and some of the described operations may be replaced or eliminated for other embodiments of the method.

[0044] The nanostructure transistors described below (e.g., nanosheet transistors, nanowire transistors, multi-bridge channel transistors, nanoribbon FETs, gate-all-around (GAA) transistor structures) can be patterned using any suitable method. For example, the structure can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, thereby allowing the creation of patterns with pitches, for example, smaller than those achievable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern a GAA structure.

[0045] Embodiments of this disclosure relate to semiconductor structures having a back-side power rail architecture and methods for forming the semiconductor structure. In some embodiments, the semiconductor structure includes a two-level contact structure, wherein the source terminals of circuits in a cell region are electrically connected to a front-side power rail via a first-level contact structure and a second-level contact structure on the first-level contact structure. Therefore, the mask pattern for the photolithography process used to form the first-level contact structure can be moved rearward toward the cell region. The spacing between the mask patterns can be increased, and the process window for the photolithography process can be widened. Thus, a good balance can be achieved between the layout design and the process window for the photolithography process.

[0046] Furthermore, in some embodiments of this disclosure, the semiconductor structure includes a second type of contact structure adjacent to the sidewalls of two or more first type of contact structures to electrically connect the two or more first type of contact structures to each other. Therefore, the second type of contact structure can be used as a front-side power rail to replace the front-side power supply. This can reduce the density and / or complexity of the front-side metal wiring, and thus enable continuous miniaturization of semiconductor devices and improve their performance.

[0047] Figure 1 This is a perspective view of a semiconductor structure 100 according to some embodiments of the present disclosure. According to some embodiments, the semiconductor structure 100 includes a substrate 102 and a fin structure 104 above the substrate 102, such as... Figure 1 As shown in the figure. According to some embodiments, substrate 102 includes a p-type well PW and an n-type well NW closely adjacent to the p-type well PW. According to some embodiments, fin structure 104N is formed in the p-type well PW of substrate 102, and fin structure 104P is formed in the n-type well NW of substrate 102. According to some embodiments, fin structures 104N and 104P are active regions of semiconductor structure 100.

[0048] To better understand the semiconductor structure 100, XYZ coordinate references are provided in the accompanying drawings of embodiments of this disclosure. The X and Y axes are generally oriented in a lateral (or horizontal) direction parallel to the main surface of the substrate 102. The Y axis is lateral (e.g., substantially perpendicular) to the X axis. The Z axis is generally oriented in a vertical direction perpendicular to the main surface (or XY plane) of the substrate 102.

[0049] Figure 1 This is a perspective view of a semiconductor structure 100 according to some embodiments of the present disclosure. According to some embodiments, the semiconductor structure 100 includes a substrate 102 and a fin structure 104 above the substrate 102, such as... Figure 1 As shown in the figure. According to some embodiments, fin structure 104 is an active region of semiconductor structure 100. To better understand semiconductor structure 100, XYZ coordinate references are provided in the drawings of embodiments of this disclosure. The X and Y axes are generally oriented in a lateral (or horizontal) direction parallel to the main surface of substrate 102. The Y axis is lateral (e.g., substantially perpendicular) to the X axis. The Z axis is generally oriented in a vertical direction. The vertical direction is perpendicular to the main surface of substrate 102 (or the XY plane).

[0050] According to some embodiments, the fin structure 104 includes a lower fin element 103 formed from a substrate 102. In some embodiments, the lower fin element 103 is a protrusion of the substrate 102 and also serves as a base portion of the fin structure 104. According to some embodiments, the lower fin element 103 is surrounded by an isolation structure 110. According to some embodiments, the fin structure 104 also includes an upper fin element formed from an epitaxial stack comprising alternating first semiconductor layers 106 and second semiconductor layers 108. According to some embodiments, the second semiconductor layer 108 will form a nanostructure (e.g., nanowire or nanosheet) and serve as a channel for the resulting semiconductor device.

[0051] According to some embodiments, the fin structure 104 extends in the X direction. That is, according to some embodiments, the fin structure 104 has a longitudinal axis parallel to the X direction. The X direction can also be referred to as the channel extension direction. Current in the resulting semiconductor device (i.e., nanostructure transistor) flows through the channel in the X direction. According to some embodiments, the fin structure 104 is defined as a plurality of channel regions and a plurality of source / drain regions, wherein the channel regions and source / drain regions are arranged alternately. It should be noted that in embodiments of this disclosure, source / drain regions or source / drain components may refer to a source or a drain, individually or collectively, depending on the context.

[0052] According to some embodiments, the gate structure 112 is formed having a longitudinal axis parallel to the Y direction and extending across and / or surrounding the channel region of the fin structure 104. According to some embodiments, the source / drain regions of the fin structure 104 are exposed from the gate structure 112. The Y direction can also be referred to as the gate wiring direction. Although in Figure 1 A fin structure 104 is shown, but the semiconductor structure 100 may include more than one fin structure 104. Furthermore, Figure 1 Three gate structures 112 (or channel regions) are shown for illustrative purposes and are not intended to be limiting. The number of fin structures and gate structures may depend on the design requirements of the integrated circuit and / or the performance considerations of the semiconductor device.

[0053] Figure 1 Reference cross sections used in later figures are also shown. Cross section XX lies in a plane parallel to the longitudinal axis (i.e., the X direction) of fin structure 104 and passes through fin structure 104. Cross section Y1-Y1 lies in a plane parallel to the longitudinal axis (i.e., the Y direction) of gate structure 104 and spans the source / drain regions of fin structure 104. Cross section Y2-Y2 lies in a plane parallel to the longitudinal axis (i.e., the Y direction) of gate structure 112 and passes through one of the gate structures 112.

[0054] Figures 2A-1 to 2N-5 The semiconductor structure 100 is shown being formed at various intermediate stages according to some embodiments of the present disclosure. Figure 2A-1 , Figure 2A-2 , Figure 2A-3 The semiconductor structure 100, after forming the active regions 104N1, 104N2, and 104P1, the isolation structure 110, the STI capping layer 111, the dummy gate structure 112, the gate spacer layer 118, and the fin spacer layer 119, respectively corresponds to Figure 1 Cross-sectional views of lines XX, Y1-Y1, and Y2-Y2. According to some embodiments, a substrate 102 is provided, such as... Figures 2A-1 to 2A-3As shown in the figure. Substrate 102 may be a portion of a semiconductor wafer, semiconductor chip (or die), etc. In some embodiments, substrate 102 is a silicon substrate. In some embodiments, substrate 102 includes: elemental semiconductors, such as germanium; compound semiconductors, such as gallium nitride (GaN), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); alloy semiconductors, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Furthermore, substrate 102 may optionally include an epitaxial layer (epi layer), which may be strained for performance enhancement, may include a silicon-on-insulator (SOI) structure, and / or have other suitable enhancement components.

[0055] According to some embodiments, an n-type dopant (such as phosphorus or arsenic) may be implanted into the substrate 102 to form an n-type well (not shown). According to some embodiments, a p-type dopant (such as boron or BF2) may be implanted into the substrate 102 to form a p-type well (not shown). In some embodiments, the ion implantation process may be performed several times with different doses and different energy intensities. In some embodiments, the ion implantation process may include punch-through (APT) implantation.

[0056] According to some embodiments, active regions 104N1 and 104N2 (collectively referred to as 104N) and active region 104P1 are formed above substrate 102, such as Figures 2A-1 to 2A-3 As shown in the diagram, active regions 104N1 and 104N2 are formed in a p-type well, and active region 104P1 is formed in an n-type well. Although the embodiment shows one active region formed in the n-type well, two active regions can be formed in the n-type well and are collectively referred to as 104P. In some embodiments, active regions 104N1, 104N2, and 104P1 extend in the X direction. According to some embodiments, the formation of active regions 104N1, 104N2, and 104P1 includes forming an epitaxial stack over a substrate 102 using an epitaxial growth process. According to some embodiments, the epitaxial stack includes alternating first semiconductor layers 106 and second semiconductor layers 108. The epitaxial growth process can be molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), or vapor phase epitaxy (VPE) or another suitable technique.

[0057] In some embodiments, the first semiconductor layer 106 is made of a first semiconductor material, and the second semiconductor layer 108 is made of a second semiconductor material. According to some embodiments, the first semiconductor material used for the first semiconductor layer 106 has a different lattice constant than the second semiconductor material used for the second semiconductor layer 108. In some embodiments, the first semiconductor material and the second semiconductor material have different oxidation rates and / or etch selectivity. In some embodiments, the first semiconductor layer 106 is made of SiGe, wherein the percentage of germanium (Ge) in SiGe is in the range of about 20 atomic% to about 50 atomic%, and the second semiconductor layer 108 is made of pure or substantially pure silicon. In some embodiments, the first semiconductor layer 106 is Si... 1-x Ge x (where x is greater than approximately 0.3) or Ge (x = 1.0), and the second semiconductor layer 108 is Si or Si 1-y Ge y , where y is less than approximately 0.4 and x > y.

[0058] According to some embodiments, a first semiconductor layer 106 is configured as a sacrificial layer and is removed to form a gap for accommodating gate material, and a second semiconductor layer 108 is formed to create a nanostructure (e.g., nanowire or nanosheet) extending laterally between source / drain components and serves as a channel for the resulting semiconductor device (such as a nanostructured transistor). According to some embodiments, the formation of active regions 104N1, 104N2, and 104P1 further includes patterning the epitaxial stack and the underlying well using photolithography and etching processes to form trenches and active regions 104N1, 104N2, and 104P1 protruding from between the trenches. According to some embodiments, a p-type well protruding from between the trenches forms the lower fin element 103P of active regions 104N1 and 104N2, and an n-type well protruding from between the trenches forms the lower fin element 103N of active region 104P1. According to some embodiments, the remaining portion of the epitaxial stack (including semiconductor layers 106 and 108) forms the upper fin elements of the active regions 104N and 104P.

[0059] In some embodiments, the thickness of each of the first semiconductor layers 106 is in the range of about 3 nm to about 20 nm. In some embodiments, the thickness of each of the second semiconductor layers 108 is in the range of about 3 nm to about 20 nm. The thickness of the second semiconductor layer 108 may be greater than, equal to, or less than the first semiconductor layer 106, depending on the amount of gate material to be filled into the gaps formed at the locations where the first semiconductor layer 106 is removed. Although in Figures 2A-1 to 2A-3 The diagram shows three first semiconductor layers 106 and three second semiconductor layers 108, but the number is not limited to three, and can be two or four, and less than 10.

[0060] According to some embodiments, an isolation structure 110 is formed to surround the lower fin elements 103N and 103P of the active regions 104N1, 104N2 and 104P1, such as Figure 2A-2 and Figure 2A-3 As shown in the diagram. According to some embodiments, the isolation structure 110 is configured to electrically isolate the active regions 104N and 104P from each other, and is also referred to as a shallow trench isolation (STI) component. In some embodiments, the isolation structure 110 has a substantially flat top surface. In some other embodiments, the isolation structure 110 has a curved top surface.

[0061] According to some embodiments, the formation of the isolation structure 110 includes forming an insulating material to overfill the trench. In some embodiments, the insulating material is made of silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), oxygen-doped silicon carbide (SiC:O), oxygen-doped silicon carbonitride (Si(O)CN), or combinations thereof. In some embodiments, the insulating material is deposited using CVD (such as flowable CVD (FCVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), high-density plasma CVD (HDP-CVD), or high aspect ratio process (HARP)), atomic layer deposition (ALD), another suitable technique, or combinations thereof.

[0062] According to some embodiments, a planarization process (e.g., chemical mechanical polishing (CMP), etching back, or a combination thereof) is performed on the insulating material. According to some embodiments, the insulating material is then recessed by an etching process (such as dry plasma etching and / or wet chemical etching) until the upper fin elements of the active regions 104N1, 104N2, and 104P1 are exposed. According to some embodiments, the top portions of the lower fin elements 103N and 103P may be further exposed from the isolation structure 110.

[0063] According to some embodiments, an STI cover layer 111 may optionally be formed on the upper surface of the isolation structure 110, such as... Figure 2A-2 and Figure 2A-3As shown in the diagram, the STI capping layer 111 is made of a dielectric material such as silicon nitride (SiN), silicon oxide (SiO2), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), and / or oxygen-doped silicon carbonitride (Si(O)CN). The STI capping layer 111 and the isolation structure 110 are made of different materials and have significant differences in etch selectivity. For example, the isolation structure 110 is made of silicon oxide (SiO), and the STI capping layer 111 is made of silicon nitride (SiN). According to some embodiments, the formation of the STI capping layer 111 includes globally and conformally depositing a dielectric material over the semiconductor structure 100 using ALD, CVD (such as LPCVD, PECVD, or HDP-CVD), or a combination thereof, followed by an etching process. According to some embodiments, the top portions of the lower fin elements 103N and 103P of the active regions 104N1, 104N2, and 104P1 can be exposed from the STI capping layer 111.

[0064] According to some embodiments, the dummy gate structure 112 is formed across the active regions 104N1, 104N2, and 104P1 and the STI capping layer 111 (and the underlying isolation structure 110), as... Figure 2A-1 and Figure 2A-3 As shown in the diagram. According to some embodiments, the dummy gate structure 112 is configured as a sacrificial structure and will be replaced by the final gate stack. According to some embodiments, the dummy gate structure 112 surrounds the channel regions of the active regions 104N and 104P.

[0065] According to some embodiments, the dummy gate structure 112 includes a dummy gate dielectric layer 114 and a dummy gate electrode layer 116 above the dummy gate dielectric layer 114. In some embodiments, the dummy gate dielectric layer 114 is conformally formed along the upper fin of the active region 104 using ALD, CVD, thermal oxidation, physical vapor deposition (PVD), another suitable technique, or a combination thereof. In some embodiments, the dummy gate dielectric layer 114 is made of one or more dielectric materials, such as silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), HfO2, HfZrO, HfSiO, HfTiO, and HfAlO. In some embodiments, the dummy gate electrode layer 116 is made of a semiconductor material such as polycrystalline silicon or polycrystalline silicon germanium. In some embodiments, the material for the dummy gate electrode layer 116 is deposited using CVD, ALD, another suitable technique, or a combination thereof. Once the material for the dummy gate electrode layer 116 is deposited, the material for the dummy gate electrode layer 116 is planarized, and the material for the dummy gate electrode layer 116 and the dielectric material are patterned into the dummy gate structure 112 using photolithography and etching processes.

[0066] According to some embodiments, a gate spacer layer 118 is formed along the opposite sidewalls of the dummy gate structure 112, and a fin spacer layer 119 is formed along the opposite sidewalls of the active regions 104N and 104P, such as... Figure 2A-1 and Figure 2A-2 As shown in the diagram. According to some embodiments, the gate spacer layer 118 is used to offset subsequently formed source / drain components and to separate the source / drain components from the gate structure. In some embodiments, the gate spacer layer 118 and the fin spacer layer 119 are formed of one or more continuous dielectric materials. For example, in some embodiments, the formation of the gate spacer layer 118 and the fin spacer layer 119 includes globally and conformally depositing dielectric material over the semiconductor structure 100 using ALD, CVD (such as LPCVD, PECVD, or HDP-CVD), or a combination thereof, followed by a subsequent anisotropic etching process.

[0067] In some embodiments, the dielectric material may be silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), oxygen-doped silicon carbide (SiC:O), oxygen-doped silicon carbonitride (Si(O)CN), silicon carbide (SiC), or another suitable dielectric material. In some embodiments, the gate spacer layer 118 may include an air gap and / or a porous form of the aforementioned dielectric material. According to some embodiments, after an anisotropic etching process, the vertical portions of the dielectric material retained on opposite sides of the dummy gate structure 112 form the gate spacer layer 118, while the vertical portions of the dielectric material retained on opposite sides of the active regions 104N1, 104N2, and 104P1 form the fin spacer layer 119.

[0068] Figure 2B-1 , Figure 2B-2 , Figure 2B-3 The semiconductor structure 100, after forming the internal spacer layer 122, the intermediate components 123 and 124, the source / drain components 126N and 126P, the contact etch stop layer (CESL) 128, the first interlayer dielectric (ILD) layer 130, and the ILD capping layer 132, respectively corresponds to Figure 1 Cross-sectional views of lines XX, Y1-Y1, and Y2-Y2.

[0069] According to some embodiments, a source / drain component 126N is formed in and / or above the source / drain region of the active region 104N, and a source / drain component 126P is formed in and / or above the source / drain region of the active region 104P1, such as... Figure 2B-1 and Figure 2B-2As shown in the diagram. According to some embodiments, the formation of source / drain components 126N and 126P includes recessing the source / drain regions of active regions 104N and 104P1 using a dummy gate structure 112 and a gate spacer layer 118 as a mask to form source / drain recesses SDRs (indicated by dashed lines) on opposite sides of the dummy gate structure 112. According to some embodiments, the source / drain recesses SDRs may extend into the lower fin elements 103P and 103N. In some embodiments, the recessing process includes anisotropic etching processes such as dry plasma etching, isotropic etching processes such as dry chemical etching, remote plasma etching, or wet chemical etching, or combinations thereof.

[0070] According to some embodiments, during the etching process, the STI capping layer 111 and the isolation structure 110 are also recessed to form an STI groove STR, such as... Figure 2B-2 As shown in the diagram. During the etching process, the STI capping layer 111 prevents the isolation structure 110 from being excessively recessed, and thus prevents the lower fin elements 103P and 103N from being exposed from the STI recess STR. In some embodiments, the bottom of the STI recess STR extends downward to a depth deeper than the bottom of the source / drain recess. Furthermore, the fin spacer layer 119 is also recessed during the etching process. In some other embodiments, the isolation structure 110 may not be recessed during the etching process.

[0071] Subsequently, according to some embodiments, an etching process is performed to laterally recess the first semiconductor layer 106 of the active region 104 from the source / drain trench, thereby forming a groove, and then an inner spacer layer 122 is formed in the groove, such as Figure 2B-1 As shown in the diagram. According to some embodiments, the inner spacer layer 122 is adjacent to the recessed side of the first semiconductor layer 106. According to some embodiments, the inner spacer layer 122 can prevent direct contact between the source / drain components and the gate stack, and is configured to reduce the parasitic capacitance between the gate stack and the source / drain components.

[0072] In some embodiments, the internal spacer layer 122 is made of a dielectric material such as silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbonitride oxynitride (SiOCN), oxygen-doped silicon carbonitride (Si(O)CN), and / or combinations thereof. In some embodiments, the internal spacer layer 122 may include air gaps and / or a porous form of the aforementioned dielectric material. In some embodiments, the internal spacer layer 122 is made of a different material than the gate spacer layer 118. In some embodiments, the internal spacer layer 122 is formed by depositing dielectric material to fill the trench using ALD, CVD (such as PECVD, LPCVD, or HARP), another suitable technique, or a combination thereof, and then etching away the dielectric material outside the trench using an anisotropic etching process such as dry plasma etching, an isotropic etching process such as dry chemical etching, remote plasma etching, or wet chemical etching, or a combination thereof.

[0073] According to some embodiments, intermediate members 123 and 124 are optionally formed in the source / drain grooves SDR on the lower fin elements 103N and 103P, such as Figure 2B-1 and Figure 2B-2 As shown in the figure. In some embodiments, the first interposer 123 is made of an epitaxial semiconductor material such as silicon, silicon-germanium, or germanium, and is formed by MBE, MOCVD, or VPE, another suitable technique, or a combination thereof. In an embodiment, the first interposer 123 is made of undoped silicon. In some embodiments, the exposed top surfaces of the lower fin elements 103P and 103N are covered by the first interposer 123. In some embodiments, a second interposer 124 is formed on the first interposer 123 and does not cover the sidewalls of the bottommost second semiconductor layer 108. In some embodiments, the second interposer 124 is made of a dielectric material such as silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbonitride oxynitride (SiOCN), and / or oxygen-doped silicon carbonitride (Si(O)CN). In some embodiments, the second interposer 124 is formed using a deposition process and a subsequent etch-back process. In some other embodiments, the second intermediate component 124 is formed only above the lower fin element 103P (i.e., in the p-type well), but not on the lower fin element 103N (i.e., in the n-type well), which can increase the volume of the subsequently formed p-type source / drain component.

[0074] According to some embodiments, source / drain components 126N are grown from the exposed side of the second semiconductor layer 108 in the p-type well, and source / drain components 126P are grown from the exposed side of the second semiconductor layer 108 in the n-type well, using one or more epitaxial growth processes. Figure 2B-1 and Figure 2B-2 As shown in the diagram. The epitaxial growth process can be MBE, MOCVD, or VPE, or another suitable technique. According to some embodiments, source / drain components 126N and 126P fill the source / drain recess SDR. According to some embodiments, source / drain components 126N and 126P are located on dielectric interposer 124 and adjacent to the second semiconductor layer 108 and the internal spacer layer 122.

[0075] In some embodiments, the thickness (i.e., the dimension in the Z direction) of the source / drain components 126N and 126P differs from the width (i.e., the dimension in the Y direction) of the source / drain components 126N and 126P, such as... Figure 2B-2 As shown in the figure. In some embodiments, the widths of the source / drain components 126N and 126P are greater than the widths of the lower fin elements 103P and 103N, such that portions of the source / drain components 126N and 126P are suspended above the fin spacer layer 119 and the isolation structure 110.

[0076] In some embodiments, source / drain components 126N and 126P can be formed separately. For example, a patterned mask layer (such as a photoresist layer and / or a hard mask layer) is formed to cover the semiconductor structure 100 above the p-type well, and then the source / drain component 126P is grown. The patterned mask layer can then be removed. Similarly, a patterned mask layer (such as a photoresist layer and / or a hard mask layer) can be formed to cover the semiconductor structure 100 above the n-type well, and then the source / drain component 126N is grown. The patterned mask layer can then be removed. In some embodiments, source / drain components 126N and 126P are doped in situ during the epitaxial process.

[0077] In some embodiments, the source / drain component 126N is doped with an n-type dopant during the epitaxial growth process. For example, the n-type dopant may be phosphorus (P) or arsenic (As). For instance, the source / drain component 126N may be epitaxially grown Si doped with phosphorus to form a silicon:phosphorus (Si:P) source / drain component and / or doped with arsenic to form a silicon:arsenic (Si:As) source / drain component. In some embodiments, the concentration of the dopant (e.g., P) in the source / drain component 126N is from about 2 × 10⁻⁶. 19 / cm -3 Approximately 3×10 21 / cm -3 Within the range.

[0078] The source / drain component 126P is made of a semiconductor material, such as SiGe, Si, GaAs, another suitable semiconductor material, or a combination thereof. In some embodiments, the source / drain component 126P is doped with a p-type dopant during the epitaxial growth process. For example, the p-type dopant may be boron (B) or BF2. For example, the source / drain component 126P may be SiGe epitaxially grown to form a silicon-germanium:boron (SiGe:B) source / drain component. In some embodiments, the concentration of the dopant (e.g., B) in the source / drain component 126P is from about 1 × 10⁻⁶. 19 / cm -3 Approximately 6×10 20 / cm -3 Within the range.

[0079] In some embodiments, each of the source / drain components 126N and 126P may include multiple semiconductor layers with different doping concentrations. For example, a first epitaxial layer with a lower doping concentration of the source / drain component is first grown on the exposed sidewall of the second semiconductor layer 108, and then a second epitaxial layer with a higher doping concentration of the source / drain component is grown on the first epitaxial layer to fill the remaining portion of the source / drain trench SDR. The doping concentration of the second epitaxial layer may be one or two orders of magnitude greater than that of the first epitaxial layer.

[0080] In some embodiments, once the source / drain component 126P is grown, an additional implantation process is performed to re-dop the source / drain component 126P with p-type dopant. Similarly, in some embodiments, once the source / drain component 126N is grown, an additional implantation process is performed to re-dop the source / drain component 126N with n-type dopant. An annealing process (such as RTA) is performed to activate the dopant in the source / drain components 126P and 126N and / or recrystallize the heavily doped regions of the source / drain components 126P and 126N.

[0081] According to some embodiments, a contact etch stop layer 128 is formed over the semiconductor structure 100 to cover the source / drain components 126N and 126P, such as Figure 2B-1 and Figure 2B-2As shown in the figure. In some embodiments, the contact etch stop layer 128 is made of a dielectric material, such as silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), oxygen-doped silicon carbide (SiC:O), oxygen-doped silicon carbonitride (Si(O)CN), silicon carbide (SiC), or another suitable dielectric material. In some embodiments, the contact etch stop layer 128 is globally and conformally deposited using ALD, CVD (such as LPCVD, PECVD, HDP-CVD, and HARP), another suitable method, and / or combinations thereof. In some embodiments, the dielectric constant of the contact etch stop layer 128 is greater than the dielectric constant of the isolation structure 110, the dielectric constant of the gate spacer layer 118, and the dielectric constant of the internal spacer layer 122.

[0082] According to some embodiments, a first interlayer dielectric layer 130 is formed above the contact etch stop layer 128, such as... Figure 2B-1 and Figure 2B-2 As shown in the diagram. According to some embodiments, the first interlayer dielectric layer 130 fills the gaps between the dummy gate structures 112. In some embodiments, the first interlayer dielectric layer 130 is made of a dielectric material, such as undoped silicate glass (USG), doped silicon oxide, such as borosilicate glass (BPSG), fluoride-doped silicate glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG), and / or another suitable dielectric material. In some embodiments, the dielectric constant of the contact etch stop layer 128 is greater than the dielectric constant of the first interlayer dielectric layer 130. In some embodiments, the thickness of the contact etch stop layer 128 along portions of the gate spacer layer 128 and the source / drain components 126N and 126P is less than the thickness (i.e., the dimension in the Z direction) and width (i.e., the dimensions in the X and Y directions) of the first interlayer dielectric layer 130. In some embodiments, the dielectric material for the first interlayer dielectric layer 130 is deposited using techniques such as CVD (e.g., HDP-CVD, PECVD, HARP, or FCVD), another suitable technique, or a combination thereof. According to some embodiments, the dielectric material for the contact etch stop layer 128 and the first interlayer dielectric layer 130 above the top surface of the dummy gate electrode layer 116 is removed using techniques such as CMP.

[0083] According to some embodiments, an etching process is performed to recess the first interlayer dielectric layer 130 to form a trench, thereby exposing the contact etch stop layer 128, and forming an ILD capping layer 132 in the trench, such as... Figure 2B-1 and Figure 2B-2As shown in the diagram. Therefore, the top portion of the first interlayer dielectric layer 130 above the source / drain components 126N and 126P is replaced with an ILD capping layer 132. In some embodiments, the ILD capping layer 132 is made of a dielectric material different from the first interlayer dielectric layer 120, such as silicon nitride (SiN), silicon oxynitride (SiON), oxygen-doped silicon carbonitride (Si(O)CN), or another suitable dielectric material. In some embodiments, the ILD capping layer 132 is formed using a deposition process followed by a planarization process, such as an etching process or a CMP process.

[0084] Figure 2C-1 This is a perspective view of the semiconductor structure 100 after the final gate stack 134 and gate dicing member 140 have been formed, and Figure 2C-2 , Figure 2C-3 , Figure 2C-4 They correspond to respectively Figure 1 The cross-sectional views of lines XX, Y1-Y1, and Y2-Y2 are shown. For simplicity and clarity, intermediate component 124 is shown in... Figure 2C-1 Not shown in the figure. According to some embodiments, one or more etching processes are performed to remove the dummy gate structure 112 to form a gate trench, and to remove the first semiconductor layer 106 of the active regions 104N1, 104N2, and 104P to form a gap. In some embodiments, the gate trench exposes the channel regions of the active regions 104N and 104P. In some embodiments, the gate trench further exposes the sidewalls of the gate spacer layer 118 facing the channel regions. The etching processes include anisotropic etching processes such as dry plasma etching, isotropic etching processes such as dry chemical etching, remote plasma etching, or wet chemical etching, or combinations thereof. According to some embodiments, the inner spacer layer 122 may protect the source / drain components 126N and 126P from damage during the etching process. In some embodiments, the gap also exposes the sidewalls of the inner spacer layer 122 facing the channel regions.

[0085] According to some embodiments, after the etching process, the four main surfaces of the second semiconductor layer 108 are exposed. According to some embodiments, the exposed second semiconductor layer 108 forms a nanostructure 108. According to some embodiments, the nanostructures 108 are vertically stacked above the lower fin elements 103N and 103P and spaced apart from each other. According to some embodiments, the nanostructures 108 serve as the channel layer of the resulting semiconductor device (e.g., a nanostructured transistor such as a GAA transistor).

[0086] According to some embodiments, a final gate stack 134 is formed in the gate trenches and gaps to encapsulate the nanostructure 108, such as... Figure 2C-1 , Figure 2C-2 and Figure 2C-4As shown in the diagram. The final gate stack 134 can join the channel region, allowing current to flow between the source / drain components 126N / 126P during operation. The final gate stack 134 enclosing the nanostructure 108 is combined with the adjacent source / drain components 126N / 126P to form a nanostructure transistor, such as an n-channel nanostructure transistor. Figure 2N-4 and Figure 2N-5 The NMOSFET shown) and p-channel nanostructure transistors ( Figure 2N-4 and Figure 2N-5 (The PMOSFET shown). In some embodiments, the final gate stack 134 extends in the Y direction. That is, according to some embodiments, the final gate stack 134 has a longitudinal axis parallel to the Y direction.

[0087] In some embodiments, each of the final gate stack 134 includes a gate dielectric layer 136 and a metal gate electrode layer 138. In some embodiments, the gate dielectric layer 136 may include an interface layer and a high-k dielectric layer. In some embodiments, the interface layer is formed on the exposed surface of the nanostructure 108 and the exposed top surface of the lower fin elements 103N and 103P. In some embodiments, the interface layer encapsulates the nanostructure 108. In some embodiments, the interface layer is made of chemically formed silicon oxide. In some embodiments, the interface layer is nitrogen-doped silicon oxide. In some embodiments, the interface layer is formed using one or more cleaning processes, such as those including ozone (O3), ammonium hydroxide-hydrogen peroxide-water mixtures, and / or hydrochloric acid-hydrogen peroxide-water mixtures. In some embodiments, semiconductor materials from the nanostructure 108 and the lower fin elements 103N and 103P are oxidized to form the interface layer.

[0088] According to some embodiments, a high-k dielectric layer is conformally formed along the interface layer to encapsulate the nanostructure 108. According to some embodiments, the high-k dielectric layer is also conformally formed along the sidewalls of the gate spacer layer 118 facing the channel region. According to some embodiments, the high-k dielectric layer is also conformally formed along the sidewalls of the inner spacer layer 122 facing the channel region. In some embodiments, the high-k dielectric layer is a dielectric material having a high dielectric constant (k value), for example, greater than 10, such as greater than 20, such as greater than 30. In some embodiments, the high-k dielectric layer comprises hafnium oxide (HfO2), TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, LaO, Al2O3, ZrO, TiO, Ta2O5, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO3 (BST), combinations thereof, or another suitable material. The high-k dielectric layer can be deposited using ALD, PVD, CVD, and / or another suitable technique. In some embodiments, the dielectric constant of the high-k dielectric layer is higher than that of the interface layer. In some embodiments, the dielectric constant of the high-k dielectric layer is higher than that of the gate spacer layer 118 and the inner spacer layer 122. In some embodiments, the dielectric constant of the high-k dielectric layer is at least twice the dielectric constant of the first interlayer dielectric layer 130.

[0089] According to some embodiments, a metal gate electrode layer 138 is formed to overfill the remaining portions of the gate trenches and gaps. In some embodiments, the metal gate electrode layer 138 is made of more than one conductive material, such as metals, metal alloys, conductive metal oxides and / or metal nitrides, another suitable conductive material, and / or combinations thereof. For example, the metal gate electrode layer 138 may be made of Ti, Ag, Al, TiAlN, TiAl, TiAlC, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, WN, Cu, W, Re, Ir, Co, Ni, Pt, another suitable conductive material, or a multilayer thereof. The metal gate electrode layer 138 may be a multilayer structure having a diffusion barrier layer, a work function layer having a selected work function to enhance device performance for an n-channel FET or p-channel FET, a capping layer to prevent oxidation of the work function layer, an adhesive layer, and a metal filler layer or another suitable layer to reduce the total resistance of the gate stack.

[0090] According to some embodiments, a planarization process such as CMP can be performed on the semiconductor structure 100 to remove material from the gate dielectric layer 136, the metal gate electrode layer 138, and the gate spacer layer 118 until the top surface of the ILD capping layer 132 is exposed. According to some embodiments, the top surface of the final gate stack 134 is substantially flush with the top surface of the ILD capping layer 132. According to some embodiments, after forming the final gate stack 134, a gate dicing feature 140 is formed between the active regions 104N1 and 104N2, such as... Figure 2C-1 , Figure 2C-3 and Figure 2C-4 As shown in the diagram. According to some embodiments, the gate dicing member 140 penetrates the final gate stack 134, the gate spacer layer 118, the ILD capping layer 132, the contact etch stop layer 128, and the first interlayer dielectric layer 130, and enters the isolation structure 110. According to some embodiments, the gate dicing member 140 extends in the X direction, cutting the final gate stack 134 into several segments that are physically and electrically isolated from each other.

[0091] The gate dicing member 140 may also be referred to as a diced metal gate (CMG) pattern. In some embodiments, the gate dicing member 140 is configured to define the boundaries of cell regions of the semiconductor structure 100. For example, according to some embodiments, the semiconductor structure 100 (or substrate 102) is defined as or includes a plurality of cell regions, such as a first cell region C1 and a second cell region C2. According to some embodiments, interconnected circuits are formed in the respective cell regions to form an integrated circuit. In some embodiments, the gate dicing member 140 corresponds to or overlaps with the boundaries of cell regions C2 and C1. In some embodiments, cell regions C1 and C2 are logic cells.

[0092] The gate dicing component 140 is made of a dielectric material, such as silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbonitride oxynitride (SiOCN), oxygen-doped silicon carbonitride (Si(O)CN), silicon oxide (SiO2), or combinations thereof. In some embodiments, the gate dicing component 140 comprises a dielectric material having a dielectric constant greater than 7.9, such as LaO, AlO, AlON, ZrO, HfO, ZnO, ZrN, ZrAlO, TiO, TaO, YO, TaCN, or combinations thereof. According to some embodiments, the formation of the gate dicing component 140 includes: patterning the semiconductor structure 100 using photolithography and etching processes to form a gate dicing opening; and depositing a dielectric material to overfill the gate dicing opening. In some embodiments, the gate dicing component 140 includes a dielectric filling layer 142 along the gate dicing opening and a dielectric filling layer 144 located on the dielectric filling layer 142 in the gate dicing opening. In some embodiments, the gate dicing component 140 may be a single-layer structure. According to some embodiments, a planarization process (e.g., CMP, etch-back process, or a combination thereof) is then performed on the dielectric material until the final gate stack 134 is exposed.

[0093] Figures 2D-1 to 2I The formation of the front contact structure is shown. Figure 2D-1 This is a top view of the semiconductor structure 100 after the formation of the mask layer 146 and the first patterned mask layer 148, and Figure 2D-2 and Figure 2D-3 They correspond to respectively Figure 1 or Figure 2D-1 Cross-sectional views of line XX and line Y1-Y1. Figure 2D-1 An active region 104P2 formed in an n-type well in the first unit region C1 is also shown. According to some embodiments, active regions 104N1 and 104N2 are located between active regions 104P1 and 104P2 (collectively referred to as 104P).

[0094] According to some embodiments, a mask layer 146 is formed over the semiconductor structure 100, such as... Figure 2D-2 and Figure 2D-3 As shown in the figure. In some embodiments, the mask layer is made of a dielectric material, such as silicon, silicon oxide, silicon nitride, silicon oxynitride, and / or another suitable material. According to some embodiments, a first patterned mask layer 148 is formed over the semiconductor structure 100, as shown in the figure. Figure 2D-1 , Figure 2D-2 and Figure 2D-3As shown in the diagram. According to some embodiments, the first patterned mask layer 148 has a trench pattern 150 between the final gate stack 134. According to some embodiments, the trench pattern 150 extends along the Y direction and extends across the source / drain regions of the active regions 104P1, 104N1, 104N2, and 104P2. The trench pattern 150 may also be referred to as a line MD (metal on drain) pattern.

[0095] In some embodiments, the first patterned mask layer 148 is a patterned photoresist layer. For example, the photoresist is formed by spin coating and then patterned to have a trench pattern 150 by exposing it to light using a suitable photomask (or intermediate mask). Exposed or unexposed portions of the photoresist can be removed, depending on whether a positive or negative resist is used. In alternative embodiments, a hard mask layer (not shown) can be formed on the semiconductor structure 100. The hard mask layer can include silicon, silicon oxide, silicon nitride, and / or another suitable material, or be formed from silicon, silicon oxide, silicon nitride, and / or another suitable material. The hard mask layer can be etched using a patterned photoresist layer, which can be formed by photolithography as described above, to have the trench pattern 150.

[0096] Figure 2E-1 This is a top view of the semiconductor structure 100 after the formation of the second patterned mask layer 152, and Figure 2E-2 and Figure 2E-3 They correspond to respectively Figure 1 or Figure 2E-1 The cross-sectional views of lines XX and Y1-Y1. According to some embodiments, a second patterned mask layer 152 is formed above the first patterned mask layer 148, such as... Figure 2E-1 , Figure 2E-2 and Figure 2E-3 As shown in the diagram. According to some embodiments, the second patterned mask layer 152 includes mask patterns located between active regions 104P1 and 104N2, between active regions 104N2 and 104N1, and between 104N1 and 104P2, respectively. According to some embodiments, the mask pattern extends along the X direction and across the trench pattern 150 (i.e., a line MD pattern). The mask pattern may also be referred to as a cut MD pattern. According to some embodiments, the line MD pattern ( Figures 2D-1 to 2D-3 150) is divided into MD pattern 151 by cutting MD pattern 152, and MD pattern 151 is used to define the contact structure.

[0097] In some embodiments, the second patterned mask layer 152 is a patterned photoresist layer. For example, the photoresist is formed by spin coating and then patterned to have a mask pattern by exposing it to light using a suitable photomask (or intermediate mask). Exposed or unexposed portions of the photoresist can be removed, depending on whether a positive or negative resist is used. In alternative embodiments, a hard mask layer (not shown) can be formed on the semiconductor structure 100. The hard mask layer can include silicon, silicon oxide, silicon nitride, and / or another suitable material, or be formed from silicon, silicon oxide, silicon nitride, and / or another suitable material. The hard mask layer, which can be formed by photolithography as described above, can be etched using a patterned photoresist layer to have a mask pattern.

[0098] In some embodiments, such as Figure 2E-3 As shown, the source / drain component 126N(S) on the active region 104N2 in cell region C2 is used for a Vdd / Vss node (e.g., a source terminal), which is electrically connected to a power rail in the metal layer. In some embodiments, the source / drain component 126N(D) on the active region 104N1 in cell region C1 is used for a non-Vdd / Vss node (e.g., a drain terminal), which is electrically connected to a signal line in the metal layer. That is, in the illustrated embodiment, the source terminal of the circuit in cell region C2 is adjacent to the drain terminal of the circuit in cell region C1. The embodiments are not limited thereto. In some other embodiments, the source terminal of the circuit in cell region C2 may be adjacent to the source terminal of the circuit in cell region C1. In some embodiments, the mask pattern 152A corresponds to or overlaps with the boundary between cell regions C1 and C2 and between the source / drain component 126N(D) on the active region 104N1 and the source / drain component 126N(S) on the active region 104N2.

[0099] In some embodiments, the spacing between the mask pattern 152A and the active region 104N2 is greater than the spacing between the mask pattern 152A and the active region 104N1. In some embodiments, the mask pattern 152A does not vertically overlap with the source / drain component 126N(S) on the active region 104N2. In some embodiments, the mask pattern 152A may partially overlap with the source / drain component 126N(D) on the active region 104N1. In some embodiments, the edge 152A1 of the mask pattern 152A is located between the edge E1 of the active region 104N2 and an imaginary center line CL (or the boundary between cell regions C1 and C2) equidistant from the active regions 104N1 and 104N2, such as... Figure 2E-1 As shown in the diagram. Specifically, the distance between edge 152A1 and edge E1 is less than the distance between edge 152A1 and centerline CL.

[0100] In some embodiments, the mask pattern 152A has a width CD1 in the Y direction and is spaced apart from the mask pattern 152 in the first cell region C1 by a spacing CD2. The width CD1 and the spacing CD2 can be the minimum width and spacing (critical dimensions) achievable by the photolithography process for forming the diced MD pattern. If the mask pattern 152A is positioned toward (or even overlaps with) the active region 104N1 in the first cell region C1, the spacing CD2 may be too small, potentially exceeding the process window of the photolithography process. Furthermore, reducing the overlap between the MD pattern 151 in the cell region C1 and the source / drain regions 126N(D) on the active region 104N1 can lower the contact resistance of the resulting contact structure. Conversely, if the mask pattern 152A is positioned toward the active region 104N2 in the second cell region C2, the spacing CD2 can be increased, thereby widening the process window of the photolithography process.

[0101] However, the positioning of the mask pattern 152A depends on the layout of the semiconductor structure 100. Power rails are defined at a centerline CL equidistant from the active regions 104N1 and 104N2 (or the boundary between cell regions C1 and C2). Therefore, positioning the mask pattern 152A towards the active region 104N1 in the first cell region C1 can extend the contact structure in the second cell region C2 to be close to the power rail connected thereto, thereby satisfying the layout design. Thus, as the size of semiconductor devices continues to shrink, balancing layout design and lithography process windows can become quite challenging. This embodiment utilizes a two-level contact structure to achieve a good balance between layout design and lithography process windows, which will be discussed in detail later.

[0102] Figure 2F-1 and Figure 2F-2 The semiconductor structure 100 corresponds to the following after the etching process: Figure 1Cross-sectional views of lines XX and Y1-Y1. According to some embodiments, an etching process is performed using a second patterned mask layer 152 and a first patterned hard mask layer 148 to transfer the MD pattern 151 into the mask layer 146, and then into the ILD capping layer 132, the contact etch stop layer 128, the first interlayer dielectric layer 130, and the source / drain components 126N and 126P, thereby forming contact openings 154 (including 154A), as shown. Figure 2F-1 and Figure 2F-2 As shown in the diagram. The etching process can be anisotropic. The etching process can include dry etching, such as reactive ion etching (RIE), neutral beam etching (NBE), inductively coupled plasma (ICP) etching, another suitable method, or a combination thereof. In some embodiments, the etching process is performed until the source / drain components 126N and 126P are exposed. Afterward, the first patterned mask layer 148 and the second patterned mask layer 150 can be removed during the etching process or using additional etching or ashing processes.

[0103] Figure 2G-1 This is a three-dimensional view of the semiconductor structure 100 after the formation of the contact structure 158, and Figure 2G-2 , Figure 2G-3 They correspond to respectively Figure 1 Cross-sectional views of lines XX and Y1-Y1. According to some embodiments, a contact pad 160 is formed in the contact opening 154, such as... Figure 2G-2 and Figure 2G-3 As shown in the diagram. According to some embodiments, the contact pad 160 extends along the sidewall of the contact opening 154 and partially fills the contact opening 154. In some embodiments, the contact pad 160 is made of a dielectric material, such as silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbonitride oxynitride (SiOCN), and / or oxygen-doped silicon carbonitride (Si(O)CN) or combinations thereof. In some embodiments, the formation of the contact pad 160 includes depositing a dielectric material and a subsequent etch-back process to re-expose the source / drain components 126N and 126P. In some embodiments, the etch-back process may extend the contact opening 154 to a deeper location.

[0104] According to some embodiments, a silicide layer 162 is formed on the exposed top surfaces of the source / drain components 126N and 126P, such as... Figure 2G-1 , Figure 2G-2 and Figure 2G-3As shown in the figure. In some embodiments, the silicide layer 162 formed on the n-type source / drain component 126N is made of WSi, NiSi, TiSi, and / or CoSi. In some embodiments, the silicide layer 162 formed on the p-type source / drain component 126P is made of WSiGe, NiSiGe, TiSiGe, and / or CoSiGe. In some embodiments, the formation of the silicide layer 162 includes: pre-cleaning the exposed surfaces of the source / drain components 126N and 126P; depositing a metal material; and subsequent one or more annealing processes. According to some embodiments, semiconductor material (e.g., Si or SiGe) from the source / drain components 126N and 126P reacts with a metal material to form the silicide layer 162. Unreacted metal material is then removed using a post-cleaning process.

[0105] According to some embodiments, a contact structure 158 is formed in the contact opening 154 on the silicide layer 162, such as Figure 2G-1 , Figure 2G-2 and Figure 2G-3 As shown in the diagram. According to some embodiments, contact structure 158 rests on source / drain components 126N and 126P. In some embodiments, such as... Figure 2G-1 and Figure 2G-3 As shown, contact structure 158 on the active region 104N2 in cell region C2 is used for Vdd / Vss nodes (e.g., source terminals) and is referred to as 158A, and contact structure 158 on the active region 104N1 in cell region C1 is used for non-Vdd / Vss nodes (e.g., drain terminals) and is referred to as 158B. In each of cell regions C1 and C2, there may be one or more contact structures for Vdd / Vss nodes and one or more contact structures for non-Vdd / Vss nodes.

[0106] Contact structure 158 may have a multilayer structure. For example, one or more conductive materials include a barrier / adhesive layer and a bulk metal layer on the barrier / adhesive layer. In some embodiments, the barrier / adhesive layer may be made of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), cobalt-tungsten (CoW), another suitable material, or a combination thereof. In some embodiments, the bulk metal layer is made of one or more conductive materials having low resistance and good gap-filling ability, such as cobalt (Co), nickel (Ni), tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), rhodium (Rh), iridium (Ir), platinum (Pt), aluminum (Al), ruthenium (Ru), molybdenum (Mo), another suitable metallic material, or a combination thereof.

[0107] In some embodiments, one or more conductive materials are deposited using CVD, PVD, electron beam evaporation, ALD, electroplating (ECP), electrodeposition-free deposition (ELD), another suitable method, or a combination thereof to overfill the contact opening. In some embodiments, the bulk metal layer is formed using a selective deposition technique such as cyclic CVD or ELD processes, and it is not necessary to form a barrier / adhesive layer before depositing the bulk metal material. One or more conductive materials above the top surface of the ILD capping layer 132 are planarized using, for example, CMP, until the gate electrode layer 144 is exposed. In some embodiments, the top surface of the gate electrode layer 144 is substantially flush with the top surface of the contact structure 158 and the top surface of the ILD capping layer 132. In some embodiments, the conductivity of the contact structure 158 is greater than the conductivity of the silicide layer 160, and the conductivity of the silicide layer 160 is greater than the conductivity of the source / drain components 126N and 126P.

[0108] Figure 2H This is a perspective view of the semiconductor structure 100 after the formation of the etch stop layer 163 and the second interlayer dielectric layer 164. According to some embodiments, the etch stop layer 163 and the second interlayer dielectric layer 164 are subsequently formed on the semiconductor structure 100, such as... Figure 2H As shown in the diagram. In some embodiments, the etch stop layer 163 is made of a dielectric material, such as silicon nitride (SiN), silicon oxide (SiO2), silicon oxynitride (SiON), silicon carbide (SiC), oxygen-doped silicon carbide (SiC:O), oxygen-doped silicon carbonitride (Si(O)CN), or combinations thereof. In some embodiments, the second interlayer dielectric layer 164 is made of a dielectric material, such as USG, BPSG, FSG, PSG, BSG, or another suitable dielectric material. In some embodiments, the etch stop layer 163 and the second interlayer dielectric layer 164 are deposited using CVD (such as HDP-CVD, PECVD, HARP, or FCVD), another suitable technique, or a combination thereof.

[0109] According to some embodiments, a patterning process is performed on the second interlayer dielectric layer 164 and the etch stop layer 163 to form contact openings 166, such as... Figure 2HAs shown in the diagram. The patterning process may include a photolithography process and a subsequent etching process. According to some embodiments, contact opening 166 corresponds to and partially exposes the top surface of contact structure 158A, which serves as the source terminal for circuitry in cell regions C1 and C2. In some embodiments, contact structure 158B for the drain terminal remains covered by etch stop layer 163. In some embodiments, contact opening 166 also partially exposes the top surface of gate dicing member 140. That is, according to some embodiments, contact opening 166 is formed closer to the cell boundary than contact structure 158A. In some embodiments, along the X direction, contact opening 166 may expose contact pad 160 and contact etch stop layer 128, but gate spacer layer 118 and final gate stack 134 remain covered by etch stop layer 163.

[0110] Figure 2I This is a perspective view of the semiconductor structure 100 after the contact structure 168 has been formed. According to some embodiments, a contact structure 168 is formed in the contact opening 166, which rests on the contact structure 158A, such as... Figure 2I As shown in the diagram, contact structures 158A and 158B may be referred to as first-level contact structures, while contact structure 168 may be referred to as a second-level contact structure. According to some embodiments, the second-level contact structure 168 is configured to extend the source terminal to a boundary closer to the cell regions C2 and C1. According to some embodiments, the second-level contact structure 168 on the active region 104N2 extends towards the active region 104N1 beyond the edge of the first-level contact structure 158A on the active region 104N2. In some embodiments, the second-level contact structure 168 may extend to a centerline CL equidistant from the active regions 104N1 and 104N2.

[0111] Contact structure 168 may have a multilayer structure. For example, one or more conductive materials include a barrier / adhesive layer and a bulk metal layer on the barrier / adhesive layer. In some embodiments, the barrier / adhesive layer may be made of Ta, TaN, Ti, TiN, CoW, another suitable material, or a combination thereof. In some embodiments, the bulk metal layer is made of one or more conductive materials having low resistance and good gap-filling ability, such as Co, Ni, W, Ti, Ta, Cu, Rh, Ir, Pt, Al, Ru, Mo, another suitable metallic material, or a combination thereof. In some embodiments, one or more conductive materials are deposited using CVD, PVD, electron beam evaporation, ALD, electroplating (ECP), electrodeposition-free deposition (ELD), another suitable method, or a combination thereof to overfill contact opening 166. In some embodiments, the bulk metal layer is formed using a selective deposition technique such as cyclic CVD or ELD processes, and it is not necessary to form a barrier / adhesive layer before depositing the bulk metal material. One or more conductive materials above the top surface of the second interlayer dielectric layer 164 are planarized using, for example, CMP. In some embodiments, the top surface of the contact structure 168 is flush with the top surface of the second interlayer dielectric layer 164.

[0112] Figure 2J After the formation of the third interlayer dielectric layer 170, the via 172, the intermetallic dielectric layer 174, and the metal line 176, the semiconductor structure 100 corresponds to... Figure 1 A cross-sectional view of line Y1-Y1. According to some embodiments, a third interlayer dielectric layer 170 is formed on the semiconductor structure 100, such as... Figure 2J As shown in the diagram. In some embodiments, the third interlayer dielectric layer 170 is made of a dielectric material such as silicon nitride (SiN), silicon oxide (SiO2), silicon oxynitride (SiON), silicon carbide (SiC), oxygen-doped silicon carbide (SiC:O), oxygen-doped silicon carbonitride (Si(O)CN), or combinations thereof. In some embodiments, the third interlayer dielectric layer 170 is deposited using CVD (such as HDP-CVD, PECVD, HARP, or FCVD), another suitable technique, or a combination thereof.

[0113] According to some embodiments, a through-hole 172 is formed in or through the third interlayer dielectric layer 170, connecting to the second-level contact structure 168, such as... Figure 2JAs shown in the diagram. Although a via 172 is shown, the embodiments are not limited thereto. According to some embodiments, a via 172 can be formed through the third interlayer dielectric layer 170, the second interlayer dielectric layer 164, and the etch stop layer 163 to terminate on the first-level contact structure 158B. According to some embodiments, a via 172 can be formed through the third interlayer dielectric layer 170, the second interlayer dielectric layer 164, and the etch stop layer 163 to terminate on the final gate stack 134.

[0114] In some embodiments, the formation of via 172 includes patterning a third interlayer dielectric layer 170, a second interlayer dielectric layer 164, and an etch stop layer 163 using one or more photolithography processes and one or more etching processes to form a via opening. The etching process may include dry etching, such as RIE, NBE, ICP etching, another suitable method, or a combination thereof. Subsequently, according to some embodiments, one or more conductive materials are deposited using CVD, PVD, electron beam evaporation, ALD, ECP, ELD, another suitable method, or a combination thereof to overfill the via opening. One or more conductive materials above the upper surface of the second interlayer dielectric layer 164 are planarized using, for example, CMP. The via 172 may have a multilayer structure. For example, a barrier / adhesive layer (not shown) may optionally be deposited along the sidewalls and bottom surface of the via opening. In some embodiments, the barrier / adhesive layer may be made of Ta, TaN, Ti, TiN, CoW, another suitable material, or a combination thereof. In some embodiments, the bulk metal layer is made of one or more conductive materials having low resistance and good gap-filling ability, such as Co, Ni, W, Ti, Ta, Cu, Rh, Ir, Pt, Al, Ru, Mo, another suitable metallic material, or combinations thereof.

[0115] According to some embodiments, an intermetallic dielectric layer 174 is formed above the via 172 and the third intermetallic dielectric layer 170, and a metal line 176 of the front first-level metal layer is formed through the intermetallic dielectric layer 174, such as... Figure 2J As shown in the diagram. According to some embodiments, metal line 176 extends in the X direction. According to some embodiments, metal line 176 may be a Vss power rail electrically connected to the n-type source / drain component 126N(S) for the Vdd / Vss node. Although only the Vss power rail 176 is shown, embodiments may also include a Vdd power rail 176 electrically connected to the p-type source / drain component 126P for the Vdd / Vss node. Furthermore, according to some embodiments, metal line 176 may include signal lines electrically connected to the final gate stack 134 and / or source / drain components 126N and 126P for non-Vdd / Vss nodes.

[0116] In some embodiments, the intermetallic dielectric layer 174 is made of one or more dielectric materials, such as silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), aluminum oxide (Al2O3), dielectric materials having a low dielectric constant (low k) (such as SiCOH, SiOCN, and / or SiOC), or combinations thereof. In some embodiments, the intermetallic dielectric layer 174 is made of an extremely low k (ELK) dielectric material having a dielectric constant (k) of less than about 3.0 or even less than about 2.5. In some embodiments, the dielectric constant of the intermetallic dielectric layer 174 is lower than the dielectric constant of the second intermetallic dielectric layer 164 and the dielectric constants of the first intermetallic dielectric layer 130, the second intermetallic dielectric layer 164, and the third intermetallic dielectric layer 170.

[0117] In some embodiments, the ELK dielectric material includes carbon-doped silicon oxide, amorphous fluorinated carbon, parylene, bisbenzocyclobutene (BCB), polytetrafluoroethylene (PTFE) (Teflon), or silicon carbide polymer (SiOC). In some embodiments, the ELK dielectric material includes porous versions of existing dielectric materials, such as hydrogen silsesquioxane (HSQ), porous methyl silsesquioxane (MSQ), porous polyarylene ether (PAE), porous filaments, or porous silicon oxide (SiO2). In some embodiments, the intermetallic dielectric layer 174 is formed using CVD (such as LPCVD, HARP, and FCVD), ALD, spin coating, another suitable method, or a combination thereof. A post-curing process (e.g., UV curing) can be performed on the deposited ELK dielectric material used for the intermetallic dielectric layer 174 to form a porous structure.

[0118] In some embodiments, the formation of the metal line 176 includes patterning the intermetallic dielectric layer 174 using photolithography and etching processes to form trenches. Subsequently, according to some embodiments, one or more conductive materials are deposited using CVD, PVD, electron beam evaporation, ALD, ECP, ELD, another suitable method, or combinations thereof to overfill the trenches. One or more conductive materials above the upper surface of the intermetallic dielectric layer 174 are planarized using, for example, CMP. The metal line 176 may have a multilayer structure, for example, including a barrier / adhesive layer and a bulk metal layer. The barrier layer may be made of Ta, TaN, Ti, TiN, CoW, another suitable material, or combinations thereof. In some embodiments, the bulk metal layer is made of one or more conductive materials, such as Co, Ni, W, Ti, Ta, Cu, Rh, Ir, Pt, Al, Ru, Mo, or combinations thereof.

[0119] According to embodiments of this disclosure, dual-level contact structures 158A and 168 are formed, wherein the first-level contact structure 158A is disposed near the active region 104N2 in the second unit region C2, and the second-level contact structure 160 is disposed near the active region 104N1 in the first unit region C1. Therefore, the source terminals of the circuit in the second unit region C2 can be electrically connected to the power rail 176 through the dual-level contact structures 158A and 168, while the mask pattern 152A ( Figure 2E-1 ) can be positioned toward the active region 104N2 in the second unit region C2, thereby making the interval CD2 ( Figure 2E-1 The process window for the lithography process used to form the diced MD pattern can be increased, and the process window for the lithography process can be widened. Therefore, a good balance can be achieved between the layout design and the process window for the lithography process.

[0120] In the case of a single-layer contact structure, as the edge of the contact structure 158A on the active region 104N2 extends toward the source / drain component 126N(D) on the active region 104N1, the leakage risk between the contact structure 158A on the active region 104N2 and the source / drain component 126N(D) on the active region 104N1 may increase, thereby reducing the reliability of the resulting semiconductor device (e.g., time-dependent dielectric breakdown (TDDB)). According to embodiments of this disclosure, the contact structure 158A can be moved backward from the centerline CL, which is equidistant from the active regions 104N1 and 104N2. Therefore, the spacing S1 between the contact structure 158A and the source / drain component 126N(D) can be increased, thereby improving the reliability of the resulting semiconductor device.

[0121] The semiconductor structure 100 may undergo a further front-side BEOL process to form various interconnect conductive components (not shown) over the semiconductor structure 100, such as the front second metal layer (F_M2) to the front tenth metal layer (F_M10) and vias between two adjacent metal layers.

[0122] Figure 2K This is a perspective view of the semiconductor structure 100 after the flipping and planarization processes. According to some embodiments, the semiconductor structure 100 is flipped vertically, such as... Figure 2KAs shown in the figure. In some embodiments, prior to flipping the semiconductor structure 100, a carrier substrate (not shown) sealing the front side of the semiconductor structure 100 may be formed over the front side of the semiconductor structure 100 to protect the components of the semiconductor structure 100 during subsequent back-side processes. According to some embodiments, after flipping the semiconductor structure 100, the back-side surface of the substrate 102 (the back side of the semiconductor structure 100) faces upward. According to some embodiments, a planarization process, such as a polishing process, CMP, etching process, or a combination thereof, is used to remove the substrate 102 from the back side of the semiconductor structure 100 until the lower fin elements 103N and 103P and the isolation structure 110 are exposed, as shown. Figure 2K As shown in the image.

[0123] Figure 2L This is a perspective view of the semiconductor structure 100 after the formation of the etch stop layer 178 and the mask layer 180, and the patterning process. According to some embodiments, the etch stop layer 178 and the mask layer 180 are subsequently formed on the back side of the semiconductor structure 100, such as... Figure 2L As shown in the diagram. In some embodiments, the etch stop layer 178 is made of a dielectric material, such as silicon nitride (SiN), silicon oxide (SiO2), silicon oxynitride (SiON), silicon carbide (SiC), oxygen-doped silicon carbide (SiC:O), oxygen-doped silicon carbonitride (Si(O)CN), or a combination thereof. In some embodiments, the mask layer 180 is made of a dielectric material, such as USG, BPSG, FSG, PSG, BSG, or another suitable dielectric material. In some embodiments, the etch stop layer 178 and the second interlayer dielectric layer 164 are deposited using CVD (such as HDP-CVD, PECVD, HARP, or FCVD), another suitable technique, or a combination thereof.

[0124] According to some embodiments, a patterning process is performed on the mask layer 180 and the etch stop layer 178, the lower fin element 103P, and the intermediate components 124 and 123 to form the contact opening 182, such as Figure 2L As shown in the diagram. According to some embodiments, contact opening 182 corresponds to and exposes the back surface of source / drain component 128N(S), which serves as the source terminal for circuitry in cell regions C1 and C2. According to some embodiments, the patterning process may include forming a patterned mask layer over the semiconductor structure 100 and a subsequent etching process. The etching process may include dry etching, such as RIE, NBE, ICP etching, another suitable method, or a combination thereof.

[0125] The etching process can have multiple etching steps. For example, a first etching step transfers the opening pattern to the mask layer 180 and the etch stop layer 178, and then a second etching step transfers the opening pattern to the lower fin elements 103P and the intermediate members 124 and 123. Due to the difference in etch selectivity between the isolation structure 110 and the lower fin elements 103P and 103N, the lower portion of the contact opening 182 is formed to be self-aligned with the lower fin elements 103P and 103N and the intermediate members 124 and 123. Therefore, the opening pattern of the patterned mask layer can have a larger size in the X and / or Y directions than the lower fin element 103P, thereby widening the process window for forming the contact opening 182.

[0126] Figure 2M This is a perspective view of the semiconductor structure 100 after the formation of the contact structure 184. According to some embodiments, contact pads 186 are formed in the contact openings 182, such as... Figure 2M As shown in the diagram. According to some embodiments, contact pad 186 extends along the sidewall of contact opening 182 and partially fills contact opening 182. The material and formation of contact pad 186 may be the same as or similar to contact pad 160 as described above. According to some embodiments, a silicide layer (not shown) may be formed on the back surface of the source / drain component 126N exposed in contact opening 182. In some embodiments, the material and formation of silicide layer 186 may be similar to or the same as silicide layer 162 as described above.

[0127] According to some embodiments, a contact structure 184 is formed in the contact opening 182, such as Figure 2MAs shown in the diagram. Contact structure 184 may be referred to as a back-side contact structure (or back-side via), and contact structures 158A and 158B, as well as contact structure 168, may be referred to as a front-side contact structure. In some embodiments, the formation of contact structure 184 includes depositing one or more conductive materials for contact structure 184 to overfill contact opening 182. In some embodiments, one or more conductive materials are deposited using CVD, PVD, electron beam evaporation, ALD, ECP, ELD, another suitable method, or a combination thereof to overfill contact opening 182. One or more conductive materials are planarized using, for example, CMP until a third etch stop layer 178 is exposed. In some embodiments, mask layer 180 is removed during the planarization process. Contact structure 184 may have a multilayer structure. For example, a barrier / adhesive layer (not shown) may optionally be deposited along the sidewalls and bottom surface of contact opening 182. The barrier layer may be made of Ta, TaN, Ti, TiN, CoW, another suitable material, or a combination thereof. In some embodiments, the bulk metal layer is made of one or more conductive materials, such as Co, Ni, W, Ti, Ta, Cu, Rh, Ir, Pt, Al, Ru, Mo, or combinations thereof.

[0128] Figure 2N-1 , Figure 2N-2 and Figure 2N-3 After the formation of the intermetallic dielectric layer 188 and the metal line 190, the semiconductor structure 100 corresponds to... Figure 1 Cross-sectional views of line XX, line Y1-Y1, and line Y2-Y2, and Figure 2N-4 and Figure 2N-5 The front and back layouts of the semiconductor structure 100 are shown. According to some embodiments, an intermetallic dielectric layer 188 is formed over the back-side contact structure 184 and the etch stop layer 178, such as… Figures 2N-1 to 2N-3 As shown in the diagram. The material and formation of the intermetallic dielectric layer 188 may be the same as or similar to that of the intermetallic dielectric layer 174 as described above. According to some embodiments, metal lines 190 forming a back-side first-level metal layer are formed through the intermetallic dielectric layer 188, as shown in... Figure 2N-2 and Figure 2N-5 As shown in the diagram. According to some embodiments, the metal line 190 extends in the X direction. According to some embodiments, the metal line 190 may be a Vss power rail electrically connected to an n-type source / drain component 126N(S) for the Vdd / Vss node. Although only the Vss power rail 190 is shown, embodiments may also include a Vdd power rail 190 electrically connected to a p-type source / drain component 126P for the Vdd / Vss node. The material and formation of the metal line 190 may be the same as or similar to the metal line 176 described above.

[0129] In some embodiments, the contact structure 158A on the active region 104N2 extends beyond the edge distance D1 of the active region 104N2 facing the active region 104N1, such as... Figure 2N-4 As shown in the illustration. In some embodiments, the contact structure 158B on the active region 104N1 extends beyond the edge distance D2 of the active region 104N1 facing the active region 104N2. In the illustrated embodiment, distance D1 is greater than distance D2. In some embodiments, the contact structure 158B partially rests on the source / drain component 126N on the active region 104N2, and the silicide layer 162 between the contact structure 158B and the source / drain component 126N may have an L-shape in cross-sectional view. In some other embodiments, distance D1 is substantially the same as distance D2.

[0130] In some embodiments, the edge 158A1 of the contact structure 158A is located between the edge E1 of the active region 104N2 and the center line CL (or the boundary between the unit regions C1 and C2) which is equidistant from the active regions 104N1 and 104N2. Specifically, the distance between the edge 158A1 and the edge E1 is less than the distance between the edge 158A1 and the center line CL.

[0131] In some embodiments, the spacing of the final gate stack 134 (the sum of the width of the final gate stack (dimension in the X direction) and the spacing between the final gate stacks 134) may be equal to or less than about 44 nm, for example, in the range from about 22 nm to about 44 nm. In some embodiments, the width (dimension in the Y direction) of the active regions 104N and 104P may be equal to or less than 32 nm, for example, in the range from about 16 nm to about 32 nm. In some embodiments, the spacing between the active regions 104N and 104P may be equal to or less than 30 nm, for example, in the range from about 15 nm to about 30 nm.

[0132] In some embodiments, contact structure 168 perpendicularly overlaps with active region 104N2 and contact structure 158A. In some embodiments, contact structure 168 extends to a centerline CL equidistant from active regions 104N1 and 104N2. Contact structure 168 may extend beyond the centerline CL. In the illustrated embodiment, via 172 on contact structure 168 perpendicularly overlaps with contact structure 158A but not with active region 104N2. Via 172 rests completely on contact structure 168. In some other embodiments, via 172 may not overlap with contact structure 158A. Although via 172 has a rectangular profile in the layout, the embodiments are not limited thereto. For example, via 172 has a circular profile. In some embodiments, back contact structure 184 is shorter than front contact structure 158A in the Y direction, such as... Figure 2N-5As shown in the figure. In some embodiments, the back metal line 190 is wider in the Y direction than the front metal line 176.

[0133] As semiconductor devices continue to shrink, scaling of the metal layers in a BEOL (Block Array of Optical Layers) has become limited by resistance and capacitance due to increasingly smaller linewidths and line spacing. Therefore, performance improvements (e.g., increased speed) of semiconductor devices (e.g., logic circuits) cannot rely solely on device boost; attention must also be paid to the RC delay of the metal conductors (e.g., metal lines) and the IR voltage drop of the power supply (e.g., the actual voltage positions of Vdd and Vss during operation for the logic circuit). A back-side power rail can provide back-end metal wiring for semiconductor devices on the back side of the substrate, thereby reducing the overall resistance of the BEOL metal layer (e.g., contact resistance and / or sheet resistance) and / or reducing the complexity of metal wiring on the front side of the substrate. In embodiments of this disclosure, the power rails are disposed on both sides of the semiconductor structure 100, which can further reduce the overall resistance of the metal layers. Therefore, the back-side power rail architecture can facilitate the continued scaling of semiconductor devices.

[0134] The semiconductor structure 100 may undergo a further back-side BEOL process to form various interconnect conductive components (not shown) over the semiconductor structure 100, such as back-side metal layers and vias between two adjacent metal layers.

[0135] Figure 3-1 and Figure 3-2 The front and back layouts of the semiconductor structure are shown, and Figure 3-3 It is a 3D diagram of a semiconductor structure. Figure 3-1 , Figure 3-2 and Figure 3-3 The embodiments are similar to Figures 2A-1 to 2N-5 In some embodiments, the same reference numerals denote the same elements formed by the same process. In some embodiments, a back-side metal line 190 is electrically connected to two back-side contact structures 184 formed on the active region 104N2. In some embodiments, a front-side metal line 176 is electrically connected to two second-level contact structures 168 formed on the active region 104N2.

[0136] Figure 4-1 and Figure 4-2 The semiconductor structures are shown to correspond to the following respectively. Figure 1 Cross-sectional views of line XX and line Y1-Y1. Figure 4-1 and Figure 4-2 The embodiments are similar to Figures 2A-1 to 2N-5In some embodiments, the same reference numerals denote the same elements formed by the same process, except that the first-level contact structures 158A and 158B are higher than the final gate stack 134, for example, by about 10-20 nm. In some embodiments, an etch stop layer 202 and a fourth interlayer dielectric layer 204 are subsequently formed on the semiconductor structure 100 before the formation of the first-level contact structures 158A and 158B. The materials and formation of the etch stop layer 202 and the fourth interlayer dielectric layer 204 may be similar to or the same as those of the etch stop layer 163 and the second interlayer dielectric layer 164 described above. According to some embodiments, the first-level contact structures 158A and 158B are formed through the fourth interlayer dielectric layer 204 and the etch stop layer 202, as shown in some embodiments. Figure 4-1 and Figure 4-2 As shown in the image.

[0137] Figure 5-1 and Figure 5-2 The front and back layouts of the semiconductor structure are shown, and Figure 5-3 This is a cross-sectional view of a semiconductor structure. Figure 5-1 , Figure 5-2 and Figure 5-3 The embodiments are similar to Figures 2A-1 to 2N-5 In some embodiments, the same reference numerals denote the same elements formed by the same process. In some embodiments, the source / drain component 126N(S) on the active region 104N1 in the first cell region C1 faces the source / drain component 126N(S) on the active region 104N2 in the second cell region C2. That is, in the illustrated embodiment, the source terminal of the circuit in cell region C2 is adjacent to the source terminal of the circuit in cell region C1. According to some embodiments, the source / drain components 126N(S) on the active regions 104N1 and 104N2 are electrically connected to each other through a first-level contact structure 158A and a second-level contact structure 168 and share the same front-side metal line 176. In some embodiments, the second-level contact structure 168 rests on the two first-level contact structures 158A formed on the active regions 104N1 and 104N2, respectively. In some embodiments, a via 172 may be provided at a position equidistant from the active regions 104N1 and 104N2. According to some embodiments, the source / drain components 126N(S) on the active regions 104N1 and 104N2 share the same back-side metal line 190 through the back-side contact structure 184.

[0138] Figure 6 A three-dimensional view of the semiconductor structure is shown. Figure 6 The embodiments are similar to Figures 2A-1 to 2N-5In some embodiments, the same reference numerals denote the same elements formed by the same process, except that a second-level contact structure 168' is formed on the contact plug 158B for the drain terminal. That is, the second-level contact structure 168' is electrically connected to a signal line in the metal layer. In some embodiments, the second-level contact structure 168' extends toward the interior of the cell region C2 above the source / drain component 126P. The second-level contact structure 168' can increase design flexibility for integrated circuits.

[0139] Figure 7-1 and Figure 7-2 The front and back layouts of the semiconductor structure are shown, and Figure 7-3 It is a 3D diagram of a semiconductor structure. Figure 7-1 , Figure 7-2 and Figure 7-3 The embodiments are similar to Figures 2A-1 to 2N-5 In some embodiments, the same reference numerals denote the same elements formed by the same process. In some embodiments, a first-level contact structure 158A is higher than the final gate stack 134, and a second-level contact structure 168 electrically connects the two first-level contact structures 158A, which are formed on the active region 104N2 and on opposite sides of one of the final gate stacks 134. In some embodiments, no vias are formed on the second-level contact structure 168. In some embodiments, a back-side metal line 190 electrically connects two back-side contact structures 184 formed on the active region 104N2. Therefore, the second-level contact structure 168 can be used as a front-side power rail to replace the power supply of the front-side metal layer, thereby reducing the density and / or complexity of the front-side metal wiring and improving the performance of the semiconductor device, for example, lower power consumption.

[0140] Figure 8-1 The front-side layout of the semiconductor structure is shown, and Figure 8-2 It is the corresponding semiconductor structure Figure 1 A cross-sectional view of line XX. Figure 8-1 and Figure 8-2 The embodiments are similar to Figures 2A-1 to 2N-5In some embodiments, the same reference numerals denote the same elements formed by the same process. According to some embodiments, a second-level contact structure 168' is formed on the contact plug 158B for the drain terminal. According to some embodiments, the second-level contact structure 168' extends in the Y direction to the final gate stack 134. Therefore, the contact plug 158B and the final gate stack 134 are electrically connected to each other via the contact structure 168'. In some embodiments, the semiconductor structure includes a static random access memory (SRAM) device. For example, the drain terminal of the pull-down transistor of the SRAM device is electrically connected to the gate terminal of the transmission gate transistor of the SRAM device via the contact structure 168'.

[0141] Figure 9 It is the corresponding semiconductor structure Figure 1 A cross-sectional view of line Y1-Y1. Figure 9 The embodiments are similar to Figures 2A-1 to 2N-5 In the embodiments described, the same reference numerals denote the same elements formed by the same process, except that the contact structure 158B is completely grounded on the source / drain component 126N on the active region 104N2. The silicide layer 162 between the contact structure 158B and the source / drain component 126N is planar, which reduces the contact resistance of the resulting semiconductor device.

[0142] Figures 10A to 10I-5 The semiconductor structure 100A is shown being formed at various intermediate stages according to some embodiments of the present disclosure. Figures 10A to 10I-5 The embodiments are similar to Figures 2A-1 to 2N-5 In the embodiments, the same reference numerals denote the same elements formed by the same process. Figure 10A This is a 3D view of the semiconductor structure 100A. Continuing from... Figures 2C-1 to 2C-4 The semiconductor structure 100A includes: active regions 104N1, 104N2, and 104P2; source / drain components 126N and 126P located on the lower fin element 103 of the active regions 104N1, 104N2, and 104P2; a final gate stack 134 enclosing the nanostructure of the active regions 104N1, 104N2, and 104P2; and a gate dicing component 140 dicing through the final gate stack 134, such as... Figure 10A As shown in the image.

[0143] Figure 10B This is a perspective view of the semiconductor structure 100A after the formation of contact structures 158A and 158B. In some embodiments, an etch stop layer 202 and a fourth interlayer dielectric layer 204 are subsequently formed on the semiconductor structure 100A. The materials and formation of the etch stop layer 202 and the fourth interlayer dielectric layer 204 may be similar to or the same as those of the etch stop layer 163 and the second interlayer dielectric layer 164 described above.

[0144] According to some embodiments, contact structures 158A and 158B are formed to pass through the fourth interlayer dielectric layer 204 and the etch stop layer 202, the ILD capping layer 132, the contact etch stop layer 128, and the first interlayer dielectric layer 130, and are terminated on the source / drain components 126N and 126P, as shown. Figure 10B As shown in the illustration. In some embodiments, the contact structure 158 for the Vdd / Vss node (e.g., the source terminal) is referred to as 158A, and the contact structure 158 for the non-Vdd / Vss node (e.g., the drain terminal) is referred to as 158B. According to some embodiments, the top surfaces of contact structures 158A and 158B are higher than the top surface of the final gate stack 134. In the illustrated embodiment, the source terminal of the circuit in cell region C2 is adjacent to the drain terminal of the circuit in cell region C1.

[0145] In some embodiments, the spacing between active regions 104N1 and 104N2 can be large, and the balance between the layout design for forming the diced MD pattern described above and the process window of the photolithography process may be less important. Therefore, in the illustrative embodiment, contact structure 158A may extend to an imaginary center line CL equidistant from the active regions 104N1 and 104N2 (or the boundary between cell regions C1 and C2). Contact pad 160 and silicide layer 162 are formed using the steps described above prior to the formation of contact structures 158A and 158B.

[0146] Figure 10C This is a perspective view of the semiconductor structure 100A after the formation of the etch stop layer 163 and the second interlayer dielectric layer 164. According to some embodiments, the etch stop layer 163 and the second interlayer dielectric layer 164 are subsequently formed on the semiconductor structure 100A. According to some embodiments, the second interlayer dielectric layer 164 and the etch stop layer 163 are patterned to form contact trenches 210, such as... Figure 10C As shown in the image.

[0147] According to some embodiments, the contact trench 210 extends in the X direction and is located above the gate dicing member 140 (or the boundary between active regions 104N1 and 104N2). According to some embodiments, the contact trench 210 partially exposes the top surface and sidewalls of at least two contact structures 158A for source terminals of circuits in cell regions C1 and C2, respectively. In some embodiments, the contact structure 158B for the drain terminal remains covered by an etch stop layer 163. In some embodiments, the contact trench 210 may have an uneven structure in a top view. As used herein, "uneven" refers to a depression or protrusion on one or both sides of a member.

[0148] Figure 10D-1 and Figure 10D-2 This is a perspective view of semiconductor structure 100A after the formation of contact structure 212. According to some embodiments, contact structure 212 is formed in contact trench 210. According to some embodiments, contact structure 212 extends in the X direction and laterally abuts contact structure 158A. Contact structure 212 may be referred to as a die-casting device (MD). According to some embodiments, the portion of contact structure 212 adjacent to contact structure 158A in the first cell region C1 is offset relative to the portion of contact structure 212 adjacent to contact structure 158A in the second cell region C2. Therefore, contact structure 212 has a bump-and-recess structure or a serpentine profile. According to some embodiments, contact structure 158A has a protrusion surrounded by contact structure 212 in a top view. In some other embodiments where the spacing between active regions 104N1 and 104N2 is larger, contact structure 212 may not have a bump-and-recess structure. In some embodiments, the bottom surface of contact structure 212 is higher than the top surface of the final gate stack 134 by more than about 4 nm.

[0149] Contact structure 212 may have a multilayer structure. For example, one or more conductive materials include a barrier / adhesive layer and a bulk metal layer on the barrier / adhesive layer. In some embodiments, the barrier / adhesive layer may be made of Ta, TaN, Ti, TiN, CoW, another suitable material, or a combination thereof. In some embodiments, the bulk metal layer is made of one or more conductive materials having low resistance and good gap-filling ability, such as Co, Ni, W, Ti, Ta, Cu, Rh, Ir, Pt, Al, Ru, Mo, another suitable metallic material, or a combination thereof. In some embodiments, one or more conductive materials are deposited using CVD, PVD, electron beam evaporation, ALD, electroplating (ECP), electrodeposition-free deposition (ELD), another suitable method, or a combination thereof to overfill contact trench 210. In some embodiments, the bulk metal layer is formed using a selective deposition technique such as cyclic CVD or ELD processes, and it is not necessary to form a barrier / adhesive layer before depositing the bulk metal material. One or more conductive materials above the top surface of the fourth interlayer dielectric layer 204 are planarized using, for example, CMP. In some embodiments, the top surface of contact structure 212 is flush with the top surfaces of contact structures 158A and 158B and the top surface of the fourth interlayer dielectric layer 204. In some embodiments, contact structures 158A and 158B and contact structure 212 are higher than the final gate stack 134, for example, by about 10-20 nm.

[0150] Figure 10EThis is a perspective view of the semiconductor structure 100A after the formation of the etch stop layer 169, the third interlayer dielectric layer 170, and the via 172. According to some embodiments, the etch stop layer 169 and the third interlayer dielectric layer 170 are subsequently formed on the semiconductor structure 100A. The material and formation of the etch stop layer 169 can be similar to or the same as the etch stop layer 163 described above. According to some embodiments, a via 172 is formed in or through the third interlayer dielectric layer 170 and the etch stop layer 169, connecting to the contact structure 158B, as shown below. Figure 10E As shown in the diagram. According to some embodiments, via 172 may be formed through the third interlayer dielectric layer 170, the second interlayer dielectric layer 164, and the etch stop layer 163, and terminate on the final gate stack 134. In some embodiments, no via is formed on contact structures 158A and 212. That is, the top surfaces of contact structures 158A and 212 are completely covered by the etch stop layer 163.

[0151] The semiconductor structure 100A may undergo a further front-side BEOL process to form various interconnect conductive components (not shown) over the semiconductor structure 100A, such as the front first metal layer (F_M1) to the front tenth metal layer (F_M10) and vias between adjacent metal layers. In some embodiments, the contact structure 212 may be used as a front-side power rail to replace the power supply of the front metal layer, thereby reducing the density and / or complexity of the front metal wiring.

[0152] Figure 10F This is a perspective view of semiconductor structure 100A after the flipping and planarization processes. According to some embodiments, semiconductor structure 100A is flipped vertically. According to some embodiments, substrate 102 is removed from the back side of semiconductor structure 100A until the lower fin elements 103N and 103P and the isolation structure 110 are exposed.

[0153] Figure 10G This is a perspective view of the semiconductor structure 100A after the formation of the etch stop layer 178 and the mask layer 180. According to some embodiments, the etch stop layer 178 and the mask layer 180 are subsequently formed on the back side of the semiconductor structure 100A. According to some embodiments, the mask layer 180 and the etch stop layer 178, the lower fin element 103P, and the intermediate members 124 and 123 are patterned to form contact openings 182. According to some embodiments, the contact openings 182 correspond to and partially expose the back surface of the source / drain member 128N(S), which serves as the source terminal for circuits in cell regions C1 and C2.

[0154] Figure 10HThis is a perspective view of the semiconductor structure 100A after the formation of the contact structure 184. According to some embodiments, a contact pad 186 is formed along the sidewall of the contact opening 182, and the contact structure 184 is formed to fill the contact opening 182. According to some embodiments, prior to the formation of the contact structure 184, a silicide layer (not shown) may be formed on the back surface of the source / drain component 126N exposed in the contact opening 182.

[0155] Figure 10I-1 , Figure 10I-2 and Figure 10I-3 After the formation of the intermetallic dielectric layer 188 and the metal line 190, the semiconductor structure 100A corresponds to... Figure 1 Cross-sectional views of line XX, line Y1-Y1, and line Y2-Y2, and Figure 10I-4 and Figure 10I-5 The front and back layouts of the semiconductor structure 100 are shown. According to some embodiments, an intermetallic dielectric layer 188 is formed over the back-side contact structure 184 and the etch stop layer 178. According to some embodiments, a metal line 190 is formed through the intermetallic dielectric layer 188 to form a first-level metal layer on the back side. According to some embodiments, the metal line 190 may be a Vss power rail electrically connected to an n-type source / drain component 126N(S) for the Vdd / Vss node. Although only the Vss power rail 190 is shown, embodiments may also include a Vdd power rail 190 electrically connected to a p-type source / drain component 126P for the Vdd / Vss node.

[0156] In some embodiments, such as Figure 10I-4 As shown, contact structure 212 has a first side located in cell region C1 and a second side located in cell region C2. The first side has a first sidewall S1A intersecting the sidewall of contact structure 158A for the source terminal, a second sidewall S1B facing the contact structure 158B for the drain terminal, and a connecting wall S1C connecting the first sidewall S1A and the second sidewall S1B. In some embodiments, the distance D3 between the first sidewall S1A and the active region 104N2 is smaller than the distance D4 between the second sidewall S1B and the active region 104N2. A relatively large distance D4 can improve the reliability of the resulting semiconductor device (e.g., TDDB). In some embodiments, the connecting wall S1C may be a linear sidewall extending in the Y direction or inclined between the X and Y directions, or optionally a curved sidewall.

[0157] Similarly, in some embodiments, the second side of the contact structure 212 has a first sidewall S2A intersecting the sidewall of the contact structure 158A for the source terminal, a second sidewall S2B facing the contact structure 158B for the drain terminal, and a connecting wall S2C connecting the first sidewall S2A and the second sidewall S2B. In some embodiments, the distance between the first sidewall S2A and the active region 104N1 is smaller than the distance between the second sidewall S2B and the active region 104N1. In some embodiments, the connecting wall S2C may be a linear sidewall extending in the Y direction or inclined between the X and Y directions, or alternatively, it may be a curved sidewall.

[0158] According to some embodiments, the source / drain components 126N(S) on active regions 104N1 and 104N2 are electrically connected to and share the same back-side metal line 190 via a back-side contact structure 184, such as Figure 10I-5 As shown in the diagram, the semiconductor structure 100A may undergo a further back-side BEOL process to form various interconnect conductive components (not shown) over the semiconductor structure 100A, such as back-side metal layers and vias between two adjacent metal layers.

[0159] Figure 11-1 and Figure 11-2 The front and back layouts of the semiconductor structure are shown. Figure 11-1 and Figure 11-2 The embodiments are similar to Figures 10A to 10I-5 In some embodiments, the same reference numerals denote the same elements formed by the same process, except that the contact structure 212 has no protrusions or recesses. According to some embodiments, the sidewalls of the contact structure 212 extending in the X direction are straight.

[0160] Figure 12-1 and Figure 12-2 The front and back layouts of the semiconductor structure are shown, and Figure 12-3 It is a 3D diagram of a semiconductor structure. Figure 12-1 , Figure 12-2 and Figure 12-3 The embodiments are similar to Figures 10A to 10I-5 In some embodiments, the same reference numerals denote the same elements formed by the same process. In some embodiments, contact structure 212 electrically connects two contact structures 158A formed on opposite sides of one of the final gate stacks 134 on the active region 104N2. In some embodiments, back-side metal line 190 electrically connects two back-side contact structures 184 formed on the active region 104N2.

[0161] Figure 13 A three-dimensional view of the semiconductor structure is shown. Figure 13 The embodiments are similar to Figures 10A to 10I-5In some embodiments, the same reference numerals denote the same elements formed by the same process, except that a contact structure 212' is formed on the sidewall of the contact plug 158B for the drain terminal. That is, the contact structure 212' is electrically connected to a signal line in the metal layer via a via (not shown). In some embodiments, the contact structure 212' extends in the Y direction toward the interior of the cell region above the source / drain component 126P. The contact structure 212' can increase design flexibility for integrated circuits.

[0162] As described above, embodiments of this disclosure relate to a semiconductor structure with a back-side power rail architecture. The semiconductor structure 100 includes a two-level contact structure, wherein the source terminals of a circuit in the second cell region C2 are electrically connected to a front-side power rail 176 via a first-level contact structure 158A and a second-level contact structure 168. Therefore, the diced MD pattern 152A used to form the first-level contact structure 158A can be moved rearward toward the second cell region C2. The spacing CD2 between the diced MD patterns can be increased, and the process window for the photolithography process can be widened. Thus, a good balance can be achieved between the layout design and the process window for the photolithography process.

[0163] Furthermore, in some embodiments of this disclosure, the semiconductor structure 100A includes a microcontroller flyer 212 located on the sidewall of the contact structure 158A. The microcontroller flyer 212 is electrically connected to two or more contact structures 158A and can be used as a front-side power rail to replace the front-side power supply. Therefore, the density and / or complexity of the front-side metal wiring can be reduced, and thus continuous miniaturization of the semiconductor device can be achieved, and the performance of the semiconductor device can be improved, for example, by reducing power consumption.

[0164] Embodiments of semiconductor structures and methods for forming them can be provided. A method for forming a semiconductor structure may include forming a first type of contact structure on the front surface of a source / drain component, forming a second type of contact structure on the first contact structure, and forming a back-side contact structure on the back surface of the source / drain component. In some embodiments, the second type of contact structure may rest on the first contact structure and extend toward the cell boundary, thereby electrically connecting the source terminal of the transistor to a power rail. Therefore, a good balance can be achieved between layout design and process windows for photolithography. In some embodiments, the second type of contact structure may laterally abut the first contact structure to electrically connect the two first contact structures for the source terminal to each other. Therefore, the density and / or complexity of the front-side metal wiring can be reduced.

[0165] In some embodiments, a method for forming a semiconductor structure is provided. The method includes forming a first transistor over a substrate. The first transistor includes a first plurality of nanostructures extending longitudinally along a first direction over a first fin element, a first source / drain component located on a first substrate portion, and a first gate stack extending longitudinally across the first substrate portion along a second direction and surrounding the first plurality of nanostructures. The second direction is different from the first direction. The method also includes forming a first contact structure on the first source / drain component. The conductivity of the first contact structure is greater than the conductivity of the first source / drain component. The method also includes forming a second contact structure on the first contact structure. The second contact structure extends beyond the edge of the first contact structure. The method also includes: removing the substrate; forming a first opening through the first substrate portion to expose a back surface of the first source / drain component; and forming a third contact structure in the first opening. In a cross-sectional view, the third contact structure is narrower than the first contact structure.

[0166] In some embodiments, a method for forming a semiconductor structure is provided. The method includes forming a plurality of active regions over a substrate. Each active region includes a substrate portion and a nanostructure stacked over the substrate portion. The plurality of active regions extend longitudinally along a first direction. The method also includes: forming an isolation structure adjacent to the substrate portion of the plurality of active regions; and forming a plurality of source / drain components on the substrate portion of the active regions. Each source / drain component includes a portion suspended above the isolation structure. The method also includes: forming a plurality of gate stacks across the substrate portion of the plurality of active regions to surround the nanostructure of the active regions; forming a plurality of front-side contact structures on the source / drain components; forming an interlayer dielectric layer over the contact structures; and etching the interlayer dielectric layer to form a trench. The trench extends longitudinally along the first direction and is located between a first active region and a second active region among the plurality of active regions. The trench exposes a first front-side contact structure and a second front-side contact structure among the plurality of front-side contact structures. The method also includes: forming a conductive material in the trench; and forming a metal line below the substrate portion of the first and second active regions. The metal wire is electrically connected to the first front contact structure, the second front contact structure, and the conductive material.

[0167] In some embodiments, a semiconductor structure is provided. The semiconductor structure includes: a first plurality of nanostructures located above a first substrate portion; a gate stack enclosing the first plurality of nanostructures; a first source / drain component adjacent to a first side of the first plurality of nanostructures; a contact etch stop layer covering the first source / drain component; and an interlayer dielectric layer located above the contact etch stop layer. The dielectric constant of the contact etch stop layer differs from the dielectric constant of the interlayer dielectric layer. The semiconductor structure also includes a first first-level contact structure located on the front surface of the first source / drain component. The first first-level contact structure is electrically coupled to the first source / drain component through a silicide layer, and the conductivity of the silicide layer is between the conductivity of the first first-level contact structure and the conductivity of the first source / drain component. The semiconductor structure also includes a first second-level contact structure located on the first first-level contact structure. In a top view, the first second-level contact structure includes a first portion located inside the first first-level contact structure and a second portion located outside the first first-level contact structure. The semiconductor structure also includes a first back-side contact structure located on the back-side surface of the first source / drain component. The first back-side contact structure overlaps perpendicularly with the first first-level contact structure and the first second-level contact structure.

[0168] Some embodiments of this application provide a method for forming a semiconductor structure, comprising: forming a first transistor over a substrate, wherein the first transistor includes a first plurality of nanostructures extending longitudinally over a first substrate portion along a first direction, a first source / drain component located on the first substrate portion, and a first gate stack extending longitudinally across the first substrate portion along a second direction and surrounding the first plurality of nanostructures, wherein the second direction is different from the first direction; forming a first contact structure on the first source / drain component, wherein the conductivity of the first contact structure is greater than the conductivity of the first source / drain component; forming a second contact structure on the first contact structure, wherein the second contact structure extends beyond the edge of the first contact structure; removing the substrate; forming a first opening through the first substrate portion to expose a back surface of the first source / drain component; and forming a third contact structure in the first opening, wherein, in a cross-sectional view, the third contact structure is narrower than the first contact structure.

[0169] In some embodiments, the method further includes: forming a via on the second contact structure; and forming a metal line on the via, wherein the metal line extends longitudinally along the first direction and the metal line provides a Vss voltage or a Vdd voltage. In some embodiments, the method further includes: forming a second transistor over the substrate, wherein the second transistor includes a second plurality of nanostructures extending longitudinally over a second substrate portion along the first direction, a second source / drain component located on the second substrate portion, and a first gate stack extending longitudinally across the second substrate portion along the second direction and surrounding the second plurality of nanostructures; forming a gate dicing component through the first gate stack between the first source / drain component and the second source / drain component; and forming a fourth contact structure on the second source / drain component, wherein, in a top view, the second contact structure extends from the first contact structure toward the fourth contact structure.

[0170] In some embodiments, the method further includes: forming a first patterned mask layer over the first transistor and the second transistor, wherein the first patterned mask layer has an opening pattern directly above the first source / drain component and the second source / drain component; forming a second patterned mask layer over the first patterned mask layer, wherein the second patterned mask layer has a mask pattern transverse to the opening pattern and located between the first source / drain component and the second source / drain component, wherein, in a top view, the distance between the opening pattern and the first substrate portion is greater than the distance between the opening pattern and the second substrate portion; etching an interlayer dielectric layer located over the first source / drain component and the second source / drain component to form a first opening exposing the first source / drain component and a second opening exposing the second source / drain component; and forming the first contact structure and the second contact structure in the first opening and the second opening, respectively. In some embodiments, the method further includes: forming a second transistor over the substrate, wherein the second transistor includes a second plurality of nanostructures extending longitudinally along the first direction over a second substrate portion, a second source / drain component located on the second substrate portion, and a first gate stack extending longitudinally along the second direction across the second substrate portion and surrounding the second plurality of nanostructures; forming a fourth contact structure on the second source / drain component, forming a fifth contact structure on the fourth contact structure, wherein the fifth contact structure extends beyond the edge of the fourth contact structure; and forming a first metal line electrically connected to the second contact structure and the fifth contact structure over the second contact structure and the fifth contact structure. In some embodiments, the method further includes: forming a sixth contact structure on the back side of the second source / drain component; and forming a second metal line electrically connected to the third contact structure and the sixth contact structure below the third contact structure and the sixth contact structure. In some embodiments, the top surface of the first contact structure is substantially flush with the top surface of the gate stack. In some embodiments, the method further includes: forming a second transistor over the substrate, wherein the second transistor includes a second plurality of nanostructures extending longitudinally over a second substrate portion along the first direction, a second source / drain component located on the second substrate portion, and a first gate stack extending longitudinally across the second substrate portion along the second direction and surrounding the second plurality of nanostructures, wherein the second contact structure extends to a centerline equidistant from the first substrate portion and the second substrate portion.In some embodiments, the method further includes: forming a second transistor over the substrate, wherein the second transistor includes a second plurality of nanostructures extending longitudinally along the first direction over a second substrate portion, a second source / drain component located on the second substrate portion, and a first gate stack extending longitudinally along the second direction across the second substrate portion and surrounding the second plurality of nanostructures, and wherein the second contact structure extends directly above the second source / drain component. In some embodiments, the first source / drain component is doped with an n-type dopant, and the second source / drain component is doped with a p-type dopant.

[0171] Other embodiments of this application provide a method for forming a semiconductor structure, comprising: forming a plurality of active regions over a substrate, wherein each of the active regions includes a substrate portion and a nanostructure stacked over the substrate portion, and the plurality of active regions extend longitudinally along a first direction; forming an isolation structure adjacent to the substrate portion of the plurality of active regions; forming a plurality of source / drain components on the substrate portion of the active regions, wherein each source / drain component includes a portion suspended above the isolation structure; and forming a plurality of gate stacks across the substrate portion of the plurality of active regions to surround the nanostructure of the active regions; A plurality of front contact structures are formed on the source / drain components; an interlayer dielectric layer is formed above the contact structures; the interlayer dielectric layer is etched to form a trench, wherein the trench extends longitudinally along the first direction and is located between a first active region and a second active region in the plurality of active regions, and the trench exposes the first front contact structure and the second front contact structure in the plurality of front contact structures; a conductive material is formed in the trench; and a metal line is formed below the substrate portion of the first active region and the second active region, wherein the metal line is electrically connected to the first front contact structure, the second front contact structure and the conductive material.

[0172] In some embodiments, the method further includes: forming a gate dicing member through a first gate stack of the plurality of gate stacks, wherein the trench overlaps perpendicularly with the gate dicing member. In some embodiments, in a top view, the trench has an edge having a first surface exposing the first contact structure and a second surface offset relative to the first sidewall, and a connecting wall connecting the first surface and the second surface. In some embodiments, the first front contact plug is located directly above the first active region, and the second front contact plug is located directly above the first active region. In some embodiments, the trench exposes the top surface of the first contact structure. In some embodiments, forming the conductive material in the trench includes: depositing the conductive material in the trench and over the interlayer dielectric layer; and polishing the conductive material until the plurality of front contact structures are exposed. In some embodiments, the method further includes: forming a first back-side contact structure on the back surface of a first source / drain member on the first active region; and forming a second back-side contact structure on the back surface of a second source / drain member on the second active region, wherein the metal wire is formed on the first back-side contact structure and the second contact structure.

[0173] Some embodiments of this application provide a semiconductor structure, including: a first plurality of nanostructures located above a first substrate portion; a gate stack enclosing the first plurality of nanostructures; a first source / drain component adjacent to a first side of the first plurality of nanostructures; a contact etch stop layer covering the first source / drain component; an interlayer dielectric layer located above the contact etch stop layer, wherein the dielectric constant of the contact etch stop layer is different from the dielectric constant of the interlayer dielectric layer; and a first first-level contact structure located on the front surface of the first source / drain component, wherein the first first-level contact structure is electrically coupled to the first source / drain component through a silicide layer. The device includes a source / drain component, wherein the conductivity of the silicide layer is between the conductivity of the first first-level contact structure and the conductivity of the first source / drain component; a first second-level contact structure located on the first first-level contact structure, wherein, in a top view, the first second-level contact structure includes a first portion located inside the first first-level contact structure and a second portion located outside the first first-level contact structure; and a first back-side contact structure located on the back-side surface of the first source / drain component, wherein the first back-side contact structure vertically overlaps the first first-level contact structure and the first second-level contact structure.

[0174] In some embodiments, the semiconductor structure further includes: a second substrate portion laterally spaced from the first substrate portion; a second plurality of nanostructures located above the second substrate portion; a second source / drain component adjacent to a first side of the second plurality of nanostructures; and a second first-level contact structure located on the front surface of the second source / drain component, wherein the first first-level contact structure has an edge located between an edge of the first substrate portion and a center line equidistant from the first substrate portion and the second substrate portion, wherein a first distance between the edge of the first first-level contact structure and the edge of the first substrate portion is less than a second distance between the edge of the first first-level contact structure and the center line. In some embodiments, the semiconductor structure further includes: a second source / drain component adjacent to a second side of the first plurality of nanostructures; a second first-level contact structure located on the front surface of the second source / drain component; a second second-level contact structure located on the second first-level contact structure; a first via located on the first second-level contact structure; a second via located on the second second-level contact structure; a first metal line located on the first via and the second via; and a second back-side contact structure located on the back surface of the second source / drain component.

[0175] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of the embodiments of this disclosure. Those skilled in the art should understand that they can readily use the embodiments of this disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the embodiments of this disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the embodiments of this disclosure.

Claims

1. A method for forming a semiconductor structure, comprising: A first transistor is formed over a substrate, wherein the first transistor includes a first plurality of nanostructures extending longitudinally over a first substrate portion in a first direction, a first source / drain component located on the first substrate portion, and a first gate stack extending longitudinally across the first substrate portion in a second direction and surrounding the first plurality of nanostructures, wherein the second direction is different from the first direction. A first contact structure is formed on the first source / drain component, wherein the conductivity of the first contact structure is greater than the conductivity of the first source / drain component; A second contact structure is formed on the first contact structure, wherein the second contact structure extends beyond the edge of the first contact structure; Remove the substrate; A first opening is formed through the first substrate portion to expose the back surface of the first source / drain component; and A third contact structure is formed in the first opening, wherein, in a cross-sectional view, the third contact structure is narrower than the first contact structure.

2. The method for forming the semiconductor structure according to claim 1, further comprising: A through hole is formed in the second contact structure; as well as A metal wire is formed on the through-hole, wherein the metal wire extends longitudinally along the first direction, and the metal wire provides a Vss voltage or a Vdd voltage.

3. The method for forming the semiconductor structure according to claim 1, further comprising: A second transistor is formed over the substrate, wherein the second transistor includes a second plurality of nanostructures extending longitudinally over the second substrate portion along the first direction, a second source / drain component located on the second substrate portion, and a first gate stack extending longitudinally across the second substrate portion along the second direction and surrounding the second plurality of nanostructures; A gate dicing member is formed by passing through the first gate stack between the first source / drain member and the second source / drain member; and A fourth contact structure is formed on the second source / drain component, wherein, in a top view, the second contact structure extends from the first contact structure toward the fourth contact structure.

4. The method for forming the semiconductor structure according to claim 3, further comprising: A first patterned mask layer is formed above the first transistor and the second transistor, wherein the first patterned mask layer has an opening pattern directly above the first source / drain component and the second source / drain component; A second patterned mask layer is formed above the first patterned mask layer, wherein the second patterned mask layer has a mask pattern that is transverse to the opening pattern and located between the first source / drain component and the second source / drain component, wherein, in a top view, the distance between the opening pattern and the first base portion is greater than the distance between the opening pattern and the second base portion; Etching the interlayer dielectric layer above the first source / drain component and the second source / drain component to form a first opening exposing the first source / drain component and a second opening exposing the second source / drain component; and The first contact structure and the second contact structure are formed in the first opening and the second opening, respectively.

5. The method for forming the semiconductor structure according to claim 1, further comprising: A second transistor is formed over the substrate, wherein the second transistor includes a second plurality of nanostructures extending longitudinally over the second substrate portion along the first direction, a second source / drain component located on the second substrate portion, and a first gate stack extending longitudinally across the second substrate portion along the second direction and surrounding the second plurality of nanostructures; A fourth contact structure is formed on the second source / drain component. A fifth contact structure is formed on the fourth contact structure, wherein the fifth contact structure extends beyond the edge of the fourth contact structure; and A first metal wire electrically connected to the second contact structure and the fifth contact structure is formed above the second contact structure and the fifth contact structure.

6. The method for forming the semiconductor structure according to claim 5, further comprising: A sixth contact structure is formed on the back side of the second source / drain component; as well as A second metal wire electrically connected to the third contact structure and the sixth contact structure is formed below the third contact structure and the sixth contact structure.

7. The method for forming the semiconductor structure according to claim 1, wherein, The top surface of the first contact structure is substantially flush with the top surface of the gate stack.

8. The method for forming the semiconductor structure according to claim 1, further comprising: A second transistor is formed over the substrate, wherein the second transistor includes a second plurality of nanostructures extending longitudinally over the second substrate portion along the first direction, a second source / drain component located on the second substrate portion, and a first gate stack extending longitudinally across the second substrate portion along the second direction and surrounding the second plurality of nanostructures, wherein the second contact structure extends to a centerline equidistant from the first substrate portion and the second substrate portion.

9. A method for forming a semiconductor structure, comprising: A plurality of active regions are formed above a substrate, wherein each of the active regions includes a substrate portion and a nanostructure stacked above the substrate portion, and the plurality of active regions extend longitudinally along a first direction; An isolation structure is formed next to the base portion of the plurality of active regions; A plurality of source / drain components are formed on the substrate portion of the active region, wherein each source / drain component includes a portion suspended above the isolation structure; The substrate portion spanning the plurality of active regions forms a plurality of gate stacks to surround the nanostructure of the active regions; Multiple front-side contact structures are formed on the source / drain components; An interlayer dielectric layer is formed above the contact structure; The interlayer dielectric layer is etched to form a trench, wherein the trench extends longitudinally along the first direction and is located between a first active region and a second active region in the plurality of active regions, and the trench exposes a first front contact structure and a second front contact structure in the plurality of front contact structures. A conductive material is formed in the trench; and A metal line is formed beneath the substrate portion of the first active region and the second active region, wherein the metal line is electrically connected to the first front contact structure, the second front contact structure and the conductive material.

10. A semiconductor structure, comprising: The first plurality of nanostructures are located above the first substrate portion; Gate stacks encapsulate the first plurality of nanostructures; The first source / drain component is adjacent to the first side of the first plurality of nanostructures; A contact etch stop layer is applied to cover the first source / drain components; An interlayer dielectric layer is located above the contact etch stop layer, wherein the dielectric constant of the contact etch stop layer is different from the dielectric constant of the interlayer dielectric layer; A first-level contact structure is located on the front surface of the first source / drain component, wherein the first-level contact structure is electrically coupled to the first source / drain component through a silicide layer, and the conductivity of the silicide layer is between the conductivity of the first-level contact structure and the conductivity of the first source / drain component. A first and second level contact structure is located on the first level contact structure, wherein, in a top view, the first and second level contact structure includes a first portion located inside the first level contact structure and a second portion located outside the first level contact structure; and A first back-side contact structure is located on the back-side surface of the first source / drain component, wherein the first back-side contact structure is perpendicularly overlapped with the first first-level contact structure and the first second-level contact structure.

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