Semiconductor device structure and method of forming the same

Abstract

Methods for forming a semiconductor device structure are provided. A method includes forming a device layer over a substrate. The device layer includes a gate stack and a gate spacer extending along sidewalls of the gate stack, and the gate stack has a gate electrode and a gate dielectric layer. The gate spacer is thicker than the gate dielectric layer, and a dielectric constant of the gate dielectric layer is greater than a dielectric constant of the gate spacer. The method includes forming an interconnect layer over the device layer. The interconnect layer includes a dielectric layer and a wire in the dielectric layer. The method includes forming a first bonding layer over the interconnect layer. The method includes implanting a portion of the first bonding layer. The method includes bonding a carrier substrate to the first bonding layer through a second bonding layer. Embodiments of the present application also relate to semiconductor device structures.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor device structures and methods of forming the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advancements in IC materials and design have resulted in multiple generations of ICs. Each generation features smaller and more complex circuits than the previous one. However, these advancements have increased the complexity of handling and manufacturing ICs.

[0003] In the development of ICs, functional density (i.e., the number of interconnect devices per chip area) has generally increased, while geometric dimensions (i.e., the smallest components (or lines) that can be created using manufacturing processes) have decreased. This miniaturization process typically provides benefits by increasing production efficiency and reducing associated costs.

[0004] However, as component sizes continue to shrink, manufacturing processes become increasingly difficult to implement. Therefore, forming reliable semiconductor devices in ever-smaller dimensions remains a challenge. Summary of the Invention

[0005] Some embodiments of this application provide a method for forming a semiconductor device structure, comprising: forming a device layer over a substrate, wherein the device layer includes a gate stack and a gate spacer extending along a sidewall of the gate stack, the gate stack having a gate electrode and a gate dielectric layer, the gate spacer being thicker than the gate dielectric layer, and the dielectric constant of the gate dielectric layer being greater than the dielectric constant of the gate spacer; forming an interconnect layer over the device layer, wherein the interconnect layer includes a dielectric layer and a conductor located in the dielectric layer; forming a first bonding layer over the interconnect layer; implanting a portion of the first bonding layer; and bonding a carrier substrate to the first bonding layer through a second bonding layer.

[0006] Other embodiments of this application provide a method for forming a semiconductor device structure, comprising: forming a first bonding layer over a carrier substrate; implanting a first portion of the first bonding layer; sequentially forming a device layer, an interconnect layer, and a second bonding layer over the substrate, wherein the device layer includes a channel structure and an epitaxial structure located adjacent to the channel structure, the epitaxial structure having a first portion and a second portion, the second portion being spaced apart from the channel structure by the first portion, the first portion and the second portion having different dopant concentrations, the interconnect layer including a first conductor, a second conductor, a dielectric layer, and a conductive via, the second conductor being closer to the substrate than the first conductor, the first conductor being thicker than the second conductor, the first conductor being located in the dielectric layer, and the conductive via extending through the dielectric layer and electrically connecting the first conductor and the second conductor; and bonding the first bonding layer to the second bonding layer.

[0007] Some embodiments of this application provide a semiconductor device structure, including: a substrate; a first bonding layer located above the substrate; a second bonding layer located above the first bonding layer and having a first doped region doped with a first dopant; an interconnect layer located above the second bonding layer and having a first dielectric layer, a second dielectric layer, a first conductor located in the first dielectric layer and a second conductor located in the second dielectric layer, wherein the first conductor is spaced apart from the second conductor by the first dielectric layer; and a device layer located above the interconnect layer, wherein the first dielectric layer farther from the device layer is thicker than the second dielectric layer closer to the device layer, and the device layer includes a channel structure, an epitaxial structure adjacent to the channel structure, and a titanium-containing gate electrode located above the channel structure. Attached Figure Description

[0008] Various aspects of the embodiments of this disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0009] Figures 1A to 1D This is a top view of various stages of a process for forming a portion of a semiconductor device structure, according to some embodiments.

[0010] Figures 2A to 2D These are cross-sectional views of various stages of a process for forming a portion of a semiconductor device structure, according to some embodiments.

[0011] Figures 3A to 3T These are cross-sectional views of various stages of a process for forming a portion of a semiconductor device structure, according to some embodiments.

[0012] Figures 4A to 4F These are cross-sectional views of various stages of a process for forming a semiconductor device structure, according to some embodiments.

[0013] Figures 5A to 5C These are cross-sectional views of various stages of a process for forming a semiconductor device structure, according to some embodiments. Detailed Implementation

[0014] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of embodiments of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0015] Furthermore, for ease of description, this document uses spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one element or component and another (or other elements or components) as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0016] Those skilled in the art will understand the term "substantially" in the specification (such as "substantially flat" or "substantially coplanar"). In some embodiments, the adjective "substantially" may be removed. Where applicable, the term "substantially" may also include embodiments utilizing "completely," "entirely," "all," etc. The term "substantially" can vary in different technologies and within the range of deviations understood by those skilled in the art. For example, the term "substantially" may also refer to 85% or more of the specified content, such as 95% or more of the specified content, specifically, 99% or more of the specified content, including 100% of the specified content, but embodiments of this disclosure are not limited thereto. Furthermore, terms such as "substantially parallel" or "substantially perpendicular" can be interpreted as not excluding minor deviations from the specified arrangement and may include, for example, deviations up to 10°. The word "substantially" does not exclude "entirely," for example, a composition "substantially free of" Y may be completely free of Y.

[0017] The term "about" can vary across different technologies and is within the range of deviations understood by those skilled in the art. When used in conjunction with a specific distance or dimension, the term "about" should be interpreted as not excluding minor deviations from the specified distance or dimension. For example, the term "about" can include a deviation of up to 10% of the specified content, but embodiments of this disclosure are not limited thereto. The term "about" in relation to a numerical value x can mean ±5% or ±10% of the specified content, but embodiments of this disclosure are not limited thereto.

[0018] Some embodiments of this disclosure are described. Additional operations may be provided before, during, and / or after the stages described in these embodiments. For different embodiments, some of the described stages may be replaced or eliminated. Additional components may be added to the semiconductor device structure. For different embodiments, some of the components described below may be replaced or eliminated. Although some embodiments are discussed using operations performed in a particular order, these operations may be performed in another logical order.

[0019] Embodiments of this disclosure form semiconductor device structures with FinFETs. The bumps can be patterned using any suitable method. For example, the bumps can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, thereby allowing the creation of patterns with a pitch, for example, smaller than that achievable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the bumps. The source / drain structure can refer to a source or a drain, individually or jointly, depending on the context.

[0020] The nanostructure transistors described below (e.g., nanosheet transistors, nanowire transistors, multi-bridge channel transistors, nanoribbon FETs, gate-all-around (GAA) transistor structures) can be patterned using any suitable method. For example, the structure can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, thereby allowing the creation of patterns with, for example, smaller pitches than that achievable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed and patterned using a photolithography process over a substrate. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern a GAA structure.

[0021] Figures 2A to 2DThese are cross-sectional views of various stages of a process for forming a portion of a semiconductor device structure, according to some embodiments. For example... Figure 2A As shown, a substrate 100 is received or provided. In some embodiments, the substrate 100 is a bulk semiconductor substrate, such as a semiconductor wafer. The substrate 100 may include silicon or other elemental semiconductor materials, such as germanium. The substrate 100 may be undoped or doped (e.g., p-type, n-type, or a combination thereof).

[0022] In some other embodiments, substrate 100 comprises a compound semiconductor. For example, the compound semiconductor comprises a semiconductor having the chemical formula Al. X1 Ga X2 In X3 As Y1 P Y2 N Y3 Sb Y4 The composition is defined as one or more group III-V compound semiconductors, wherein X1, X2, X3, Y1, Y2, Y3, and Y4 represent relative proportions. Each of them is greater than or equal to zero, and together they equal 1. The compound semiconductor may include silicon carbide, gallium arsenide, indium arsenide, indium phosphide, one or more other suitable compound semiconductors, or combinations thereof. Other suitable compound semiconductors, including group II-VI compound semiconductors, may also be used.

[0023] In some embodiments, substrate 100 is an active layer of a semiconductor-on-insulator (SOI) substrate. The SOI substrate can be fabricated using a SIMOX process, a wafer bonding process, another suitable method, or a combination thereof. In some other embodiments, substrate 100 comprises a multilayer structure. For example, substrate 100 includes a silicon-germanium layer formed on a bulk silicon layer.

[0024] like Figure 2A As shown, according to some embodiments, a semiconductor stack having multiple semiconductor layers is formed over a substrate 100. In some embodiments, the semiconductor stack includes multiple semiconductor layers 102a, 102b, and 102c. The semiconductor stack also includes multiple semiconductor layers 104a, 104b, and 104c. In some embodiments, semiconductor layers 102a-102c and semiconductor layers 104a-104c are arranged and configured alternately, such as... Figure 2A As shown in the image.

[0025] In some embodiments, semiconductor layers 102a-102c serve as sacrificial layers (or sacrificial nanostructures) to be removed in subsequent processes to release semiconductor layers 104a-104c. The released semiconductor layers 104a-104c may form multiple semiconductor nanostructures and serve as the channel structure for one or more transistors.

[0026] In some embodiments, the semiconductor layers 104a-104c used to form the channel structure are made of a material different from that of semiconductor layers 102a-102c. In some embodiments, semiconductor layers 104a-104c are made of or comprise silicon. In some other embodiments, semiconductor layers 104a-104c are made of or comprise silicon, germanium, another suitable material, or a combination thereof. In some embodiments, semiconductor layers 102a-102c are made of or comprise silicon-germanium.

[0027] In some other embodiments, semiconductor layers 104a-104c are made of silicon-germanium, and semiconductor layers 102a-102c are made of silicon-germanium having a different germanium atom concentration than that of semiconductor layers 104a-104c. Due to the different compositions, different etch selectivity and / or different oxidation rates can be achieved between semiconductor layers 102a-102c and semiconductor layers 104a-104c during subsequent processing.

[0028] Semiconductor layers 102a-102c and semiconductor layers 104a-104c include any combination of semiconductor materials that can provide desired etch selectivity, desired oxidation rate differences and / or desired performance characteristics (e.g., materials that maximize current).

[0029] In some embodiments, semiconductor layers 102a-102c and 104a-104c are formed using multiple epitaxial growth operations. In some embodiments, semiconductor layers 102a-102c and 104a-104c may be configured as a superlattice structure with alternating layers of different semiconductor materials. Each of semiconductor layers 102a-102c and 104a-104c may be formed using selective epitaxial growth (SEG), CVD processes (e.g., vapor phase epitaxy (VPE), low-pressure chemical vapor deposition (LPCVD), ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, one or more other suitable processes, or combinations thereof.

[0030] In some embodiments, semiconductor layers 102a-102c and 104a-104c are grown in situ within the same process chamber. In some embodiments, the growth of semiconductor layers 102a-102c and 104a-104c is performed alternately and sequentially within the same process chamber to complete the formation of the semiconductor stack. In some embodiments, the vacuum of the process chamber is not disrupted until the epitaxial growth of the semiconductor stack is completed.

[0031] Subsequently, hard mask elements are formed over the semiconductor stack to assist in the subsequent patterning of the semiconductor stack. Each hard mask element may include a first mask layer 108 and a second mask layer 110, such as... Figure 2B As shown in the diagram. The first mask layer 108 and the second mask layer 110 can be made of different materials. One or more photolithography processes and one or more etching processes are used to pattern the semiconductor stack into multiple fin structures.

[0032] Fin structures can be patterned using any suitable method. For example, fin structures can be patterned using one or more photolithography processes, including dual patterning or multiple patterning processes. Dual patterning or multiple patterning processes can combine photolithography and self-alignment processes, thereby allowing the creation of patterns with, for example, a smaller pitch than that achievable using a single, direct photolithography process.

[0033] According to some embodiments, the semiconductor stack is partially removed to form multiple fin structures (including fin structures 106A and 106B) and multiple trenches 112, such as Figure 2B As shown in the diagram. During the etching process that forms the fin structure, the substrate 100 may also be partially removed. The protruding portions of the retained substrate 100 form semiconductor protrusions 101A and 101B.

[0034] The fin structure 106A may include portions of semiconductor layers 102a-102c and 104a-104c and an underlying semiconductor protrusion 101A, such as... Figure 2B As shown in the diagram, the fin structure 106B may include portions of semiconductor layers 102a-102c and 104a-104c and the underlying semiconductor protrusion 101B, as... Figure 2B As shown in the image.

[0035] Figures 1A to 1D These are top views of various stages of a process for forming a portion of a semiconductor device structure, according to some embodiments. Figure 1A As shown, according to some embodiments, a plurality of fin structures 106A and 106B are formed. In some embodiments, the fin structures 106A and 106B are longitudinally oriented. In some embodiments, the longitudinal directions of the fin structures 106A and 106B are substantially parallel to each other, as shown. Figure 1A As shown in some embodiments, Figure 2B It is along Figure 1A The cross-sectional view of the structure cut by line 2B-2B in the diagram.

[0036] Subsequently, according to some embodiments, an isolation structure 115 is formed, such as... Figure 1B and Figure 2C As shown in some embodiments, Figure 2C It is along Figure 1B A cross-sectional view of the structure cut by line 2C-2C. (See figure.) Figure 1B As shown, a portion of the isolation structure 115 extends between fin structures 106A and 106B. Figure 2CAs shown, according to some embodiments, the isolation structure 115 is formed laterally around the lower portions of the fin structures 106A and 106B. In some embodiments, the isolation structure 115 includes a dielectric filler 114 and a pad layer 113 adjacent to the semiconductor protrusions 101A and 101B.

[0037] In some embodiments, the isolation structure 115 comprises one or more oxide-based materials. In some embodiments, one or more dielectric layers for forming the dielectric filler 114 are deposited over the fin structures 106A and 106B and the substrate 100. The dielectric layers may be made of silicon oxide, silicon oxynitride, borosilicate glass (BSG), phosphosilicate glass (PSG), borosilicate phosphosilicate glass (BPSG), fluorinated silicate glass (FSG), low-k materials, porous dielectric materials, one or more other suitable materials, or combinations thereof, or may include silicon oxide, silicon oxynitride, borosilicate glass (BSG), phosphosilicate glass (PSG), borosilicate phosphosilicate glass (BPSG), fluorinated silicate glass (FSG), low-k materials, porous dielectric materials, one or more other suitable materials, or combinations thereof.

[0038] The padding layer 113 may be made of or comprise silicon nitride, silicon oxynitride, silicon carbide, silicon carbide, one or more other suitable materials or combinations thereof. The dielectric layer and padding layer 113 may be deposited using a flowable chemical vapor deposition (FCVD) process, an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, one or more other suitable processes or combinations thereof.

[0039] Subsequently, a planarization process is used to partially remove the dielectric layer and pad layer 113. Hard mask elements (including the first mask layer 108 and the second mask layer 110) can also be used as stop layers for the planarization process. The planarization process may include chemical mechanical polishing (CMP), grinding, dry polishing, etching, one or more other suitable processes, or combinations thereof.

[0040] Subsequently, one or more etching processes are used to partially remove the dielectric layer and the pad layer 113. Therefore, the remaining portion of the dielectric layer forms the dielectric filler 114 of the isolation structure 115. The upper portions of the fin structures 106A and 106B protrude from the top surface of the isolation structure 115, as shown... Figure 2C As shown in the image.

[0041] In some embodiments, the etching process used to form the isolation structure 115 is carefully controlled to ensure that the top surface of the isolation structure 115 is positioned at a suitable height level, such as... Figure 2CAs shown in the figure. In some embodiments, the top surface of the isolation structure 115 is located below the bottom surface of the semiconductor layer 102a, which serves as a sacrificial layer. Therefore, the sides of the bottom sacrificial layer (i.e., semiconductor layer 102a) are exposed and not covered by the isolation structure 115, thereby facilitating the subsequent removal process of semiconductor layers 102a-102c.

[0042] In some embodiments, the top surface of the isolation structure 115 is non-planar, such as... Figure 2C As shown in the diagram. In some embodiments, the isolation structure 115 has a first portion PA and a second portion PB. The first portion PA is located next to the semiconductor protrusion 101A. The first portion PA is located between the second portion PB and the semiconductor protrusion 101A, and the first portion PA is thicker than the second portion PB. In some embodiments, the isolation structure 115 gradually becomes thinner in a direction away from the semiconductor protrusion 101A, as shown in the diagram. Figure 2C As shown in the figure. In some embodiments, the first portion PA has a curved upper surface.

[0043] Subsequently, the hard mask elements (including the first mask layer 108 and the second mask layer 110) are removed. Optionally, in some other embodiments, the hard mask elements are removed or consumed during the planarization process and / or etch-back process that forms the isolation structure 115.

[0044] Subsequently, according to some embodiments, dummy gate stacks 120A and 120B are formed to extend across fin structures 106A and 106B, as shown. Figure 1C As shown in some embodiments, Figure 2D It is along Figure 1C A cross-sectional view of the structure cut by the 2D-2D line.

[0045] Figures 3A to 3T These are cross-sectional views of various stages of a process for forming a portion of a semiconductor device structure, according to some embodiments. In some embodiments, Figure 3A It shows along Figure 1C The cross-sectional view of the structure cut from line 3A to 3A.

[0046] like Figure 1C , Figure 2D and Figure 3A As shown, according to some embodiments, dummy gate stacks 120A and 120B partially cover fin structures 106A and 106B and extend across fin structures 106A and 106B. In some embodiments, dummy gate stacks 120A and 120B enclose fin structures 106A and 106B.

[0047] like Figure 2D As shown, the dummy gate stack 120B extends across and encloses fin structures 106A and 106B. Figure 1CAs shown, other portions of fin structures 106A and 106B are exposed and not covered by dummy gate stacks 120A or 120B. In some embodiments, dummy gate stacks 120A and 120B are longitudinally oriented along a first direction, while fin structures 106A and 106B are longitudinally oriented along a second direction other than the first direction. In some embodiments, the first direction is substantially perpendicular to the second direction, such as... Figure 1C As shown in the figure. In some embodiments, a portion of the isolation structure 115 is disposed between the fin structures 106A and 106B.

[0048] like Figure 2D and Figure 3A As shown, each of the dummy gate stacks 120A and 120B includes a dummy gate dielectric layer 116 and a dummy gate electrode 118. The dummy gate dielectric layer 116 may be made of or comprise silicon oxide or another suitable material. The dummy gate electrode 118 may be made of or comprise polysilicon or another suitable material.

[0049] In some embodiments, a dummy gate dielectric layer and a dummy gate electrode layer are sequentially deposited over the isolation structure 115 and the fin structures 106A and 106B. The dummy gate dielectric layer can be deposited using an ALD process, a CVD process, one or more other suitable processes, or a combination thereof. The dummy gate electrode layer can be deposited using a CVD process. Subsequently, the dummy gate dielectric layer and the dummy gate electrode layer are patterned to form dummy gate stacks 120A and 120B.

[0050] In some embodiments, hard mask elements 122 and 124 are used to assist in the patterning process for forming dummy gate stacks 120A and 120B. Using hard mask elements 122 and 124 as etch masks, one or more etch processes are used to partially remove the dummy gate dielectric material layer and the dummy gate electrode layer. Therefore, the remaining portions of the dummy gate dielectric material layer and the dummy gate electrode layer form the dummy gate stacks 120A and 120B.

[0051] Subsequently, according to some embodiments, one or more spacer layers are deposited over the dummy gate stacks 120A and 120B, the fin structures 106A and 106B, and the exposed portions of the isolation structure 115. The spacer layers extend along the top and sidewalls of the dummy gate stacks 120A and 120B. The spacer layers also extend along the top of the fin structures 106A and 106B.

[0052] In some embodiments, the spacer layers are made of different materials. In some other embodiments, the spacer layers are made of the same material. The spacer layers may be made of silicon nitride, silicon carbide, silicon carbide oxide, silicon carbide oxide, silicon oxide, another suitable material, or a combination thereof, or may include silicon nitride, silicon carbide, silicon carbide oxide, silicon carbide oxide, silicon oxide, another suitable material, or a combination thereof. The spacer layers may be deposited sequentially using CVD, ALD, physical vapor deposition (PVD), another suitable process, or a combination thereof.

[0053] Subsequently, according to some embodiments, the spacer layer is partially removed. One or more anisotropic etching processes can be used to partially remove the spacer layer. Therefore, the remaining portion of the spacer layer forms the gate spacer 128', as... Figure 1D and Figure 3B As shown in some embodiments, Figure 3B It shows along Figure 1D The cross-sectional view of the structure cut by line 3B to 3B.

[0054] According to some embodiments, the gate spacer 128' extends along the sidewalls of the dummy gate stacks 120A and 120B, such as Figure 3B As shown in the diagram. In some embodiments, similar to the dummy gate stacks 120A and 120B, the gate spacer 128' extends longitudinally along a first direction, while the fin structures 106A and 106B extend longitudinally along a second direction other than the first direction. In some embodiments, the first direction is substantially perpendicular to the second direction.

[0055] Subsequently, fin structures 106A and 106B are partially removed to form multiple grooves 130 for accommodating subsequently formed epitaxial structures, which can then be used as source / drain structures. Figure 3B One of the grooves 130 is shown in the figure. For example... Figure 3B As shown, the groove 130 exposes the sides of the semiconductor layers 104a-104c, and an epitaxial structure, such as a source / drain structure, will subsequently be formed on the sides of the semiconductor layers 104a-104c. A source / drain structure can refer to either a source structure or a drain structure, either alone or together, depending on the context.

[0056] One or more etching processes can be used to form the groove 130. In some embodiments, a dry etching process is used to form the groove 130. Alternatively, a wet etching process can be used to form the groove 130. In some embodiments, the groove 130 extends into the fin structure 106A. In some embodiments, the groove 130 further extends into the semiconductor protrusion 101A, such as... Figure 3BAs shown in the figure. In some embodiments, the gate spacer 128' and the recess 130 are formed simultaneously using the same etching process performed in the same process chamber.

[0057] In some embodiments, the recess 130 has substantially vertical sidewalls. The profile of the recess 130 can be precisely adjusted by adjusting the etching process parameters. In these cases, due to the profile of the recess 130, the upper semiconductor layer (such as semiconductor layer 104c) is substantially the same width as the lower semiconductor layer (such as semiconductor layer 104b).

[0058] However, the embodiments of this disclosure have many variations. In some other embodiments, each of the recesses 130 has sloping sidewalls. The upper portion of the recess 130 is larger (or wider) than the lower portion of the recess 130. In these cases, due to the contour of the recess 130, the upper semiconductor layer (such as semiconductor layer 104c) is narrower than the lower semiconductor layer (such as semiconductor layer 104b).

[0059] Subsequently, the semiconductor layers 102a-102c, which serve as sacrificial layers, are removed. Therefore, according to some embodiments, a [structure / form] is formed. Figure 3C The structure shown is illustrated. Semiconductor layers 102a-102c can be removed using one or more etching processes. After removing semiconductor layers 102a-102c, multiple recesses 202 are formed, as shown... Figure 3C As shown in the image.

[0060] The remaining portion of semiconductor layers 104a-104c released from semiconductor layers 102a-102c forms multiple semiconductor nanostructures 104a', 104b', and 104c', such as Figure 3C As shown. Supported by dummy gate stacks 120A and 120B (see also...) Figure 2D After removing the semiconductor layers 102a-102c, the semiconductor nanostructures 104a'-104c' remain firmly in place.

[0061] Subsequently, according to some embodiments, a dielectric layer is deposited to overfill the groove 202 and to surround the semiconductor nanostructures 104a'-104c'. The dielectric layer may also extend over the top and sidewalls of the dummy gate stacks 120A and 120B.

[0062] The dielectric layer may be made of oxide materials, nitride materials, another suitable material, or combinations thereof. The dielectric layer may be made of silicon oxide, silicon oxynitride, aluminum oxide, silicon nitride, another suitable material, or combinations thereof, or may include silicon oxide, silicon oxynitride, aluminum oxide, silicon nitride, another suitable material, or combinations thereof.

[0063] In some embodiments, the dielectric layer is a single layer. In some other embodiments, the dielectric layer comprises multiple sublayers. In some embodiments, the sublayers of the dielectric layer are made of the same material. In some other embodiments, some of the sublayers of the dielectric layer are made of different materials.

[0064] The dielectric layer can be deposited using CVD, ALD, flowable chemical vapor deposition (FCVD), another suitable process, or a combination thereof. In some embodiments, the formation of the dielectric layer also involves one or more etching processes for shaping the profile of the deposited sublayer of the dielectric layer.

[0065] like Figure 3D As shown, according to some embodiments, a plurality of dielectric nanostructures 206a, 206b, and 206c are formed in the groove 202. In some embodiments, one or more etching processes are used to partially remove the previously deposited dielectric layer. The portion of the dielectric layer located outside the groove 202 is removed. Therefore, the remaining portion of the dielectric layer forms the dielectric nanostructures 206a, 206b, and 206c, as shown. Figure 3D As shown in the figure, dielectric nanostructures 206a, 206b, and 206c can be used as sacrificial nanostructures.

[0066] like Figure 3E As shown, according to some embodiments, dielectric nanostructures 206a-206c are partially removed to pull back the sides of the dielectric nanostructures 206a-206c. One or more etching processes can be used to partially remove the dielectric nanostructures 206a-206c. Therefore, the sides of the dielectric nanostructures 206a-206c recede from the sides of the semiconductor nanostructures 104a'-104c'. Figure 3E As shown, grooves 132A, 132B, and 132C are formed by the lateral etching of dielectric nanostructures 206a-206c. Grooves 132A-132C can be used to accommodate internal spacers that will be formed later.

[0067] In some embodiments, the lower recess (such as recess 132A) is wider or deeper than the upper recess (such as recess 132B). Figure 3E As shown, groove 132A has a depth DA, groove 132B has a depth DB, and groove 132C has a depth DC. In some embodiments, depth DA is greater than depth DB, and depth DB is greater than depth DC. In some other embodiments, depths DA, DB, and DC are substantially equal to each other.

[0068] like Figure 3FAs shown, according to some embodiments, a plurality of internal spacers 136A, 136B, and 136C are formed. In some embodiments, an insulating layer is deposited to overfill grooves 132A-132C. The insulating layer may be made of or comprise silicon carbide (SiCN), silicon carbide oxynitride (SiOCN), silicon carbide oxynitride (SiOC), silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, another suitable material, or a combination thereof, or may include silicon carbide (SiCN), silicon carbide oxynitride (SiOCN), silicon carbide oxynitride (SiOC), silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, another suitable material, or a combination thereof.

[0069] In some embodiments, the dielectric nanostructures 206a-206c are made of silicon oxide, and the insulating layer is made of silicon oxynitride, silicon nitride, another suitable material, or a combination thereof.

[0070] In some embodiments, the dielectric nanostructures 206a-206c are made of silicon oxynitride, and the insulating layer is made of carbon-containing silicon oxynitride, another suitable material, or a combination thereof. In some embodiments, the dielectric nanostructures 206a-206c are made of aluminum oxide, and the insulating layer is made of carbon-containing silicon oxynitride, another suitable material, or a combination thereof.

[0071] In some embodiments, the insulating layer used to form the internal spacers 136A-136C is a single layer. In some other embodiments, the insulating layer comprises multiple sublayers. Some of the sublayers may be made of different materials and / or contain different compositions. The insulating layer may be deposited using a CVD process, an ALD process, another suitable process, or a combination thereof.

[0072] Subsequently, one or more etching processes are used to partially remove the insulating layer. The portion of the insulating layer located outside the grooves 132A-132C is removed. Therefore, according to some embodiments, the remaining portion of the insulating layer forms the internal spacers 136A-136C, such as... Figure 3F As shown in the diagram. One or more etching processes may include dry etching, wet etching, or a combination thereof.

[0073] Internal spacers 136A-136C cover the sides of dielectric nanostructures 206a-206c, such as Figure 3F As shown in the diagram, the internal spacers 136A-136C can be used to prevent damage to subsequently formed epitaxial structures (e.g., those used as source / drain structures) during subsequent processes for removing dielectric nanostructures 206a-206c.

[0074] In some embodiments, the internal spacers 136A-136C are made of a low-k material having a dielectric constant lower than that of silicon oxide. In these cases, the internal spacers 136A-136C can also be used to reduce the parasitic capacitance between the subsequently formed source / drain structure and the gate stack. Therefore, the operating speed of the semiconductor device structure can be improved.

[0075] like Figure 3F As shown, internal spacer 136A has a width WA, internal spacer 136B has a width WB, and internal spacer 136C has a width WC. In some embodiments, width WA is greater than width WB, and width WB is greater than width WC. In some other embodiments, widths WA, WB, and WC are substantially equal to each other.

[0076] like Figure 3G As shown, according to some embodiments, a semiconductor interposer 137 and an interposer 208 are sequentially formed above the bottom of the recess 130. In some embodiments, the semiconductor interposer 137 is an undoped epitaxial structure. In some embodiments, the semiconductor interposer 137 is substantially free of n-type or p-type dopant. The semiconductor interposer 137 can be used as an isolation structure.

[0077] In some embodiments, the semiconductor interposer 137 is a single-layer structure. In some other embodiments, the semiconductor interposer 137 includes multiple sublayers. The semiconductor interposer 137 can help reduce or prevent current leakage from the epitaxial structure that will be formed later. The semiconductor interposer 137 can provide a relatively flat surface to facilitate the subsequent formation of the epitaxial structure.

[0078] Semiconductor interposer 137 may be made of or comprise silicon, silicon germanium, another suitable material, or a combination thereof. Semiconductor interposer 137 may be formed using selective epitaxial growth (SEG) processes, CVD processes (e.g., vapor phase epitaxy (VPE), low-pressure chemical vapor deposition (LPCVD), ultra-high vacuum CVD (UHV-CVD) processes), molecular beam epitaxy, another suitable process, or a combination thereof.

[0079] In some embodiments, the formation of the semiconductor interposer 137 involves one or more etching processes for precisely shaping the contour of the semiconductor interposer 137. The etching process may also remove epitaxial material grown on the sides of the semiconductor nanostructures 104a'-104c' during the formation of the semiconductor interposer 137.

[0080] Intermediate component 208 may be made of or include a dielectric material. Intermediate component 208 may be made of or include silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride, silicon carbide, another suitable material or a combination thereof.

[0081] In some other embodiments, the interfacing component 208 is made of or comprises a semiconductor material. In some embodiments, the interfacing component 208 is a single-layer structure. In some other embodiments, the interfacing component 208 comprises multiple sublayers.

[0082] In some embodiments, a dielectric layer (such as a silicon nitride layer) is deposited over the dummy gate stacks 120A and 120B and the sidewalls of the recess 130. A barrier layer is formed and then etched back over the dielectric layer. After the etch-back barrier layer, the upper portion of the dielectric layer is exposed. The exposed portion of the dielectric layer is then removed. The barrier layer is then removed.

[0083] The remaining portion of the dielectric layer has a thinner portion extending along the sidewall of the groove 130 and a thicker portion positioned directly above the semiconductor interposer 137. The dielectric layer is then thinned using an etching process. Thus, the thinner portion extending along the sidewall of the groove 130 is removed. The thicker portion positioned directly above the semiconductor interposer 137 becomes thinner and forms the interposer 208.

[0084] like Figure 3H As shown, according to some embodiments, epitaxial structures 138 are formed above the sides of the intermediate component 208 and the semiconductor nanostructures 104a'-104c'. Multiple epitaxial structures 138 are formed adjacent to the semiconductor nanostructures 104a'-104c'. Figure 3H Only one of the extensional structures 138 is shown in the diagram.

[0085] In some embodiments, the epitaxial structure 138 is connected to the semiconductor nanostructures 104a'-104c'. In some embodiments, the epitaxial structure 138 passes through the filled groove 130 to ensure full contact with the sidewalls of the adjacent semiconductor nanostructures 104a'-104c'.

[0086] In some embodiments, the epitaxial structure 138 has a lightly doped first portion 138a adjacent to the semiconductor nanostructures 104a'-104c'. In some embodiments, the epitaxial structure 138 also has a second portion 138b spaced apart from the sidewalls of the semiconductor nanostructures 104a'-104c' by the first portion 138a.

[0087] In some embodiments, the epitaxial structure 138 further includes a third portion 138c surrounded by the second portion 138b. In some embodiments, the first portion 138a, the second portion 138b, and the third portion 138c of the epitaxial structure 138 are doped with the same dopant but have different dopant concentrations. In some embodiments, the third portion 138c has a higher dopant concentration than the second portion 138b, and the second portion 138b, in turn, has a higher dopant concentration than the first portion 138a.

[0088] In some embodiments, the epitaxial structure 138 is an n-type doped epitaxial structure. The epitaxial structure 138 may include epitaxially grown silicon, epitaxially grown silicon germanium (SiGe), or another suitable epitaxially grown semiconductor material. The n-type dopant may include phosphorus (P), antimony (Sb), arsenic (As), another suitable element, or a combination thereof.

[0089] In some embodiments, the epitaxial structure 138 is a p-type doped epitaxial structure. The epitaxial structure 138 may include epitaxially grown silicon germanium (SiGe), epitaxially grown silicon, or another suitable epitaxially grown semiconductor material. In some embodiments, the epitaxial structure 138 is doped with one or more suitable p-type dopants. For example, the epitaxial structure 138 is a SiGe source / drain component doped with boron (B), gallium (Ga), indium (In), or another suitable dopant.

[0090] In some embodiments, the epitaxial structure 138 is doped in situ during epitaxial growth. The initial reactive gas mixture used to form the epitaxial structure 138 contains a dopant. In some other embodiments, the epitaxial structure 138 is not doped during its growth. Instead, after the formation of the epitaxial structure 138, it is doped in a subsequent process.

[0091] In some embodiments, doping is achieved using an ion implantation process, a plasma immersion ion implantation process, a gas and / or solid source diffusion process, another suitable process, or a combination thereof. In some embodiments, the epitaxial structure 138 is further exposed to one or more annealing processes to activate the dopant. For example, a rapid thermal annealing process is used.

[0092] In some embodiments, the formation of the epitaxial structure 138 involving thermal processing is performed after the semiconductor layers 102a-102c are replaced with dielectric nanostructures 206a-206c. Because the semiconductor layers 102a-102c have been previously removed, germanium diffusion from these layers into the nearby semiconductor nanostructures 104a'-104c' is prevented during the formation of the epitaxial structure 138. Therefore, the semiconductor nanostructures 104a'-104c' can have a low atomic concentration of germanium impurities, enhancing the quality and reliability of the semiconductor nanostructures 104a'-104c'.

[0093] like Figure 3I As shown, according to some embodiments, a contact etch stop layer 139 and a dielectric layer 140 are sequentially formed over the epitaxial structure 138 to laterally surround the dummy gate stacks 120A and 120B. The contact etch stop layer 139 may be made of silicon nitride, silicon oxynitride, silicon carbide, aluminum oxide, another suitable material, or a combination thereof, or may include silicon nitride, silicon oxynitride, silicon carbide, aluminum oxide, another suitable material, or a combination thereof.

[0094] The dielectric layer 140 may be made of silicon oxide, silicon oxynitride, borosilicate glass (BSG), phosphosilicate glass (PSG), borosilicate phosphosilicate glass (BPSG), fluorinated silicate glass (FSG), low-k material, porous dielectric material, another suitable material, or a combination thereof, or may include silicon oxide, silicon oxynitride, borosilicate glass (BSG), phosphosilicate glass (PSG), borosilicate phosphosilicate glass (BPSG), fluorinated silicate glass (FSG), low-k material, porous dielectric material, another suitable material, or a combination thereof.

[0095] In some embodiments, an etch stop material layer and a dielectric material layer are deposited sequentially. The etch stop material layer can be deposited using a CVD process, an ALD process, a PVD process, one or more other suitable processes, or a combination thereof. The dielectric material layer can be deposited using an FCVD process, a CVD process, an ALD process, another suitable process, or a combination thereof.

[0096] Subsequently, a planarization process is used to partially remove the etch stop material layer and the dielectric material layer. Therefore, the remaining portions of the etch stop material layer and the dielectric material layer form the contact etch stop layer 139 and the dielectric layer 140, respectively. Figure 3I As shown in the figure. Planarization processes may include CMP processes, grinding processes, etching processes, dry polishing processes, one or more other suitable processes, or combinations thereof.

[0097] In some embodiments, hard mask elements 122 and 124 defining dummy gate stacks 120A and 120B are removed during the planarization process. In some embodiments, after the planarization process, the top surfaces of the contact etch stop layer 139, dielectric layer 140, gate spacer 128', and dummy gate electrode 118 are substantially flush, as... Figure 3I As shown in the image.

[0098] After that, as Figure 3J As shown, according to some embodiments, dummy gate stacks 120A and 120B and dielectric nanostructures 206a-206c (which serve as sacrificial nanostructures) are removed. In some embodiments, one or more etching processes are used to remove the dummy gate stacks 120A and 120B and dielectric nanostructures 206a-206c. Thus, a plurality of trenches 142 and recesses 144 are formed, as... Figure 3J As shown in the image.

[0099] Due to high etch selectivity, the semiconductor nanostructures 104a'-104c' are etched only slightly (or essentially not). The semiconductor nanostructures 104a'-104c' suspended above the semiconductor protrusions 101A and 101B can be used as the channel structure for transistors.

[0100] In some other embodiments, the etchant used to remove the dielectric nanostructures 206a-206c also slightly removes the semiconductor nanostructures 104a'-104c'. Therefore, after removing the dielectric nanostructures 206a-206c, the resulting semiconductor nanostructures 104a'-104c' become thinner.

[0101] In some embodiments, the internal portions of the semiconductor nanostructures 104a'-104c' are substantially the same thickness as the edge portions of the semiconductor nanostructures 104a'-104c'. In some other embodiments, the internal portions of the semiconductor nanostructures 104a'-104c' are thinner than the edge portions of the semiconductor nanostructures 104a'-104c'.

[0102] After removing the dielectric nanostructures 206a-206c (which serve as sacrificial nanostructures), a groove 144 is formed. Grooves 144 surround each of the semiconductor nanostructures 104a'-104c'. Figure 3J As shown, although a groove 144 is formed between semiconductor nanostructures 104a'-104c', adjacent elements such as epitaxial structure 138 continue to support semiconductor nanostructures 104a'-104c'. Therefore, after the removal of dummy gate stacks 120A and 120B and dielectric nanostructures 206a-206c, the released semiconductor nanostructures 104a'-104c' remain in place.

[0103] like Figure 3K As shown, according to some embodiments, metal gate stacks 156A and 156B are formed to fill trench 142. The metal gate stacks 156A and 156B further extend into recess 144 to enclose each of semiconductor nanostructures 104a'-104c'.

[0104] Each of the metal gate stacks 156A and 156B includes multiple metal gate stack layers. The metal gate stack layers of the metal gate stacks 156A and 156B may include a gate dielectric layer 150, a power function adjustment layer 152, and a conductive filler 154. The power function adjustment layer 152 and the conductive filler 154 can be used together as the gate electrode of the metal gate stacks 156A and 156B.

[0105] In some embodiments, the formation of metal gate stacks 156A and 156B involves the deposition of a plurality of metal gate stack layers filling trench 142 and recess 144. The metal gate stack layers extend into the recess 144 to enclose each of the semiconductor nanostructures 104a'-104c'.

[0106] In some embodiments, the gate dielectric layer 150 is made of or comprises a dielectric material having a high dielectric constant (high K). In some embodiments, the gate dielectric layer 150 has a higher dielectric constant than the gate spacer 128'. In some embodiments, the gate dielectric layer 150 has a higher dielectric constant than the inner spacers 136A-136C.

[0107] In some embodiments, the gate dielectric layer 150 is thinner than each of the gate spacer 128' and the inner spacers 136A-136C. In some embodiments, a contact etch stop layer 139 is located between the gate dielectric layer 150 and the dielectric layer 140, as shown below. Figure 3K As shown in the image.

[0108] The gate dielectric layer 150 may be made of or comprise a metal-containing dielectric material. The gate dielectric layer 150 may be made of or comprise hafnium oxide, zirconium oxide, aluminum oxide, hafnium dioxide-alumina alloy, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, one or more other suitable high-k materials, or combinations thereof. The gate dielectric layer 150 may be deposited using ALD, CVD, one or more other suitable processes, or combinations thereof.

[0109] In some embodiments, an interface layer is formed on the surface of the semiconductor nanostructures 104a'-104c' prior to the formation of the gate dielectric layer 150. The interface layer is very thin and is made of, for example, silicon oxide or germanium oxide.

[0110] In some embodiments, the interface layer is formed by applying an oxidant to the surface of the semiconductor nanostructures 104a'-104c'. For example, a liquid containing hydrogen peroxide may be applied to or provided to the surface of the semiconductor nanostructures 104a'-104c' to form the interface layer.

[0111] The power function adjustment layer 152 can be used to provide the desired power function to the transistor to enhance device performance, including an improved threshold voltage. In some embodiments, the power function adjustment layer 152 surrounding the semiconductor nanostructures 104a'-104c' is used to form an NMOS device. The power function adjustment layer 152 is an n-type power function adjustment layer. The n-type power function adjustment layer is capable of providing a power function value suitable for the device, such as equal to or less than about 4.5 eV.

[0112] The n-type work function adjustment layer may include a metal, a metal carbide, a metal nitride, or a combination thereof. For example, the n-type work function adjustment layer includes titanium nitride, tantalum, tantalum nitride, one or more other suitable materials, or a combination thereof. In some embodiments, the n-type work function is a titanium-containing layer. The titanium-containing layer may be made of TiAl, TiAlC, TiAlO, TiAlN, one or more other suitable materials, or a combination thereof, or may include TiAl, TiAlC, TiAlO, TiAlN, one or more other suitable materials, or a combination thereof.

[0113] In some embodiments, the power function adjustment layer 152 surrounding the semiconductor nanostructures 104a'-104c' is used to form a PMOS device. In these cases, the power function adjustment layer 152 is a p-type power function adjustment layer. The p-type power function adjustment layer is capable of providing a power function value suitable for the device, such as equal to or greater than about 4.8 eV.

[0114] The p-type work function adjustment layer may include a p-type metal, a metal carbide, a metal nitride, another suitable material, or a combination thereof. For example, the p-type metal includes titanium nitride, tantalum nitride, tungsten nitride, titanium, one or more other suitable materials, or a combination thereof. In some embodiments, the p-type work function adjustment layer is a titanium-containing layer.

[0115] The power function adjustment layer 152 may also be made of hafnium, zirconium, titanium, tantalum, aluminum, metal carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, aluminum carbide), aluminum compounds, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides, or combinations thereof, or may include hafnium, zirconium, titanium, tantalum, aluminum, metal carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, aluminum carbide), aluminum compounds, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides, or combinations thereof. The thickness and / or composition of the power function adjustment layer 152 can be precisely adjusted to adjust the power function level.

[0116] The power function adjustment layer 152 can be deposited over the gate dielectric layer 150 using ALD, CVD, PVD, electroplating, electroless plating, one or more other suitable processes, or combinations thereof. In some embodiments, the formation of the power function adjustment layer involves one or more patterning processes. Therefore, the n-type power function adjustment layer and the p-type power function adjustment layer can be selectively formed over different regions.

[0117] In some embodiments, different portions of the metal gate stacks 156A and 156B encapsulate semiconductor nanostructures 104a'-104c' of different devices, including PMOS and NMOS devices. Therefore, different portions of the metal gate stacks 156A and 156B have different types or different combinations of power function adjustment layers. Multiple deposition processes and multiple patterning processes can be used to selectively form different power function adjustment layers at different portions of the metal gate stacks 156A and 156B.

[0118] In some embodiments, a barrier layer is formed before the power function adjustment layer 152 to make the gate dielectric layer 150 interface with the subsequently formed power function adjustment layer 152. The barrier layer may also be used to prevent diffusion between the gate dielectric layer 150 and the subsequently formed power function adjustment layer 152.

[0119] The barrier layer may be made of or comprise a metal-containing material. Metal-containing materials may include titanium nitride, tantalum nitride, one or more other suitable materials, or combinations thereof. The barrier layer may be deposited using ALD, CVD, PVD, electroplating, electroless plating, one or more other suitable processes, or combinations thereof.

[0120] In some embodiments, the conductive filler 154 of the metal gate stacks 156A and 156B is made of or comprises a metallic material. The metallic material may include tungsten, aluminum, copper, cobalt, one or more other suitable materials, or combinations thereof. A conductive layer for forming the conductive filler 154 may be deposited over the power function adjustment layer 152 using CVD, ALD, PVD, electroplating, electroless plating, one or more other suitable processes, or combinations thereof.

[0121] In some embodiments, a barrier layer is formed over the power function adjustment layer 152 prior to the formation of the conductive layer for forming the conductive filler 154. The barrier layer can be used to prevent the subsequently formed conductive layer from diffusing or penetrating into the power function adjustment layer 152.

[0122] The barrier layer may be made of tantalum nitride, titanium nitride, one or more other suitable materials, or a combination thereof, or may include tantalum nitride, titanium nitride, one or more other suitable materials, or a combination thereof. The barrier layer may be deposited using ALD, PVD, electroplating, electroless plating, one or more other suitable processes, or a combination thereof.

[0123] Subsequently, according to some embodiments, a planarization process is performed to remove portions of the metal gate stack layer located outside the trenches 142 and recesses 144. Therefore, the remaining portions of the metal gate stack layer form metal gate stacks 156A and 156B, as... Figure 3K As shown in the image.

[0124] In some embodiments, the groove 144 is filled after the functional adjustment layer 152 is formed. Therefore, according to some embodiments, it is possible to prevent the subsequently formed conductive filler 154 from entering the groove 144, such as... Figure 3K As shown in the figure. In some embodiments, conductive filler 154 fills the remaining spacing of trench 142.

[0125] like Figure 3K As shown, each of the metal gate stacks 156A and 156B has an upper portion positioned above the semiconductor nanostructure 104c'. Each of the metal gate stacks 156A and 156B also has a lower portion positioned below the semiconductor nanostructure 104c'.

[0126] like Figure 3K As shown, the lower portion has: a first portion with a width W1, a second portion with a width W2, and a third portion with a width W3. The third portion is positioned between semiconductor nanostructures 104c' and 104b' and is located next to the internal spacer 136C. The second portion is positioned between semiconductor nanostructures 104b' and 104a' and is located next to the internal spacer 136B.

[0127] The first portion is positioned between the semiconductor nanostructure 104a' and the semiconductor protrusion 101A, and is located next to the internal spacer 136A. In some embodiments, the width W3 is greater than the width W2, and the width W2 is in turn greater than the width W1.

[0128] In some embodiments, prior to the formation of the epitaxial structure 138, the semiconductor layers 102a-102c are replaced with dielectric nanostructures 206a-206c. During the thermal process for forming the epitaxial structure 138, the germanium-containing semiconductor layers 102a-102c have been removed. Therefore, the diffusion of germanium impurities from the semiconductor layers 102a-102c to the semiconductor nanostructures 104a'-104c' is significantly reduced or prevented.

[0129] Therefore, the semiconductor nanostructures 104a'-104c' have a low atomic concentration of germanium impurities, which enhances the quality and reliability of the semiconductor nanostructures 104a'-104c'. The semiconductor nanostructures 104a'-104c' can have an atomic concentration of germanium impurities ranging from about 0% to about 0.01%.

[0130] In some embodiments, the semiconductor nanostructures 104a'-104c' are primarily composed of silicon, which imparts high etch selectivity compared to the dielectric nanostructures 206a-206c. Therefore, removing the dielectric nanostructures 206a-206c and releasing the semiconductor nanostructures 104a'-104c' requires no or only minimal over-etching. This significantly reduces the surface roughness of the semiconductor nanostructures 104a'-104c', which in turn reduces current congestion and surface scattering. Consequently, the electrical properties of the semiconductor nanostructures 104a'-104c', including carrier mobility, are enhanced.

[0131] like Figure 3L As shown, according to some embodiments, an etch stop layer 158 and a dielectric layer 160 are deposited sequentially. The material and formation method of the etch stop layer 158 may be the same as or similar to those of the contact etch stop layer 139. The material and formation method of the dielectric layer 160 may be the same as or similar to those of the dielectric layer 140.

[0132] Subsequently, according to some embodiments, a metal-semiconductor compound structure 162 and a conductive contact 164 are formed, such as... Figure 3L As shown in the figure. In some embodiments, dielectric layer 160, etch stop layer 158, dielectric layer 140 and contact etch stop layer 139 are partially removed to form contact openings that expose the epitaxial structure 138.

[0133] Next, a protective layer 159 is deposited over the sidewalls and bottom of the contact opening. Then, one or more etching processes are used to remove the portion of the protective layer 159 located at the bottom of the contact opening and to deepen the contact opening. Thus, the contact opening extends further into the epitaxial structure 138.

[0134] Following a cleaning operation on the surface of the epitaxial structure 138, a metal layer (such as titanium and / or nickel) is deposited on the epitaxial structure 138. A thermal operation can be used to initiate a reaction between the metal layer and the epitaxial structure 138. This forms a metal-semiconductor compound structure 162. The remaining portion of the metal layer extending on the sidewalls of the contact opening can then be removed using a cleaning operation.

[0135] Next, a conductive layer is deposited to overfill the contact openings. The conductive layer can be made of tungsten, cobalt, ruthenium, titanium, another suitable material, or a combination thereof, or may include tungsten, cobalt, ruthenium, titanium, another suitable material, or a combination thereof. The conductive layer can be deposited using CVD, ALD, PVD, electroplating, another suitable process, or a combination thereof. A planarization process (such as CMP) is then used to remove the portion of the conductive layer outside the contact openings.

[0136] Therefore, according to some embodiments, the remaining portion of the conductive layer forms a conductive contact 164, such as... Figure 3L As shown in the diagram, the conductive contact 164 can be used as a front conductive structure electrically connected to the epitaxial structure 138.

[0137] In some embodiments, the conductivity of the metal-semiconductor compound structure 162 is between the conductivity of the epitaxial structure 138 and the conductivity of the conductive contact 164. In some embodiments, each of the metal-semiconductor compound structure 162 and the conductive contact 164 has a higher conductivity than the epitaxial structure 138. In some embodiments, the metal-semiconductor compound structure 162 includes a curved profile, such as... Figure 3L As shown in the image.

[0138] like Figure 3L As shown, according to some embodiments, a transistor 7 is formed together by a metal gate stack 156A or 156B, a semiconductor nanostructure 104a'-104c' surrounded by the corresponding metal gate stack 156A or 156B, internal spacers 136A, 136B and 136C located on opposite sides of the corresponding metal gate stack 156A or 156B, and an epitaxial structure 138 located on opposite sides of the corresponding metal gate stack 156A or 156B.

[0139] According to some embodiments, transistor 7, semiconductor interposer 137, interposer 208, contact etch stop layer 139, dielectric layer 140, etch stop layer 158, dielectric layer 160, protective layer 159, metal-semiconductor compound structure 162, and conductive contact 164 are collectively referred to as device layer 10.

[0140] like Figure 3L and Figure 3MAs shown, according to some embodiments, an interconnect layer 320 is formed above the device layer 10. According to some embodiments, the interconnect layer 320 includes a dielectric layer 322, a conductor 324, and a conductive via 326. According to some embodiments, the conductor 324 is located in the dielectric layer 322. According to some embodiments, the conductive via 326 is located in the dielectric layer 322.

[0141] According to some embodiments, the conductive via 326 extends through the dielectric layer 322 and is electrically connected between the wires 324 and between the wires 324 and the transistors 7 of the device layer 10.

[0142] According to some embodiments, dielectric layer 322 includes dielectric layers 322a, 322b, and 322c. According to some embodiments, dielectric layer 322a, which is farther from device layer 10, is thicker than dielectric layer 322b, which is closer to device layer 10. According to some embodiments, dielectric layers 322 together form dielectric structure 322A.

[0143] According to some embodiments, wire 324 includes wires 324a, 324b, and 324c. According to some embodiments, wires 324a, 324b, and 324c are located in dielectric layers 322a, 322b, and 322c, respectively. According to some embodiments, wire 324a is spaced apart from wire 324b by dielectric layer 322a.

[0144] According to some embodiments, wire 324b is closer to substrate 100 than wire 324a. According to some embodiments, wire 324a is thicker than wire 324b. According to some embodiments, some extensions of conductive via 326 pass through dielectric layer 322a and electrically connect between wires 324a and 324b. According to some embodiments, some extensions of conductive via 326 pass through dielectric layer 322b and electrically connect between wires 324b and 324c.

[0145] According to some embodiments, interconnect layer 320 includes a sparse region A1 and a dense region A2. According to some embodiments, the dense region A2 surrounds the sparse region A1. According to some embodiments, the conductor density in the sparse region A1 is lower than the conductor density in the dense region A2.

[0146] According to some embodiments, the conductor density in the sparse region A1 is defined as the ratio of the total top surface area of ​​the topmost conductor 324 (i.e., conductor 324a) in the sparse region A1 to the total top surface area of ​​the interconnect layer 320 in the sparse region A1.

[0147] According to some embodiments, the conductor density in the dense line region A2 is defined as the ratio of the total top surface area of ​​the topmost conductor 324 (i.e., conductor 324a) in the dense line region A2 to the total top surface area of ​​the interconnect layer 320 in the dense line region A2.

[0148] Because the material of the conductor 324 (e.g., metal) is harder than the material of the dielectric layer 322 (e.g., oxide), the conductor 324 in the densely wired region A2 may exert lateral compressive stress on the dielectric layer 322 in the sparsely wired region A1. The lateral compressive stress may cause deformation of the dielectric layer 322, the conductor 324, and the conductive via 326 in the sparsely wired region A1.

[0149] This deformation of the conductor 324 and the conductive via 326 may affect the electrical properties. Furthermore, according to some embodiments, the interconnect layer 320 exhibits a convex surface 320a in the sparse region A1 and a substantially flat surface 320b in the dense region A2.

[0150] According to some embodiments, the convex surface 320a is connected to the substantially flat surface 320b. According to some embodiments, the height H320a of the convex surface 320a (relative to the substantially flat surface 320b) ranges from about 5 nm to about 100 nm.

[0151] According to some embodiments, the dielectric layer 322 is made of an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), a fluorosilicate glass (FSG), a low-k dielectric material, or another suitable dielectric material. The dielectric layer 322 can be formed by a chemical vapor deposition process, an atomic layer deposition process, a physical vapor deposition (PVD) process, or another suitable process.

[0152] According to some embodiments, the wire 324 is made of a conductive material, such as a metal (e.g., copper, aluminum, gold, silver, or tungsten) or an alloy thereof. According to some embodiments, the conductive via 326 is made of a conductive material, such as a metal (e.g., copper, aluminum, gold, silver, or tungsten) or an alloy thereof.

[0153] like Figure 3M As shown, according to some embodiments, a bonding layer 20 is formed over the interconnect layer 320. According to some embodiments, the bonding layer 20 is made of an oxide (e.g., silicon oxide or titanium oxide), a nitride (e.g., silicon nitride), or another suitable dielectric material.

[0154] According to some embodiments, the bonding layer 20 is formed by a deposition process and a planarization process. The deposition process includes chemical vapor deposition, atomic layer deposition, physical vapor deposition (PVD), or another suitable process. According to some embodiments, the planarization process includes chemical mechanical polishing.

[0155] like Figure 3NAs shown, according to some embodiments, a mask layer 1 is formed over the bonding layer 20. According to some embodiments, the mask layer 1 has an opening 1a that exposes a portion 22 of the bonding layer 20. According to some embodiments, the portion 22 of the bonding layer 20 is located over the convex surface 320a of the interconnect layer 320. According to some embodiments, the mask layer 1 is made of a polymeric material such as a photoresist material.

[0156] like Figure 3N and Figure 3O As shown, according to some embodiments, dopant D1 is implanted into portion 22 of the bonding layer 20. According to some embodiments, after the implantation process, the substrate 100 and the elements formed thereon are removed from the implantation chamber (not shown), thereby exposing the substrate 100 and the elements formed thereon to ambient air.

[0157] According to some embodiments, after the implantation process, the bonding layer 20 has a doped region R11. According to some embodiments, the doped region R11 is doped with a dopant D1. According to some embodiments, the concentration of the dopant D1 decreases toward the interconnect layer 320.

[0158] According to some embodiments, the concentration of dopant D1 ranges from about 1E19 atoms / cm³. 3 Approximately 1E22 atoms / cm 3 According to some embodiments, the concentration of dopant D1 ranges from about 1E20 atoms / cm³. 3 Approximately 1E22 atoms / cm 3 .

[0159] Because the dopant D1 from the implantation process breaks some of the bonds between atoms in the implanted portion 22, these atoms can bind with hydrogen (which can come from H2O molecules in the ambient air) after the implanted portion 22 is exposed to ambient air. This can cause the volume of the implanted portion 22 to increase, thereby applying compressive stress (e.g., vertical compressive stress) to the line sparse region A1 of the interconnect layer 320.

[0160] According to some embodiments, this compressive stress reduces or eliminates deformation of the wires 324 and conductive vias 326 in the sparse region A1, which improves electrical properties. According to some embodiments, after the implantation process, the convex surface 320a of the interconnect layer 320 becomes a substantially flat surface 320a1.

[0161] According to some embodiments, the dopant D1 includes a Group IVA element, a Group VA element, or a Group VIIIA element. According to some embodiments, the dopant D1 includes C, Si, Ge, N, As, Ar, or Xe. According to some embodiments, the bonding layer 20 contains hydrogen.

[0162] According to some embodiments, the concentration of hydrogen in the bonding layer 20 is greater than the concentration of dopant D1. According to some embodiments, the concentrations of hydrogen and dopant D1 are measured using secondary ion mass spectrometry (SIMS). According to some embodiments, the hydrogen concentration decreases towards the interconnect layer 320. According to some embodiments, the hydrogen concentration ranges from approximately 1E21 atoms / cm². 3 Approximately 1E23 atoms / cm 3 .

[0163] According to some embodiments, the implantation process includes a high-current ion implantation process. According to some embodiments, the process energy range of the implantation process is from about 0.2 keV to about 60 keV. According to some embodiments, the dose range of the implantation process is from about 5E13 ions / cm³. 2 Approximately 1E17 ions / cm 2 .

[0164] According to some embodiments, the implantation tilt angle relative to the vertical axis of the implantation surface (i.e., the top surface 21 of the bonding layer 20) ranges from about 0 degrees to about 80 degrees. According to some embodiments, the process temperature of the implantation process ranges from about -100°C to about 500°C. According to some embodiments, the implantation depth ranges from about 0 nm to about 1000 nm. According to some embodiments, the process gas includes CH4, N2, SiH4, AsH3, or GeF4.

[0165] like Figure 3P As shown, according to some embodiments, mask layer 1 is removed. According to some embodiments, the thickness T100 of substrate 100 ranges from about 500 μm to about 900 μm. According to some embodiments, the thickness T1 of device layer 10 and interconnect layer 320 ranges from about 1 μm to about 10 μm.

[0166] According to some embodiments, the thickness T20 of the bonding layer 20 ranges from about 100 nm to about 200 nm. According to some embodiments, the thickness T20 of the bonding layer 20 is less than the thickness T1 of the device layer 10 and the interconnect layer 320.

[0167] like Figure 3Q As shown, according to some embodiments, a carrier substrate 30 is provided. According to some embodiments, the carrier substrate 30 has a surface 32. The carrier substrate 30 includes, for example, a semiconductor substrate. The carrier substrate 30 includes, for example, a semiconductor wafer (such as a silicon wafer) or a portion of a semiconductor wafer. In some embodiments, the carrier substrate 30 is made of an elemental semiconductor material such as silicon or germanium, including a single-crystal structure, a polycrystalline structure, or an amorphous structure.

[0168] In some other embodiments, the carrier substrate 30 is made of compound semiconductors (such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide), alloy semiconductors (such as SiGe or GaAsP), or combinations thereof. The carrier substrate 30 may also include multilayer semiconductors, semiconductor-on-insulator (SOI) (such as silicon-on-insulator or germanium-on-insulator), or combinations thereof.

[0169] like Figure 3Q As shown, according to some embodiments, a bonding layer 40 is formed over the surface 32 of the carrier substrate 30. According to some embodiments, the bonding layer 40 is made of an oxide (e.g., silicon oxide or titanium oxide), a nitride (e.g., silicon nitride), or another suitable dielectric material.

[0170] According to some embodiments, the bonding layer 40 is formed by a deposition process and a planarization process. The deposition process includes chemical vapor deposition, atomic layer deposition, physical vapor deposition (PVD), or another suitable process. According to some embodiments, the planarization process includes chemical mechanical polishing. According to some embodiments, the thickness T40 of the bonding layer 40 ranges from about 10 nm to about 500 nm.

[0171] like Figure 3R As shown, according to some embodiments, the carrier substrate 30 is bonded to the bonding layer 20 via a bonding layer 40. According to some embodiments, the bonding layer 40 is connected to the bonding layer 20. According to some embodiments, the bonding layer 40 is in direct contact with the bonding layer 20.

[0172] like Figure 3S As shown, according to some embodiments, the substrate 100 is thinned. Therefore, the semiconductor protrusion 101A and the isolation structure 115 ( Figure 3S The bottom of the substrate 100 (not shown) is exposed. The substrate 100 can be thinned using a planarization process such as CMP. The semiconductor protrusion 101A and the isolation structure 115 can now be used together as a substrate.

[0173] like Figure 3T As shown, a patterned mask element 172 is formed over a semiconductor protrusion 101A. The patterned mask element 172 has openings defining the location and contour of via openings to be formed later. The patterned mask element 172 may be made of silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride, silicon carbide, another suitable material, or a combination thereof, or may include silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride, silicon carbide, another suitable material, or a combination thereof. The formation of the patterned mask element 172 may include a deposition process to form a mask layer, followed by a patterning process defining the mask layer as the patterned mask element 172. The patterning process may include one or more photolithography processes and one or more etching processes.

[0174] Subsequently, using patterned mask element 172 as an etching mask, an etching process is used to partially remove the semiconductor protrusion 101A to form via opening 177. Semiconductor interposers 137 and 208 are also partially removed, thereby deepening the via opening 177 to expose the bottom of epitaxial structure 138.

[0175] Subsequently, a protective layer 174 is deposited over the sidewalls and bottom of the via opening 177. Then, one or more etching processes are used to remove the portion of the protective layer 174 located at the bottom of the via opening 177, further deepening the via opening 177. Therefore, according to some embodiments, the via opening 177 further extends into the epitaxial structure 138, such as... Figure 3T As shown in the image.

[0176] Following a cleaning operation on the exposed bottom surface of the epitaxial structure 138, a metal layer (such as titanium and / or nickel) is deposited on the epitaxial structure 138. A thermal operation can be used to initiate a reaction between the metal layer and the epitaxial structure 138. This forms a metal-semiconductor compound structure 176. The remaining portion of the metal layer extending on the sidewalls of the via opening 177 can then be removed using a cleaning operation.

[0177] After that, as Figure 3T As shown, according to some embodiments, a back-side conductive structure 178 is formed to partially or completely fill the via opening 177. In some embodiments, a conductive layer is deposited to overfill the via opening 177. The conductive layer may be made of tungsten, cobalt, ruthenium, titanium, another suitable material, or a combination thereof, or may include tungsten, cobalt, ruthenium, titanium, another suitable material, or a combination thereof. The conductive layer may be deposited using a CVD process, an ALD process, a PVD process, an electroplating process, another suitable process, or a combination thereof. A planarization process (such as a CMP process) is then used to remove the portion of the conductive layer outside the via opening 177. Thus, the remaining portion of the conductive layer forms the back-side conductive structure 178, as shown. Figure 3T As shown in the image.

[0178] In some embodiments, the conductivity of the metal-semiconductor compound structure 176 is between the conductivity of the epitaxial structure 138 and the conductivity of the back-side conductive structure 178. In some embodiments, each of the metal-semiconductor compound structure 176 and the back-side conductive structure 178 has a higher conductivity than the epitaxial structure 138. In some embodiments, the metal-semiconductor compound structure 176 includes a curved profile, such as... Figure 3T As shown in the figure. According to some embodiments, in this step, a semiconductor device structure 200 is essentially formed.

[0179] Figures 4A to 4FThese are cross-sectional views of various stages of a process for forming a semiconductor device structure, according to some embodiments. For example... Figure 4A As shown, according to some embodiments, a carrier substrate 30 and a bonding layer 40 are provided. According to some embodiments, the bonding layer 40 is formed over the surface 32 of the carrier substrate 30.

[0180] like Figure 4B As shown, according to some embodiments, a mask layer 2 is formed over the bonding layer 40. According to some embodiments, the mask layer 2 has an opening 2a that exposes a portion 42 of the bonding layer 40. According to some embodiments, the mask layer 2 is made of a polymer material such as a photoresist material.

[0181] like Figure 4B As shown, according to some embodiments, dopant D2 is implanted into portion 42 of the bonding layer 40 and portion 32p of the carrier substrate 30 located below portion 42. According to some embodiments, after the implantation process, the carrier substrate 30 and the elements formed thereon are removed from the implantation chamber (not shown), thereby exposing the carrier substrate 30 and the elements formed thereon to ambient air.

[0182] Because the dopant D2 from the implantation process breaks some of the bonds between the atoms in the (implanted) portions 32 and 42, these atoms can combine with hydrogen (from ambient air). This may result in an increase in the volume of the (implanted) portions 32 and 42. Therefore, according to some embodiments, after the implantation process is performed, portion 32p has a convex surface 32a, and portion 42 has a convex surface 42a.

[0183] According to some embodiments, after the implantation process, the bonding layer 40 has a doped region R22, and the carrier substrate 30 has a doped region R33. According to some embodiments, the doped region R22 is doped with dopant D2. According to some embodiments, the doped region R33 is doped with dopant D2.

[0184] According to some embodiments, the concentration of dopant D2 in the doped region R22 decreases toward the carrier substrate 30. According to some embodiments, in the doped region R33, the concentration of dopant D2 increases from the convex surface 32a to a certain depth, and then decreases from that depth to the surface 34 of the carrier substrate 30. According to some embodiments, the depth ranges from about 100 nm to about 200 nm.

[0185] According to some embodiments, the concentration of dopant D2 ranges from about 1E19 atoms / cm³. 3 Approximately 1E20 atoms / cm 3 According to some embodiments, dopant D2 includes a group IVA element, a group VA element, or a group VIIIA element. According to some embodiments, dopant D2 includes C, Si, Ge, N, As, Ar, or Xe.

[0186] According to some embodiments, the bonding layer 40 contains hydrogen. According to some embodiments, the concentration of hydrogen in the bonding layer 40 is greater than the concentration of dopant D2. According to some embodiments, the hydrogen concentration decreases toward the carrier substrate 30. According to some embodiments, the hydrogen concentration ranges from about 1E20 atoms / cm³. 3 Approximately 1E21 atoms / cm 3 .

[0187] According to some embodiments, the process energy range of the implantation process is from about 0.2 keV to about 60 keV. According to some embodiments, the dose range of the implantation process is from about 5E13 ions / cm³. 2 Approximately 1E17 ions / cm 2 According to some embodiments, the injection tilt angle ranges from about 0 degrees to about 80 degrees relative to the vertical axis of the injection surface (i.e., the top surface 21 of the bonding layer 40).

[0188] According to some embodiments, the process temperature range for the implantation process is from about -100°C to about 500°C. According to some embodiments, the implantation depth ranges from about 0 nm to about 1000 nm. According to some embodiments, the process gas includes CH4, N2, SiH4, AsH3, or GeF4.

[0189] like Figure 4C As shown, according to some embodiments, mask layer 2 is removed. Figure 4D As shown, according to some embodiments, a substrate 100, a device layer 10, an interconnect layer 320, and a bonding layer 20 are provided. According to some embodiments, the device layer 10, the interconnect layer 320, and the bonding layer 20 are sequentially formed over the substrate 100. According to some embodiments, the substrate 100, the device layer 10, the interconnect layer 320, and the bonding layer 20 are... Figure 3M Those are the same as those in the text.

[0190] like Figure 4D and Figure 4E As shown, according to some embodiments, bonding layer 40 is bonded to bonding layer 20. According to some embodiments, during the bonding process, the carrier substrate 30 and the (implanted) portions 32 and 42 of bonding layer 40 apply compressive stress to the line sparse region A1 of interconnect layer 320.

[0191] According to some embodiments, this compressive stress reduces or eliminates deformation of the conductors 324 and conductive vias 326 in the sparse region A1, which improves electrical properties. According to some embodiments, after the bonding process is performed, the convex surface 320a of the interconnect layer 320 becomes a substantially flat surface 320a1.

[0192] According to some embodiments, after the bonding process is performed, the convex surface 32a of a portion 32p of the carrier substrate 30 becomes a substantially flat surface 32a1. According to some embodiments, after the bonding process is performed, the convex surface 42a of a portion 42 of the bonding layer 40 becomes a substantially flat surface 42a1.

[0193] like Figure 4F As shown, according to some embodiments, implementation Figures 3S to 3T The steps involve forming a patterned mask element 172, a protective layer 174, a metal-semiconductor compound structure 176, and a back-side conductive structure 178. According to some embodiments, in this step, a semiconductor device structure 300 is substantially formed.

[0194] Figures 5A to 5C These are cross-sectional views of various stages of a process for forming a semiconductor device structure, according to some embodiments. For example... Figure 5A As shown, according to some embodiments, a substrate 100, a device layer 10, an interconnect layer 320, and a bonding layer 20 are provided. According to some embodiments, the device layer 10, the interconnect layer 320, and the bonding layer 20 are located above the substrate 100.

[0195] According to some embodiments, the substrate 100, device layer 10, interconnect layer 320, and bonding layer 20 are similar to Figure 3P Those in the process, except for interconnect layer 320, still have convex surface 320a after the implantation process is performed.

[0196] like Figure 5A As shown, according to some embodiments, a carrier substrate 30 and a bonding layer 40 are provided. According to some embodiments, the carrier substrate 30 and the bonding layer 40 are coupled with… Figure 4D Those are the same as those in the text.

[0197] like Figure 5A and Figure 5B As shown, according to some embodiments, bonding layer 40 is bonded to bonding layer 20. According to some embodiments, after bonding layer 40 is bonded to bonding layer 20, the (implanted) portion 42 of bonding layer 40 is bonded to the (implanted) portion 22 of bonding layer 20. According to some embodiments, the doped region R22 of bonding layer 40 is located between the doped region R11 of bonding layer 20 and the doped region R33 of carrier substrate 30.

[0198] According to some embodiments, during the bonding process, the carrier substrate 30 and the (implanted) portions 32 and 42 of the bonding layer 40 apply compressive stress to the line sparse region A1 of the interconnect layer 320.

[0199] According to some embodiments, this compressive stress reduces or eliminates deformation of the conductors 324 and conductive vias 326 in the sparse region A1, which improves electrical properties. According to some embodiments, after the bonding process is performed, the convex surface 320a of the interconnect layer 320 becomes a substantially flat surface 320a1.

[0200] According to some embodiments, after the bonding process is performed, the convex surface 32a of a portion 32p of the carrier substrate 30 becomes a substantially flat surface 32a1. According to some embodiments, after the bonding process is performed, the convex surface 42a of a portion 42 of the bonding layer 40 becomes a substantially flat surface 42a1.

[0201] like Figure 5C As shown, according to some embodiments, implementation Figures 3S to 3T The steps involve forming a patterned mask element 172, a protective layer 174, a metal-semiconductor compound structure 176, and a back-side conductive structure 178. According to some embodiments, this step essentially forms a semiconductor device structure 400.

[0202] The processes and materials used to form semiconductor device structures 300 and 400 can be similar to or the same as those described above for forming semiconductor device structure 200. Figures 1A to 5C The elements represented by the same or similar reference numerals in the document have the same or similar structure and materials. Therefore, their detailed descriptions will not be repeated here.

[0203] According to some embodiments, a semiconductor device structure and a method for forming the same are provided. The method (for forming the semiconductor device structure) implants a portion of a bonding layer above a line-sparse region of an interconnect layer. Because the material of the conductive wires is harder than the material of the dielectric layer, the conductive wires in the line-dense region of the bonding layer may exert lateral compressive stress on the dielectric layer in the line-sparse region. This lateral compressive stress may cause deformation of the line-sparse region. Because dopants from the implantation process break the bonds between atoms in the implanted portion, these atoms can combine with hydrogen, which increases the volume of the (implanted) portion, thereby applying compressive stress to the line-sparse region of the interconnect layer. This compressive stress reduces or eliminates deformation of the line-sparse region, which improves electrical properties.

[0204] According to some embodiments, a method for forming a semiconductor device structure is provided. The method includes forming a device layer over a substrate. The device layer includes a gate stack and a gate spacer extending along a sidewall of the gate stack, and the gate stack has a gate electrode and a gate dielectric layer. The gate spacer is thicker than the gate dielectric layer, and the dielectric constant of the gate dielectric layer is greater than the dielectric constant of the gate spacer. The method includes forming an interconnect layer over the device layer. The interconnect layer includes a dielectric layer and wires in the dielectric layer. The method includes forming a first bonding layer over the interconnect layer. The method includes implanting a portion of the first bonding layer. The method includes bonding a carrier substrate to the first bonding layer via a second bonding layer.

[0205] According to some embodiments, a method for forming a semiconductor device structure is provided. The method includes forming a first bonding layer over a carrier substrate. The method includes implanting a first portion of the first bonding layer. The method includes sequentially forming a device layer, an interconnect layer, and a second bonding layer over the substrate. The device layer includes a channel structure and an epitaxial structure adjacent to the channel structure. The epitaxial structure has a first portion and a second portion, and the second portion is spaced apart from the channel structure by the first portion. The first portion and the second portion have different dopant concentrations. The interconnect layer includes a first conductive line, a second conductive line, a dielectric layer, and a conductive via, wherein the second conductive line is closer to the substrate than the first conductive line, the first conductive line is thicker than the second conductive line, the first conductive line is located in the dielectric layer, and the conductive via extends through the dielectric layer and electrically connects the first conductive line and the second conductive line. The method includes bonding the first bonding layer to the second bonding layer.

[0206] According to some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a carrier substrate. The semiconductor device structure includes a first bonding layer above the carrier substrate. The semiconductor device structure includes a second bonding layer located above the first bonding layer and having a first doped region doped with a first dopant. The semiconductor device structure includes an interconnect layer located above the second bonding layer and having a first dielectric layer, a second dielectric layer, a first conductive line in the first dielectric layer, and a second conductive line in the second dielectric layer. The first conductive line is spaced apart from the second conductive line by the first dielectric layer. The semiconductor device structure includes a device layer above the interconnect layer. The first dielectric layer, located away from the device layer, is thicker than the second dielectric layer, located closer to the device layer. The device layer includes a channel structure, an epitaxial structure adjacent to the channel structure, and a titanium-containing gate electrode located above the channel structure.

[0207] Some embodiments of this application provide a method for forming a semiconductor device structure, comprising: forming a device layer over a substrate, wherein the device layer includes a gate stack and a gate spacer extending along a sidewall of the gate stack, the gate stack having a gate electrode and a gate dielectric layer, the gate spacer being thicker than the gate dielectric layer, and the dielectric constant of the gate dielectric layer being greater than the dielectric constant of the gate spacer; forming an interconnect layer over the device layer, wherein the interconnect layer includes a dielectric layer and a conductor located in the dielectric layer; forming a first bonding layer over the interconnect layer; implanting a portion of the first bonding layer; and bonding a carrier substrate to the first bonding layer through a second bonding layer.

[0208] In some embodiments, the interconnect layer has a first substantially flat surface and a convex surface connected to the first substantially flat surface before the portion of the first bonding layer is injected, and the portion of the first bonding layer is located above the convex surface of the interconnect layer. In some embodiments, the convex surface of the interconnect layer becomes a second substantially flat surface after the portion of the first bonding layer is injected. In some embodiments, injecting the portion of the first bonding layer includes: forming a mask layer over the first bonding layer, wherein the mask layer has an opening exposing the portion of the first bonding layer; injecting a dopant into the portion of the first bonding layer; and removing the mask layer. In some embodiments, the dopant includes a Group IVA element, a Group VA element, or a Group VIIIA element. In some embodiments, the dopant includes C, Si, Ge, N, As, Ar, or Xe. In some embodiments, the concentration of the dopant decreases toward the interconnect layer. In some embodiments, the first bonding layer includes hydrogen. In some embodiments, a first concentration of hydrogen in the first bonding layer is greater than a second concentration of the dopant. In some embodiments, the first concentration of hydrogen decreases toward the interconnect layer.

[0209] Other embodiments of this application provide a method for forming a semiconductor device structure, comprising: forming a first bonding layer over a carrier substrate; implanting a first portion of the first bonding layer; sequentially forming a device layer, an interconnect layer, and a second bonding layer over the substrate, wherein the device layer includes a channel structure and an epitaxial structure located adjacent to the channel structure, the epitaxial structure having a first portion and a second portion, the second portion being spaced apart from the channel structure by the first portion, the first portion and the second portion having different dopant concentrations, the interconnect layer including a first conductor, a second conductor, a dielectric layer, and a conductive via, the second conductor being closer to the substrate than the first conductor, the first conductor being thicker than the second conductor, the first conductor being located in the dielectric layer, and the conductive via extending through the dielectric layer and electrically connecting the first conductor and the second conductor; and bonding the first bonding layer to the second bonding layer.

[0210] In some embodiments, the first portion of the first bonding layer is further implanted into the carrier substrate, wherein a second portion of the carrier substrate is implanted into the first bonding layer. In some embodiments, the interconnect layer has a first substantially flat surface and a first convex surface connected to the first substantially flat surface before the first bonding layer is bonded to the second bonding layer, and the first convex surface becomes a second substantially flat surface after the first bonding layer is bonded to the second bonding layer. In some embodiments, the first portion of the first bonding layer has a second convex surface after the first portion of the first bonding layer is implanted into the first bonding layer, and the second convex surface becomes a third substantially flat surface after the first bonding layer is bonded to the second bonding layer. In some embodiments, the method further includes implanting a second portion of the second bonding layer before bonding the first bonding layer to the second bonding layer, wherein the first portion of the first bonding layer is bonded to the second portion of the second bonding layer after the first bonding layer is bonded to the second bonding layer.

[0211] Some embodiments of this application provide a semiconductor device structure, including: a substrate; a first bonding layer located above the substrate; a second bonding layer located above the first bonding layer and having a first doped region doped with a first dopant; an interconnect layer located above the second bonding layer and having a first dielectric layer, a second dielectric layer, a first conductor located in the first dielectric layer and a second conductor located in the second dielectric layer, wherein the first conductor is spaced apart from the second conductor by the first dielectric layer; and a device layer located above the interconnect layer, wherein the first dielectric layer farther from the device layer is thicker than the second dielectric layer closer to the device layer, and the device layer includes a channel structure, an epitaxial structure adjacent to the channel structure, and a titanium-containing gate electrode located above the channel structure.

[0212] In some embodiments, the concentration of the first dopant decreases toward the interconnect layer. In some embodiments, the first bonding layer has a second doped region located below the first doped region and doped with a second dopant. In some embodiments, the substrate has a third doped region located below the second doped region and doped with a third dopant. In some embodiments, the first dopant includes C, Si, Ge, N, As, Ar, or Xe.

[0213] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of the embodiments of this disclosure. Those skilled in the art should understand that they can readily use the embodiments of this disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the embodiments of this disclosure, and that various changes, substitutions, and alterations can be made therein without departing from the spirit and scope of the embodiments of this disclosure.

Claims

1. A method for forming a semiconductor device structure, comprising: A device layer is formed above a substrate, wherein the device layer includes a gate stack and a gate spacer extending along the sidewall of the gate stack, the gate stack having a gate electrode and a gate dielectric layer, the gate spacer being thicker than the gate dielectric layer, and the dielectric constant of the gate dielectric layer being greater than the dielectric constant of the gate spacer. An interconnect layer is formed above the device layer, wherein the interconnect layer includes a dielectric layer and wires located in the dielectric layer; A first bonding layer is formed above the interconnect layer; The portion injected into the first bonding layer; and The carrier substrate is bonded to the first bonding layer via a second bonding layer.

2. The method for forming the semiconductor device structure according to claim 1, wherein, The interconnect layer has a first substantially flat surface and a convex surface connected to the first substantially flat surface before the portion of the first bonding layer is injected, and the portion of the first bonding layer is located above the convex surface of the interconnect layer.

3. The method for forming the semiconductor device structure according to claim 2, wherein, The convex surface of the interconnect layer becomes a second substantially flat surface after the portion of the first bonding layer is injected.

4. The method for forming the semiconductor device structure according to claim 1, wherein, The portion of the first bonding layer injected includes: A mask layer is formed over the first bonding layer, wherein the mask layer has an opening that exposes the portion of the first bonding layer; Injecting the dopant into the portion of the first bonding layer; and Remove the mask layer.

5. The method for forming the semiconductor device structure according to claim 4, wherein, The dopant includes elements from Group IVA, Group VA, or Group VIIIA.

6. The method for forming the semiconductor device structure according to claim 5, wherein, The dopant includes C, Si, Ge, N, As, Ar, or Xe.

7. The method for forming the semiconductor device structure according to claim 4, wherein, The concentration of the dopant decreases toward the interconnect layer.

8. The method for forming the semiconductor device structure according to claim 4, wherein, The first bonding layer comprises hydrogen.

9. A method for forming a semiconductor device structure, comprising: A first bonding layer is formed above the carrier substrate; Injecting a first portion of the first bonding layer; A device layer, an interconnect layer, and a second bonding layer are sequentially formed on a substrate. The device layer includes a channel structure and an epitaxial structure located next to the channel structure. The epitaxial structure has a first portion and a second portion. The second portion is spaced apart from the channel structure by the first portion. The first portion and the second portion have different dopant concentrations. The interconnect layer includes a first conductor, a second conductor, a dielectric layer, and a conductive via. The second conductor is closer to the substrate than the first conductor. The first conductor is thicker than the second conductor. The first conductor is located in the dielectric layer. The conductive via extends through the dielectric layer and electrically connects the first conductor and the second conductor. as well as The first bonding layer is bonded to the second bonding layer.

10. A semiconductor device structure, comprising: Substrate; A first bonding layer is located above the substrate; The second bonding layer is located above the first bonding layer and has a first doped region doped with a first dopant. An interconnect layer, located above the second bonding layer, and having a first dielectric layer, a second dielectric layer, a first conductor located in the first dielectric layer, and a second conductor located in the second dielectric layer, wherein the first conductor is spaced apart from the second conductor by the first dielectric layer; and A device layer is located above the interconnect layer, wherein a first dielectric layer farther from the device layer is thicker than a second dielectric layer closer to the device layer, and the device layer includes a channel structure, an epitaxial structure adjacent to the channel structure, and a titanium-containing gate electrode located above the channel structure.

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