A method and apparatus for fabricating bulk transistors and silicon-on-insulator transistors based on silicon recess differences

Abstract

The application discloses a manufacturing method of bulk transistor and silicon-on-insulator transistor based on silicon groove difference, which comprises the following steps: providing a first silicon wafer, forming a shallow trench isolation structure on the first silicon wafer, and completing well implantation and channel implantation; and the method further comprises the following steps: S1, performing differential silicon groove etching on the silicon surface corresponding to different device areas of the first silicon wafer to form silicon grooves with different depths; S2, depositing oxide on the silicon surface of the differential silicon groove; S3, performing chemical mechanical polishing and etching back on the oxide to planarize the surface of the first silicon wafer; S4, providing a second silicon wafer implanted with hydrogen ions, and bonding the second silicon wafer to the first silicon wafer to perform smart cutting and separation; and S5, simultaneously forming gate structures of bulk transistors and silicon-on-insulator transistors on the first silicon wafer. Compared with the prior art, the method has the advantages that a manufacturing method and device of bulk transistor and silicon-on-insulator transistor based on silicon groove difference are provided, and seamless integration of FDSOI structure and Bulk structure on the same wafer is realized.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, specifically to a method and apparatus for manufacturing block transistors and silicon-on-insulator transistors based on silicon groove differences. Background Technology

[0002] In semiconductor integrated circuit manufacturing, with the continuous development of display technology, the requirements for device performance of display driver chips (DDI) are increasing.

[0003] On the one hand, the logic circuit section requires low-power, high-performance transistors, and FDSOI transistors are an ideal choice due to their excellent subthreshold characteristics, low leakage current and good RF performance. On the other hand, the output drive section requires block transistors that can withstand higher voltages to ensure sufficient driving capability and voltage withstand performance.

[0004] However, simultaneously fabricating FDSOI transistors and Bulk transistors on the same wafer presents numerous process challenges.

[0005] In traditional methods, the gate oxide layer thickness of low-voltage devices (such as FDSOI) and high-voltage devices (such as BulkHV) differs greatly, typically by a height difference of about 4,000 angstroms. This leads to a large difference in the aspect ratio of each device region in the subsequent metal contact process, making it difficult to control the contact hole size and increasing the process complexity and manufacturing cost. To integrate silicon-on-insulator transistors and bulk transistors on the same substrate, oxide layers of different thicknesses require multiple photolithography and deposition processes, resulting in a lengthy manufacturing process. When using a back-gate process to fabricate metal gates, gate depression defects are prone to occur, affecting device performance and yield.

[0006] Therefore, there is an urgent need for a semiconductor manufacturing solution that features a simple process, good device coplanarity, and the ability to integrate multiple types of transistors on a common substrate. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to overcome the above-mentioned technical defects and provide a method and apparatus for manufacturing a bulk transistor and a silicon-on-insulator transistor based on silicon trench difference to achieve seamless integration of FDSOI structure and Bulk structure on the same wafer.

[0008] To solve the above-mentioned technical problems, the technical solution provided by the present invention is as follows: a method for manufacturing a block transistor and a silicon-on-insulator transistor based on silicon trench differences, comprising providing a first silicon wafer, forming a shallow trench isolation structure on the first silicon wafer, and completing well implantation and channel implantation, and further comprising the following steps: S1: Differentiated silicon groove etching is performed on the silicon surface of the first silicon wafer corresponding to different device regions to form silicon grooves of different depths. The silicon groove depths in the regions corresponding to silicon devices on the insulator and medium-voltage devices are the same, while the silicon groove depths in the regions corresponding to high-voltage devices are greater than the silicon groove depths in the aforementioned regions. S2: Deposit oxide on the silicon surface of the differentiated silicon trenches, filling all the silicon trenches and covering the silicon wafer surface; S3: Perform chemical mechanical polishing and etching on the oxide to planarize the surface of the first silicon wafer; S4: Provide a second silicon wafer implanted with hydrogen ions, bond the second silicon wafer to the first silicon wafer, and separate the second silicon wafer by intelligent cutting to transfer the thin silicon layer of the second silicon wafer to the first silicon wafer to form a silicon-on-insulator structure; S5: The gate structures of a bulk transistor and a silicon-on-insulator transistor are simultaneously formed on the first silicon wafer. The gate structure includes a high-dielectric-constant gate dielectric layer and a metal gate layer, and the gate top surface height is consistent in all device regions.

[0009] Preferably, the differential silicon trench etching in S1 includes: A first photoresist is coated on a first silicon wafer. Using the first photoresist as a mask, the entire area of ​​the first silicon wafer is etched for the first time to form an initial silicon groove with a depth of 200 to 400 angstroms. The first photoresist is removed, and the second photoresist is recoated. Using the second photoresist as a mask, the silicon in the corresponding high-voltage device region is etched a second time to form a second silicon trench with a depth of about 400 to 1000 angstroms.

[0010] Preferably, the silicon groove depth of the silicon device region on the insulator and the silicon groove depth of the medium voltage device region are the same, and the oxide dielectric filling the grooves of the two are of the same thickness, and they are prepared simultaneously using a dual oxidation process.

[0011] Preferably, in step S3, chemical mechanical polishing and etching remove excess oxide from the surface of the first silicon wafer, so that the top surface of the remaining oxide is flush with the silicon surface. In S4, the region corresponding to the silicon-on-insulator device is composed of a thin silicon layer and oxides in the groove, forming a silicon-on-insulator structure. The regions corresponding to the medium-voltage and high-voltage devices are composed of a thin silicon layer and the bulk silicon of the first silicon wafer, forming a silicon-based structure for the block transistor.

[0012] Preferably, the intelligent cutting in S4 includes: The second silicon wafer is bonded with the implantation surface facing the front of the first silicon wafer. The bonded structure is then heat-treated to cause the second silicon wafer to undergo interlayer peeling along the hydrogen ion enrichment layer.

[0013] Preferably, the high dielectric constant gate dielectric layer in S5 is formed by atomic layer deposition on the front side of the entire wafer in one step, with a thickness of 20 angstroms to 30 angstroms.

[0014] Preferably, the metal gate layer in S5 is made of TiN, WN, or W, has a deposition thickness of 3800 angstroms, and is deposited directly on a high dielectric constant gate dielectric layer.

[0015] Preferably, the high-voltage device region includes at least two high-voltage device partitions with different withstand voltage levels, and the silicon groove depth of each high-voltage device partition is adjusted by an independent etching process to form oxide media of different thicknesses.

[0016] Another aspect of the present invention discloses a semiconductor device based on silicon trench differences, comprising a bulk transistor and a silicon-on-insulator transistor, including the same silicon substrate on which silicon-on-insulator transistor units and bulk transistor units are integrated. The silicon substrate has silicon grooves with varying depths inside, and the grooves are filled with oxide dielectric. A top silicon layer is provided above the oxide dielectric corresponding to the silicon-on-insulator transistor unit, thus forming a silicon-on-insulator structure. The oxide dielectric corresponding to the block transistor unit is embedded inside the silicon substrate. The top surface height of the gate structure of all transistor units is consistent. The gate structure includes a high dielectric constant gate dielectric layer and a metal gate layer.

[0017] The advantages of this invention compared to existing technologies are as follows: This invention forms buried oxide structures of varying depths through differentiated silicon trench etching. The oxide layer thickness of the FDSOI and the medium-voltage device region is consistent, allowing for simultaneous fabrication using a dual-oxide scheme, simplifying the process steps. Global planarization is achieved through oxide filling and chemical mechanical polishing. After gate fabrication, the top surfaces of all device regions are coplanar, eliminating height differences between devices and ensuring consistent aspect ratios in subsequent metal contact processes. This reduces the difficulty of contact hole control and improves process yield. The use of a gate-first process for metal gate fabrication avoids gate recess defects, resulting in better process stability. Combined with intelligent dicing technology, silicon layer transfer is achieved, donor wafers can be reused, and the depth of the high-voltage partitioned trenches is adjustable, adapting to various voltage withstand requirements. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the intelligent cutting process.

[0019] Figure 2 This is the first schematic diagram of differentiated silicon groove etching.

[0020] Figure 3 This is a second schematic diagram of the differential silicon groove etching.

[0021] Figure 4 This is a schematic diagram of oxide deposition.

[0022] Figure 5 This is a schematic diagram of the bonding of the second silicon wafer.

[0023] Figure 6 This is a schematic diagram of intelligent cutting and separation. Detailed Implementation

[0024] The specific embodiments of the present invention will be further described below with reference to the accompanying drawings. Identical components are indicated by the same reference numerals.

[0025] It should be noted that the terms “front,” “back,” “left,” “right,” “up,” and “down” used in the following description refer to the directions shown in the attached diagram, while the terms “inside” and “outside” refer to the directions toward or away from the geometric center of a specific component, respectively.

[0026] To make the content of this invention easier to understand, the technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings.

[0027] Combined with appendix Figures 1-6 As shown, a first silicon wafer is provided as a substrate. After shallow trench isolation, well implantation and trench implantation are completed, differentiated silicon trench etching is performed on the active areas of different devices on the first silicon wafer. The first silicon wafer is divided into a silicon-on-insulator device area, a medium-voltage device area and a high-voltage device area. The high-voltage device area can be further divided into at least two high-voltage device partitions with different withstand voltage levels. The etching process consists of two steps: (1) First silicon etching: The first photoresist is uniformly coated on the surface of the first silicon wafer and the first photoresist pattern is formed after exposure and development; the first photoresist is used as a mask to perform silicon etching on all device areas of the first silicon wafer to form an initial silicon groove with a depth of about 200 angstroms to 400 angstroms in all areas.

[0028] (2) Second silicon etching: The first photoresist is removed by ashing process, and the second photoresist is recoated on the surface of the first silicon wafer. After exposure and development, a second photoresist pattern is formed covering the silicon device area on the insulator and the medium voltage device area, and exposing the high voltage device area. Using the second photoresist as a mask, the silicon in the high voltage device area is etched twice, so that the total depth of the silicon groove in the high voltage device area reaches 400 angstroms to 1000 angstroms.

[0029] The silicon trench structure with different depths is ultimately formed by two etching processes: the silicon trench depth in the silicon device area on the insulator is the same as that in the medium voltage device area, while the silicon trench depth in the high voltage device area is greater than that in the aforementioned areas; the trench depth of different high voltage device zones can be adjusted separately by independent etching processes to form oxide media with different thicknesses.

[0030] An oxide dielectric is deposited on the front side of the first silicon wafer after the differential silicon trench etching is completed, so that the oxide fills all silicon trenches and covers the entire silicon wafer surface. Among them, the silicon trench depth of the silicon-on-insulator device area and the medium-voltage device area are the same, and the oxide dielectric filling thickness in the trenches of the two is the same. The two are fabricated simultaneously using a dual oxide process, which can reduce the number of photolithography steps.

[0031] The deposited oxide is chemically and mechanically polished and etched to remove excess oxide from the silicon surface of the first silicon wafer, so that the top surface of the remaining oxide is flush with the silicon surface of the first silicon wafer, thereby achieving global planarization of the entire wafer.

[0032] A second silicon wafer is provided, and hydrogen ion implantation is performed on the second silicon wafer in advance to form a hydrogen ion enrichment layer at a predetermined depth inside the second silicon wafer.

[0033] The implantation surface of the second silicon wafer is aligned with the front side of the first silicon wafer for wafer bonding. After bonding, the overall structure is heat-treated to cause interlayer peeling of the second silicon wafer along the hydrogen ion enrichment layer, and the top thin silicon layer of the second silicon wafer is completely transferred to the first silicon wafer.

[0034] After stripping, the region corresponding to the silicon-on-insulator device is formed by the top thin silicon layer and the oxide in the groove to form the silicon-on-insulator structure; the region corresponding to the medium-voltage device and the high-voltage device is formed by the top thin silicon layer and the bulk silicon of the first silicon wafer to form the silicon-based structure of the block transistor, thereby realizing the integration of the silicon-on-insulator transistor and the block transistor on the same substrate.

[0035] The second silicon donor wafer remaining after intelligent cutting and peeling can be reused in subsequent bonding processes after surface flattening treatment.

[0036] On the first silicon wafer where the silicon layer transfer is completed, the gate structures of all devices are fabricated simultaneously. The specific process is as follows: (1) A high dielectric constant gate dielectric layer is deposited on the front side of the entire wafer in one go using atomic layer deposition process, with a deposition thickness of 20 angstroms to 30 angstroms. This deposition process does not require additional photolithography patterning steps, and all device areas can be covered in one deposition.

[0037] (2) A metal gate layer is directly deposited on a high dielectric constant gate dielectric layer. The material of the metal gate layer is TiN, WN or W, and the deposition thickness is 3000~4000 angstroms. Then, the metal gate is patterned by photolithography and etching processes to finally form the gate structure of each device.

[0038] In its specific implementation, this invention employs a gate-first process route, which can avoid gate depression defects that are easily generated in subsequent gate processes. Since the substrate surface has been planarized through silicon trench filling and chemical mechanical polishing in the early stage, after the metal gate layer is deposited, the top surface of the gate of all device regions is on the same horizontal plane, and there is no height difference between the devices. In the subsequent metal contact process, the aspect ratio of each device region is consistent, which greatly reduces the difficulty of adjusting the contact hole size.

[0039] The semiconductor device fabricated through the above steps integrates silicon-on-insulator (SiI) transistor units and bulk transistor units on the same silicon substrate. The silicon substrate has silicon trenches with varying depths, and the trenches are filled with oxide dielectric. A top silicon layer is provided above the oxide dielectric corresponding to the SiI transistor unit, forming a fully depleted SiI structure. The oxide dielectric corresponding to the bulk transistor unit is embedded inside the silicon substrate. The top surface height of the gate structure of all transistor units is consistent, and the gate structure includes a high-dielectric-constant gate dielectric layer and a metal gate layer.

[0040] The contents not described in detail in this specification are existing technologies known to those skilled in the art.

[0041] All standard parts used in this invention can be purchased from the market, and irregular parts can be customized according to the description and drawings. The specific connection methods of each part adopt conventional methods such as bolts, rivets, and welding that are mature in the prior art. The machinery, parts and equipment adopt conventional models in the prior art, and the circuit connection adopts conventional connection methods in the prior art, which will not be described in detail here. The contents not described in detail in this specification belong to the prior art known to those skilled in the art.

[0042] The present invention and its embodiments have been described above. This description is not restrictive, and the accompanying drawings are only one embodiment of the present invention; the actual structure is not limited thereto. In conclusion, if those skilled in the art are inspired by this description and design similar structures and embodiments without departing from the spirit of the invention, such designs should fall within the protection scope of the present invention.

Claims

1. A method for manufacturing a bulk transistor based on silicon trench differences and a silicon-on-insulator transistor, characterized in that: The method includes providing a first silicon wafer, forming a shallow trench isolation structure on the first silicon wafer, and completing well implantation and trench implantation, and also includes the following steps: S1: Differentiated silicon groove etching is performed on the silicon surface of the first silicon wafer corresponding to different device regions to form silicon grooves of different depths. The silicon groove depths in the regions corresponding to silicon devices on the insulator and medium-voltage devices are the same, while the silicon groove depths in the regions corresponding to high-voltage devices are greater than the silicon groove depths in the aforementioned regions. S2: Deposit oxide on the silicon surface of the differentiated silicon trenches, filling all the silicon trenches and covering the silicon wafer surface; S3: Perform chemical mechanical polishing and etching on the oxide to planarize the surface of the first silicon wafer; S4: Provide a second silicon wafer implanted with hydrogen ions, bond the second silicon wafer to the first silicon wafer, and separate the second silicon wafer by intelligent cutting to transfer the thin silicon layer of the second silicon wafer to the first silicon wafer to form a silicon-on-insulator structure; S5: The gate structures of a bulk transistor and a silicon-on-insulator transistor are simultaneously formed on the first silicon wafer. The gate structure includes a high-dielectric-constant gate dielectric layer and a metal gate layer, and the gate top surface height is consistent in all device regions.

2. The method for manufacturing a block transistor and a silicon-on-insulator transistor based on silicon trench differences according to claim 1, characterized in that: The differentiated silicon trench etching in S1 includes: A first photoresist is coated on a first silicon wafer. Using the first photoresist as a mask, the entire area of ​​the first silicon wafer is etched for the first time to form an initial silicon groove with a depth of 200 to 400 angstroms. The first photoresist is removed, and the second photoresist is recoated. Using the second photoresist as a mask, the silicon in the corresponding high-voltage device area is etched a second time to form a second silicon trench with a depth of 400 to 1000 angstroms.

3. The method for manufacturing a block transistor and a silicon-on-insulator transistor based on silicon trench differences according to claim 1, characterized in that: The silicon groove depths of the silicon device region and the medium-voltage device region on the insulator are consistent, and the oxide dielectric filling thickness in the grooves of both is the same. They are prepared simultaneously using a dual oxidation process.

4. The method for manufacturing a block transistor and a silicon-on-insulator transistor based on silicon trench differences according to claim 1, characterized in that: In step S3, chemical mechanical polishing and etching remove excess oxide from the surface of the first silicon wafer, so that the top surface of the remaining oxide is flush with the silicon surface. In S4, the region corresponding to the silicon-on-insulator device is composed of a thin silicon layer and oxides in the groove, forming a silicon-on-insulator structure. The regions corresponding to the medium-voltage and high-voltage devices are composed of a thin silicon layer and the bulk silicon of the first silicon wafer, forming a silicon-based structure for the block transistor.

5. The method for manufacturing a block transistor and a silicon-on-insulator transistor based on silicon trench differences according to claim 1, characterized in that: The intelligent cutting in S4 includes: The second silicon wafer is bonded with the implantation surface facing the front of the first silicon wafer. The bonded structure is then heat-treated to cause the second silicon wafer to undergo interlayer peeling along the hydrogen ion enrichment layer.

6. The method for manufacturing a block transistor and a silicon-on-insulator transistor based on silicon trench differences according to claim 1, characterized in that: The high dielectric constant gate dielectric layer in S5 is formed by atomic layer deposition on the front side of the entire wafer in one step, with a thickness of 20 angstroms to 30 angstroms.

7. The method for manufacturing a block transistor and a silicon-on-insulator transistor based on silicon trench differences according to claim 6, characterized in that: The metal gate layer in S5 is made of TiN, WN, or W, with a deposition thickness of 3800 angstroms, and is deposited directly on a high dielectric constant gate dielectric layer.

8. The method for manufacturing a block transistor and a silicon-on-insulator transistor based on silicon trench differences according to claim 1, characterized in that: The high-voltage device region includes at least two high-voltage device zones with different withstand voltage levels. The silicon groove depth of each high-voltage device zone is adjusted by an independent etching process to form oxide media of different thicknesses.

9. A semiconductor device based on silicon trench difference, comprising a bulk transistor and a silicon-on-insulator transistor, obtained by the method of any one of claims 1-8, characterized in that: Includes the same silicon substrate, on which silicon-on-insulator transistor units and bulk transistor units are integrated; The silicon substrate has silicon grooves with varying depths inside, and the grooves are filled with oxide dielectric. A top silicon layer is provided above the oxide dielectric corresponding to the silicon-on-insulator transistor unit, thus forming a silicon-on-insulator structure. The oxide dielectric corresponding to the block transistor unit is embedded inside the silicon substrate. The top surface height of the gate structure of all transistor units is consistent. The gate structure includes a high dielectric constant gate dielectric layer and a metal gate layer.

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