Method for manufacturing a semiconductor device and semiconductor device

Abstract

The present disclosure relates to a semiconductor device manufacturing method and a semiconductor device, and relates to the technical field of integrated circuits, comprising: providing a substrate; the substrate comprising a first limiting groove and a second limiting groove; forming a first protective layer on the top surface of the substrate, and at least rounding the corner between the first limiting groove and the first active region; forming a first well in the first active region of the substrate, and after forming a second well in the second active region of the substrate, removing the first protective layer; the first well and the second well are used to manufacture transistors with different voltage amplitudes; the height difference between the bottom surface of the first limiting groove and the bottom surface of the second limiting groove is related to the voltage amplitude; and in the process of forming a first gate structure, a first limiting structure is formed, a second limiting structure is formed, and a second gate structure is formed; the height difference between the top surface of the first active region and the top surface of the second active region is related to the voltage amplitude. At least the performance of the semiconductor device can be improved.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and in particular to a method for fabricating a semiconductor device and the semiconductor device itself. Background Technology

[0002] To accommodate the voltage amplitude of the transistor, the top surface of the active region of some transistors needs to be lower than the top surface of the substrate.

[0003] However, in conventional techniques, when forming the active region below the substrate's top surface, the etching micro-load effect causes a noticeable warping morphology at the interface between the transistor's limiting structure and the active region, thus affecting the performance of the semiconductor device. Therefore, avoiding the adverse effects of the warping morphology at the interface between the transistor's limiting structure and the active region on semiconductor devices has become one of the urgent technical problems to be solved. Summary of the Invention

[0004] Therefore, it is necessary to address the technical problem of how to avoid the adverse effects of the warp shape at the junction of the limiting structure and the active region on semiconductor devices in the prior art, and to provide a method for fabricating a semiconductor device and a semiconductor device.

[0005] In a first aspect, this disclosure provides a method for fabricating a semiconductor device, comprising:

[0006] A substrate is provided; the substrate includes a first limiting groove for defining a first active region and a second limiting groove for defining a second active region; the top surface of the first active region is lower than the top surface of the second active region;

[0007] A first protective layer is formed on the top surface of the substrate, and at least the corner between the first limiting groove and the first active region is rounded.

[0008] After forming a first well in a first active region of the substrate and a second well in a second active region of the substrate, the first protective layer is removed; the first well and the second well are used to fabricate transistors with different voltage amplitudes, and the height difference between the bottom surface of the first limiting groove and the bottom surface of the second limiting groove is related to the voltage amplitude; and

[0009] During the process of forming a first gate structure on the top surface of the first active region, a first limiting structure is formed in the first limiting groove, a second limiting structure is formed in the second limiting groove, and a second gate structure is formed on the top surface of the second active region. The top surface of the first gate structure is flush with the top surface of the second gate structure, and the height difference between the top surface of the first active region and the top surface of the second active region is related to the voltage amplitude.

[0010] In some embodiments, a substrate is provided, comprising:

[0011] A first and a second positioning groove with flush bottom surfaces are formed within the substrate;

[0012] The top surface of the substrate, the first limiting groove, and the second limiting groove are modified; and

[0013] A gate groove surrounded by a first limiting groove is formed, and the first limiting groove is etched to a preset depth. The bottom surface of the first limiting groove after being deepened is lower than the bottom surface of the second limiting groove. The bottom surface of the gate groove is used to form the top surface of the first active region.

[0014] In some embodiments, the modification treatment employs a plasma treatment process with an energy range of 50 eV to 100 eV.

[0015] In some embodiments, the height difference between the bottom surface of the gate groove and the top surface of the substrate ranges from 80 angstroms to 200 angstroms.

[0016] In some embodiments, the preset depth ranges from 100 angstroms to 250 angstroms.

[0017] In some embodiments, a first protective layer is formed using a thermal oxidation process, wherein the temperature range of the thermal oxidation process is 1000°C to 1200°C.

[0018] In some embodiments, the thickness of the first protective layer ranges from 70 angstroms to 100 angstroms.

[0019] In some embodiments, after rounding, the angle range of the corner between the first limiting groove and the first active area is 101°~108°.

[0020] In some embodiments, the voltage amplitude range of the transistor fabricated using the first well is 8V to 12V.

[0021] In some embodiments, the voltage amplitude of the transistor fabricated using the second well ranges from 0.9V to 2.5V.

[0022] In some embodiments, forming a first well and a second well includes:

[0023] A first barrier layer is formed on the top surface of the first protective layer;

[0024] The first blocking layer is graphically represented to form a first window, which exposes the first active region.

[0025] The first well is formed within the first active region;

[0026] A second barrier layer is formed on the top surface of the first protective layer;

[0027] The second blocking layer is graphically represented to form a second window, which exposes the second active region.

[0028] A second well is formed within the second active region; and

[0029] Remove the second barrier layer and the first barrier layer.

[0030] In some embodiments, the ion implantation energy ranges from 80 keV to 600 keV when forming the first well.

[0031] In some embodiments, when forming the second well, the ion implantation energy ranges from 3 keV to 300 keV.

[0032] In some embodiments, forming a first gate structure, a first limiting structure, a second limiting structure, and a second gate structure includes:

[0033] A first gate oxide layer is formed on the top surface of the substrate;

[0034] A third barrier layer is formed on the top surface of the first gate oxide layer;

[0035] Remove the third barrier layer and the first gate oxide layer outside the first active region; the top surface of the third barrier layer is flush with the top surface of the second active region;

[0036] Simultaneously, a first limiting structure is formed within the first limiting groove, and a second limiting structure is formed within the second limiting groove; and

[0037] A second gate oxide layer is formed on the top surface of the substrate. The second gate oxide layer at least covers the third barrier layer and the second active region. The first gate oxide layer, the third barrier layer and the second gate oxide layer on the top surface of the first active region constitute the first gate structure, and the second gate oxide layer on the top surface of the second active region constitutes the second gate structure.

[0038] In some embodiments, forming a first limiting structure and a second limiting structure includes:

[0039] A filling layer is formed on the top surface of the substrate, the filling layer at least filling the first limiting groove and the second limiting groove; and

[0040] Remove the filling layer outside the first and second limiting grooves.

[0041] In some embodiments, the thickness of the first gate oxide layer ranges from 80 angstroms to 200 angstroms.

[0042] In some embodiments, the thickness of the third barrier layer ranges from 10 angstroms to 30 angstroms.

[0043] In some embodiments, the thickness of the first gate structure ranges from 200 angstroms to 500 angstroms.

[0044] In some embodiments, the thickness of the second gate oxide layer ranges from 5 angstroms to 50 angstroms.

[0045] In some embodiments, the thickness of the filler layer ranges from 2000 angstroms to 4000 angstroms.

[0046] In a second aspect, this disclosure provides a semiconductor device, comprising:

[0047] The substrate includes a first limiting groove for defining a first active region, a second limiting groove for defining a second active region, a first well located within the first active region, and a second well located within the second active region; the first well and the second well are used to fabricate transistors with different voltage amplitudes, the top surface of the first active region is lower than the top surface of the second active region, and the height difference between the bottom surfaces of the first limiting groove and the second limiting groove is related to the voltage amplitude; and

[0048] The first gate structure is located on the top surface of the first active region, the first limiting structure is located in the first limiting groove, the second limiting structure is located in the second limiting groove, and the second gate structure is located on the top surface of the second active region. The top surface of the first gate structure is flush with the top surface of the second gate structure, and the height difference between the top surface of the first active region and the top surface of the second active region is related to the voltage amplitude.

[0049] The corner between the first limiting groove and the first active area is rounded.

[0050] The method for fabricating the semiconductor device and the semiconductor device in the embodiments of this disclosure include the following unexpected technical effects:

[0051] By forming a first limiting groove and a first active region on the substrate, the corner between the first limiting groove and the first active region is exposed. Before forming the gate structure and the limiting structure, the corner between the first limiting groove and the first active region is rounded. This ensures that when the first gate structure located on the top surface of the first active region is subsequently formed, the gate oxide layer grown at the corner has a uniform thickness, reducing the stress of the gate oxide layer at the corner. This improves the reliability of the transistor in the first active region and thus enhances the performance of the semiconductor device.

[0052] Furthermore, the substrate includes a first limiting groove for defining a first active region and a second limiting groove for defining a second active region. A first well is formed in the first active region of the substrate, and a second well is formed in the second active region of the substrate. The first well and the second well are used to fabricate transistors with different voltage amplitudes, and the height difference between the bottom surface of the first limiting groove and the bottom surface of the second limiting groove is related to the voltage amplitude of the transistor. This allows the first limiting groove to adapt to the voltage withstand requirements of the transistor fabricated in the first well, and the second limiting groove to adapt to the voltage withstand requirements of the transistor fabricated in the second well, thereby improving the performance of the semiconductor device.

[0053] Furthermore, during the process of forming a first gate structure on the top surface of the first active region on the substrate, a second gate structure is formed on the top surface of the second active region on the substrate. The top surfaces of the first gate structure and the second gate structure are flush. The height difference between the top surfaces of the first active region and the second active region on the substrate is related to the voltage amplitude of the transistor, so that the thickness of the first gate structure and the thickness of the second gate structure are adapted to transistors with different voltage amplitudes, thereby improving the gate control capability of the transistor gate structure and improving the performance of the semiconductor device.

[0054] Furthermore, a first protective layer is formed on the top surface of the substrate, and at least the corner between the first limiting groove and the first active region is rounded to make the first protective layer more uniform at the corner. Moreover, the first protective layer is removed after the formation of the first and second wells, ensuring that the uniform first protective layer avoids damage caused by the ion implantation process during the formation of the first and second wells. Attached Figure Description

[0055] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0056] Figure 1 This is a schematic flowchart of a method for fabricating a semiconductor device provided in one embodiment;

[0057] Figure 2 This is a schematic diagram of the longitudinal section of the semiconductor structure obtained after forming a first limiting groove and a second limiting groove on a substrate in a semiconductor device fabrication method provided in one embodiment.

[0058] Figure 3 This is a schematic diagram of the longitudinal section of the semiconductor structure obtained after removing the first hard mask layer in the semiconductor device fabrication method provided in one embodiment.

[0059] Figure 4 This is a schematic diagram of the longitudinal section of the semiconductor structure obtained after patterning the second photoresist layer in a semiconductor device fabrication method provided in one embodiment.

[0060] Figure 5 This is a schematic diagram of the longitudinal section of the semiconductor structure obtained after forming a gate groove in a semiconductor device fabrication method provided in one embodiment;

[0061] Figure 6 This is a schematic diagram of the longitudinal section of the semiconductor structure obtained after forming the first protective layer in the semiconductor device fabrication method provided in one embodiment;

[0062] Figure 7 This is a schematic diagram of the longitudinal section of the semiconductor structure obtained after forming the first well in a method for fabricating a semiconductor device provided in one embodiment.

[0063] Figure 8 This is a schematic diagram of the longitudinal section of the semiconductor structure obtained after forming the second well in the semiconductor device fabrication method provided in one embodiment;

[0064] Figure 9 This is a schematic diagram of the longitudinal section of the semiconductor structure obtained after removing the first protective layer in the semiconductor device fabrication method provided in one embodiment.

[0065] Figure 10 This is a schematic diagram of the longitudinal section of the semiconductor structure obtained after forming the first gate oxide layer in the semiconductor device fabrication method provided in one embodiment;

[0066] Figure 11 This is a schematic diagram of the longitudinal section of the semiconductor structure obtained after forming the third barrier layer in the semiconductor device fabrication method provided in one embodiment;

[0067] Figure 12 This is a schematic diagram of the longitudinal section of the semiconductor structure obtained after patterning the fifth photoresist layer in a semiconductor device fabrication method provided in one embodiment.

[0068] Figure 13 This is a schematic diagram of the longitudinal section of the semiconductor structure obtained after removing the first gate oxide layer and the third barrier layer outside the first active region in the semiconductor device fabrication method provided in one embodiment.

[0069] Figure 14 This is a schematic diagram of the longitudinal section of the semiconductor structure obtained after forming a filling layer in the semiconductor device fabrication method provided in one embodiment;

[0070] Figure 15 This is a schematic diagram of the longitudinal section of the semiconductor structure obtained after forming the first limiting structure and the second limiting structure in the semiconductor device fabrication method provided in one embodiment.

[0071] Figure 16 This is a schematic diagram of the longitudinal section of the semiconductor structure obtained after forming the second gate oxide layer in a method for fabricating a semiconductor device provided in one embodiment.

[0072] Explanation of reference numerals in the attached figures:

[0073] 100, First transistor; 110, First limiting groove; 120, Gate groove; 130, First well; 200, Second transistor; 210, Second limiting groove; 220, Second well; 310, Substrate; 311, First substrate; 312, Second substrate; 321, Second protective layer; 322, First hard mask layer; 331, Second hard mask layer; 332, Second photoresist layer; 340, First protective layer; 351, First barrier layer; 352, Third photoresist layer; 361, Second barrier layer; 362, Fourth photoresist layer; 371, First gate oxide layer; 372, Third barrier layer; 373, Second gate oxide layer; 380, Fifth photoresist layer; 390, Filler layer. Detailed Implementation

[0074] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0075] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0076] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0077] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0078] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0079] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of preferred embodiments (and intermediate structures) of the present disclosure, thus allowing for variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the present disclosure.

[0080] In this embodiment, neglecting the flatness of the substrate surface, the direction parallel to the substrate surface is, for example, a first direction, and the stacking direction or the direction away from the substrate surface (the thickness direction of the substrate) is, for example, a second direction. In this embodiment, the first direction can be the ox direction, and the second direction can be the oz direction. The "longitudinal section" in this embodiment is perpendicular to the top surface of the substrate.

[0081] Please refer to Figure 1 In some embodiments, this application provides a method for fabricating a semiconductor device, including steps S10 to S40:

[0082] Step S10, providing a substrate; the substrate includes a first limiting groove for defining a first active region and a second limiting groove for defining a second active region; the top surface of the first active region is lower than the top surface of the second active region.

[0083] In step S20, a first protective layer is formed on the top surface of the substrate, and at least the corner between the first limiting groove and the first active region is rounded.

[0084] In step S30, after forming a first well in the first active region of the substrate and a second well in the second active region of the substrate, the first protective layer is removed; the first well and the second well are used to fabricate transistors with different voltage amplitudes, and the height difference between the bottom surface of the first limiting groove and the bottom surface of the second limiting groove is related to the voltage amplitude.

[0085] In step S40, during the process of forming the first gate structure on the top surface of the first active region, a first limiting structure is formed in the first limiting groove, a second limiting structure is formed in the second limiting groove, and a second gate structure is formed on the top surface of the second active region. The top surface of the first gate structure is flush with the top surface of the second gate structure, and the height difference between the top surface of the first active region and the top surface of the second active region is related to the voltage amplitude.

[0086] The semiconductor device fabrication method in this embodiment forms a first limiting groove and a first active region on a substrate, exposing the corner between the first limiting groove and the first active region. Before forming the gate structure and the limiting structure, the corner between the first limiting groove and the first active region is rounded. This ensures that when the first gate structure located on the top surface of the first active region is subsequently formed, the gate oxide layer grown at the corner has a uniform thickness, reducing the stress of the gate oxide layer at the corner, thereby improving the reliability of the transistor in the first active region and thus improving the performance of the semiconductor device.

[0087] Furthermore, the substrate includes a first limiting groove for defining a first active region and a second limiting groove for defining a second active region. A first well is formed in the first active region of the substrate, and a second well is formed in the second active region of the substrate. The first well and the second well are used to fabricate transistors with different voltage amplitudes, and the height difference between the bottom surface of the first limiting groove and the bottom surface of the second limiting groove is related to the voltage amplitude of the transistor. This allows the first limiting groove to adapt to the voltage withstand requirements of the transistor fabricated in the first well, and the second limiting groove to adapt to the voltage withstand requirements of the transistor fabricated in the second well, thereby improving the performance of the semiconductor device.

[0088] Furthermore, during the process of forming a first gate structure on the top surface of the first active region on the substrate, a second gate structure is formed on the top surface of the second active region on the substrate. The top surfaces of the first gate structure and the second gate structure are flush. The height difference between the top surfaces of the first active region and the second active region on the substrate is related to the voltage amplitude of the transistor, so that the thickness of the first gate structure and the thickness of the second gate structure are adapted to transistors with different voltage amplitudes, thereby improving the gate control capability of the transistor gate structure and improving the performance of the semiconductor device.

[0089] Furthermore, a first protective layer is formed on the top surface of the substrate, and at least the corner between the first limiting groove and the first active region is rounded to make the first protective layer more uniform at the corner. Moreover, the first protective layer is removed after the formation of the first and second wells, ensuring that the uniform first protective layer avoids damage caused by the ion implantation process during the formation of the first and second wells.

[0090] Please refer to Figure 2In one embodiment, the substrate 310 may be constructed of a semiconductor material, an insulating material, a conductive material, or any combination thereof. The substrate 310 may be a single-layer structure or a multi-layer structure. For example, the substrate 310 may be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates, or II / VI semiconductor substrates. Alternatively, for example, the substrate 310 may be a layered substrate comprising materials such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator.

[0091] Please continue to refer to this. Figure 2 In one embodiment, the substrate 310 has a double-layer structure, including a first substrate 311 and a second substrate 312. The first substrate 311 can be a P-type heavily doped type or an N-type heavily doped type, and the second substrate 312 can have the same doping type as the first substrate 311, and the doping concentration of the second substrate 312 is higher than that of the first substrate 311.

[0092] Please continue to refer to this. Figure 2 For example, the substrate 310 is a P-type substrate 310, so that a P-channel metal-oxide-semiconductor (PMOS) can be fabricated on the substrate 310.

[0093] In one embodiment, step S10, which provides substrate 310, may include steps S11 to S13.

[0094] Step S11: A first limiting groove 110 and a second limiting groove 210 with their bottom surfaces flush are formed in the substrate 310.

[0095] Please continue to refer to this. Figure 2 For example, a second protective layer 321 is formed on the top surface of the substrate 310. A first hard mask layer 322 is formed on the top surface of the second protective layer 321. A first photoresist layer (not shown) is spin-coated on the top surface of the first hard mask layer 322, and the first photoresist layer is patterned such that openings defining the first limiting groove 110 and the second limiting groove 210 are formed on the first photoresist layer. The first hard mask layer 322, the second protective layer 321, and the substrate 310 are etched based on the openings on the first photoresist layer, thereby forming the first limiting groove 110 and the second limiting groove 210 with flush bottoms on the substrate 310. Please refer to Figure 2 and Figure 3 After forming the first limiting groove 110 and the second limiting groove 210, the first photoresist layer and the first hard mask layer 322 are removed.

[0096] Please continue to refer to this. Figure 2 For example, the second protective layer 321 may be formed using at least one process, such as thermal oxidation or deposition. The material of the second protective layer 321 may include silicon oxide (SiO2) or the like.

[0097] Please continue to refer to this. Figure 2 For example, a first hard mask layer 322 may be formed on the top surface of the second protective layer 321 using a process such as chemical vapor deposition. The material of the first hard mask layer 322 may include silicon nitride (SiN) or the like.

[0098] Please refer to Figure 3 For example, at least one of wet etching and dry etching can be used to remove the first hard mask layer 322 and the first photoresist layer.

[0099] Step S12 involves modifying the top surface of the substrate 310, the first limiting groove 110, and the second limiting groove 210.

[0100] Please continue to refer to this. Figure 3 For example, the modification treatment can employ a plasma treatment process with an energy range of 50 eV to 100 eV, such as 50 eV, 60 eV, 75 eV, 90 eV, or 100 eV. For instance, at least one of ionized argon plasma, hydrogen plasma, and helium plasma can be used to bombard the top surface of the substrate 310, the bottom of the first limiting groove 110, and the bottom of the second limiting groove 210. In step S12, the top surface of the substrate 310 refers to the surface of the uppermost material of the substrate 310. For example, if the top surface of the substrate 310 still retains a second protective layer 321 in step S11, then in step S12, plasma is used to bombard the top surface of the second protective layer 321 and the first limiting groove 110 and the second limiting groove 210 exposed by the second protective layer 321.

[0101] Step S13: A gate groove 120 surrounded by the first limiting groove 110 is formed, and the first limiting groove 110 is etched to a preset depth. The bottom surface of the first limiting groove 110 after being deepened is lower than the bottom surface of the second limiting groove 210. The bottom surface of the gate groove 120 is used to form the top surface of the first active region.

[0102] Please refer to Figure 4 For example, a second hard mask layer 331 is spin-coated onto the top surface of the second protective layer 321. The second hard mask layer 331 covers the top surface of the second protective layer 321 and fills the first limiting groove 110 and the second limiting groove 210. After planarizing the second hard mask layer 331, a second photoresist layer 332 is spin-coated onto the top surface of the second hard mask layer 331. The second photoresist layer 332 is patterned to form corresponding openings. Please refer to... Figure 5The opening on the second photoresist layer 332 etches the second hard mask layer 331, the second protective layer 321, and the substrate 310, forming a gate recess 120 surrounded by the first limiting groove 110 in the first active region. The bottom surface of the gate recess 120 is the top surface of the first active region. Since the top surface of the second active region is the original top surface of the substrate 310, the height difference between the bottom surface of the gate recess 120 and the top surface of the second active region can be equal to the height difference between the bottom surface of the gate recess 120 and the top surface of the substrate 310, without considering the flatness of the top surface of the substrate 310. During the etching of the substrate 310 to form the gate recess 120, the first limiting groove 110 is also exposed. Because the first limiting groove 110 was modified before the gate recess 120 was formed, the first limiting groove 110 is easily etched deeper during the formation of the gate recess 120, so that the bottom surface of the first limiting groove 110 on the substrate 310 is lower than the bottom surface of the second limiting groove 210. After the gate recess 120 is formed, the second hard mask layer 331 and the second photoresist layer 332 can be removed.

[0103] Please continue to refer to this. Figure 5 For example, the second hard mask layer 331 may include at least one of carbon and bottom anti-reflective coating (BARC).

[0104] Please continue to refer to this. Figure 5 For example, the height difference between the bottom surface of the gate groove 120 and the top surface of the substrate 310 ranges from 80 angstroms to 200 angstroms, such as 80 angstroms, 100 angstroms, 120 angstroms, 150 angstroms, 180 angstroms, and 200 angstroms.

[0105] Please continue to refer to this. Figure 5For example, after etching the first limiting groove 110 to a preset depth, the bottom surface of the first limiting groove 110 can be lower than the bottom surface of the second limiting groove 210 by a preset depth. That is, by controlling the preset depth of etching the first limiting groove 110, the height difference between the bottom surfaces of the first limiting groove 110 and the second limiting groove 210 can be controlled. The height difference between the bottom surfaces of the first limiting groove 110 and the second limiting groove 210 can be related to the voltage amplitude of the first transistor 100 formed in the first active region and the second transistor 200 formed in the second active region. For example, the voltage amplitude of the first transistor 100 can be greater than the voltage amplitude of the second transistor 200, so that for the first transistor 100 and the second transistor 200, the first transistor 100 can be a medium-voltage MOS (MVMOS), and the second transistor 200 can be a low-voltage MOS (LVMOS). For example, the voltage amplitude range of the first transistor 100 is 8V to 12V, such as 8V, 9V, 10V, 11V, or 12V. For example, the voltage amplitude range of the second transistor 200 is 0.9V to 2.5V, such as 0.9V, 1V, 2V, or 2.5V. The bottom surface of the first limiting groove 110 is lower than the bottom surface of the second limiting groove 210 so that the corresponding limiting structure formed subsequently can meet the voltage withstand requirements of the corresponding transistor.

[0106] Please continue to refer to this. Figure 5 For example, the preset depth of etching the first limiting groove 110 ranges from 100 angstroms to 250 angstroms, such as 100 angstroms, 120 angstroms, 150 angstroms, 180 angstroms, 200 angstroms, 220 angstroms, and 250 angstroms.

[0107] Please refer to Figure 6In one embodiment, when forming a first protective layer 340 on the top surface of the substrate 310 in step S20, and at least rounding the corner between the first limiting groove 110 and the first active region, a thermal oxidation process can be used to form the first protective layer 340. When forming the first protective layer 340 using a thermal oxidation process, the oxidation rate of the corner between the first limiting groove 110 and the first active region is much greater than that of the planar sidewall. More of the substrate 310 at the corner is consumed to generate a thicker first protective layer 340, and the corner naturally forms a rounded arc, eliminating the need for an additional etching rounding process. During thermal oxidation, not only can the corner between the first limiting groove 110 and the first active region be rounded, but also the corner between the other sidewall of the first limiting groove 110 and the top surface of the substrate 310 can be rounded simultaneously, as can the corner between the second limiting groove 210 and the top surface of the substrate 310. This improves the reliability of the transistors formed by the first and second active regions and enhances the performance of the semiconductor device. In other examples, other methods can also be used to round the corner between the first limiting groove 110 and the first active area.

[0108] It should be noted that, in Figure 6 In the embodiment, the first protective layer 340 and the second protective layer 321 are made of the same material, for example, both are SiO2, so only the marking of the first protective layer 340 is shown, and the marking of the second protective layer 321 is not shown. In fact, in Figure 6 In one embodiment, a second protective layer 321 is further provided at a portion of the location between the substrate 310 and the first protective layer 340. In other examples, the second protective layer 321 may be removed before the first protective layer 340 is formed. In other examples, the material of the first protective layer 340 may also be different from the material of the second protective layer 321.

[0109] Please continue to refer to this. Figure 6 For example, the first protective layer 340 can be formed by processes such as in-situ steam generation (ISSG).

[0110] Please continue to refer to this. Figure 6 For example, the temperature range of the thermal oxidation process is 1000℃~1200℃, such as 1000℃, 1050℃, 1100℃, 1150℃, and 1200℃.

[0111] Please continue to refer to this. Figure 6 For example, the thickness of the first protective layer 340 ranges from 70 angstroms to 100 angstroms, such as 70 angstroms, 75 angstroms, 80 angstroms, 85 angstroms, 90 angstroms, 95 angstroms, and 100 angstroms.

[0112] Please continue to refer to this. Figure 6For example, after the rounding process, the angle range of the corner between the first limiting groove 110 and the first active area is 101°~108°, such as 101°, 103°, 105°, 108°.

[0113] In one embodiment, step S30, forming the first well 130 and the second well 220, includes steps S31 to S37:

[0114] Please refer to Figure 7 In step S31, a first barrier layer 351 is formed on the top surface of the first protective layer 340. Exemplarily, the first barrier layer 351 can be formed using a spin coating process. The material of the first barrier layer 351 may include at least one of carbon and an undercoat antireflective coating.

[0115] Please continue to refer to this. Figure 7 In step S32, the first barrier layer 351 is patterned to form a first window, which exposes the first active region. Exemplarily, a third photoresist layer 352 is spin-coated onto the top surface of the first barrier layer 351. The third photoresist layer 352 is exposed and developed to form an opening defining the first limiting groove 110 and the gate recess 120. The first barrier layer 351 is etched based on the opening on the third photoresist layer 352, thereby exposing at least the first active region. In some examples, exposing the first active region may be exposing the first protective layer 340 within the first limiting groove 110 and the gate recess 120.

[0116] Please continue to refer to this. Figure 7 In step S33, a first well 130 is formed in the first active region. For example, the first well 130 can be formed using processes such as ion implantation.

[0117] Please continue to refer to this. Figure 7 For example, the first well 130 can be formed by ion implantation in 3 to 5 stages. The energy range of ion implantation when forming the first well 130 is 80 keV to 600 keV, for example 80 keV, 100 keV, 200 keV, 300 keV, 400 keV, 500 keV, and 600 keV.

[0118] Please continue to refer to this. Figure 7 For example, the voltage amplitude range of the first transistor 100 prepared by the first well 130 is 8V~12V, such as 8V, 9V, 10V, 11V, 12V.

[0119] Please continue to refer to this. Figure 7 For example, the substrate 310 is a P-type substrate 310. When forming the first well 130, elements such as phosphorus (P) or arsenic (As) can be implanted to form an N-type well, thereby forming a PMOS.

[0120] Please refer to Figure 8 In step S34, a second barrier layer 361 is formed on the top surface of the first protective layer 340. Exemplarily, the second barrier layer 361 can be formed using a spin coating process. The material of the second barrier layer 361 may include at least one of carbon and an undercoat antireflective coating.

[0121] Please continue to refer to this. Figure 8 In step S35, the second barrier layer 361 is patterned to form a second window, which exposes the second active region. Exemplarily, a fourth photoresist layer 362 is spin-coated onto the top surface of the second barrier layer 361. The fourth photoresist layer 362 is patterned to form an opening defining the second limiting groove 210 and the second active region. The second barrier layer 361 is etched based on the opening in the fourth photoresist layer 362 to expose the second active region. In some examples, exposing the second active region may be exposing the first protective layer 340 within the second limiting groove 210 and on the top surface of the second active region.

[0122] Please continue to refer to this. Figure 8 In step S36, a second well 220 is formed in the second active region. For example, the second well 220 can be formed using processes such as ion implantation.

[0123] Please continue to refer to this. Figure 8 For example, the second well 220 can be formed by ion implantation in 3 to 5 stages. The energy range of ion implantation when forming the second well 220 is 3 keV to 300 keV, for example, 3 keV, 50 keV, 100 keV, 200 keV, and 300 keV.

[0124] Please continue to refer to this. Figure 8 For example, the voltage amplitude range of the second transistor 200 prepared by the second well 220 is 0.9V to 2.5V, such as 0.9V, 1V, 2V, 2.5V.

[0125] Please continue to refer to this. Figure 8 For example, the substrate 310 is a P-type substrate 310. When forming the second well 220, elements such as phosphorus (P) or arsenic (As) can be implanted to form an N-type well, thereby forming a PMOS.

[0126] Please refer to Figure 9 Step S37: Remove the second barrier layer 361 and the first barrier layer 351. For example, a wet etching process can be used to remove the first barrier layer 351 and the second barrier layer 361.

[0127] It should be noted that this embodiment does not limit the order in which the first well 130 and the second well 220 are formed. The first well 130 can be formed first, followed by the second well 220; or the second well 220 can be formed first, followed by the first well 130. For example, if the first well 130 is formed first, only the third photoresist layer 352 can be removed, so that the second barrier layer 361 is formed on the top surface of the first barrier layer 351. The first barrier layer 351 and the second barrier layer 361 can use the same material, and the first barrier layer 351 and the second barrier layer 361 can be removed together after the second well 220 is formed.

[0128] In this embodiment, when the first well 130 and the second well 220 are formed by ion implantation, the top of the first active region can be protected by a first protective layer 340, and the top of the second active region can be protected by a first protective layer 340 and a second protective layer 321, which can reduce the damage caused by the ion implantation process. Furthermore, since the corner between the first active region and the first limiting groove 110 is rounded when the first protective layer 340 is formed, the first protective layer 340 at the corner is evenly distributed, thereby further reducing the damage caused by the ion implantation process.

[0129] Please continue to refer to this. Figure 9 After removing the second barrier layer 361 and the first barrier layer 351, the first protective layer 340 can be removed. For example, a wet etching process can be used to remove the first protective layer 340.

[0130] In one embodiment, step S40, forming a first gate structure, a first limiting structure, a second limiting structure, and a second gate structure, includes steps S41 to S45:

[0131] Please refer to Figure 10 In step S41, a first gate oxide layer 371 is formed on the top surface of the substrate 310. Exemplarily, the first gate oxide layer 371 can be grown on the top surface of the substrate 310 using at least one of ISSG and High Temperature Oxide (HTO) processes. The first gate oxide layer 371 at least covers the bottom of the gate recess 120, all the sidewalls and bottom of the limiting grooves, and the top surface of the second active region. Exemplarily, the first gate oxide layer 371 can be generated first using the ISSG process and then using the HTO process. Exemplarily, the material of the first gate oxide layer 371 includes SiO2. Exemplarily, the thickness of the first gate oxide layer 371 ranges from 80 angstroms to 200 angstroms, for example, 80 angstroms, 100 angstroms, 120 angstroms, 150 angstroms, 170 angstroms, and 200 angstroms.

[0132] Please refer to Figure 11In step S42, a third barrier layer 372 is formed on the top surface of the first gate oxide layer 371. Exemplarily, the third barrier layer 372 can be formed using processes such as chemical vapor deposition. The third barrier layer 372 covers the top surface of the first gate oxide layer 371, at least covering the top surface of the first gate oxide layer 371 above the first active region. Exemplarily, the material of the third barrier layer 372 includes at least one of titanium nitride (TiN) and silicon nitride (SiN). Exemplarily, the thickness of the third barrier layer 372 ranges from 10 angstroms to 20 angstroms, for example, 10 angstroms, 12 angstroms, 15 angstroms, 18 angstroms, or 20 angstroms.

[0133] Please refer to Figure 12 and Figure 13 In step S43, the third barrier layer 372 and the first gate oxide layer 371 outside the first active region are removed. Exemplarily, a fifth photoresist layer 380 can be formed on the top surface of the third barrier layer 372. The fifth photoresist layer 380 is patterned so that only the portion of the fifth photoresist layer 380 above the first active region is retained. Based on the protection of the fifth photoresist layer 380, the excess third barrier layer 372 and the first gate oxide layer 371 outside the first active region are removed using processes such as dry plasma etching. The top surface of the third barrier layer 372 is flush with the top surface of the second active region, making the top surface of the third barrier layer 372 flatter and the third barrier layer 372 more uniform.

[0134] Please refer to Figures 13 to 15 In step S44, a first limiting structure is formed within the limiting groove, and a second limiting structure is formed within the second limiting groove 210. Exemplarily, a filling layer 390 is formed on the top surface of the substrate 310, the filling layer 390 at least filling the first limiting groove 110 and the second limiting groove 210; the filling layer 390 outside the first limiting groove 110 and the second limiting groove 210 is removed. Exemplarily, the filling layer 390 can be formed using a silicon oxide deposition process. Exemplarily, the thickness of the filling layer 390 ranges from 2000 angstroms to 4000 angstroms, for example, 2000 angstroms, 2200 angstroms, 2500 angstroms, 2700 angstroms, 3000 angstroms, 3200 angstroms, 3500 angstroms, 3700 angstroms, and 4000 angstroms. For example, a chemical mechanical planarization (CMP) process can be used to remove excess filler layer 390 outside the first limiting groove 110 and the second limiting groove 210. The filler layer 390 in the first limiting groove 110 constitutes a first limiting structure for limiting the first active region, and the filler layer 390 in the second limiting groove 210 constitutes a second limiting structure for limiting the second active region.

[0135] Please refer to Figure 16In step S45, a second gate oxide layer 373 is formed on the top surface of the substrate 310. The second gate oxide layer 373 at least covers the third barrier layer 372 and the second active region. Exemplarily, the exposed second active region can be cleaned using a wet process before forming the second gate oxide layer 373. Exemplarily, the second gate oxide layer 373 can be grown on the top surface of the substrate 310 using at least one of ISSG and HTO processes. Exemplarily, the material of the second gate oxide layer 373 includes SiO2. Exemplarily, the thickness of the second gate oxide layer 373 ranges from 5 angstroms to 50 angstroms, for example, 5 angstroms, 10 angstroms, 20 angstroms, 30 angstroms, 40 angstroms, and 50 angstroms. The first gate oxide layer 371, the third barrier layer 372, and the second gate oxide layer 373 within the first active region constitute a first gate structure, and the second gate oxide layer 373 within the second active region constitutes a second gate structure. For example, the thickness of the first gate structure ranges from 200 angstroms to 500 angstroms, such as 200 angstroms, 250 angstroms, 300 angstroms, 350 angstroms, 400 angstroms, 450 angstroms, and 500 angstroms.

[0136] Please refer to Figures 1-16 This application also provides a semiconductor device formed using the fabrication method of the semiconductor device in any of the above embodiments. The semiconductor device includes a substrate 310. The substrate 310 includes a first limiting groove 110 for defining a first active region, a second limiting groove 210 for defining a second active region, a first well 130 located within the first active region, and a second well 220 located within the second active region. The first well 130 and the second well 220 are respectively used to fabricate transistors with different voltage amplitudes. The top surface of the first active region is lower than the top surface of the second active region, and the height difference between the bottom surface of the first limiting groove 110 and the bottom surface of the second limiting groove 210 is related to the voltage amplitude. The semiconductor device also includes a first gate structure located on the top surface of the first active region, a first limiting structure located within the first limiting groove 110, a second limiting structure located within the second limiting groove 210, and a second gate structure located on the top surface of the second active region. The top surface of the first gate structure is flush with the top surface of the second gate structure, and the height difference between the top surface of the first active region and the top surface of the second active region is related to the voltage amplitude. The corner between the first limiting groove 110 and the first active area is rounded.

[0137] Please continue to refer to this. Figures 1-16 The semiconductor device fabrication method and semiconductor device in this disclosure embodiment have the following unexpected technical effects:

[0138] By forming a first limiting groove 110 and a first active region on the substrate 310, the corner between the first limiting groove 110 and the first active region is exposed. Before forming the gate structure and the limiting structure, the corner between the first limiting groove 110 and the first active region is rounded. This ensures that when the first gate structure located on the top surface of the first active region is subsequently formed, the thickness of the gate oxide layer grown at the corner is uniform, reducing the stress of the gate oxide layer at the corner. This improves the reliability of the transistor in the first active region and thus improves the performance of the semiconductor device.

[0139] Furthermore, the substrate 310 includes a first limiting groove 110 for defining a first active region and a second limiting groove 210 for defining a second active region. A first well 130 is formed in the first active region of the substrate 310, and a second well 220 is formed in the second active region of the substrate 310. The first well 130 and the second well 220 are respectively used to fabricate transistors with different voltage amplitudes. The height difference between the bottom surface of the first limiting groove 110 and the bottom surface of the second limiting groove 210 is related to the voltage amplitude of the transistor, so that the first limiting groove 110 is adapted to the voltage withstand requirement of the transistor fabricated in the first well 130, and the second limiting groove 210 is adapted to the voltage withstand requirement of the transistor fabricated in the second well 220, thereby improving the performance of the semiconductor device.

[0140] Furthermore, during the process of forming the first gate structure on the top surface of the first active region on the substrate 310, a second gate structure is formed on the top surface of the second active region on the substrate 310. The top surfaces of the first gate structure and the second gate structure are flush. The height difference between the top surfaces of the first active region and the second active region on the substrate 310 is related to the voltage amplitude of the transistor, so that the thickness of the first gate structure and the thickness of the second gate structure are adapted to transistors with different voltage amplitudes, thereby improving the gate control capability of the transistor gate structure and improving the performance of the semiconductor device.

[0141] Furthermore, a first protective layer 340 is formed on the top surface of the substrate 310, and at least the corner between the first limiting groove 110 and the first active region is rounded, making the first protective layer 340 more uniform at the corner. Moreover, the first protective layer 340 is removed after the formation of the first well 130 and the second well 220, ensuring that the uniform first protective layer 340 avoids damage caused by the ion implantation process during the formation of the first well 130 and the second well 220.

[0142] It should be understood that, although Figure 1 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0143] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0144] The embodiments described above are merely illustrative of several implementation methods of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these modifications and improvements all fall within the scope of protection of this disclosure.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: Provide substrate; The substrate includes a first limiting groove for defining a first active region and a second limiting groove for defining a second active region; The top surface of the first active region is lower than the top surface of the second active region; A first protective layer is formed on the top surface of the substrate, and at least the corner between the first limiting groove and the first active region is rounded. After forming a first well in the first active region of the substrate and a second well in the second active region of the substrate, the first protective layer is removed; the first well and the second well are respectively used to fabricate transistors with different voltage amplitudes, and the height difference between the bottom surface of the first limiting groove and the bottom surface of the second limiting groove is related to the voltage amplitude; and During the process of forming a first gate structure on the top surface of the first active region, a first limiting structure is formed in the first limiting groove, a second limiting structure is formed in the second limiting groove, and a second gate structure is formed on the top surface of the second active region. The top surface of the first gate structure is flush with the top surface of the second gate structure, and the height difference between the top surface of the first active region and the top surface of the second active region is related to the voltage amplitude.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The provision of the substrate includes: The first limiting groove and the second limiting groove are formed in the substrate with their bottom surfaces flush; The top surface of the substrate, the first limiting groove, and the second limiting groove are modified; and A gate groove is formed surrounded by the first limiting groove, and the first limiting groove is etched to a predetermined depth. The bottom surface of the first limiting groove after being deepened is lower than the bottom surface of the second limiting groove. The bottom surface of the gate groove is used to form the top surface of the first active region.

3. The method for fabricating a semiconductor device according to claim 2, characterized in that, Includes at least one of the following features: The modification treatment employs a plasma treatment process, the energy range of which is 50eV~100eV. The height difference between the bottom surface of the gate groove and the top surface of the substrate ranges from 80 angstroms to 200 angstroms; The preset depth ranges from 100 angstroms to 250 angstroms.

4. The method for fabricating a semiconductor device according to claim 1, characterized in that, Includes at least one of the following features: The first protective layer is formed by a thermal oxidation process, wherein the temperature range of the thermal oxidation process is 1000℃~1200℃; The thickness of the first protective layer ranges from 70 angstroms to 100 angstroms; After the rounding process, the angle range of the corner between the first limiting groove and the first active area is 101°~108°. The voltage amplitude range of the transistor fabricated using the first well is 8V~12V; The voltage amplitude range of the transistor fabricated using the second well is 0.9V to 2.5V.

5. The method for fabricating a semiconductor device according to claim 1, characterized in that, Forming the first well and the second well includes: A first barrier layer is formed on the top surface of the first protective layer; The first blocking layer is graphically represented to form a first window, which exposes the first active region. The first well is formed within the first active region; A second barrier layer is formed on the top surface of the first protective layer; The second blocking layer is graphically represented to form a second window, which exposes the second active region. The second well is formed within the second active region; and Remove the second barrier layer and the first barrier layer.

6. The method for fabricating a semiconductor device according to claim 5, characterized in that, Includes at least one of the following features: When forming the first well, the ion implantation energy range is 80 keV to 600 keV; When forming the second well, the ion implantation energy range is 3 keV to 300 keV.

7. The method for fabricating a semiconductor device according to claim 1, characterized in that, The formation of a first gate structure, a first limiting structure, a second limiting structure, and a second gate structure includes: A first gate oxide layer is formed on the top surface of the substrate; A third barrier layer is formed on the top surface of the first gate oxide layer; Remove the third barrier layer and the first gate oxide layer outside the first active region; the top surface of the third barrier layer is flush with the top surface of the second active region; Simultaneously, the first limiting structure is formed within the first limiting groove, and the second limiting structure is formed within the second limiting groove; and A second gate oxide layer is formed on the top surface of the substrate. The second gate oxide layer at least covers the third barrier layer and the second active region. The first gate oxide layer, the third barrier layer and the second gate oxide layer on the top surface of the first active region constitute the first gate structure, and the second gate oxide layer on the top surface of the second active region constitutes the second gate structure.

8. The method for fabricating a semiconductor device according to claim 7, characterized in that, Forming the first limiting structure and the second limiting structure includes: A filling layer is formed on the top surface of the substrate, the filling layer at least filling the first limiting groove and the second limiting groove; and Remove the filling layer outside the first limiting groove and the second limiting groove.

9. The method for fabricating a semiconductor device according to claim 8, characterized in that, Includes at least one of the following features: The thickness of the first gate oxide layer ranges from 80 angstroms to 200 angstroms; The thickness of the third barrier layer ranges from 10 angstroms to 30 angstroms; The thickness of the first gate structure ranges from 200 angstroms to 500 angstroms; The thickness of the second gate oxide layer ranges from 5 angstroms to 50 angstroms; The thickness of the filling layer ranges from 2000 angstroms to 4000 angstroms.

10. A semiconductor device, characterized in that, include: The substrate includes a first limiting groove for defining a first active region, a second limiting groove for defining a second active region, a first well located within the first active region, and a second well located within the second active region; the first well and the second well are respectively used to fabricate transistors with different voltage amplitudes, the top surface of the first active region is lower than the top surface of the second active region, and the height difference between the bottom surface of the first limiting groove and the bottom surface of the second limiting groove is related to the voltage amplitude; and The first gate structure is located on the top surface of the first active region, the first limiting structure is located in the first limiting groove, the second limiting structure is located in the second limiting groove, and the second gate structure is located on the top surface of the second active region. The top surface of the first gate structure is flush with the top surface of the second gate structure, and the height difference between the top surface of the first active region and the top surface of the second active region is related to the voltage amplitude. The corner between the first limiting groove and the first active area is rounded.

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