Semiconductor device including gate interconnect lines

Abstract

A semiconductor device including a gate interconnect line is disclosed. A semiconductor device is presented including a SiC semiconductor body. The SiC semiconductor body includes an array of transistor cells at a first side of the SiC semiconductor body. The semiconductor device further includes a gate interconnect line. At least a portion of the gate interconnect line is arranged between an edge of the SiC semiconductor body and the array of transistor cells. The semiconductor device further includes an intermediate dielectric arranged between the gate interconnect line and the SiC semiconductor body. The semiconductor device further includes a p-doped well region. The semiconductor device further includes an n-doped interconnect region arranged between the gate interconnect line and the p-doped well region. The n-doped interconnect region and the p-doped well region are electrically connected together by a first contact arranged at the first side between the gate interconnect line and the edge of the SiC semiconductor body. The n-doped interconnect region and the p-doped well region are also electrically connected together by a second contact at the first side. The gate interconnect line is arranged between the first contact and the second contact.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices and methods for manufacturing such devices, with a particular focus on silicon carbide (SiC) semiconductor technology. Specifically, this disclosure relates to the arrangement and interconnection of transistor cell arrays, gate interconnects, and doped regions within a SiC semiconductor body to optimize electrical performance and integration. Background Technology

[0002] The development of next-generation semiconductor devices (such as insulated-gate field-effect transistors (IGFETs), insulated-gate bipolar transistors (IGBTs), or junction field-effect transistors (JFETs) such as metal-oxide-semiconductor field-effect transistors (MOSFETs)) aims to increase device functionality per chip area while meeting specified quality and reliability requirements.

[0003] In the field of semiconductor devices, particularly those utilizing silicon carbide (SiC) technology, transistor cell arrays are commonly used in a variety of applications, including power electronics. Such devices typically involve integrating multiple doped regions within the SiC semiconductor body to facilitate electrical connections and enhance device performance. Gate interconnects and dielectric layers are often combined to manage electrical signals and isolate different regions within the semiconductor device, such as in the edge-terminating regions surrounding the transistor cell regions. The arrangement and properties of these components are crucial for achieving desired electrical characteristics, such as avalanche robustness.

[0004] Despite substantial advancements in SiC semiconductor technology, challenges remain in optimizing electrical connectivity and minimizing resistance between doped regions without unduly increasing the required chip area. Additionally, the geometry of contacts and interconnects can impact the overall device performance and reliability. The need to balance the thickness and width of various components, such as contacts and dielectric layers, further complicates the design process.

[0005] Therefore, providing semiconductor devices that at least partially meet the above challenges is a technical problem. Summary of the Invention

[0006] Examples of this disclosure relate to a semiconductor device. The semiconductor device includes a SiC semiconductor body. The SiC semiconductor body includes an array of transistor cells on a first side of the SiC semiconductor body. The semiconductor device also includes a gate interconnect. At least a portion of the gate interconnect is disposed between an edge of the SiC semiconductor body and the transistor cell array. The semiconductor device also includes an intermediate dielectric disposed between the gate interconnect and the SiC semiconductor body. The semiconductor device also includes a p-doped well region. The semiconductor device also includes an n-doped interconnect region disposed between the gate interconnect and the p-doped well region. The n-doped interconnect region and the p-doped well region are electrically connected together by a first contact disposed on the first side between the gate interconnect and the edge of the SiC semiconductor body. The n-doped interconnect region and the p-doped well region are also electrically connected together by a second contact on the first side. The gate interconnect is disposed between the first contact and the second contact.

[0007] Another example of this disclosure relates to another method of manufacturing a semiconductor device. The method includes forming a transistor cell array on a first side of a SiC semiconductor body. The method also includes forming an intermediate dielectric on the SiC semiconductor body. The method further includes forming a gate interconnect on the intermediate dielectric. At least a portion of the gate interconnect is formed between an edge of the SiC semiconductor body and the transistor cell array. The method also includes forming a p-doped well region. The method further includes forming an n-doped interconnect region disposed between the gate interconnect and the p-doped well region. The n-doped interconnect region and the p-doped well region are electrically connected together by a first contact disposed on the first side between the gate interconnect and the edge of the SiC semiconductor body. The n-doped interconnect region and the p-doped well region are also electrically connected together by a second contact on the first side. The gate interconnect is disposed between the first contact and the second contact.

[0008] Those skilled in the art will recognize the additional features and advantages upon reading the following detailed description and reviewing the accompanying drawings. Attached Figure Description

[0009] The accompanying drawings are included to provide a further understanding of the embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of semiconductor devices and, together with the description, serve to explain the principles of the embodiments. Further embodiments are described in the following detailed description and claims.

[0010] Figure 1 A cross-sectional view of a semiconductor device is schematically and exemplaryly illustrated, the semiconductor device including a portion of gate interconnects disposed between the edge of a SiC semiconductor body and an array of transistor cells.

[0011] Figure 2 yes Figure 1An exemplary and more detailed illustration of a cross-sectional view.

[0012] Figure 3A This is a top view of a corner portion of a transistor cell array and the surrounding gate interconnects, illustrating an example configuration of a semiconductor device.

[0013] Figure 3B It is along Figure 3A An exemplary illustration of a cross-sectional view of line B-B'.

[0014] Figure 3C It is along Figure 3A An exemplary illustration of a cross-sectional view of line C-C'.

[0015] Figure 3D It is in the area of ​​online B-B' and A-A'. Figure 3A A more detailed illustration of the top view. Detailed Implementation

[0016] In the following detailed description, reference is made to the accompanying drawings, which form part of this document and illustrate, by way of illustration, specific examples in which a semiconductor substrate can be processed. It is to be understood that other examples may be utilized and structural or logical changes may be made without departing from the scope of this disclosure. For example, a feature illustrated or described for one example may be used on or in combination with other examples to produce yet another further example. This disclosure is intended to include such modifications and variations. Examples are described using specific language and should not be construed as limiting the scope of the appended claims. The drawings are not to scale and are for illustrative purposes only. Unless otherwise stated, corresponding elements are designated by the same reference numerals in different drawings.

[0017] The terms “having,” “comprising,” “including,” and “including” are open-ended and indicate the presence of the stated structure, element, or feature but do not exclude the presence of additional elements or features. The quantifiers “a,” “one,” and the pronoun “the” are intended to include both plural and singular forms unless the context clearly indicates otherwise.

[0018] The term "electrical connection" can describe a permanent, low-resistance connection between electrically connected components, such as a direct contact between related components or a low-resistance connection via a metal and / or heavily doped semiconductor material. The term "electrical coupling" can include one or more intermediate elements adapted for signal and / or power transmission that can be connected between electrically coupled components, such as elements controllable to temporarily provide a low-resistance connection in a first state and a high-resistance electrical decoupling in a second state.

[0019] If two elements A and B are combined using "or", this should be understood to disclose all possible combinations, namely, only A, only B, and A and B, unless otherwise explicitly or implicitly specified. Alternative terms for the same combinations are "at least one of A and B" or "A and / or B".

[0020] The range given for physical dimensions includes boundary values. For example, the range for parameter y from a to b is read as a≤y≤b. This also applies to ranges with a boundary value (such as "at most" and "at least").

[0021] The main components of layers or structures derived from chemically synthesized compounds or alloys are elements whose atoms form the chemically synthesized compounds or alloys. For example, silicon (Si) and carbon (C) are the main components of silicon carbide (SiC) layers.

[0022] The term “on” is not to be interpreted as simply “directly on”. Rather, if an element is “on” another element (e.g., a layer is “on” another layer or “on” a substrate), then a further component (e.g., a further layer) may be located between the two elements (e.g., if a layer is “on” a substrate, then a further layer may be located between that layer and the substrate).

[0023] An example configuration of a semiconductor device includes an array of transistor cells on a first side of a SiC semiconductor body. The semiconductor device also includes a gate interconnect. At least a portion of the gate interconnect is disposed between an edge of the SiC semiconductor body and the transistor cell array. The semiconductor device also includes an intermediate dielectric disposed between the gate interconnect and the SiC semiconductor body. The semiconductor device further includes a p-doped well region. The semiconductor device also includes an n-doped interconnect region disposed between the gate interconnect and the p-doped well region. The n-doped interconnect region and the p-doped well region are electrically connected together by a first contact disposed on the first side between the gate interconnect and the edge of the SiC semiconductor body. The n-doped interconnect region and the p-doped well region are also electrically connected together by a second contact on the first side. The gate interconnect is disposed between the first contact and the second contact.

[0024] For example, a semiconductor device may be part of an integrated circuit or may be a discrete semiconductor device or semiconductor module. For example, a semiconductor device may be or may include an insulated-gate field-effect transistor (IGFET), an insulated-gate bipolar transistor (IGBT), or a junction field-effect transistor (JFET), such as a metal-oxide-semiconductor field-effect transistor (MOSFET). The semiconductor device may be a vertical semiconductor device having a load current flowing between a first side and a second side opposite to the first surface. Vertical power semiconductor devices may be configured to conduct currents greater than 1A, or greater than 10A, or greater than 30A, or greater than 50A, or greater than 75A, or even greater than 100A, and may also be configured to block voltages between load electrodes, such as the voltage between the collector and emitter of an IGBT, or the voltage between the drain and source of a MOSFET or JFET, in the range of hundreds to thousands of volts, such as 300V, 400V, 650V, 1.2kV, 1.7kV, 3.3kV, 4.5kV, 5.5kV, 6kV, 6.5kV, and 10kV. The blocking voltage can correspond to, for example, the voltage level specified in the datasheet of a power semiconductor device.

[0025] Semiconductor devices can be based on SiC semiconductor substrates derived from crystalline SiC materials. By way of example, crystalline SiC materials can have a hexagonal crystal lattice. For example, the semiconductor material can be 2H-SiC (2H polytype SiC), 6H-SiC, or 15R-SiC. By way of example, the semiconductor material is 4H polytype silicon carbide (4H-SiC). The SiC semiconductor body can include or be constituted by a SiC semiconductor substrate having one or more semiconductor layers, such as layers epitaxially grown thereon. For example, the semiconductor layers (multiple layers) can be formed as part of a multi-epitaxial method for forming a superjunction structure (SJ structure), and / or for forming a current diffusion layer, and / or for forming device layers for including doped regions such as source regions and body regions. During the multi-epitaxial method for forming the SJ structure, masked p-implantation and / or n-implantation can be used between successive epitaxial growths.

[0026] For example, the first side can be the front or top side of the SiC semiconductor body, and the SiC semiconductor body can also have a second side, which can be the back or rear side of the SiC semiconductor body. For example, the SiC semiconductor body can be attached to the lead frame via the second side. For example, bonding pads can be arranged on the first side of the SiC semiconductor body, and bonding wiring can be bonded to the bonding pads.

[0027] To achieve the desired current carrying capacity, the semiconductor device can be designed using multiple semiconductor device cells connected in parallel. These parallel-connected semiconductor device cells can be, for example, formed in the shape of strips or strip segments. Of course, semiconductor device cells can also have any other shape, such as circular, elliptical, or polygonal shapes like hexagons or octagons. The semiconductor device cells can be arranged in a transistor cell array within a SiC semiconductor body. The transistor cell array can be a region in which the emitter region of the IGBT (or the source region of the MOSFET or JFET) and the collector region of the IGBT (or the drain region of the MOSFET or JFET) are arranged opposite each other along a vertical direction. In the transistor cell array, load current can enter or leave the SiC semiconductor body of the semiconductor device, for example via contact plugs on a first side of the SiC semiconductor body. The semiconductor device may also include an edge-terminating region, which may include a termination structure. In the blocking mode or reverse-biased mode of the semiconductor device, the blocking voltage between the transistor cell array and the field-free region decreases laterally across the termination structure. Compared to the transistor cell array, the termination structure can have a higher or slightly lower voltage blocking capability. For example, the termination structure may include a junction termination extension (JTE) with or without lateral doping variation (VLD), one or more laterally separated guard rings, or any combination thereof.

[0028] Gate interconnects can be disposed outside the active transistor cell array, such as in the edge region of the chip. Gate interconnects (also referred to as gate channels) can partially or completely surround the transistor cell array. For example, gate interconnects can be formed near one, two (e.g., opposite), three, or four edges of the SiC semiconductor body or die. Gate interconnects can include one or more conductive materials, such as metals, metal alloys, such as Cu, Au, AlCu, AlSiCu, Ti, W, TiW, Mo, Au, NiP, Ta, Ag, or alloys thereof, and metal composites, such as TiN. For example, one or more conductive materials can form a layer stack. For example, gate interconnects can electrically connect gate electrodes in the transistor cell array to gate pads. For example, gate interconnects can be fused to or form gate pads on a first side of the SiC semiconductor body.

[0029] For example, an intermediate dielectric can be disposed on a first side between the gate interconnect and the surface of the SiC semiconductor body. For example, the top side of the intermediate dielectric can be directly adjacent to the bottom side of the gate interconnect. The bottom side of the intermediate dielectric can be directly adjacent to the surface of the SiC semiconductor body on the first side. The intermediate dielectric can include one or more dielectric materials, such as oxides of SiO2, nitrides of Si3N4, and aluminosilicates such as Al2O3, ZrO2, HfO2, AlN, and AlSiO4. x The high-k dielectric can be silicon-doped HfO2, lanthanum-doped HfO2, TiO2, Y2O3 or Si3N4, ONO (oxide-nitride-oxide), or any stacked combination thereof. For example, the oxide can be a thermally applied oxide and / or a deposited and annealed oxide. The intermediate dielectric can extend laterally into the edge-termination region and / or be partially disposed on the surface of the SiC semiconductor body at the first side of the transistor cell array.

[0030] The first contact may include one or more conductive materials, such as metals, metal alloys, metal composites, metal silicides, or any combination thereof. For example, one or more conductive materials may form a layer stack. For example, the first contact may include a silicide layer or a stack of silicide layers, such as a silicide of Ni, or a silicide of NiAl, or a silicide of Ti, or any combination thereof. Optional blocking portions of a diffusion barrier layer or barrier layer stack may be formed on the silicide layer or silicide layer stack, such as a barrier layer including Ti, TiN, Ti / TiN, Mo, or any combination thereof. Optional pads may be formed on the silicide layer or silicide layer stack, or on the barrier layer or barrier layer stack. For example, a pad layer or pad layer stack may include W, Mo, or any combination thereof. The first contact can provide an ohmic connection between a p-doped well region and an n-doped interconnect region.

[0031] The second contact may include the material or combination of materials as described above with respect to the gate interconnect and / or the first contact. For example, the layer composition of the second contact may correspond to the layer composition of the first contact, and further, to the layer composition of the gate interconnect on top of the layer composition of the first contact.

[0032] For example, p-doped well regions can be formed by one, two, three, four or even more overlapping distributions of electrically activated dopants, introduced, for example, through multiple ion implantations at different ion implantation energies.

[0033] The examples described herein can allow for chip area savings, particularly in the passive region between the transistor cell array and the SiC semiconductor substrate or the edge of the chip / die. Chip area savings can be achieved by omitting densely packed source or emitter interconnects, which provide low-ohmic connections from the termination structure to the source or emitter electrodes. These low-ohmic connections are provided via n-doped interconnect regions that ensure a lower resistance path compared to p-doped well regions, and are supported by first and second contacts on the first side of the SiC semiconductor body.

[0034] For example, the sheet resistance of an n-doped interconnect region can be 20% less or even less than that of a p-doped well region. This feature results in a significant improvement in the electrical performance of the semiconductor device by ensuring a lower resistance path within the n-doped interconnect region compared to the p-doped well region (including, for example, the p-doped regions of the termination structure) used to electrically connect, for example, the source contact, to the end portion of the adjacent termination structure of the p-doped well region. Thus, a low-ohmic connection from the termination structure in the edge termination region to the source or emitter electrode (e.g., the second contact) can be achieved without the chip area consumption required when placing the source or emitter interconnect between the edge of the semiconductor body and the transistor cell array.

[0035] For example, the sheet resistance of an n-doped interconnect region can range from 300 ohms / square to 900 ohms / square. By providing an n-doped interconnect region, the sheet resistance for interconnecting the termination structures in the edge termination region to the source or emitter contact can be significantly lower than the minimum sheet resistance achievable by the upper limit of the p-doped well region, taking into account a reasonable depth for the p-type doping concentration and the doping constraints of the substrate material SiC.

[0036] For example, the thickness of the first contact along the vertical direction can be less than the thickness of the gate interconnect. For example, the thickness of the first contact can be in the range of 0.4% to 20% or 0.4% to 3% of the thickness of the gate interconnect.

[0037] For example, the width of the first contact can be in the range of 4% to 30% or 5% to 10% of the width of the gate interconnect. Exemplary values ​​for the width of the first contact can be in the range of 0.4 μm to 3 μm or 0.5 μm to 2 μm. For example, the minimum lateral dimension (e.g., width) can be limited by the minimum contact hole width in the intermediate dielectric.

[0038] For example, the thickness of the first contact can be less than the thickness of the intermediate dielectric. For instance, the thickness of the first contact can be in the range of 10% to 30% of the thickness of the intermediate dielectric. By placing the first contact within a contact opening in the intermediate dielectric, chip area consumption imposed by design rules constraining the minimum width and distance of source interconnects or source channels formed in the metal layers of the wiring hierarchy in the wiring region can be avoided. This allows for a reduction in chip area consumption.

[0039] For example, a p-doped well region can be a p-doped edge-termination region in an edge-termination structure. A p-doped edge-termination region can have a higher sheet resistance than a p-doped well region. For example, a p-doped edge-termination region can be part of a JTE or VLD termination structure.

[0040] For example, the vertical extent of a p-doped edge-termination region can be larger than that of an n-doped interconnect region. Similarly, the vertical extent of a p-doped well region can be larger than that of a p-doped edge-termination region. This allows for better management of the electric field distribution and enhances device performance and reliability.

[0041] For example, the maximum doping concentration in a p-doped well region can be from 10 18 cm -3 Up to 10 19 cm -3 Within a certain range. For example, the vertical range of the p-doped well region can be from 0.5 μm to 1.0 μm or even larger.

[0042] For example, the source region and n-doped interconnect region in a transistor cell array can have a matched vertical concentration distribution of n-type dopant. This simplifies the fabrication of semiconductor devices by simultaneously forming the source region and the n-doped interconnect region. For example, the source region and the n-doped interconnect region can be formed simultaneously using a single lithographic mask process and subsequent ion implantation.

[0043] For example, the transistor cell array may include a plurality of strip-shaped transistor cells extending parallel to a first lateral direction. The n-doped interconnect region may include a first sub-region extending parallel to a first edge of the SiC semiconductor body along the first lateral direction. The n-doped interconnect region may also include a second sub-region extending parallel to a second edge of the SiC semiconductor body along a second lateral direction. This can contribute to the low-ohmic connection between the termination structure in the edge termination region and the source or emitter electrode by connecting the termination structure in the edge termination region via different edges of the SiC semiconductor body.

[0044] For example, the width of the first sub-region along the second lateral direction can be less than three times the width of the gate interconnect above the first sub-region.

[0045] For example, the width of the second sub-region may alternate between a first width and a second width along a second lateral direction. The second width may be smaller than the first width. For example, the alternating widths of the second sub-region may be formed by grooves in the second sub-region, such as at opposite edges of the second sub-region facing one edge of the transistor cell array.

[0046] For example, the second width is in the range of 10% to 30% of the first width. For example, the contact may be arranged in a contact opening in an intermediate dielectric above a recess formed in the second sub-region. For example, the contact may electrically connect the gate electrode and the gate interconnect in a transistor cell array.

[0047] For example, the trench gate structure segment can be laterally defined by adjacent segments of the second sub-region having a first width along a second lateral direction. The trench gate structure segment can be arranged between the transistor cell array and the edge-termination array.

[0048] For example, a trench gate structure segment may be adjacent to a segment of the second sub-region having a second width along a first lateral direction. For example, a dielectric (e.g., a gate dielectric) in a trench gate structure segment may be directly adjacent to a lateral end of the second sub-region having a second width.

[0049] For example, the gate electrode of the trench gate structure segment can be electrically connected to the gate interconnect above the trench gate structure segment via a contact opening in the intermediate dielectric.

[0050] The details regarding the structural or functional or technical benefits of the features described above in relation to semiconductor devices (such as FETs, JFETs, or IGBTs) also apply to the exemplary methods described herein. Processing a SiC semiconductor body may include one or more optional additional features corresponding to one or more aspects mentioned in conjunction with the proposed concept or one or more examples described above or below.

[0051] The description and accompanying drawings are merely illustrative of the principles of this disclosure. Furthermore, all examples recorded herein are intended primarily for illustrative purposes only to aid the reader in understanding the principles of this disclosure and the concepts contributed by the inventors(s) to advance the art. All statements herein recounting the principles, aspects, and examples of this disclosure, as well as specific examples thereof, are intended to cover their equivalents.

[0052] It should be understood that the disclosure of multiple actions, processes, operations, steps, or functions in the specification or claims is not to be construed as being in a particular order, unless otherwise expressly or implicitly stated, for example by a word such as "after," for technical reasons. Therefore, the disclosure of multiple actions or functions will not limit them to a particular order unless such actions or functions are not interchangeable for technical reasons. Furthermore, in some examples, a single action, function, process, operation, or step may accordingly include or be decomposed into multiple sub-actions, sub-functions, sub-processes, sub-operations, or sub-steps. Unless expressly excluded, such sub-actions may be included in and are part of the disclosure of that single action.

[0053] Another example of this disclosure relates to a method of manufacturing a semiconductor device. The method includes forming a transistor cell array on a first side of a SiC semiconductor body. The method also includes forming an intermediate dielectric on the SiC semiconductor body. The method further includes forming a gate interconnect on the intermediate dielectric. At least a portion of the gate interconnect is formed between an edge of the SiC semiconductor body and the transistor cell array. The method also includes forming a p-doped well region. The method further includes forming an n-doped interconnect region disposed between the gate interconnect and the p-doped well region. The n-doped interconnect region and the p-doped well region are electrically connected together by a first contact disposed on the first side between the gate interconnect and the edge of the SiC semiconductor body. The n-doped interconnect region and the p-doped well region are also electrically connected together by a second contact on the first side. The gate interconnect is disposed between the first contact and the second contact.

[0054] For example, the method may also include simultaneously forming n-doped source regions in the transistor cell array and the n-doped interconnect region by introducing an n-type dopant into the SiC semiconductor body. Simultaneously forming n-doped source regions in the transistor cell array and the n-doped interconnect region may include introducing an n-type dopant through laterally spaced mask openings via one or more ion implantation processes.

[0055] The examples and features described above and below can be combined.

[0056] Further details and aspects are mentioned in conjunction with the examples described above or below. A SiC semiconductor wafer or body that processes a semiconductor device may include one or more optional additional features corresponding to one or more aspects mentioned in conjunction with the proposed concept or one or more examples described above or below.

[0057] The description and accompanying drawings are merely illustrative of the principles of this disclosure. Furthermore, all examples recorded herein are intended primarily for illustrative purposes only to aid the reader in understanding the principles of this disclosure and the concepts contributed by the inventors(s) to advance the art. All statements herein recounting the principles, aspects, and examples of this disclosure, as well as specific examples thereof, are intended to cover their equivalents.

[0058] Further examples of semiconductor devices are explained below with reference to the accompanying drawings. The functional and structural details described with respect to the examples above will also apply to the exemplary embodiments illustrated in the figures and further described below.

[0059] The details regarding the structural, functional, or technical benefits of the features described above also apply to the examples below and vice versa.

[0060] Figure 1 An example configuration of a semiconductor device 100 including a SiC semiconductor body 102 is illustrated. The SiC semiconductor body 102 includes a transistor cell array 104 (not shown in detail) located at a first side 1021 of the SiC semiconductor body 102. A gate interconnect 108 is arranged such that at least a portion of it lies between an edge 110 of the SiC semiconductor body 102 and the transistor cell array 104. An intermediate dielectric 112 is located between the gate interconnect 108 and the SiC semiconductor body 102, providing electrical insulation.

[0061] The semiconductor device 100 also includes a p-doped well region 116 and an n-doped interconnect region 118. The n-doped interconnect region 118 is located between the gate interconnect 108 and the p-doped well region 116, for example, embedded in the p-doped well region 116. The electrical connection between the n-doped interconnect region 118 and the p-doped well region 116 is established by a first contact C1 located at a first side 1021 between the gate interconnect 108 and the edge 110 of the SiC semiconductor body 102. Additionally, a second contact C2 at the first side 1021 further connects the n-doped interconnect region 118 and the p-doped well region 116. The gate interconnect 108 is located between the first contact C1 and the second contact C2. The second contact C2 may be part of a first load electrode of a transistor cell region, such as a source or emitter electrode, as part of a wiring region at the first side 1021 of the SiC semiconductor body 102.

[0062] Figure 2 A cross-sectional view of another configuration example of the semiconductor device 100 is illustrated. Figure 1 Compared to the diagram Figure 2 The exemplary illustrations provide some further exemplary details.

[0063] An n-doped interconnect region 118 is located between the gate interconnect 108 and the p-doped well region 116. One end of the n-doped interconnect region 118 and the p-doped well region 116 are electrically connected by a first contact C1 located at a first side 1021 in the contact opening of the intermediate dielectric 112. The other end of the n-doped interconnect region 118 and the p-doped well region 116 are electrically connected by a second contact C2 located at the first side 1021. The second contact C2 fills the contact opening of the intermediate dielectric 112 and merges into the load electrode (e.g., source or emitter electrode) of the transistor cell array 104. For example, the layer composition of the second contact C2 as a bottom portion can correspond to the layer composition of the first contact, and the top portion of the bottom portion can correspond to the layer composition of the gate interconnect 108. In other words, the bottom portion of the second contact C2 and the first contact C1 can be formed simultaneously, and the top portion of the second contact C2 and the gate interconnect 108 can be formed simultaneously.

[0064] The thickness t1 of the first contact C1 along the vertical direction y is less than the thickness t2 of the gate interconnect 108. The thickness t1 of the first contact C1 is also less than the thickness t3 of the intermediate dielectric 112.

[0065] The width w1 of the first sub-region 1181 along the second lateral direction x2 is less than three times the width w2 of the gate interconnect 108 above the first sub-region 1181.

[0066] The p-doped well region 116 transitions into the p-doped edge-termination region 1141 of the edge-termination structure 114. The p-doped edge-termination region 1141 may have a higher sheet resistance than the p-doped well region 116. The vertical range v1 of the p-doped edge-termination region 1141 is greater than the vertical range v2 of the n-doped interconnect region 118, and the vertical range v3 of the p-doped well region 116 is greater than the vertical range v1 of the p-doped edge-termination region 1141. In some further examples, the vertical range v3 of the p-doped well region 116 may be equal to the vertical range v1 of the p-doped edge-termination region 1141.

[0067] The transistor cell array 104 includes a trench gate structure 119, which includes a gate electrode 1201 that is partially electrically isolated from the surrounding SiC semiconductor body 102 by a gate dielectric 1202. Channel current flows from the n-doped source region 124 into a channel region adjacent to the sidewall of the trench gate structure 119 in the p-doped body region 126, and the conductivity of the channel region is controlled by a field effect via a voltage applied to the gate electrode 1201.

[0068] Figure 3AA schematic top view illustrates an example configuration of a semiconductor device 100 having a transistor cell array 104, which includes a plurality of strip-shaped transistor cells TC extending parallel along a first lateral direction x1. A gate interconnect 108 includes a first portion 1081 extending parallel to a first edge 1101 of a SiC semiconductor body 102 along the first lateral direction x1. The first portion 1081 becomes a second portion 1082 of the gate interconnect 108 extending parallel to a second edge 1102 of the SiC semiconductor body 102 via a corner interconnect portion 1083 of the gate interconnect 108.

[0069] Figure 2 The diagram shows along Figure 3A An exemplary cross-sectional view of line A-A'.

[0070] Figure 3B The diagram illustrates along Figure 3A The cross-sectional view of line B-B' provides a detailed depiction of the structural configuration, highlighting the integration of the gate interconnects, intermediate dielectric, and doped regions.

[0071] The SiC semiconductor body 102 serves as a base substrate on which devices are constructed. The first side 1021 of the semiconductor body is where the transistor cell array is located, although in... Figure 3B Specific cells are not depicted. Gate interconnect 108 is shown above intermediate dielectric 112. Intermediate dielectric 112 acts as an insulating layer, separating gate interconnect 108 from the underlying SiC semiconductor body 102.

[0072] Figure 3B Also shown is an n-doped interconnect region 118, labeled 1182 in this view, located between the intermediate dielectric 112 and the p-doped well region 116, having a width w12. The n-doped interconnect region 1182 is electrically connected to the p-doped well region 116 via a first contact C1 located at the first side 1021. Figure 3B The diagram illustrates a trench gate structure segment 120, in which the gate electrode 1201 extends vertically through an intermediate dielectric 112. Contact openings 122 in the intermediate dielectric 112 allow the gate electrode 1201 to be electrically connected to the gate interconnect 108, ensuring proper functioning of the trench gate structure segment 120. The intermediate dielectric 112 acts as an insulating layer, separating the second contact C2 from the underlying gate electrode 1201.

[0073] Figure 3C The diagram illustrates along Figure 3A The cross-sectional view along line C-C' provides a detailed depiction of the structural configuration, highlighting the integration of the gate interconnects, intermediate dielectric, and doped regions.

[0074] Figure 3C Also shown is an n-doped interconnect region 118, labeled 1182 in this view, located between the intermediate dielectric 112 and the p-doped well region 116, with a width w11. Similar to... Figure 3B The n-doped interconnect region 1182 is electrically connected to the p-doped well region 116 via a first contact C1 located on the first side 1021. Figure 3C The middle part is omitted Figure 3B The trench gate structure segment 120 extends along the first lateral direction x1 and terminates below the second contact C2. The n-doped interconnect region 1182 is electrically connected to the p-doped well region 116 via the second contact C2 in the contact opening of the intermediate dielectric 112.

[0075] Figure 3D yes Figure 3A A more detailed illustration of the top view in the areas B-B' and A-A'.

[0076] The width of the second sub-region 1182 of the n-doped interconnect region 118 alternates between a first width w11 and a second width w12 along a second lateral direction x2. The second width w12 is smaller than the first width w11. This alternating width configuration is crucial for the layout and electrical characteristics of the semiconductor device by ensuring that: i) the gate electrode 1201 in the trench gate structure segment 120 is electrically connected to the gate interconnect 108, as shown in Figure 3B As shown in the diagram; ii) the n-doped interconnect region 118 is electrically connected to the p-doped well region 116 via the second contact C2, as in Figure 3C As shown in the diagram.

[0077] While specific examples have been illustrated and described herein, those skilled in the art will appreciate that various alternatives and / or equivalent implementations may be made in place of the specific examples shown and described without departing from the scope of the invention. This application is intended to cover any adaptations or variations of the specific examples discussed herein. Therefore, the invention is intended to be limited only by the claims and their equivalents.

[0078] It should be noted that the methods and devices, including their preferred embodiments, as outlined in this document can be used alone or in combination with other methods and devices disclosed in this document. Furthermore, features outlined in the context of a device are also applicable to the corresponding method, and vice versa. Moreover, all aspects of the methods and devices outlined in this document can be combined arbitrarily. In particular, the features of the claims can be combined with each other in any manner.

[0079] It should be noted that the description and accompanying drawings are merely illustrative of the principles of the proposed methods and systems. Those skilled in the art will be able to implement various arrangements, which, while not explicitly described or shown herein, embody the principles of the invention and are included within its spirit and scope. Furthermore, all examples and embodiments outlined in this document are primarily intended for illustrative purposes only to aid the reader in understanding the principles of the proposed methods and systems. Moreover, all statements herein providing the principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to cover their equivalents.

Claims

1. A semiconductor device (100), comprising: SiC semiconductor body (102), which includes a transistor cell array (104) on a first side (1021) of the SiC semiconductor body (102). Gate interconnect (108), wherein at least a portion of the gate interconnect (108) is disposed between the edge (110) of the SiC semiconductor body (102) and the transistor cell array (104); An intermediate dielectric (112) is disposed between the gate interconnect (108) and the SiC semiconductor body (102); p-doped well region (116); and An n-doped interconnect region (118) is disposed between a gate interconnect (108) and a p-doped well region (116), wherein the n-doped interconnect region (118) and the p-doped well region (116) are electrically connected together by a first contact (C1) disposed on a first side (1021) between the gate interconnect (108) and the edge (110) of the SiC semiconductor body (102), and the n-doped interconnect region (118) and the p-doped well region (116) are also electrically connected together by a second contact (C2) disposed on the first side (1021), and the gate interconnect (108) is disposed between the first contact (C1) and the second contact (C2).

2. The semiconductor device (100) according to the preceding claim, wherein the sheet resistance of the n-doped interconnect region (118) is 20% less or less than the sheet resistance of the p-doped well region (116).

3. The semiconductor device (100) according to any one of the preceding claims, wherein the sheet resistance of the n-doped interconnect region (118) is in the range of 300 ohms / square to 900 ohms / square.

4. The semiconductor device (100) according to any of the preceding claims, wherein the thickness (t1) of the first contact (C1) along the vertical direction (y) is less than the thickness (t2) of the gate interconnect (108).

5. The semiconductor device (100) according to any one of the preceding claims, wherein the width of the first contact is in the range of 4% to 30% of the width of the gate interconnect (108).

6. The semiconductor device (100) according to any one of the preceding claims, wherein the thickness (t1) of the first contact (C1) is less than the thickness (t3) of the intermediate dielectric (112).

7. The semiconductor device (100) according to any one of the preceding claims, wherein the p-doped well region (116) becomes the p-doped edge termination region (1141) of the edge termination structure (114), the p-doped edge termination region (1141) having a higher sheet resistance than the p-doped well region (116).

8. The semiconductor device (100) according to the preceding claim, wherein the vertical extent (v1) of the p-doped edge termination region (1141) is greater than the vertical extent (v2) of the n-doped interconnect region (118), and the vertical extent (v3) of the p-doped well region (116) is greater than the vertical extent (v1) of the p-doped edge termination region (1141).

9. The semiconductor device (100) according to any one of the preceding two claims, wherein the maximum doping concentration in the p-doped well region (116) is from 10 18 cm -3 Up to 10 19 cm -3 The vertical range (v3) of the p-doped well region (116) is from 0.5 μm to 1.0 μm.

10. The semiconductor device (100) according to any one of the preceding claims, wherein the source region and the n-doped interconnect region (118) in the transistor cell array (104) have a matching vertical concentration distribution of n-type dopant.

11. The semiconductor device (100) according to any one of the preceding claims, wherein the transistor cell array (104) includes a plurality of strip-shaped transistor cells (TC) extending parallel along a first lateral direction (x1), wherein the n-doped interconnect region (118) includes a first sub-region (1181) extending parallel to a first edge (1101) of the SiC semiconductor body (102) along the first lateral direction (x1), and the n-doped interconnect region (118) further includes a second sub-region (1182) extending parallel to a second edge (1102) of the SiC semiconductor body (102) along a second lateral direction (x2).

12. The semiconductor device (100) according to the preceding claim, wherein the width (w1) of the first sub-region (1181) along the second lateral direction (x2) is less than three times the width (w2) of the gate interconnect (108) above the first sub-region (1181).

13. The semiconductor device (100) according to any one of the preceding two claims, wherein the width of the second sub-region (1182) alternates between a first width (w11) and a second width (w12) along a second lateral direction (x2), the second width (w12) being smaller than the first width (w11).

14. The semiconductor device (100) according to the preceding claim, wherein the second width (w12) is in the range of 10% to 30% of the first width (w11).

15. The semiconductor device (100) according to any one of the preceding four claims, wherein the trench gate structure segment (120) is laterally defined along a second lateral direction (x2) by an adjacent segment of the second sub-region (1182) having a first width (w11).

16. The semiconductor device (100) according to the preceding claim, wherein the trench gate structure segment (120) is adjacent to a segment of the second sub-region (1182) having a second width (w12) along a first lateral direction (x1).

17. The semiconductor device (100) according to the preceding claim, wherein the gate electrode (1201) of the trench gate structure segment (120) is electrically connected to the gate interconnect (108) above the trench gate structure segment via a contact opening (122) in the intermediate dielectric (112).

18. A method for manufacturing a semiconductor device (100), the method comprising: A transistor cell array (104) is formed on the first side (1021) of the SiC semiconductor body (102). An intermediate dielectric (112) is formed on the SiC semiconductor body (102). A gate interconnect (108) is formed on an intermediate dielectric (112), wherein at least a portion of the gate interconnect (108) is formed between the edge (110) of the SiC semiconductor body (102) and the transistor cell array (104); Forming a p-doped well region (116); and An n-doped interconnect region (118) is formed between a gate interconnect (108) and a p-doped well region (116), wherein the n-doped interconnect region (118) and the p-doped well region (116) are electrically connected together by a first contact (C1) at a first side (1021) between the gate interconnect (108) and the edge (110) of the SiC semiconductor body (102), and the n-doped interconnect (118) and the p-doped well region (116) are also electrically connected together by a second contact (C2) at the first side (1021), and the gate interconnect (108) is arranged between the first contact (C1) and the second contact (C2).

19. The method according to the preceding claim, comprising: By introducing an n-type dopant into the SiC semiconductor body (102), the n-doped source region and the n-doped interconnect region (118) in the transistor cell array (104) are formed simultaneously.

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