Semiconductor device and method of manufacturing the same

Abstract

The application provides a semiconductor device and a manufacturing method thereof, the method comprising: providing a substrate, the substrate comprising a core region and an input / output region, a plurality of gate structures being formed on the substrate in the core region and the input / output region; forming a hard mask layer, the mask layer covering sidewalls and top of the gate structures and a surface of the substrate; thinning the hard mask layer in the core region; etching the substrate to form a recess with the hard mask layer as a barrier layer; and forming an epitaxial layer in the recess. The application can increase the effective distance between the gate structure of the input / output region and the epitaxial layer formed in the recess, thereby increasing the breakdown voltage of the device of the input / output region; meanwhile, the micro loading effect in the recess etching and epitaxial growth process caused by the difference in pattern density between the two regions can be reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit technology, and in particular to a semiconductor device and its fabrication method. Background Technology

[0002] Due to the demand for high drive speeds, some input / output (I / O) circuits utilize silicon-germanium (SiGe) technology. Compared to I / O devices without SiGe, those with SiGe are more prone to gate-to-SiGe breakdown, failing to meet reliability requirements at high operating voltages. Therefore, increasing the effective distance between the gate and SiGe is necessary to improve the breakdown voltage of SiGe-based I / O devices. Furthermore, due to the differences in size and density between the core region and the I / O region, micro-loading occurs during the epitaxial growth of SiGe.

[0003] Furthermore, for chips with certain custom functionalities, the turn-on speed requirement for the input / output region is sometimes lower than that of the core region. This means the threshold voltage of devices in the input / output region is higher than that in the core region. Therefore, in actual fabrication, the requirements for various ions involved in threshold voltage regulation differ. For example, the BF2 (boron difluoride) ion concentration in the input / output region must be lower than that in the core region. However, the BF2 concentration affects the etching rate of the sigma grooves during silicon-germanium formation. Higher BF2 concentrations result in a slower etching rate. This leads to a higher etching rate in the input / output region compared to the core region when both regions are simultaneously etched. Consequently, the groove volume in the input / output region is larger than that in the core region. However, the higher threshold voltage in the input / output region results in a smaller distance between the larger sigma groove and the gate, making it more susceptible to breakdown. Summary of the Invention

[0004] The purpose of this invention is to provide a semiconductor device and its fabrication method, which improves the problems of low breakdown voltage in the input and output regions and micro-load effects during the groove etching and epitaxial growth process, without the need to add a new photomask.

[0005] To address the aforementioned technical problems, according to a first aspect of the present invention, a method for fabricating a semiconductor device is provided, comprising the following steps:

[0006] A substrate is provided, the substrate including a core region and an input / output region, and multiple gate structures are formed on the substrate in both the core region and the input / output region;

[0007] A hard mask layer is formed, which covers the sidewalls, top, and surface of the substrate of the gate structure;

[0008] Reduce the thickness of the hard mask layer within the core region;

[0009] The substrate is etched using the hard mask layer as a barrier layer to form a groove; and

[0010] An epitaxial layer is formed within the groove.

[0011] Optionally, a method for reducing the thickness of the hard mask layer within the core region includes:

[0012] A first photoresist layer is formed on the hard mask layer;

[0013] The first photoresist layer is exposed using a first photomask as a mask, and then developed to form a first patterned photoresist layer, which exposes the core region.

[0014] Using the first patterned photoresist layer as a mask, the hard mask layer within the core region is etched to remove a portion of the hard mask layer's thickness; and

[0015] Remove the first patterned photoresist layer.

[0016] Optionally, the gate structure includes a gate oxide layer, a gate, and a sidewall located sequentially on the substrate and between the gate oxide layer and the gate sidewall; the method for forming the gate oxide layer in the input / output region and the core region includes:

[0017] A gate oxide layer is formed on the substrate;

[0018] A second photoresist layer is formed on the gate oxide layer;

[0019] The second photoresist layer is exposed using a second photomask as a mask, and then developed to form a second patterned photoresist layer, which exposes the core region.

[0020] Using the second patterned photoresist layer as a mask, the gate oxide layer within the core region is etched to remove a portion of the gate oxide layer; and

[0021] Remove the second patterned photoresist layer.

[0022] Optionally, the first photomask and the second photomask are the same photomask.

[0023] Optionally, lightly doped regions are further formed in the substrate on both sides of the gate structure, and the doping concentration of the lightly doped regions in the input / output regions is less than the doping concentration of the lightly doped regions in the core regions.

[0024] Optionally, the substrate is subjected to dry etching and wet etching processes in sequence to form sigma grooves in the substrate.

[0025] Optionally, a dry etching process is performed on the substrate to form a U-shaped groove or a trapezoidal groove in the substrate.

[0026] Optionally, after forming the epitaxial layer in the groove, the method further includes forming a capping layer on the epitaxial layer.

[0027] Optionally, the epitaxial layer includes a boron-doped silicon-germanium layer, and the capping layer includes a boron-doped silicon layer or a boron-doped silicon-germanium layer.

[0028] To solve the above-mentioned technical problems, according to a second aspect of the present invention, a semiconductor device is also provided, which is manufactured using the semiconductor device manufacturing method described above.

[0029] In summary, in the semiconductor device and its fabrication method provided by this invention, after forming a hard mask layer covering the sidewalls, top, and substrate surface of the gate structure, the thickness of the hard mask layer in the core region is reduced so that the thickness of the hard mask layer in the core region is less than the thickness of the hard mask layer in the input / output region. Subsequently, when forming a groove in the substrate, since the hard mask layer in the input / output region, which acts as a barrier layer, is relatively thick, the volume of the groove formed in the input / output region can be prevented from being too large, thereby increasing the effective distance between the gate structure (specifically the gate) in the input / output region and the epitaxial layer formed in the groove, thereby increasing the breakdown voltage of the device in the input / output region. At the same time, since the thickness of the hard mask layer in the input / output region and the core region is different, the micro-load effect caused by the difference in pattern density between the two regions during the groove etching and epitaxial growth process can also be reduced.

[0030] In addition, when reducing the thickness of the hard mask layer in the core area, the same photomask used when forming the gate oxide layer is used, so there is no need to add a new photomask, thereby saving manufacturing costs. Attached Figure Description

[0031] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:

[0032] Figure 1 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention.

[0033] Figures 2 to 7 This is a schematic diagram of the steps in a method for fabricating a semiconductor device according to an embodiment of the present invention.

[0034] Explanation of reference numerals in the attached figures:

[0035] 10-Substrate; 11-Isolation structure; 12-Lightly doped region; 20-Gate structure; 21-Gate oxide layer; 22-Gate; 23-Sidewall; 24-Gate mask layer; 30-Hard mask layer; 31-First hard mask layer; 32-Second hard mask layer; 40-First patterned photoresist layer; 50-Groove; 51-Epipolar layer; 52-Cap layer. Detailed Implementation

[0036] The core idea of ​​this invention is to reduce the thickness of the hard mask layer in the core region after forming the hard mask layer, so that the thickness of the hard mask layer in the core region is less than the thickness of the hard mask layer in the input and output regions, thereby improving the problem of low breakdown voltage in the input and output regions, and improving the problem of micro-load effect in the groove etching and epitaxial growth process, without the need to add a new photomask.

[0037] Furthermore, the present invention provides a method for fabricating a semiconductor device, comprising the following steps: providing a substrate, the substrate including a core region and an input / output region, wherein a plurality of gate structures are formed on the substrate in both the core region and the input / output region; forming a hard mask layer, the mask layer covering the sidewalls, top, and surface of the gate structures and the substrate; thinning the thickness of the hard mask layer in the core region; etching the substrate using the hard mask layer as a barrier layer to form a groove; and forming an epitaxial layer in the groove.

[0038] Accordingly, the present invention also provides a semiconductor device, which is manufactured using the semiconductor device manufacturing method described above.

[0039] In the semiconductor device and its fabrication method provided by this invention, after forming a hard mask layer covering the sidewalls, top, and substrate surface of the gate structure, the thickness of the hard mask layer in the core region is reduced so that the thickness of the hard mask layer in the core region is less than the thickness of the hard mask layer in the input / output region. Subsequently, when forming a groove in the substrate, since the hard mask layer in the input / output region, which acts as a barrier layer, is relatively thick, the volume of the groove formed in the input / output region can be avoided from being too large, thereby increasing the effective distance between the gate structure (specifically the gate) in the input / output region and the epitaxial layer formed in the groove, thereby increasing the breakdown voltage of the device in the input / output region. At the same time, since the thickness of the hard mask layer in the input / output region and the core region is different, the micro-load effect caused by the difference in pattern density between the two regions during the groove etching and epitaxial growth process can also be reduced.

[0040] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.

[0041] As used herein, the singular forms “a,” “an,” and “the” include plural objects unless otherwise expressly indicated. As used herein, the term “or” is generally used to include “and / or” unless otherwise expressly indicated. As used herein, the term “a number” is generally used to include “at least one” unless otherwise expressly indicated. As used herein, the term “at least two” is generally used to include “two or more” unless otherwise expressly indicated. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature.

[0042] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention. Please refer to... Figure 1 As shown, the method for fabricating a semiconductor device provided in this embodiment includes the following steps:

[0043] Step S1: Provide a substrate, the substrate including a core region and an input / output region, and multiple gate structures are formed on the substrate of both the core region and the input / output region;

[0044] Step S2: Form a hard mask layer, the mask layer covering the sidewalls, top, and surface of the substrate of the gate structure;

[0045] Step S3: Reduce the thickness of the hard mask layer within the core region;

[0046] Step S4: Etching the substrate using the hard mask layer as a barrier layer to form a groove; and

[0047] Step S5: An epitaxial layer is formed in the groove.

[0048] Figures 2 to 7 This is a schematic diagram illustrating the structural steps of a semiconductor device fabrication method according to an embodiment of the present invention. Next, we will combine... Figure 1 and Figures 2 to 7The method for fabricating the semiconductor device provided in the embodiments of the present invention will be described in detail.

[0049] In step S1, please refer to Figure 2 As shown, a substrate 10 is provided, the substrate 10 including a core region II and an input / output region I, and a plurality of gate structures 20 are formed on the substrate 10 of both the core region II and the input / output region I.

[0050] In this embodiment, the substrate 10 can be silicon, germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium arsenide, or it can be silicon-on-insulator or germanium-on-insulator; or it can be other materials, such as gallium arsenide or other III-V compounds. In this embodiment, the substrate 10 is a silicon substrate.

[0051] The substrate 10 includes a core region II and an input / output region I. The core region II is used to form core devices, and the input / output region I is used to form input / output devices. The input / output region I and the core region II can be isolated by an isolation structure 11, such as a shallow trench isolation structure.

[0052] Multiple gate structures 20 are formed on the substrates 10 of both the core region II and the input / output region I. Each gate structure 20 includes a gate oxide layer 21, a gate 22, and sidewalls 23 located sequentially on the substrate 10. The gate oxide layer 21 is made of, for example, silicon oxide, and the gate 22 is made of, for example, polysilicon. A gate mask layer 24 may also be formed on the gate 22 to act as a mask and protect the gate 22 during subsequent etching of the substrates 10 on both sides of the gate structure 20. The gate mask layer 24 is made of, for example, silicon nitride. The sidewalls 23 can be single-layer sidewalls located only on the sidewalls of the gate oxide layer 21 and the gate 22. The sidewalls 23 are made of, for example, silicon oxide or silicon nitride. The sidewall 23 can also be a double-layer sidewall, with the first sidewall located on the sidewall of the gate oxide layer 21 and the gate 22, and the second sidewall located on the sidewall of the gate mask layer 24 and the first sidewall. The material of the first sidewall is, for example, silicon oxide, and the material of the second sidewall is, for example, silicon nitride.

[0053] Lightly doped regions 12 may also be formed within the substrate 10 on both sides of the gate structure 20. In one embodiment, the turn-on speed of the device in the input / output region I is lower than that of the device in the core region II, that is, the threshold voltage of the input / output region I is higher than that of the core region II. Therefore, the doping concentration of the lightly doped region 12 in the input / output region I is lower than that of the lightly doped region 12 in the core region II. For example, the lightly doped region 12 can be formed by ion implantation of the substrate 10 after the formation of the gate 22 and before the formation of the sidewall 23.

[0054] In one embodiment, the thickness of the gate oxide layer 21 in the core region II may be less than the thickness of the gate oxide layer 21 in the input / output region I. The method for forming the gate oxide layer 21 in the input / output region II and the core region I may include: firstly, forming the gate oxide layer 21 on the substrate 10, the gate oxide layer 21 covering the input / output region I and the core region II; then forming a second photoresist layer on the gate oxide layer 21; then exposing the second photoresist layer using a second photomask as a mask, and developing it to form a second patterned photoresist layer, wherein the second photomask blocks the input / output region I, exposing the core region II, and therefore the second patterned photoresist layer also exposes the core region II; then etching the gate oxide layer 21 in the core region II using the second patterned photoresist layer as a mask to remove a portion of the gate oxide layer 21; finally, removing the second patterned photoresist layer.

[0055] In one embodiment, the distance between adjacent gate structures 20 in the input / output region I is greater than the distance between adjacent gate structures 20 in the core region II, that is, the devices in the input / output region I are relatively sparse, while the devices in the core region II are relatively dense.

[0056] In step S2, please refer to Figure 3 As shown, a hard mask layer 30 is formed, which covers the sidewalls, top, and surface of the substrate 10 of the gate structure 20.

[0057] In one embodiment, the hard mask layer 30 comprises a stack of a first hard mask layer 31 and a second hard mask layer 32. The first hard mask layer 31 covers the sidewalls and top of the gate structure 20 and the surface of the substrate 10, and the second hard mask layer 32 covers the first hard mask layer 31. The first hard mask layer 31 and the second hard mask layer 32 can be formed using any suitable process known to those skilled in the art, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD). The first hard mask layer 31 is, for example, a silicon oxide layer, and the second hard mask layer 32 is, for example, a silicon nitride layer. In another embodiment, the hard mask layer 30 may also be a single-layer mask layer, covering the sidewalls and top of the gate structure 20 and the surface of the substrate 10. The hard mask layer 30 may be a silicon nitride layer, but is not limited to this.

[0058] In one embodiment of the present invention, the thickness of the hard mask layer 30 needs to meet the performance requirements of the devices within the input / output region I. The thickness of the hard mask layer 30 can be appropriately adjusted to increase the effective distance between the groove and the gate 20 in subsequent etching processes, thereby improving the breakdown voltage of the devices in the input / output region. It is understood that the thickness of the second hard mask layer 32 is greater than the thickness of the first hard mask layer 31, and the thickness of the hard mask layer 30 can be adjusted by adjusting the thickness of the second hard mask layer 32.

[0059] In step S3, please refer to Figure 4 As shown, the thickness of the hard mask layer 30 within the core region II is reduced.

[0060] For example, a first photoresist layer is first formed on the hard mask layer 30. Then, a first photomask is used as a mask to expose the first photoresist layer, and development is performed to form a first patterned photoresist layer 40. The first photomask blocks the input / output region I, exposing the core region II. Therefore, the first patterned photoresist layer 40 covers the input / output region I and exposes the core region II, exposing the hard mask layer 30 (specifically, the second hard mask layer 32) within the core region II. Then, using the first patterned photoresist layer 40 as a mask, the hard mask layer 30 (specifically, the second hard mask layer 32) within the core region II is etched to remove a portion of its thickness. Finally, the first patterned photoresist layer 40 is removed.

[0061] In one embodiment, a dry etching process can be used to etch the hard mask layer 30. By controlling the etching time, the thickness of the remaining hard mask layer 30 in the core region II can meet the electrical performance requirements of the core region II.

[0062] In one embodiment, the doping concentration of the lightly doped region 12 within the input / output region I is less than that of the lightly doped region 12 within the core region II. Subsequently, when etching the substrate 10 to form a trench, the different doping concentrations of the lightly doped regions 12 result in different etching rates between the two regions. The etching rate of the input / output region I is greater than that of the core region II, leading to a larger trench size in the input / output region I. This results in a smaller distance between the trench and the gate 22, making it more prone to breakdown. In this embodiment of the invention, after the hard mask layer 30 is formed, the hard mask layer 30 in the core region II is etched to reduce its thickness. The thickness of the hard mask layer 30 formed in the two regions can be adjusted by the deposition and partial etching processes of the hard mask layer 30. That is, the thickness of the hard mask layer 30 in the input / output region I can be appropriately increased, thereby avoiding the excessive volume of the groove formed in the input / output region I. This increases the effective distance between the gate structure 20 (specifically the gate 22) of the input / output region I and the epitaxial layer formed in the groove, thereby increasing the breakdown voltage of the device in the input / output region I.

[0063] In one embodiment, the distance between adjacent gate structures 20 within the input / output region I is greater than the distance between adjacent gate structures 20 within the core region II. That is, the devices within the input / output region I are relatively sparse, while the devices within the core region II are relatively dense. When the input / output region I and the core region II are etched simultaneously, the different pattern densities lead to different etching rates. For example, the etching rate of the input / output region I will be greater than that of the core region II, resulting in a micro-loading effect. In this embodiment, after the hard mask layer 30 is formed, the hard mask layer 30 in the core region II is etched. The thickness difference of the hard mask layer 30 in the input / output region I and the core region II can be adjusted by controlling the etching amount to improve the pattern density of the two regions. For example, the thickness of the hard mask layer 30 in the input / output region I can be increased to adjust the thickness of the hard mask layer 30 covering the sidewall of the gate structure 20, thereby reducing the pattern density in the two regions and reducing the micro-load effect in the groove etching and epitaxial growth process caused by the difference in pattern density between the two regions.

[0064] In addition, the first photomask used when exposing the first photoresist layer is the same photomask used when exposing the second photoresist layer. That is, the photomask used when forming the gate oxide layer 21 is used to etch the hard mask layer 30. Therefore, there is no need to add a new photomask, thereby saving manufacturing costs.

[0065] In step S4, please refer to Figure 4 and Figure 5 As shown, the substrate 10 is etched using the hard mask layer 30 as a barrier layer to form a groove 50.

[0066] In one embodiment, the groove 50 is a sigma groove; in another embodiment, the groove 50 is a U-shaped groove or a trapezoidal groove, or other grooves known to those skilled in the art, and the present invention does not limit this.

[0067] In one embodiment, a dry etching process is performed on the substrate 10 to form a U-shaped groove or a trapezoidal groove within the substrate 10. Exemplarily, the substrate 10 is subjected to dry etching, such as isotropic dry etching. The etching gas can be selected to have a higher selectivity for both the substrate 10 and the hard mask layer 30, meaning the etching rate for the substrate 10 is greater than the etching rate for the hard mask layer 30. First, the hard mask layer 30 is etched to remove the surface of the hard mask layer 30 from the substrate 10. At this point, a portion of the hard mask layer 30 is still exposed on the sidewalls of the gate structure 20. The top portion of the hard mask layer 30 on the gate structure 20 is removed. Then, the substrate 10 is etched further to form the groove 50. During subsequent etching, the gate mask layer 24 acts as a mask layer to protect the gate 22, ultimately forming a U-shaped groove or a trapezoidal groove within the substrate 10.

[0068] In another embodiment, the substrate 10 is sequentially subjected to dry etching and wet etching processes to form sigma grooves within the substrate 10. Exemplarily, the substrate 10 is first subjected to dry etching, such as isotropic dry etching, to form U-shaped or trapezoidal grooves within the substrate 10. Next, wet etching is performed, for example using TMAM (tetramethylammonium hydroxide) solution or KOH (potassium hydroxide), utilizing its... <111> The low surface etching rate creates sigma grooves. The wet etching is directional etching, and the etching rate varies depending on the crystal orientation of the substrate 10; for example, for… <100> and <110> It has a very high etching rate, for <111> It has a very low etching rate, thus etching out sigma-shaped grooves 50.

[0069] In this embodiment, the input / output region I can obtain a larger D value (e.g., due to the obstruction of the thick hard mask layer 30) Figure 5As shown, D is the effective distance between the gate 22 and the groove 50, thereby increasing the breakdown voltage of the input / output region I device. The groove 50 formed in the core region II, due to the relatively thin hard mask layer 30, can meet the device performance requirements (mainly by epitaxially growing SiGe to provide stress); at the same time, it can reduce the loading of the groove 50 in both regions, thereby reducing the micro-loading effect.

[0070] In step S5, please refer to Figure 6 As shown, an epitaxial layer 51 is formed within the groove 50.

[0071] In this embodiment, the epitaxial layer 51 is formed by an epitaxial process. The epitaxial layer 51 includes a boron-doped silicon-germanium layer, but is not limited to this. Since the micro-loading effect during the etching process to form the groove 50 has been improved, the micro-loading effect during the epitaxial growth process has also been significantly improved.

[0072] After forming the epitaxial layer 51 within the groove 50, the process further includes forming a capping layer 52 on the epitaxial layer 51. The capping layer 52 can be formed using an epitaxial process, and the capping layer 52 includes a boron-doped silicon layer or a boron-doped silicon-germanium layer.

[0073] Please refer to Figure 6 and Figure 7 As shown, after forming the capping layer 52, the process further includes removing the hard mask layer 30 and the gate mask layer 24.

[0074] In the semiconductor device fabrication method provided by the present invention, a substrate 10 is first provided, the substrate 10 including a core region II and an input / output region I. Multiple gate structures 20 are formed on the substrate 10 in both the core region II and the input / output region I. Then, a hard mask layer 30 is formed, the mask layer 30 covering the sidewalls, top, and surface of the gate structure 20 and the substrate 10. Then, the thickness of the hard mask layer 30 in the core region II is reduced. Then, the substrate 10 is etched with the hard mask layer 30 as a barrier layer to form a groove 50. Then, an epitaxial layer 51 is formed in the groove 50. This invention reduces the thickness of the hard mask layer 30 in the core region II, making it thinner than that in the input / output region I. When a groove 50 is subsequently formed in the substrate 10, the thicker hard mask layer 30 in the input / output region I prevents the groove 50 from becoming too large, thus increasing the effective distance between the gate structure 20 (specifically, gate 22) and the epitaxial layer 51 formed in the groove 50. This, in turn, improves the breakdown voltage of the device in the input / output region I. Furthermore, the difference in thickness between the hard mask layers 30 in the input / output region I and the core region II reduces the micro-load effect caused by the difference in pattern density between the two regions during the etching of the groove 50 and the epitaxial growth process.

[0075] Accordingly, the present invention also provides a semiconductor device, which is manufactured using the semiconductor device manufacturing method described above.

[0076] In summary, in the semiconductor device and its fabrication method provided by this invention, after forming a hard mask layer covering the sidewalls, top, and substrate surface of the gate structure, the thickness of the hard mask layer in the core region is reduced so that the thickness of the hard mask layer in the core region is less than the thickness of the hard mask layer in the input / output region. Subsequently, when forming a groove in the substrate, since the hard mask layer in the input / output region, which acts as a barrier layer, is relatively thick, the volume of the groove formed in the input / output region can be prevented from being too large, thereby increasing the effective distance between the gate structure (specifically the gate) in the input / output region and the epitaxial layer formed in the groove, thereby increasing the breakdown voltage of the device in the input / output region. At the same time, since the thickness of the hard mask layer in the input / output region and the core region is different, the micro-load effect caused by the difference in pattern density between the two regions during the groove etching and epitaxial growth process can also be reduced.

[0077] In addition, when reducing the thickness of the hard mask layer in the core area, the same photomask used when forming the gate oxide layer is used, so there is no need to add a new photomask, thereby saving manufacturing costs.

[0078] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A method for fabricating a semiconductor device, characterized in that, Includes the following steps: A substrate is provided, the substrate including a core region and an input / output region, and multiple gate structures are formed on the substrate in both the core region and the input / output region; A hard mask layer is formed, which covers the sidewalls, top, and surface of the substrate of the gate structure; Reduce the thickness of the hard mask layer within the core region; The substrate is etched using the hard mask layer as a barrier layer to form a groove; and An epitaxial layer is formed within the groove.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The method for reducing the thickness of the hard mask layer within the core region includes: A first photoresist layer is formed on the hard mask layer; The first photoresist layer is exposed using a first photomask as a mask, and then developed to form a first patterned photoresist layer, which exposes the core region. Using the first patterned photoresist layer as a mask, the hard mask layer within the core region is etched to remove a portion of the hard mask layer's thickness; and Remove the first patterned photoresist layer.

3. The method for fabricating a semiconductor device according to claim 2, characterized in that, The gate structure includes a gate oxide layer, a gate, and a sidewall located between the gate oxide layer and the gate sidewall, which are sequentially located on the substrate. The method for forming the gate oxide layer in the input / output region and the core region includes: A gate oxide layer is formed on the substrate; A second photoresist layer is formed on the gate oxide layer; The second photoresist layer is exposed using a second photomask as a mask, and then developed to form a second patterned photoresist layer, which exposes the core region. Using the second patterned photoresist layer as a mask, the gate oxide layer within the core region is etched to remove a portion of the gate oxide layer; and Remove the second patterned photoresist layer.

4. The method for fabricating a semiconductor device according to claim 3, characterized in that, The first photomask and the second photomask are the same photomask.

5. The method for fabricating a semiconductor device according to claim 1, characterized in that, Lightly doped regions are also formed in the substrate on both sides of the gate structure, and the doping concentration of the lightly doped regions in the input / output region is less than the doping concentration of the lightly doped regions in the core region.

6. The method for fabricating a semiconductor device according to claim 1, characterized in that, The substrate is subjected to dry etching and wet etching processes in sequence to form sigma grooves in the substrate.

7. The method for fabricating a semiconductor device according to claim 1, characterized in that, The substrate is subjected to a dry etching process to form a U-shaped groove or a trapezoidal groove within the substrate.

8. The method for fabricating a semiconductor device according to claim 1, characterized in that, After forming the epitaxial layer in the groove, the method further includes forming a capping layer on the epitaxial layer.

9. The method for fabricating a semiconductor device according to claim 8, characterized in that, The epitaxial layer includes a boron-doped silicon-germanium layer, and the capping layer includes a boron-doped silicon layer or a boron-doped silicon-germanium layer.

10. A semiconductor device, characterized in that, It is manufactured using the method for manufacturing a semiconductor device as described in any one of claims 1 to 9.

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