Positioning of gate bus through middle point of finger in finger fets

Abstract

Disclosed is positioning of a gate bus through a middle point in a finger lateral field effect transistor. A lateral finger field effect transistor having a gate bus extending through a middle location of the finger, and wherein the source finger also extends from a source bus also located at the middle location. This reduces the length of the gate finger terminal and the source finger terminal, and thus reduces the voltage drop along the gate finger terminal and the source finger terminal. Thus, the gate to source voltage is better maintained along the entire length of the finger when the transistor is turned on. Thus, the lateral finger field effect transistor is more properly biased along the entire length of the finger of the field effect transistor. Furthermore, since the direction of current flow in the gate terminal and the source terminal is still in opposite directions, the common source inductance is at least partially cancelled out.

Description

Background Technology

[0001] Electronic circuits typically include transistors, which are devices that function as electronic switches to regulate or control the flow of current in various parts of a circuit. A lateral field-effect transistor (FET) is a type of transistor in which a semiconductor channel region is laterally disposed between the drain and source terminals. "Laterally" means in the plane of the epitaxial stack perpendicular to the direction of epitaxial growth that forms the epitaxial stack. A lateral transistor includes a source active region connected to the source terminal and a drain active region connected to the drain terminal.

[0002] When the lateral transistor is turned on, current flows laterally from the source active region through the semiconductor channel region to the drain active region. When the transistor is turned off, less current or no current flows through the semiconductor channel region between the source and drain active regions. The gate terminal is positioned over the semiconductor channel region between the source and drain terminals at such close proximity that a signal applied to the gate terminal affects whether the semiconductor channel region conducts current from the source active region to the drain active region.

[0003] The subject matter claimed herein is not limited to embodiments that address any shortcomings or operate only in environments such as those described above. Rather, this background is provided merely to illustrate an exemplary technical field in which some of the embodiments described herein can be practiced. Summary of the Invention

[0004] This summary is provided to introduce the choice of concepts in a simplified form, and the concepts are further described below in detail. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

[0005] The embodiments described herein relate to lateral finger field-effect transistors (FETs) having a gate bus extending through the middle of the fingers, and wherein source fingers also extend from the source bus, which is also located at the middle. This reduces the length of the gate and source finger terminals, and thus reduces the voltage drop along the gate and source finger terminals. Therefore, when the transistor is turned on, the gate-to-source voltage is better maintained along the entire length of the fingers. Consequently, the lateral finger FET is more appropriately biased along the entire length of the FET. Furthermore, since the direction of current flow in the gate and source terminals remains in opposite directions, the common source inductance is at least partially canceled out.

[0006] Additional features and advantages will be set forth in the following description, and will be apparent in part from the description, or may be learned by practice of the teachings herein. The features and advantages of the invention can be realized and obtained by means of the tools and combinations particularly pointed out in the appended claims. The features of the invention will become more fully apparent from the following description and the appended claims, or may be learned by practice of the invention as set forth herein. Attached Figure Description

[0007] To describe how the above-described and other advantages and features can be obtained, a more specific description of the subject matter briefly described above will be presented with reference to specific embodiments illustrated in the accompanying drawings. It is understood that these drawings depict only typical embodiments and are therefore not intended to limit the scope; the embodiments will be described and explained using additional features and details through the accompanying drawings, in which: Figure 1 The illustration shows a stacked view (top view) of a finger lateral field-effect transistor, representing a very specific example of an embodiment illustrating the broader principles described herein. Figure 2 The diagram shows... Figure 1 An example of a side view of a metal stack shown in the diagram; Figure 3 The illustration shows the process of manufacturing. Figure 1 A flowchart of a transistor method; Figures 4A to 4F The diagram shows... Figure 1 The successive manufacturing states of the transistors; and Figure 5 The illustration shows a top view of an example alternative transistor with multiple gate buses located at the midpoint of the fingers along the lateral field-effect transistor. Detailed Implementation

[0008] The embodiments described herein relate to lateral finger field-effect transistors (FETs) having a gate bus extending through the middle of the fingers, and wherein source fingers also extend from the source bus, which is also located at the middle. This reduces the length of the gate and source finger terminals, and thus reduces the voltage drop along the gate and source finger terminals. Therefore, when the transistor is turned on, the gate-to-source voltage is better maintained along the entire length of the fingers. Consequently, the lateral finger FET is more appropriately biased along the entire length of the FET. Furthermore, since the direction of current flow in the gate and source terminals remains in opposite directions, the common source inductance is at least partially canceled out.

[0009] Figure 1A layer stack view (top view) of a finger-shaped lateral field-effect transistor 100, representing a very specific example of an embodiment illustrating the broader principles described herein, is illustrated. A three-dimensional (3D) Cartesian axis 101 is also illustrated and will be used by convention for clarity when describing particular directions. Axis 101 runs through the figures and is used by convention in the description. For example, the lateral field-effect transistor 100 is formed via epitaxial growth of various layers on top of each other. The direction of this epitaxial growth is in the positive z-direction of reference axis 101 (which will be the direction from the page toward the reader). On the other hand, each layer in this epitaxial stack is layered in a plane defined by the x-axis and y-axis (also referred to herein as the “xy plane” or “lateral plane”). For clarity, this will be in the plane of the figures themselves. Thus, Figure 1 This is a top view looking downwards with respect to the direction of epitaxial growth. Unless otherwise stated, terms describing vertical relationships, movements, or directions (e.g., up, down, below, above, under, above, etc.) are relative to the z-direction.

[0010] Furthermore, to make it clear, in Figure 1 In the layer stack view, all the relevant metal layers of the epitaxial stack are visible, even though in the actual transistor, the metal layers are opaque and therefore obstruct the view of the layers below in the actual structure. However, in Figure 1 The diagram illustrates the stacking of metal layers, where when one structure lies beneath another, the underlying structure is still shown but in a lighter shade. This is for clarity, allowing for a proper visual understanding of the relationship between the upper and lower metal layers. Other non-conductive structures are not shown, allowing focus to be placed on the metal layers and their relationships with each other and with the underlying active region.

[0011] A metal layer is formed above and within the context of the underlying active regions 110A and 110B. These active regions 110A and 110B are formed of a semiconductor material. Figure 1 In the diagram, active regions 110A and 110B are shown as boxes with dashed borders and are not filled except where they are altered by the layer above. For further clarity, Figure 4A The illustration shows a manufacturing state 400A of transistor 100, showing only active regions 110A and 110B. In the conventions used herein, components that operate more with active region 110A will be designated with the suffix "A," and components that operate more with active region 110B will be designated with the suffix "B." Components operating with both active regions will not have a letter suffix or will be designated with the suffix "C."

[0012] Figure 2 The diagram shows Figure 1The illustration shows an example of a side view of the metal stack 200. The bottommost metal layer is the gate metal layer 211, which forms the gate terminal 111. The gate terminal 111 is illustrated as being defined by an outline with solid lines, except where it is altered by the layers above. For further clarity, Figure 4B The illustration shows a manufacturing state 400B of a transistor 100 with a gate terminal 111 formed over active regions 110A and 110B. The gate terminal 111 includes a gate bus 111C and finger gate terminals including finger gate terminal portions 111A and 111B. The gate terminal 111 is integrated such that both the finger gate terminal portions 111A and 111B are electrically connected to the gate bus 111C and are located within the same gate metal layer 211.

[0013] The finger gate terminal portion 111A extends from the gate bus 111C in the positive y-direction (in the lateral plane of the metal layer 211) and extends over the active region 110A. On the other hand, the finger gate terminal portion 111B extends from the gate bus 111C in the negative y-direction (in the lateral plane of the metal layer 211) and extends over the active region 110B. The finger gate terminal portions 111A and 111B are collinear. Figure 1 They occupy the same x and z coordinates and extend along the y-axis. The finger gate terminal portions 111A and 111B are in such a vertical proximity to their respective active regions 110A and 110B that a signal applied to the gate terminal 111 will apply an appropriate electric field effect to the active regions 110A and 110B in order to effectively control whether the underlying active regions are conductive (to turn on transistor 100) or non-conductive (to turn off transistor 100).

[0014] The point where the finger gate terminal portion 111A and the gate bus 111C are connected will be referred to as the "proximal end" of the finger gate terminal portion 111A, and the point of the finger gate terminal portion 111A farthest from the gate bus 111C will be referred to as the "distal end" of the finger gate terminal portion 111A. Similarly, the point where the finger gate terminal portion 111B and the gate bus 111C are connected will be referred to as the "proximal end" of the finger gate terminal portion 111B, and the point of the finger gate terminal portion 111B farthest from the gate bus 111C will be referred to as the "distal end" of the finger gate terminal portion 111B.

[0015] Moving upwards in the positive z-direction, but now skipping the shielding metal layer 212, there are source and drain metal layers 213 for forming the finger-shaped drain terminal 116 and the finger-shaped source terminal 113 including finger-shaped source portions 113A and 113B. For further clarity, the presence of the shielding metal 112 is now ignored. Figure 4DThe illustration shows a manufacturing state 400D of a transistor 100 in which a finger source terminal 113 and a finger drain terminal are formed on a gate terminal 111.

[0016] Finger-shaped source portions 113A extend from near the gate bus 111C in the positive y-direction (in the lateral plane of the metal layer 213) over the active region 110A. Conversely, finger-shaped source portions 113B extend from near the gate bus 111C in the negative y-direction (in the lateral plane of the metal layer 213) over the active region 110B. Finger-shaped source portions 113A and 113B are collinear and occupy... Figure 1 The same x and z coordinates are used, and the finger source pole portions 113A and 113B are extended along the y-axis. In addition, although not required, the finger source pole portions 113A and 113B are connected, defining a finger source pole 113.

[0017] Therefore, the finger source terminal 113 extends parallel to the finger gate terminal portions 111A and 111B. Specifically, the finger source portion 113A extends parallel to the finger gate terminal portion 111A and along the finger gate terminal portion 111A over the active region 110A; and the finger source portion 113B extends parallel to the finger gate terminal portion 111B and along the finger gate terminal portion 111B over the active region 110B. The finger source terminal 113 is not electrically connected to the gate terminal 111 but is in contact with the lower source terminal (not shown), which extends in the y direction and is in contact with the semiconductor of the corresponding active regions 110A and 110B.

[0018] The source and drain metal layers 213 also include finger drain terminals 116, which extend along the y-axis (in the transverse plane of metal layer 213) over substantially the entire y-axis extent of the active regions 110A and 110B. The finger drain terminals 116 contact the underlying drain (not shown), which extends in the y-direction and contacts the semiconductor of the respective active regions 110A and 110B.

[0019] Therefore, the finger gate terminals (forming finger gate terminal portions 111A and 111B), finger source terminal 113, and finger drain terminal 116 are substantially parallel. When a suitable signal is applied to the gate terminals, and when a high positive voltage exists at the drain compared to any voltage at the source, a large current flows from the drain to the source in the negative x-direction. The current is substantial because it occurs along the entire extent of the active region 110A (in the y-direction), allowing for a wide current flow path. Furthermore, the transistor 100 can actually have many such fingers, allowing a large amount of current to flow across the transistor.

[0020] By way of example only, transistor 100 may be a high electron mobility transistor (HEMT). In this case, the gate terminal can be positioned in the x-direction closer to the finger source terminal 113 (and the source below the contact active region) than the finger drain terminal 116 (and the drain below the contact active region). Furthermore, the finger source terminal 113 may also be connected to a field plate (not shown) for controlling the electric field distribution in the active region. As a more specific example, transistor 100 may be a gallium nitride (GaN) HEMT. However, the principles described herein are not limited to such transistors, because the reduced debiasing effect and common source inductance benefits can be achieved for any lateral field-effect transistor due to the reduced finger length of the gate and source finger portions caused by the intermediate placement of the gate bus.

[0021] Back Figure 2 A shielding metal layer 212 is formed between the gate metal layer 211 and the source and drain metal layers 213. The shielding metal layer 212 is... Figure 2 The shielding metal 112 is shown in the diagram and has a light gray fill. As an example, the shielding metal layer 212 can be made of titanium nitride (TiN). The shielding metal 112 is vertically positioned between the intersection of the gate bus 111C and the finger drain terminal 116. For clarity, Figure 4C The illustration shows a manufacturing state 400C in which the shielding metal 112 is formed on (but not in electrical contact with) the underlying gate bus 111C. This occurs... Figure 4D Before the formation of the finger source terminal and finger gate terminal, shielding metal 112 prevents high-voltage electromagnetic interference present on the finger drain terminal 116 from being applied to the voltage of the gate bus 111C. Such shielding is particularly helpful when the voltage applied to the finger drain terminal 116 is high (such as hundreds of volts or higher) and / or subjected to rapid and large voltage changes.

[0022] exist Figure 2 Moving upwards, a through-hole layer 214 exists therein, in which through-holes are formed. For example, in Figure 1 The diagram shows twelve through holes 114(1) to 114(12). The through hole layer 214 and the through holes 114(1) to 114(12) are shown as small solid filled frames. Figure 4E The illustration shows manufacturing state 400E, in which through holes 114(1) to 114(6) are formed on and in contact with drain terminal 116, through holes 114(7) to 114(9) are formed on and in contact with finger source portion 113A, and through holes 114(10) to 114(12) are formed on and in contact with finger source portion 113B.

[0023] exist Figure 2 Moving upwards, we reach bus metal layer 215. Bus metal layer 215 is used to form drain bus 117 and source bus 115. Each of bus metal layer 215, drain bus 117 and source bus 115 is illustrated as a box filled with right-sloping striped markings. Drain bus 117 is connected to finger drain terminal 116 via vias 114(1) to 114(6). Source bus 115 is above gate bus 111C. Source bus 115 is connected to finger source portion 113A of finger source terminal via vias 114(7) to 114(9), and is connected to finger source portion 113B via vias 114(10) to 114(12). Therefore, a source voltage (which may be ground) is applied to the source bus 115, a drain voltage (which may be very high, in the hundreds or thousands of volts) is applied to the drain bus 117, and a control signal is applied to the gate bus 111C to turn the transistor 100 on and off. The point where the finger source portion 113A connects to the source bus 115 is referred to as the "proximal end" of the finger source portion 113A. The point where the finger source portion 113B connects to the source bus 115 is referred to as the "proximal end" of the finger source portion 113B.

[0024] exist Figure 1 In this configuration, the gate bus 111C is located in the middle of the y-axis range of the active region of transistor 100. Compared to having a gate bus at one y-axis end of the active region, this reduces the length of current flow required to reach each end of the gate finger terminals. Therefore, the voltage drop in the gate finger terminal portions 111A and 111B is reduced, allowing more voltage to reach even the far ends of the gate finger terminal portions. Furthermore, compared to having a source bus at one y-axis end of the y-axis region, the length of the source finger portions 113A and 113B is reduced, allowing the voltage applied at the source bus to reach the far ends of the source finger portions with higher fidelity. Therefore, the lateral finger field-effect transistor is more appropriately biased along the entire length of the fingers of the field-effect transistor, reducing the debiasing effect caused by the voltage drop when current flows through the finger gate terminals.

[0025] Furthermore, since the current flows in the gate and source terminals are still in opposite directions, the common source inductance is at least partially canceled out. For example, when transistor 100 switches to on, current flows in the positive y-direction through the finger gate terminal portion 111A. Simultaneously, since the transistor is positive on, current flows in the negative y-direction through the finger source portion 113A. Therefore, the common source inductance that might otherwise arise for the active region 110A due to current flow along the y-axis is at least partially canceled out.

[0026] Accordingly, when transistor 100 switches to on, current flows in the negative y-direction through the finger gate terminal portion 111B. Simultaneously, since the transistor is positively on, current flows in the positive y-direction through the finger source portion 113B. Therefore, the common source inductance that might otherwise arise for the active region 110B due to current flow along the y-axis is at least partially canceled out. When the transistor is positively off, similar opposite currents occur in the gate and source terminals. Furthermore, because the source bus is above the gate bus, the effective inductance of the gate loop is reduced due to the relative current directions in the gate and source buses, which improves the switching performance of the transistor.

[0027] Figure 3 The illustration shows the process of manufacturing. Figure 1 A flowchart of method 300 for transistor 100. (The following is about...) Figures 4A to 4F Description method 300, Figures 4A to 4F The various stages of manufacturing are illustrated. The manufacturing process will be described in relation to the metal layer, and descriptions of the manufacturing steps involving the formation of non-conductive structural portions that provide support for the metal layer will be omitted, as the principles described herein are not limited to the mechanisms used to form such non-conductive support layers.

[0028] Manufacturing method 300 includes forming a first semiconductor active region and a second semiconductor active region (operation 301). Figure 4A The illustration shows a top view of fabrication state 400A in which active regions 110A and 110B are formed. In this example, active regions 110A and 110B form part of the conductive portion of the HEMT, wherein two wide-bandgap semiconductor layers are layered such that they form a two-dimensional electron gas (2DEG) therebetween. The 2DEG has high electron mobility, thereby allowing higher power density to be transferred.

[0029] Manufacturing method 300 then includes epitaxially depositing a first metal layer above the semiconductor active region in the epitaxial stack (action 311). For example, a first metal layer may be deposited above the semiconductor active region. Figure 2 The gate metal layer 211. Then the first metal layer is patterned to form finger gate terminals (action 312). For example, Figure 4B The diagram shows Figure 1 The transistor 100 is manufactured in state 400B, wherein the gate terminal 111 is deposited on the active regions 110A and 110B.

[0030] Subsequently, manufacturing method 300 includes epitaxially depositing a second metal layer higher than the first metal layer in the epitaxial stack (action 321). For example, it is possible to deposit... Figure 2 The shielding metal layer 212. Then the second metal layer is patterned to form the shielding metal (action 322). For example, Figure 4C The diagram shows Figure 1The transistor 100 is manufactured in state 400C, which is established by adding a shielding metal 112 over the gate terminal 111. Figure 4B The manufacturing status is above 400B.

[0031] Subsequently, manufacturing method 300 includes epitaxially depositing a third metal layer higher than the second metal layer in the epitaxial stack (action 331). For example, it is possible to deposit... Figure 2 The source and drain metal layers 213. Then, a third metal layer is patterned to form finger-shaped source and drain terminals (action 332). For example, Figure 4D The diagram shows Figure 1 The transistor 100 is manufactured in state 400D, which is established by adding source finger terminals 113 and drain finger terminals 116. Figure 4C The manufacturing process is above 400°C.

[0032] Subsequently, manufacturing method 300 includes epitaxially depositing a fourth metal layer above the third metal layer in the epitaxial stack (action 341). For example, the fourth metal layer may be... Figure 2 Metal layer 214. Then, a fourth metal layer is patterned to form vias to connect the finger source terminals and finger drain terminals to the corresponding buses (Action 342). For example, Figure 4E The diagram shows Figure 1 The transistor 100 is manufactured in state 400E, which is established by adding source finger terminals 113 and drain finger terminals 116. Figure 4D Manufacturing status 400D.

[0033] Subsequently, manufacturing method 300 includes epitaxially depositing a fifth metal layer above the fourth metal layer in the epitaxial stack (action 351). For example, the fifth metal layer may be... Figure 2 The bus metal layer 215. Then the fifth metal layer is patterned to form the source bus and drain bus (action 352). For example, Figure 4F The diagram shows Figure 1 The transistor 100 is manufactured in state 400F, which is established by adding a source bus 115 and a drain bus 117. Figure 4E Manufacturing status 400E and above. In manufacturing status 400F, manufacturing has reached... Figure 1 The state shown in the diagram.

[0034] Figure 1 An example embodiment of a lateral field-effect transistor 100 is illustrated, wherein the gate bus 111C and the source bus 115 are positioned at the midpoint of the y-range of the transistor 100, where the y-range of the transistor refers to the range along the y-axis of all active regions with respect to the fingers in the transistor 100. Therefore, in Figure 1In this embodiment, the y-range of transistor 100 extends from the top of active region 110A (maximum y-position) to the bottom of active region 110B (minimum y-position). This is advantageous because it makes the reduction in debias along each side of the gate bus approximately equal. However, the principle described herein is not limited to the gate bus and source bus being located exactly at the midpoint of the y-axis range of the finger. If the gate bus is located between 40% and 60% of the y-axis range of the finger (e.g., within 10% of the midpoint of the y-axis range of the finger), some smaller (but still helpful) debias level can be achieved. Even if the gate bus is located between 25% and 75% of the y-axis range of the finger, a certain degree of debias can be achieved.

[0035] In addition, although Figure 1 The illustration shows only one gate bus located at the middle y-axis position of the finger, but multiple gate buses and corresponding source buses can exist at various middle positions of the finger. While this increases the complexity of the patterning of the gate terminals and vias, it can further alleviate debiasing because it further reduces the distance the current travels along the finger gate terminals and the source finger gate terminals, and thus further maintains the gate-to-source voltage.

[0036] Figure 5 The illustration shows a top view of such an example lateral field-effect transistor 500. There can be even more active regions, with corresponding gate buses formed between each active region. For example, a first gate bus 511E and a first source bus 515A are formed between active regions 510A and 510B. Furthermore, a second gate bus 511F and a second source bus 515B are formed between active regions 510B and 510C. This can continue for any number of active regions located at different points along the y-axis and any number of corresponding gate and source buses located between such active regions.

[0037] In transistor 500, the first gate bus 511E has a positive finger 511A extending in the positive y-direction and a negative finger 511B extending in the negative y-direction. Similarly, the first source bus 515A is connected to the proximal ends of the negative finger 513B extending in the negative y-direction and the positive finger 513A extending in the positive y-direction. The positive finger gate terminal portion 511A extends parallel to and along the positive finger source portion 513A, and the negative finger gate terminal portion 511B extends parallel to and along the negative source portion 512B.

[0038] Moving to the interface between active regions 510B and 510C, the second gate bus 511F has a positive finger 511C extending in the positive y-direction and a negative finger 511D extending in the negative y-direction. Similarly, the second source bus 515B is connected to the proximal ends of the negative finger 513D extending in the negative y-direction and the positive finger 513C extending in the positive y-direction. The positive finger gate terminal portion 511C extends parallel to and along the positive finger source portion 513C, and is substantially merged with the negative finger gate terminal portion 511B of the first gate bus 511E. The negative finger gate terminal portion 511D extends parallel to and along the negative source portion 512D.

[0039] All gate buses are electrically connected, and each finger gate terminal portion is collinear and electrically connected via the gate bus. The finger source portions are also collinear and connected to the corresponding source bus at the proximal end of the respective finger source portion. The finger source portions can also be interconnected to define a single extended finger source terminal. This structure can continue along the y-range of the transistor's fingers for any number of gate buses.

[0040] Text support section Item 1. A lateral field-effect transistor, comprising: a source bus; a gate bus; a finger drain terminal extending in a lateral plane parallel to the epitaxial plane of an epitaxial stack; a finger source terminal extending in the lateral plane parallel to the finger drain terminal; and a finger gate terminal extending in the lateral plane parallel to the finger drain terminal and the finger source terminal, the finger source terminal comprising: a first finger source portion connected to the source bus near the gate bus at a proximal end of the first finger source portion and extending away from the gate bus in a first direction; and a second finger source portion near the gate of the second finger source portion. The bus is connected to the source bus at its proximal end and extends away from the gate bus in a second direction opposite to the first direction; and the finger gate terminal includes: a first finger gate terminal portion extending along the first finger source portion, the first finger gate terminal portion being connected to the gate bus at its proximal end and extending away from the gate bus in the first direction; and a second finger gate terminal portion extending along the second finger source portion, the second finger gate terminal portion being connected to the gate bus at its proximal end and extending away from the gate bus in the second direction opposite to the first direction.

[0041] Item 2. In the lateral field-effect transistor of Item 1, the finger gate terminal is closer to the finger source terminal than the finger drain terminal.

[0042] Item 3. The lateral field-effect transistor of Item 1, with the gate bus extending across the cross portion of the finger drain terminals.

[0043] Item 4. The lateral field-effect transistor of Item 3 further includes a shielding layer disposed in a direction perpendicular to the epitaxial plane between the intersection of the gate bus and the finger drain terminals.

[0044] Item 5. The lateral field-effect transistor of Item 1 further includes: a drain bus connected to one end of a finger drain terminal.

[0045] Item 6. The lateral field-effect transistor of Item 5, wherein the finger gate terminal and the gate bus are formed by a first metal layer, the finger drain terminal and the finger source terminal are formed by a second metal layer, and the source bus and the drain bus are formed by a third metal layer.

[0046] Item 7. Lateral field-effect transistors of Item 1, which are high electron mobility transistors (HEMTs).

[0047] Item 8. The lateral field-effect transistor of Item 7, HEMT is gallium nitride (GaN) HEMT.

[0048] Item 9. The lateral field-effect transistor of Item 8, with the source bus on top of the gate bus.

[0049] Item 10. The lateral field-effect transistor of Item 8, wherein the first metal layer, the second metal layer, and the third metal layer are formed in this order in an epitaxial stack.

[0050] Item 11. The lateral field-effect transistor of Item 1, wherein the first finger source portion and the second finger source portion are collinear.

[0051] Item 12. The lateral field-effect transistor of Item 11, wherein the finger source terminal is a single finger such that the first finger source portion and the second finger source portion are connected.

[0052] Item 13. The lateral field-effect transistor of Item 12, wherein the first finger gate terminal portion and the second finger gate terminal portion are collinear.

[0053] Item 14. The lateral field-effect transistor of Item 1, wherein the gate bus is a first gate bus, the lateral field-effect transistor further includes: a second source bus; and the second gate bus, the finger source terminals further include: a third finger source portion connected to the second source bus at a proximal end of the third finger source portion near the second gate bus, and extending away from the second gate bus in a first direction; and a fourth finger source portion connected to the second source bus at a proximal end of the fourth finger source portion near the second gate bus, and extending away from the second gate bus in a second direction; and the finger gate terminals further include: a third finger gate terminal portion extending along the third finger source portion, the third finger gate terminal portion connected to the second gate bus at a proximal end of the third finger gate terminal portion, and extending away from the second gate bus in a first direction; and a fourth finger gate terminal portion extending along the fourth finger source portion, the fourth finger gate terminal portion connected to the second gate bus at a proximal end of the fourth finger gate terminal portion, and extending away from the second gate bus in a second direction.

[0054] Item 15. The lateral field-effect transistor of Item 14, wherein the first gate bus and the second gate bus are electrically connected.

[0055] Item 16. The lateral field-effect transistor of Item 14, wherein the finger source terminal is a single finger such that the first finger source portion, the second finger source portion, the third finger source portion, and the fourth finger source portion are connected.

[0056] Item 17. The lateral field-effect transistor of Item 14, where the finger drain terminal is a single finger.

[0057] Item 18. The lateral field-effect transistor of Item 14, wherein the finger gate terminal is a single finger, such that the first finger gate terminal portion, the second finger gate terminal portion, the third finger gate terminal portion, and the fourth finger gate terminal portion are collinear.

[0058] Item 19. The lateral field-effect transistor of Item 18, wherein the first finger gate terminal portion, the second finger gate terminal portion, the third finger gate terminal portion, and the fourth finger gate terminal portion are also connected.

[0059] Item 20. A method for manufacturing a lateral field-effect transistor by forming an epitaxial stack, the method comprising: forming a first semiconductor active region and a second semiconductor active region; epitaxially depositing a first metal layer above the first semiconductor active region and the second semiconductor active region in the epitaxial stack; patterning the first metal layer to form a finger gate terminal, the finger gate terminal including a gate bus, a first finger gate terminal portion and a second finger gate terminal portion, the first finger gate terminal portion extending from the gate bus in a first direction above the first semiconductor active region parallel to an epitaxial plane of the epitaxial stack, and the second finger gate terminal portion extending from the gate bus in a second direction opposite to the first direction above the second semiconductor active region parallel to an epitaxial plane of the epitaxial stack; epitaxially depositing a second metal layer above the first metal layer in the epitaxial stack; patterning the second metal layer to form a finger drain terminal and a finger source terminal, the finger source terminal including a first finger drain terminal extending along the first finger gate terminal portion in a first direction. The method includes a finger source portion and a second finger source portion extending along a second finger gate terminal portion in a second direction; a finger drain terminal includes: a first finger drain portion and a second finger drain portion, the first finger drain portion extending along the first finger gate terminal portion in a first direction, and the second finger drain portion extending along the second finger gate terminal portion in a second direction; epitaxially depositing a third metal layer above a second metal layer in an epitaxial stack; and patterning the third metal layer to form a source bus and a drain bus, the source bus being above the proximal ends of the first finger source portion and the second finger source portion, and the drain bus being above the proximal ends of the first finger drain portion and the second finger drain portion, wherein the manufacturing method further includes forming a via extending through a portion of the epitaxial stack such that the source bus is electrically connected to the proximal ends of the first finger source portion and the second finger source portion, and the drain bus is electrically connected to an end of the finger drain terminal.

[0060] Although the subject matter has been described in language specific to structural features and / or methodological actions, it is understood that the subject matter defined in the appended claims is not necessarily limited to the features or actions described above, or the order of the actions described above. Rather, the described features and actions are disclosed as exemplary forms of implementing the claims.

[0061] This disclosure may be embodied in other specific forms without departing from its essential characteristics. The described embodiments are to be considered in all respects as illustrative rather than restrictive. All modifications falling within the meaning and scope of the equivalents of the claims are covered within their scope.

[0062] When elements are introduced in the appended claims, the quantifiers “a,” “an,” the pronouns “the,” and “the” are intended to mean the presence of one or more elements. The terms “comprising,” “including,” and “having” are intended to be inclusive and mean that additional elements may be present in addition to those listed.

Claims

1. A lateral field-effect transistor, comprising: Source bus; Gate bus; The finger-shaped drain tip extends in a transverse plane parallel to the epitaxial plane of the epitaxial stack; The finger-shaped source terminal extends parallel to the finger-shaped drain terminal in the transverse plane; as well as The finger gate terminal also extends parallel to the finger drain and finger source terminals in the lateral plane. Finger-shaped source extremes include: A first finger-shaped source portion, which is connected to the source bus at its proximal end near the gate bus and extends away from the gate bus in a first direction; and The second finger source portion is connected to the source bus near the proximal end of the second finger source portion close to the gate bus, and extends away from the gate bus in a second direction opposite to the first direction; and The finger gate terminals include: A first finger gate terminal portion extends along a first finger source portion, the first finger gate terminal portion is connected to the gate bus at its proximal end and extends away from the gate bus in a first direction; and The second finger gate terminal portion extends along the second finger source portion, the second finger gate terminal portion is connected to the gate bus at the proximal end of the second finger gate terminal portion, and extends away from the gate bus in a second direction opposite to the first direction.

2. The lateral field-effect transistor as claimed in claim 1, wherein the finger gate terminal is closer to the finger source terminal than the finger drain terminal.

3. The lateral field-effect transistor of claim 1, wherein the gate bus extends across the intersection of the finger drain terminals.

4. The lateral field-effect transistor of claim 3 further includes a shielding layer disposed in a direction perpendicular to the epitaxial plane between the intersection of the gate bus and the finger drain terminal.

5. The lateral field-effect transistor as claimed in claim 1, further comprising: Drain bus, which is connected to one or approximately one end of the finger drain terminal.

6. The lateral field-effect transistor of claim 5, wherein the finger gate terminal and the gate bus are formed by a first metal layer, the finger drain terminal and the finger source terminal are formed by a second metal layer, and the source bus and the drain bus are formed by a third metal layer.

7. The lateral field-effect transistor of claim 1, wherein the lateral field-effect transistor is a high electron mobility transistor (HEMT).

8. The lateral field-effect transistor as described in claim 7, wherein the HEMT is a gallium nitride (GaN) HEMT.

9. The lateral field-effect transistor as described in claim 8, wherein the source bus is above the gate bus.

10. The lateral field-effect transistor of claim 8, wherein the first metal layer, the second metal layer, and the third metal layer are formed in this order in an epitaxial stack.

11. The lateral field-effect transistor of claim 1, wherein the first finger source portion and the second finger source portion are collinear.

12. The lateral field-effect transistor of claim 11, wherein the finger source terminal is a single finger such that the first finger source portion and the second finger source portion are connected.

13. The lateral field-effect transistor of claim 12, wherein the first finger gate terminal portion and the second finger gate terminal portion are collinear.

14. The lateral field-effect transistor of claim 1, wherein the gate bus is a first gate bus, and the lateral field-effect transistor further comprises: Second source bus; as well as Second gate bus, Finger-shaped source extremes also include: The third finger-shaped source portion is connected to the second source bus at its proximal end near the second gate bus and extends away from the second gate bus in a first direction; and The fourth finger source portion is connected to the second source bus at its proximal end near the second gate bus and extends away from the second gate bus in a second direction; and The finger gate terminal also includes: The third finger gate terminal portion extends along the third finger source portion, the third finger gate terminal portion is connected to the second gate bus at its proximal end, and extends away from the second gate bus in a first direction; and The fourth finger gate terminal portion extends along the fourth finger source portion, the fourth finger gate terminal portion is connected to the second gate bus at its proximal end, and extends away from the second gate bus in a second direction.

15. The lateral field-effect transistor of claim 14, wherein the first gate bus and the second gate bus are electrically connected.

16. The lateral field-effect transistor of claim 14, wherein the finger source terminal is a single finger such that the first finger source portion, the second finger source portion, the third finger source portion, and the fourth finger source portion are connected.

17. The lateral field-effect transistor of claim 14, wherein the finger drain terminal is a single finger.

18. The lateral field-effect transistor of claim 14, wherein the finger gate terminal is a single finger such that the first finger gate terminal portion, the second finger gate terminal portion, the third finger gate terminal portion, and the fourth finger gate terminal portion are collinear.

19. The lateral field-effect transistor of claim 18, wherein the first finger gate terminal portion, the second finger gate terminal portion, the third finger gate terminal portion, and the fourth finger gate terminal portion are also connected.

20. A method for manufacturing a lateral field-effect transistor by forming an epitaxial stack, the method comprising: Forming the first semiconductor active region and the second semiconductor active region; In the epitaxial stack, a first metal layer is epitaxially deposited above the first semiconductor active region and the second semiconductor active region; A first metal layer is patterned to form a finger gate terminal. The finger gate terminal includes a gate bus, a first finger gate terminal portion, and a second finger gate terminal portion. The first finger gate terminal portion extends from the gate bus in a first direction above the first semiconductor active region, parallel to the epitaxial plane of the epitaxial stack. The second finger gate terminal portion extends from the gate bus in a second direction opposite to the first direction above the second semiconductor active region, parallel to the epitaxial plane of the epitaxial stack. In epitaxial stacking, a second metal layer is epitaxially deposited above the first metal layer; A second metal layer is patterned to form a finger drain terminal and a finger source terminal, the finger source terminal including a first finger source portion extending along a first finger gate terminal portion in a first direction, and a second finger source portion extending along a second finger gate terminal portion in a second direction; The finger drain terminal includes: a first finger drain portion and a second finger drain portion, the first finger drain portion extending along the first finger gate terminal portion in a first direction, and the second finger drain portion extending along the second finger gate terminal portion in a second direction. In the epitaxial stack, a third metal layer is epitaxially deposited above the second metal layer; and A third metal layer is patterned to form source and drain buses. The source buses are located on the proximal ends of the first and second finger source portions, and the drain buses are located on the proximal ends of the first and second finger drain portions. The manufacturing method further includes forming a via extending through a portion of the epitaxial stack, such that a source bus is electrically connected to a proximal end of a first finger source portion and a proximal end of a second finger source portion, and a drain bus is electrically connected to an end of a finger drain terminal.

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