Display device and manufacturing method thereof, and electronic device including the same

Abstract

A display device, a manufacturing method thereof, and an electronic device including the same are provided. The display device includes a base substrate, a barrier layer formed on the base substrate, a lower back metal pattern penetrating the barrier layer and including a protrusion or a recess, a lower transistor stacked on the lower back metal pattern and including a lower active layer and a lower gate electrode stacked on the lower active layer, and a light emitting element electrically connected with the lower transistor.

Description

Technical Field

[0001] Embodiments of this application relate to a display device, a method for manufacturing the same, and an electronic device including the display device. More specifically, it relates to a display device including electrodes and transistors, a method for manufacturing the same, and an electronic device including the display device. Background Technology

[0002] In display devices such as organic light-emitting diode (OLED) display devices and liquid crystal display devices (LCD), for example, a display substrate including thin film transistors (TFT) and various wirings can be provided, and a display structure including electrodes and a light-emitting layer can be formed on the display substrate.

[0003] The electrodes may include wiring and contact electrodes that electrically connect the transistor structure and the display structure. As the number of electrodes stacked increases, step differences may occur within the display structure, potentially leading to defects caused by these step differences. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a display device with improved structural reliability and electrical stability.

[0005] The technical problem to be solved by the present invention is to provide a method for manufacturing a display device with improved structural reliability and electrical stability.

[0006] One technical problem to be solved by the present invention is to provide an electronic device including a display device having improved structural reliability and electrical stability.

[0007] The display device may include: a base substrate; a barrier layer formed on the base substrate; a lower back metal pattern penetrating the barrier layer and including protrusions or grooves; a lower transistor stacked on the lower back metal pattern and including a lower active layer and a lower gate electrode stacked on the lower active layer; and a light-emitting element electrically connected to the lower transistor.

[0008] In several embodiments, the display device may further include: a lower contact electrode electrically connected to the lower active layer; and a lower back contact member electrically connected to the lower back metal pattern. The lower back contact member and the lower contact electrode may be connected to each other.

[0009] In several embodiments, the display device may further include: a lower gate contact electrically connected to the lower gate electrode; and a lower back contact electrically connected to the lower back metal pattern. The lower back contact and the lower gate contact may be connected to each other.

[0010] In several embodiments, the base substrate may have a display area and a peripheral circuit area. The lower back metal pattern may include: a first lower back metal pattern disposed in the display area of ​​the base substrate; and a second lower back metal pattern disposed in the peripheral circuit area of ​​the base substrate. Each of the first lower back metal pattern and the second lower back metal pattern may include the protrusion or the groove.

[0011] In several embodiments, the lower transistor may include: a first lower transistor disposed in the display region of the base substrate; and a second lower transistor disposed in the peripheral circuit region of the base substrate.

[0012] In several embodiments, the display device may further include: a first lower back contact for electrically connecting the first lower transistor to the first lower back metal pattern; and a second lower back contact for electrically connecting the second lower transistor to the second lower back metal pattern.

[0013] In several embodiments, the display device may further include: a storage capacitor stacked on the first lower transistor in the display region of the base substrate.

[0014] In several embodiments, the display device may further include: a first upper back metal pattern disposed between the first lower transistor and the storage capacitor.

[0015] In several embodiments, the display device may further include: a second upper transistor stacked on the second lower transistor in the peripheral circuit region of the base substrate.

[0016] In several embodiments, the display device may further include: contact electrodes that electrically connect the second upper transistor and the second lower transistor to each other.

[0017] In several embodiments, the display device may further include: a second upper back metal pattern disposed between the second lower transistor and the second upper transistor.

[0018] In several embodiments, the bottom surface of the lower rear metal pattern may contact the base substrate.

[0019] In several embodiments, the lower back metal pattern may have the protrusion, the thickness of which may be less than the thickness of the peripheral portion of the lower back metal pattern excluding the protrusion.

[0020] In several embodiments, the lower back metal pattern may have the groove, the depth of which may be less than 1 / 2 of the overall thickness of the lower back metal pattern.

[0021] In several embodiments, the upper surface of the periphery of the protrusion of the lower back metal pattern or the upper surface of the periphery of the groove may be located on the same plane as the upper surface of the barrier layer.

[0022] In a method for manufacturing a display device, a barrier layer can be formed on a base substrate. A trench penetrating the barrier layer can be formed by locally etching the barrier layer. A lower back metal layer and a sacrificial layer filling the trench can be sequentially formed on the base substrate. The sacrificial layer and the lower back metal layer can be planarized using an etch-back process to form a lower back metal pattern within the trench. A lower transistor can be formed on the lower back metal pattern. A light-emitting element electrically connected to the lower transistor can be formed.

[0023] In several embodiments, the etching process can be performed at a rate greater than the etching rate of the sacrificial layer on the lower back metal layer. A protrusion may be formed on the upper part of the lower back metal pattern.

[0024] In several embodiments, the etching process can be performed at a lower etching rate for the lower back metal layer than for the sacrificial layer. A groove may be formed above the lower back metal pattern.

[0025] An electronic device may include a display device, a memory, and a processor that controls the operation of the display device by executing data included in the memory. The display device may be the display device described above.

[0026] In several embodiments, the electronic device may include virtual reality or augmented reality glasses, a smartphone, a tablet PC, a laptop computer, a television (TV), a desktop display, smart glasses, a head-mounted display, a smartwatch, or a vehicle display.

[0027] According to an embodiment of the present invention, by embedding the lower back metal pattern in the barrier layer, the step difference of the thin-film transistor array substrate can be suppressed from the bottom. Therefore, it is possible to prevent the active layer or electrodes from disconnecting or short-circuiting due to the step difference, and to enhance the structural stability of the display device.

[0028] According to an exemplary embodiment, the lower back metal pattern may include protrusions or grooves, which can more effectively achieve source-sync characteristics or prevent step differences. Attached Figure Description

[0029] Figure 1 This is a schematic plan view illustrating a display device according to an exemplary embodiment.

[0030] Figure 2 This is a schematic cross-sectional view illustrating a display device according to an exemplary embodiment.

[0031] Figure 3 This is a partially enlarged cross-sectional view illustrating the shape of the metal pattern on the lower back of the display device according to an exemplary embodiment.

[0032] Figures 4 to 9 This is a schematic cross-sectional view illustrating a method of manufacturing a display device according to an exemplary embodiment.

[0033] Figure 10 This is a schematic cross-sectional view illustrating a display device according to an exemplary embodiment.

[0034] Figure 11 This is a partially enlarged cross-sectional view illustrating the shape of the metal pattern on the lower back of the display device according to an exemplary embodiment.

[0035] Figures 12 to 15 This is a schematic cross-sectional view illustrating a method of manufacturing a display device according to an exemplary embodiment.

[0036] Figure 16 This is an exploded perspective view illustrating an electronic device according to an exemplary embodiment.

[0037] Figure 17 This is a block diagram of an electronic device according to one embodiment.

[0038] Figure 18 This is a schematic diagram of an electronic device according to various embodiments.

[0039] Explanation of reference numerals in the attached figures ACT1_a: First lower active layer ACT2_a: Second lower active layer ACT2_b: Second upper active layer BML1_a: First lower part of the back metal pattern BML2_a: Second lower part of the back metal pattern BML1_b: First upper back metal pattern BML2_b: Second upper back metal pattern BC1_a: First lower back contact component BC2_a: Second lower back contact component BC2_b: Second upper back contact element CNT1_a: First lower contact electrode CNT2_a: Second lower contact electrode CNT1_b: First upper contact electrode CNT2_b: Second upper contact electrode Cst: Storage capacitor CR1: First contact area CR2: Second contact area TR1_a: First lower transistor TR2_a: Second lower transistor TR2_b: Second upper transistor PE: Pixel Electrode UE: Upper electrode 100: Base substrate 105: Barrier Layer 115: First Buffer Layer 140: Second Buffer Layer 120: First interlayer insulation layer 130: Second interlayer insulation layer 150: Third interlayer insulation layer Detailed Implementation

[0040] Hereinafter, embodiments of the present invention will be described in more detail with reference to the accompanying drawings. The same reference numerals will be used for the same constituent elements in the drawings, and repeated descriptions of the same constituent elements will be omitted. The embodiments disclosed in the accompanying drawings are exemplary and should be understood to include all modifications, equivalents, and even substitutions encompassed within the concept and scope of the present invention.

[0041] The terms “above,” “connected,” “combined,” etc., used in this specification include not only cases of direct arrangement / connection / combination, but also cases where other constituent elements are arranged in between.

[0042] Terms such as “first,” “second,” “below,” “lower side,” “above,” and “upper side” are used as relative concepts to distinguish different components or positions, and do not specify absolute positions or orders.

[0043] Figure 1 This is a schematic plan view illustrating a display device according to an exemplary embodiment.

[0044] exist Figure 1In the middle, the first direction and the second direction can refer to the base substrate 100 (refer to...). Figure 2 The upper surface of the display device or the display surface of the display device are two directions that are parallel and perpendicular to each other. For example, the first direction may correspond to the X direction (row direction) of the display device, and the second direction may correspond to the Y direction (column direction) of the display device.

[0045] The third direction can be perpendicular to the first and second directions. The third direction can be equivalent to the Z-direction (thickness direction) of the display device.

[0046] Reference Figure 1 Multiple pixels PX11 to PXnm can be arranged in the display area DA of the display device or the base substrate 100.

[0047] According to an exemplary embodiment, pixel circuitry can be arranged on a base substrate 100. The pixel circuitry includes scan lines (or gate lines) SL1 to SLn forming first to nth rows and data lines DL1 to DLm forming first to mth columns. Each of pixels PX11 to PXnm can be connected to a corresponding n-row scan line from the plurality of scan lines SL1 to SLn and a corresponding m-column data line from the plurality of data lines DL1 to DLm.

[0048] For example, scan lines SL1 to SLn can be connected to the gate electrode included in the thin-film transistor. Data lines DL1 to DLm can be connected, for example, to a contact electrode (e.g., a first contact electrode or a third contact electrode) that serves as the source electrode.

[0049] Each of pixels PX11 to PXnm may include pixel circuitry comprising transistors as described below, as well as a light-emitting element. Although not explicitly stated... Figure 1 The details are shown in the diagram, but the pixel circuit may also include wiring such as power lines and ground lines.

[0050] exist Figure 1 Although it is shown that data lines DL1 to DLm extend along the second direction and scan lines SL1 to SLn extend along the first direction, it is not necessarily limited to this.

[0051] The peripheral circuitry region (PC) may be included in the non-display area (NDA) of the display device. For example, the peripheral circuitry region (PC) may include a gate driving circuit. The gate driving circuit may be integrated into the display device using oxide semiconductor gate (OSG), amorphous silicon gate (ASG), or polysilicon gate (PSG) technology.

[0052] The peripheral circuit area PC may further include a data driver, a gate driver, a light-emitting driver, a power supply voltage generator, a timing controller, etc.

[0053] The display device may also include a printed circuit board 200. The pads 190 of the pixel circuitry (e.g., data lines) may be assembled on one side of the non-display area NDA.

[0054] The printed circuit board 200 can be electrically connected to the pixel circuit via the pad 190. For example, the printed circuit board 200 can be electrically connected to the pad 190 by a thermoforming process utilizing a conductive interposer structure such as anisotropic conductive film (ACF).

[0055] The pad 190 and integrated circuits (ICs), such as data driver circuits, can be electrically connected via the printed circuit board 200. In several embodiments, the integrated circuit (IC) chip can be mounted on the printed circuit board 200 in a chip-on-film (COF) configuration.

[0056] Figure 2 This is a schematic cross-sectional view illustrating a display device according to an exemplary embodiment. For ease of illustration, in Figure 2 The diagram shows an insulating layer (barrier layer, buffer layer, interlayer insulation layer, etc.) with a flat upper surface, but the insulating layer may have a stepped difference along the contour of the lower structure covered by the insulating layer. According to an exemplary embodiment, the stepped difference can be reduced by the structure / shape of the lower back contact.

[0057] Reference Figure 2 As described above, the display device may include a display area DA and a peripheral circuit area PC. Accordingly, the base substrate 100 may also include a display area DA and a peripheral circuit area PC. For ease of explanation, in Figure 2 The image only shows the transistors and light-emitting elements included in one pixel within the display area DA.

[0058] A first lower transistor TR1_a and a light-emitting element electrically connected to the first lower transistor TR1_a can be stacked on the display area DA of the base substrate 100. The light-emitting element may include a pixel electrode PE, a light-emitting portion EL, and a counter electrode CE.

[0059] In several embodiments, the storage capacitor Cst may be stacked on the first lower transistor TR1_a.

[0060] As described above, transistors can be formed on the peripheral circuit region PC of the base substrate 100 using a gate driver integration process.

[0061] According to an exemplary embodiment, a second lower transistor TR2_a and a second upper transistor TR2_b can be sequentially stacked from the upper surface of the base substrate 100 in the peripheral circuit region PC along a vertical direction or a thickness direction (e.g., the third direction). The second lower transistor TR2_a and the second upper transistor TR2_b may overlap each other along the vertical direction.

[0062] As described above, by stacking multiple transistors vertically on the peripheral circuit region PC, the size of the peripheral circuit region PC can be reduced. Therefore, for example, the size of the bezel area of ​​the display device can be reduced while the size of the display area DA can be relatively increased.

[0063] The base substrate 100 can be configured as a support substrate or back-plane substrate for a display device or display panel. The base substrate 100 can be a glass substrate or a plastic substrate.

[0064] In several embodiments, the base substrate 100 may include a polymeric material having transparency and a predetermined degree of flexibility. For example, the base substrate 100 may include polymeric materials such as polyimide, polysiloxane, epoxy resin, acrylic resin, and polyester. In one embodiment, the base substrate 100 may include polyimide.

[0065] In several embodiments, a glass substrate may be used as the base substrate 100.

[0066] A barrier layer 105 may be formed on the upper surface of the base substrate 100. The barrier layer 105 can block moisture that permeates through the base substrate 100 and can also prevent the diffusion of impurities between the base substrate 100 and the structures formed on the base substrate 100. The barrier layer 105 can completely cover the upper surface of the base substrate 100.

[0067] For example, barrier layer 105 may include inorganic insulating materials such as silicon oxide, silicon nitride, or silicon nitride. These may be used alone or in combination of two or more. In some embodiments, barrier layer 105 may have a stacked structure including a silicon oxide film and a silicon nitride film. In some embodiments, barrier layer 105 may also include an organic layer and may have a multilayer structure of organic and inorganic layers.

[0068] According to an exemplary embodiment, a lower back metal pattern BML1_a and BML2_a that penetrates the barrier layer 105 can be formed on the base substrate 100. The lower back metal patterns BML1_a and BML2_a may include a first lower back metal pattern BML1_a formed on the base substrate 100 of the display area DA and a second lower back metal pattern BML2_a formed on the base substrate 100 of the peripheral circuit area PC.

[0069] The lower back metal patterns BML1_a and BML2_a may include metals such as silver (Ag), tungsten (W), molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), chromium (Cr), nickel (Ni), tantalum (Ta), platinum (Pt), palladium (Pd), or alloys containing at least one of them.

[0070] The lower back metal patterns BML1_a and BML2_a can be configured as blocking layers against external light from the first lower transistor TR1_a and the second lower transistor TR2_a. The lower back metal patterns BML1_a and BML2_a can also be configured as bias electrodes.

[0071] In one embodiment, the lower back metal patterns BML1_a and BML2_a can be configured as back gate or source-sync electrodes connected to the first lower transistor TR1_a or the second lower transistor TR2_a. In another embodiment, the lower back metal patterns BML1_a and BML2_a can also be configured as floating electrodes or island electrodes separate from the first lower transistor TR1_a or the second lower transistor TR2_a.

[0072] The lower back metal patterns BML1_a and BML2_a can be electrode patterns that penetrate the barrier layer 105. According to an exemplary embodiment, the lower back metal patterns BML1_a and BML2_a can completely penetrate the barrier layer 105. In several embodiments, the lower back metal patterns BML1_a and BML2_a can penetrate the barrier layer 105 and contact the upper surface of the base substrate 100.

[0073] according to Figure 2 In the illustrated embodiment, the lower back metal patterns BML1_a and BML2_a may include protrusions PS. The shapes of the lower back metal patterns BML1_a and BML2_a including the protrusions PS will be described with reference to... Figure 3 A more detailed explanation will follow.

[0074] A first buffer layer 115 can be formed on the barrier layer 105 to cover the lower back metal patterns BML1_a and BML2_a. The first buffer layer 115 further prevents impurities from penetrating into the lower active layers ACT1_a and ACT2_a of the lower transistors TR1_a and TR2_a. The first buffer layer 115 may include inorganic insulating materials such as silicon nitride, silicon oxide, and / or silicon nitride. The first buffer layer 115 may have a single-layer structure or a multi-layer structure including the aforementioned inorganic insulating materials.

[0075] A first lower transistor TR1_a and a second lower transistor TR2_a may be disposed on the first buffer layer 115. The first lower transistor TR1_a may include a first lower active layer ACT1_a, a first lower gate insulating layer GI1_a, and a first lower gate electrode GE1_a. The second lower transistor TR2_a may include a second lower active layer ACT2_a, a second lower gate insulating layer GI2_a, and a second lower gate electrode GE2_a.

[0076] The first lower active layer ACT1_a and the second lower active layer ACT2_a may be formed on the first buffer layer 115. The first lower active layer ACT1_a and the second lower active layer ACT2_a may include silicon compound or oxide semiconductors such as polycrystalline silicon or amorphous silicon. According to an exemplary embodiment, the first lower active layer ACT1_a and the second lower active layer ACT2_a may also include oxide semiconductors such as indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), or ITZO.

[0077] For example, an oxide semiconductor layer can be formed on the first buffer layer 115 by a deposition process such as sputtering. The oxide semiconductor layer is patterned by a photolithography process, thereby forming a first lower active layer ACT1_a and a second lower active layer ACT2_a on the display area DA and the peripheral circuit area PC, respectively.

[0078] A first contact region CR1 and a second contact region CR2 can be formed on one side and the other side of each of the first lower active layer ACT1_a and the second lower active layer ACT2_a, respectively. The first contact region CR1 and the second contact region CR2 can be respectively set as the source region and the drain region. The portion of the lower active layer ACT1_a and ACT2_a between the first contact region CR1 and the second contact region CR2 can be defined as the channel region.

[0079] The first lower gate insulating layer GI1_a and the second lower gate insulating layer GI2_a can be respectively disposed on the channel regions of the first lower active layer ACT1_a and the second lower active layer ACT2_a. A first lower gate electrode GE1_a and a second lower gate electrode GE2_a can be respectively disposed on the first lower gate insulating layer GI1_a and the second lower gate insulating layer GI2_a.

[0080] In several embodiments, the first lower gate insulating layer GI1_a and the second lower gate insulating layer GI2_a may be formed in a pattern that selectively covers the channel region.

[0081] According to an exemplary embodiment, a lower gate insulating layer can be formed on the first buffer layer 115 using a deposition process such as chemical vapor deposition (CVD) with an inorganic insulating material including silicon oxide, silicon nitride, silicon nitride, etc. The lower gate insulating layer can also be formed with an inorganic insulating material including aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, etc.

[0082] The lower gate electrode layer can be formed on the lower gate insulating layer using a deposition process such as sputtering, incorporating the aforementioned metal or alloy. The lower gate electrode layer can be patterned using photolithography to form the first lower gate electrode GE1_a and the second lower gate electrode GE2_a.

[0083] Subsequently, the lower gate insulating layer can be patterned using an etching process that uses the first lower gate electrode GE1_a and the second lower gate electrode GE2_a as etching masks. Through this etching process, the first lower gate insulating layer GI1_a can be formed between the channel region of the first lower active layer ACT1_a and the first lower gate electrode GE1_a, and the second lower gate insulating layer GI2_a can be formed between the channel region of the second lower active layer ACT2_a and the second lower gate electrode GE2_a.

[0084] In several embodiments, the lower gate insulating layer may be included as a common gate insulating layer for a plurality of transistors included in the display area DA. The lower gate insulating layer may also be included as the gate insulating layer for a second lower transistor TR2_a. In this case, the etching process described above for the lower gate insulating layer may be omitted.

[0085] The first interlayer insulating layer 120 can be formed on the first buffer layer 115 to cover the lower transistors TR1_a and TR2_a. The first interlayer insulating layer 120 can be formed by a deposition process such as CVD, comprising the aforementioned inorganic insulating material.

[0086] In several embodiments, the etching process of the lower gate insulating layer may induce vacancy sites caused by etching damage on the sides of the lower active layers ACT1_a and ACT2_a. As the first interlayer insulating layer 120 is formed, hydrogen included in the first interlayer insulating layer 120 migrates to the sides of the lower active layers ACT1_a and ACT2_a, thereby forming contact regions CR1 and CR2 with increased conductivity compared to the channel region.

[0087] Lower contact electrodes CNT1_a and CNT2_a may be formed on the first interlayer insulating layer 120. The lower contact electrodes CNT1_a and CNT2_a may penetrate the first interlayer insulating layer 120 and contact or be electrically connected to the contact areas CR1 and CR2 of the lower active layers ACT1_a and ACT2_a.

[0088] The first lower contact electrode CNT1_a can be formed on the first interlayer insulating layer 120 portion of the display area DA, and can be in contact or electrically connected to the first contact area CR1 and / or the second contact area CR2 of the first lower active layer ACT1_a, respectively.

[0089] The second lower contact electrode CNT2_a can be formed on a portion of the first interlayer insulating layer 120 of the peripheral circuit region PC, and can be in contact or electrically connected to the first contact region CR1 and / or the second contact region CR2 of the second lower active layer ACT2_a.

[0090] In several embodiments, the lower gate contacts GC1 and GC2_a may be formed on the first interlayer insulating layer 120 and contact or be electrically connected to the lower gate electrodes GE1_a and GE2_a.

[0091] The first lower gate contact GC1 can penetrate the first interlayer insulating layer 120 and make contact or be electrically connected to the upper surface of the first lower gate electrode GE1_a of the first lower transistor TR1_a.

[0092] The second lower gate contact GC2_a can penetrate the first interlayer insulating layer 120 and make contact or be electrically connected to the upper surface of the second lower gate electrode GE2_a of the second lower transistor TR2_a.

[0093] In several embodiments, lower back contact members may also be formed that are in contact with or electrically connected to the lower back metal patterns BML1_a and BML2_a. The lower back contact members may include a first lower back contact member BC1_a and a second lower back contact member BC2_a formed in the display area DA and the peripheral circuit area PC, respectively.

[0094] The first lower back contact BC1_a can penetrate the first interlayer insulation layer 120 and the first buffer layer 115 and make contact or electrical connection with the first lower back metal pattern BML1_a. The second lower back contact BC2_a can penetrate the first interlayer insulation layer 120 and the first buffer layer 115 and make contact or electrical connection with the second lower back metal pattern BML2_a.

[0095] According to an exemplary embodiment, the first lower back contact BC1_a can be connected to the first lower contact electrode CNT1_a. In one embodiment, the first lower back contact BC1_a can be an integral component connected to the first lower contact electrode CNT1_a on the upper surface of the first interlayer insulating layer 120. Accordingly, for example, the first lower back metal pattern BML1_a can be configured as a source-sync electrode.

[0096] According to an exemplary embodiment, the second lower back contact BC2_a can be connected to the second lower gate contact GC2_a. In one embodiment, the second lower back contact BC2_a can be integrally connected to the second lower gate contact GC2_a on the upper surface of the first interlayer insulating layer 120. Accordingly, the second lower back metal pattern BML2_a can, for example, be configured as a lower back gate electrode. For example, the second lower transistor TR2_a can have a dual-gate structure via the second lower back metal pattern BML2_a.

[0097] For example, a lower contact hole can be formed by etching the first interlayer insulating layer 120 to expose the upper surfaces of the contact regions CR1, CR2 and the lower gate electrodes GE1_a, GE2_a. The first buffer layer 115 can be further etched to form a lower back contact hole together to expose the upper surfaces of the lower back metal patterns BML1_a, BML2_a.

[0098] The lower contact electrode layer comprising the aforementioned metal or alloy can be formed on the first interlayer insulating layer 120 by a deposition process such as sputtering to fill the lower contact holes and the lower back contact holes. The lower contact electrodes CNT1_a, CNT2_a, lower gate contacts GC1, GC2_a, and lower back contacts BC1_a, BC2_a can be formed by etching the lower contact electrode layer.

[0099] In some embodiments, the lower contact electrode layer may be formed as a multilayer structure comprising multiple metal layers (e.g., Ti layer / Al layer / Ti layer).

[0100] A second interlayer insulating layer 130 may be formed on the first interlayer insulating layer 120, covering the lower contact electrodes CNT1_a, CNT2_a, the lower gate contacts GC1, GC2_a, and the lower back contact contacts BC1_a, BC2_a. The second interlayer insulating layer 130 may be formed by a deposition process such as CVD, comprising the aforementioned inorganic insulating material.

[0101] An upper back metal pattern can be formed on the second interlayer insulating layer 130. For example, a first upper back metal pattern BML1_b can be formed on a portion of the second interlayer insulating layer 130 of the display area DA. A second upper back metal pattern BML2_b can be formed on a portion of the second interlayer insulating layer 130 of the peripheral circuit area PC.

[0102] For example, an upper back metal layer comprising the aforementioned metal or alloy can be formed on the second interlayer insulating layer 130 using a deposition process such as sputtering. The upper back metal layer can be etched using a photolithography process to form a first upper back metal pattern BML1_b and a second upper back metal pattern BML2_b.

[0103] The first upper back metal pattern BML1_b and the second upper back metal pattern BML2_b can be respectively configured as a light-shielding layer, back gate electrode, source-sync electrode, etc. for the upper structure including the storage capacitor Cst, the second upper transistor TR2_b, etc.

[0104] A second buffer layer 140 covering the first upper back metal pattern BML1_b and the second upper back metal pattern BML2_b can be formed on the second interlayer insulating layer 130. The second buffer layer 140 can be formed by a deposition process such as CVD, incorporating the aforementioned inorganic insulating material.

[0105] For example, the second buffer layer 140 can be used to block or reduce the penetration of impurities into the second upper active layer ACT2_b of the second upper transistor TR2_b.

[0106] According to an exemplary embodiment, the storage capacitor Cst and the second upper transistor TR2_b can be arranged on the second buffer layer 140 portion of the display area DA and the peripheral circuit area PC, respectively.

[0107] The second upper transistor TR2_b may include a second upper active layer ACT2_b, a second upper gate insulating layer GI2_b, and a second upper gate electrode GE2_b.

[0108] The second upper active layer ACT2-b may be formed on the second buffer layer 140. The second upper active layer ACT2-b may include silicon compound or oxide semiconductors such as polycrystalline silicon or amorphous silicon. According to an exemplary embodiment, the second upper active layer ACT2-b may also include oxide semiconductors such as indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), or ITZO.

[0109] For example, an oxide semiconductor layer can be formed on the second buffer layer 140 by a deposition process such as sputtering. The oxide semiconductor layer is then patterned by a photolithography process, thereby forming a second upper active layer ACT2-b on the peripheral circuit region PC.

[0110] A first contact region CR1 and a second contact region CR2 can be formed on one side and the other side of the second upper active layer ACT2-b, respectively. The first contact region CR1 and the second contact region CR2 can be set as the source region and the drain region, respectively. The portion of the second upper active layer ACT2-b between the first contact region CR1 and the second contact region CR2 can be defined as the channel region.

[0111] The second upper gate insulating layer GI2_b can be disposed on the channel region of the second upper active layer ACT2-b. A second upper gate electrode GE2_b can be disposed on the second upper gate insulating layer GI2_b.

[0112] like Figure 2 As shown, the second upper gate insulating layer GI2_b can be formed into a pattern that selectively covers the channel region.

[0113] According to an exemplary embodiment, an upper gate insulating layer can be formed on the second buffer layer 140 using a deposition process such as chemical vapor deposition (CVD) in a manner including the inorganic insulating material described above. The upper gate insulating layer may cover the second upper active layer ACT2_b.

[0114] The upper gate electrode layer can be formed on the upper gate insulating layer using a deposition process such as sputtering, incorporating the aforementioned metal or alloy. The upper gate electrode layer can be patterned using photolithography to form the second upper gate electrode GE2_b.

[0115] According to an exemplary embodiment, the first upper gate electrode GE1_b and the second upper gate electrode GE2_b can be formed simultaneously from the upper gate electrode layer on the display area DA.

[0116] Subsequently, the upper gate insulating layer can be patterned using an etching process that uses the first upper gate electrode GE1_b and the second upper gate electrode GE2_b as etching masks. Through this etching process, the first upper gate insulating layer GI1_b can be formed on a portion of the second buffer layer 140 of the display area DA. The second upper gate insulating layer GI2_b can be formed between the channel region of the second upper active layer ACT2_b formed on the peripheral circuit area PC and the second upper gate electrode GE2_b.

[0117] The third interlayer insulating layer 150 can be formed on the second buffer layer 140 to cover the first upper gate electrode GE1_b and the second upper transistor TR2_b. The third interlayer insulating layer 150 can be formed by a deposition process such as CVD, incorporating the aforementioned inorganic insulating material.

[0118] In several embodiments, the etching process of the upper gate insulating layer may induce vacancy sites caused by etching damage on the side of the second upper active layer ACT2_b. As the third interlayer insulating layer 150 is formed, hydrogen, including in the third interlayer insulating layer 150, moves to the side of the second upper active layer ACT2_b, thereby forming contact regions CR1, CR2 with increased conductivity compared to the channel region.

[0119] Upper contact electrodes CNT1_b and CNT2_b can be formed on the third interlayer insulating layer 150. The first upper contact electrode CNT1_b can be in contact with or electrically connected to the first lower contact electrode CNT1_a. For example, the first upper contact electrode CNT1_b can penetrate the third interlayer insulating layer 150, the second buffer layer 140, and the second interlayer insulating layer 130, and be in contact with or electrically connected to the upper surface of the first lower contact electrode CNT1_a.

[0120] The second upper contact electrode CNT2_b may include a portion that penetrates the third interlayer insulating layer 150 and is electrically connected to the contact areas CR1 and CR2 of the second upper active layer ACT2_b. The second upper contact electrode CNT2_b may also include a portion that penetrates the third interlayer insulating layer 150, the second buffer layer 140, and the second interlayer insulating layer 130 and is in contact with or electrically connected to the upper surface of the second lower contact electrode CNT2_a.

[0121] The second lower transistor TR2_a and the second upper transistor TR2_b can be electrically connected to each other and stacked vertically in the peripheral circuit region PC through the second upper contact electrode CNT2_b.

[0122] A second upper gate contact GC2_b and a second upper back contact BC2_b may also be formed on the third interlayer insulating layer 150.

[0123] The second upper gate contact GC2_b can penetrate the third interlayer insulating layer 150 and contact or be electrically connected to the upper surface of the second upper gate electrode GE2_b. The second upper back contact BC2_b can penetrate the third interlayer insulating layer 150 and the second buffer layer 140 and contact or be electrically connected to the upper surface of the second upper back metal pattern BML2_b.

[0124] The second upper gate contact GC2_b and the second upper back contact BC2_b can be formed as a single component integrally connected to each other on the upper surface of the third interlayer insulating layer 150. Accordingly, for example, the second upper back metal pattern BML2_b can be configured as the upper back gate electrode. For example, the second upper transistor TR2_b can have a dual-gate structure by means of the second upper back metal pattern BML2_b.

[0125] According to an exemplary embodiment, an upper electrode UE, which overlaps with the first upper gate electrode GE1_b across the third interlayer insulating layer 150, can be disposed on the upper surface of the third interlayer insulating layer 150. A storage capacitor Cst can be formed by a stacked structure of the first upper gate electrode GE1_b, the third interlayer insulating layer 150, and the upper electrode UE.

[0126] According to an exemplary embodiment, an upper contact hole exposing the upper surfaces of the lower contact electrodes CNT1_a, CNT2_a, and the second upper gate electrode GE2_b can be formed by etching the third interlayer insulating layer 150, the second buffer layer 140, and / or the second interlayer insulating layer 130. An upper back contact hole exposing the upper surface of the second upper back metal pattern BML2_b can also be formed together with the upper contact hole.

[0127] An upper contact electrode layer comprising the aforementioned metal or alloy can be formed on the third interlayer insulating layer 150 by a deposition process such as sputtering, in a manner that fills the upper contact holes and the upper back contact holes. The second upper contact electrode CNT2_b, the second upper gate contact GC2_b, and the second upper back contact BC2_b can be formed by etching the upper contact electrode layer. According to an exemplary embodiment, the upper electrode UE can be formed together on a portion of the third interlayer insulating layer 150 of the display area DA through the etching process of the upper contact electrode layer.

[0128] In several embodiments, the upper contact electrode layer may be formed as a multilayer structure comprising multiple metal layers (e.g., Ti layer / Al layer / Ti layer).

[0129] A first via insulating layer 160 covering the second upper contact electrode CNT2_b, the second upper gate contact GC2_b, the second upper back contact BC2_b, and the upper electrode UE can be formed on the third interlayer insulating layer 150.

[0130] A first via electrode VE1 and a second via electrode VE2 can be formed on the first via insulating layer 160 portion of the display area DA and the peripheral circuit area PC, respectively.

[0131] The first via electrode VE1 can penetrate the first via insulating layer 160 and contact or be electrically connected to the upper surface of the first upper contact electrode CNT1_b. The second via electrode VE2 can penetrate the first via insulating layer 160 and contact or be electrically connected to the upper surface of the second upper contact electrode CNT2_b.

[0132] For example, a first via can be formed by partially etching the first via insulating layer 160, exposing the upper surfaces of the first upper contact electrode CNT1_b and the second upper contact electrode CNT2_b, respectively. A via electrode layer that fills the first via and includes the aforementioned metal or alloy can be formed on the first via insulating layer 160. The first via electrode VE1 and the second via electrode VE2 can be formed by partially etching the via electrode layer.

[0133] The via electrode layer can also be formed as a multilayer structure including multiple metal layers (e.g., Ti layer / Al layer / Ti layer).

[0134] A second via insulating layer 170 covering the first via electrode VE1 and the second via electrode VE2 can be formed on the first via insulating layer 160. A pixel electrode PE electrically connected to the first via electrode VE1 can be formed on the second via insulating layer 170.

[0135] The first via insulating layer 160 and the second via insulating layer 170 can be formed by coating processes such as spin coating or slot coating processes using organic insulating materials including polyimide, epoxy resin, acrylic resin, polyester, siloxane resin, benzocyclobutene (BCB), etc.

[0136] A light-emitting element, including a pixel electrode PE, a light-emitting portion EL, and a counter electrode CE, can be stacked on the second via insulating layer 170. In some embodiments, the pixel electrode PE can be electrically connected to the first lower contact electrode CNT1_a of the first lower transistor TR1_a through the first upper contact electrode CNT1_b and the first via electrode VE1.

[0137] The pixel electrode PE can be configured as an anode and can include a high work function conductive material that promotes hole injection. The pixel electrode PE can also be configured as a transmissive electrode. The pixel electrode PE can include transparent conductive oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and indium tin zinc oxide (ITZO).

[0138] The pixel electrode PE can also be configured as a semi-transmissive electrode or a reflective electrode. The pixel electrode PE may include metals selected from Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, In, Sn, Zn, alloys of two or more of them, or compounds containing at least one of them (e.g., LiF).

[0139] The pixel electrode PE can have a single-layer structure or a multi-layer structure. For example, the pixel electrode PE can have a three-layer structure of ITO / Ag / ITO or ITO / Al / ITO.

[0140] For example, a second via exposing the upper surface of the first via electrode VE1 can be formed by locally etching the second via insulating layer 170. A pixel electrode layer filling the second via can be formed on the second via insulating layer 170 by a deposition process such as sputtering. A pixel electrode PE can be formed by locally etching the pixel electrode layer. The pixel electrode PE can be formed individually and independently for each of a plurality of pixels.

[0141] A pixel definition film (PDL) can be formed on the second via insulating layer 170. The PDL can expose at least partially the upper surface of the pixel electrode PE. The PDL can cover the periphery of the pixel electrode PE.

[0142] The light-emitting region (or pixel region) can be defined by the sidewalls of the pixel definition film (PDL). For example, green, blue, and red light-emitting regions can be separated and defined by the PDL. Accordingly, the light-emitting element can include a blue light-emitting element, a green light-emitting element, and a red light-emitting element.

[0143] In some embodiments, the light-emitting elements may all be white light-emitting elements or blue light-emitting elements.

[0144] In one embodiment, the pixel-defining film (PDL) can be formed by exposure and development processes after coating with a photosensitive organic material such as polysiloxane resin, polyimide resin, or acrylic resin. In another embodiment, the pixel-defining film (PDL) can also be formed using polymeric or inorganic materials and through printing processes such as inkjet printing.

[0145] In several embodiments, spacers SPCs may be formed on the upper surface of the pixel definition film (PDL). The spacers SPCs can be formed using the photosensitive organic material or the inorganic insulating material. Because a step difference is formed in each pixel or light-emitting region by means of the spacers SPCs, pixel-wise patterning of the light-emitting layer included in the light-emitting part (EL) can be performed more easily.

[0146] A light-emitting element (EL) can be formed on the pixel electrode (PE) and the pixel definition film (PDL). The light-emitting element (EL) may include an organic light-emitting layer, which is independently patterned for each red, green, and blue pixel, thereby generating different colors of light according to each pixel.

[0147] In one embodiment, the light-emitting portion EL can extend continuously and jointly across multiple pixels. In this case, the light-emitting portion EL can include a white light-emitting layer or a blue light-emitting layer. In one embodiment, the light-emitting portion EL can include light-emitting layers corresponding to multiple light colors that are different from each other, and can include a stack with a tandem structure.

[0148] The light-emitting element (EL) can be formed by means of organic light-emitting materials, such as thermal deposition, evaporation deposition, vacuum deposition, spin coating, inkjet printing, laser printing, casting, and laser thermal transfer.

[0149] Opposing electrodes CE can be formed on the light-emitting part EL, the pixel definition film PDL, and the spacer SPC. The opposing electrodes CE can be common electrodes that are disposed together and continuously in multiple light-emitting areas or pixels.

[0150] The counter electrode CE can be configured as an electron injection electrode or a cathode. The counter electrode CE can include metals, alloys, conductive compounds, etc., with low work function.

[0151] For example, the counter electrode CE can include lithium (Li), silver (Ag), magnesium (Mg), aluminum (Al), aluminum-lithium (Al-Li), calcium (Ca), magnesium-indium (Mg-In), magnesium-silver (Mg-Ag), ytterbium (Yb), silver-ytterbium (Ag-Yb), ITO, IZO, etc. These can be used individually or in combination of two or more.

[0152] The counter electrode CE can be configured as a transmission electrode, a semi-transmission electrode, or a reflection electrode. The counter electrode CE can have a single-layer structure or a multi-layer structure.

[0153] The light-emitting unit (EL) may further include a hole transport layer and an electron transport layer. According to an exemplary embodiment, the hole transport layer, the light-emitting layer, the electron transport layer, and the opposing electrode (CE) may be sequentially stacked from the upper surface of the pixel electrode (PE).

[0154] For example, the hole transport layer may include, for instance, 4,4',4''-[tris(3-methylphenyl)phenylamino]triphenylamine (m-MTDATA: 4,4',4"-[tris(3-methylphenyl)phenylamino]triphenylamine), 4,4',4''-tris(N,N-diphenylamino)triphenylamine (TDATA: 4,4'4"-tris(N,N-diphenylamino)triphenylamine), 4,4',4''-tris[N-(2-naphthyl)-N-phenylamino]-triphenylamine (2-TNATA: 4,4',4"-tris[N-(2-naphthyl)-N-phenylamino]-triphenylamine), N,N'-di(naphthyl)-N,N'-diphenyl-benzidine (NPB: N,N'-di(naphthyl)-N,N'-diphenyl-benzidine). Hole transport substances such as phthalene-1-yl)-N,N'-diphenyl-benzidine, N,N'-bis(3-methylphenyl)-N,N'-diphenyl-[1,1'-biphenyl]-4,4'-diamine (TPD: N,N'-bis(3-methylphenyl)-N,N'-diphenyl-[1,1'-biphenyl]-4,4'-diamine), 4,4',4''-tris(N-carbazolyl)triphenylamine (TCTA: 4,4',4"-tris(N-carbazolyl)triphenylamine), and poly(3,4-ethylenedioxythiophene) / poly(4-styrenesulfonate) (PEDOT / PSS: poly(3,4-ethylenedioxythiophene) / poly(4-styrenesulfonate)).

[0155] For example, the electron transport layer may include anthracene compounds, tris(8-hydroxyquinolinato)aluminum (Alq3:tris(8-hydroxyquinolinato)aluminum), 1,3,5-tris(1-phenyl-1H-benzo[d]imidazol-2-yl)benzene (TPBi:1,3,5-Tri(1-phenyl-1H-benzo[d]imidazol-2-yl)benzene), 2,9-dimethyl-4,7-diphenyl-1,10-phenanthroline (BCP:2,9-dimethyl-4,7-diphenyl-1,10-phenanthroline), 4,7-diphenyl-1,10-phenanthroline (Bphen:4,7-diphenyl-1,10-phenanthroline), 3-(4-biphenyl)-4-phenyl-5-tert-butylphenyl-1,2,4-triazole (TAZ:3-(4-biphenylyl)- Electron transport substances such as 4-phenyl-5-tert-butylphenyl-1,2,4-triazole, 4-(naphthalen-1-yl)-3,5-diphenyl-4H-1,2,4-triazole (NTAZ: 4-(naphthalen-1-yl)-3,5-diphenyl-4H-1,2,4-triazole), 2-(4-biphenyl)-5-(4-tert-butylphenyl)-1,3,4-oxadiazole (tBu-PBD: 2-(4-biphenylyl)-5-(4-tert-butylphenyl)-1,3,4-oxadiazole), and bis(2-methyl-8-hydroxyquinoline-N1,O8)-(1,1'-biphenyl-4-hydroxy)aluminum (BAlq: bis(2-methyl-8-quinolinolato-N1,O8)-(1,1'-biphenyl-4-olato)aluminum).

[0156] In some embodiments, a hole injection layer may also be disposed between the pixel electrode PE and the hole transport layer. An electron injection layer may also be disposed between the counter electrode CE and the electron transport layer.

[0157] In several embodiments, the light-emitting layer included in the light-emitting portion EL can be specifically patterned within a light-emitting area defined by the pixel definition film PDL. Accordingly, the light-emitting layer can be disposed separately from each of a plurality of pixels in the form of spaced-apart islands.

[0158] In several embodiments, the layers included in the light-emitting portion EL (e.g., the hole transport layer and the electron transport layer) may extend continuously and jointly across multiple light-emitting regions and the upper surface of the pixel definition film PDL.

[0159] Organic light-emitting diode (OLED) elements can be formed using the pixel electrode PE, light-emitting part EL, and counter electrode CE described above.

[0160] An encapsulation layer (not shown) may be formed on the opposing electrode CE. The encapsulation layer may be disposed on the pixel definition film PDL and the light-emitting element to protect the light-emitting element from moisture or oxygen.

[0161] The encapsulation layer may include an inorganic film (containing silicon nitride (SiN)). x ), silicon oxide (SiO) x (Indium tin oxide, indium zinc oxide or any combination thereof), organic membranes (including polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, hexamethyldisiloxane, acrylic resins (e.g., polymethyl methacrylate, polyacrylic acid, etc.), epoxy resins (e.g., aliphatic glycidyl ether, etc.) or combinations thereof), or combinations of inorganic and organic membranes.

[0162] The encapsulation layer can be formed as a single-layer structure or a multi-layer structure. In several embodiments, the encapsulation layer can have a sequentially stacked structure of a first inorganic layer, an organic layer, and a second inorganic layer.

[0163] In several embodiments, a color control layer overlapping the light-emitting portion (EL) may be disposed on the encapsulation layer. The color control layer may include a color conversion layer comprising quantum dots and / or a color filter.

[0164] According to the above embodiment, by embedding the lower back metal patterns BML1_a and BML2_a within the barrier layer 105, the step difference can be reduced from the lower structure of the display device. Accordingly, even when multiple transistors are stacked vertically in the peripheral circuit area PC and pixel driving transistors (e.g., the first lower transistor TR1_a) and storage capacitor Cst are stacked vertically in the display area DA, the step difference generated in each layer within the display device can be reduced.

[0165] Therefore, it can suppress the occurrence of active layer disconnections, wiring problems, or short circuits between electrodes that occur simultaneously with the increase in step differences in each layer.

[0166] Furthermore, the lower back metal patterns BML1_a and BML2_a may include protrusions PS to reduce the resistance of the lower back metal patterns BML1_a and BML2_a. Therefore, the back gate characteristics and / or source-sync characteristics of the lower back metal patterns BML1_a and BML2_a can be enhanced.

[0167] Figure 3 This is a partially enlarged cross-sectional view illustrating the shape of the metal pattern on the lower back of the display device according to an exemplary embodiment.

[0168] Reference Figure 3 , as reference Figure 2 Note that the lower back metal pattern BMLa can penetrate the barrier layer 105 and can include the protrusion PS.

[0169] The upper surface of the lower back metal pattern BMLa may include a first surface 50a, a second surface 50b, and a third surface 50c. The first surface 50a may correspond to the upper surface of the protrusion PS and may be located above the upper surface 105a of the barrier layer 105.

[0170] The third surface 50c can correspond to the upper surface of the peripheral portion of the lower back metal pattern BMLa, excluding the protrusion PS. The third surface 50c can be located on the same plane as the upper surface 105a of the barrier layer 105. For example... Figure 2 As shown, the third surface 50c can be configured as a contact surface that contacts the bottom surfaces of the lower contact electrodes CNT1_a and CNT2_a.

[0171] The second surface 50b can be an inclined surface connecting the first surface 50a and the third surface 50c.

[0172] As described above, the lower back metal pattern BMLa can completely penetrate the barrier layer 105 and can contact the base substrate 100.

[0173] According to an exemplary embodiment, the thickness of the protrusion PS can be less than the thickness of the lower back metal pattern BMLa (or the thickness of the barrier layer 105) excluding the protrusion PS. Therefore, an increase in the step difference caused by the protrusion PS can be prevented. In several embodiments, the thickness of the protrusion PS can be less than 1 / 2, 1 / 3, or 1 / 4 of the thickness of the lower back metal pattern BMLa (or the thickness of the barrier layer 105) excluding the protrusion PS.

[0174] Figures 4 to 9 This is a schematic cross-sectional view illustrating a method of manufacturing a display device according to an exemplary embodiment. References will be omitted. Figure 2The descriptions are detailed explanations of the composition, materials, and processes that are substantially the same or similar.

[0175] Reference Figure 4 A barrier layer 105 can be formed on the base substrate 100.

[0176] Reference Figure 5 The first trench TH1 and the second trench TH2 can be formed by locally etching the barrier layer 105 using photolithography. The first trench TH1 and the second trench TH2 can be formed in the display area DA and the peripheral circuit area PC, respectively.

[0177] The first trench TH1 and the second trench TH2 can completely penetrate the barrier layer 105 in the vertical direction. The upper surface of the base substrate 100 can be exposed through the first trench TH1 and the second trench TH2.

[0178] Reference Figure 6 A lower back metal layer BML that fills the first trench TH1 and the second trench TH2 can be formed on the barrier layer 105.

[0179] A sacrificial layer PR can be formed on the lower back metal layer BML. The sacrificial layer PR can be formed using a photoresist material through a coating process such as spin coating or slot coating.

[0180] Reference Figure 7 The upper part of the sacrificial layer PR can be planarized using a reverse etching process. For example... Figure 7 As shown, while the upper part of the sacrificial layer PR is planarized, the upper surface of the lower back metal layer BML can be exposed.

[0181] Reference Figure 8 As the etching process continues, a height difference can be created between the upper surface of the lower back metal layer BML and the upper surface of the sacrificial layer PR. According to an exemplary embodiment, the etching rate of the lower back metal layer BML (e.g., the etching rate of the metal layer) can be adjusted to be greater than the etching rate of the sacrificial layer PR (e.g., the etching rate of the organic layer such as a photoresist layer).

[0182] Therefore, the etching amount of the lower back metal layer BML around the sacrificial layer PR can be relatively increased, and the upper surface of the lower back metal layer BML can be located below the upper surface of the sacrificial layer PR.

[0183] Reference Figure 9 The etching process can be performed until the upper surface of the barrier layer 105 is exposed. Accordingly, the sacrificial layer PR can be substantially completely removed by the etching process.

[0184] As described above, under the etch-back condition where the etching rate of the sacrificial layer PR is relatively reduced, the lower back metal layer BML covered by the sacrificial layer PR may not be etched, or may be etched with a relatively small amount of etching. Therefore, the first lower back metal pattern BML1_a and the second lower back metal pattern BML2_a, including the protrusion PS, may be formed in the first trench TH1 and the second trench TH2, respectively.

[0185] As described above, a first lower back metal pattern BML1_a and a second lower back metal pattern BML2_a can be formed within the trenches TH1 and TH2 that penetrate the barrier layer 105. Therefore, the depth of the trenches TH1 and TH2 can be uniformly formed with respect to the thickness of the barrier layer 105, and the thicknesses of the first lower back metal pattern BML1_a and the second lower back metal pattern BML2_a can also be uniformly formed.

[0186] Then, as per reference Figure 2 This indicates that transistors, storage capacitors, light-emitting elements, etc., can be formed on the barrier layer 105 and the lower back metal patterns BML1_a and BML2_a.

[0187] Figure 10 This is a schematic cross-sectional view illustrating a display device according to an exemplary embodiment. Figure 11 This is a partially enlarged cross-sectional view illustrating the shape of the metal pattern on the lower back of the display device according to an exemplary embodiment.

[0188] Apart from the shape of the metal pattern on the lower back. Figure 10 The display device can have the same Figure 2 The display device has a substantially identical or similar configuration and structure. Therefore, details regarding the reference will be omitted. Figure 2 The descriptions are detailed explanations of the composition, structure, and process that are substantially the same or similar to those described.

[0189] Reference Figure 10 and Figure 11 The lower back metal pattern BML1_a may include a groove RS. According to an exemplary embodiment, the first lower back metal pattern BML1_a and the second lower back metal pattern BML2_a formed in the display area DA and the peripheral circuit area PC, respectively, may each include a groove RS.

[0190] like Figure 11 As shown, the upper surface of the lower back metal pattern BMLa may include a first surface 60a, a second surface 60b, and a third surface 60c. The first surface 60a may correspond to the bottom surface of the groove RS and may be located below the upper surface 105a of the barrier layer 105.

[0191] The third surface 60c can correspond to the upper surface of the periphery of the groove RS of the lower back metal pattern BMLa. The third surface 60c can be located on the same plane as the upper surface 105a of the barrier layer 105. For example... Figure 10 As shown, the third surface 60c can be configured as a contact surface that contacts the bottom surfaces of the lower contact electrodes CNT1_a and CNT2_a.

[0192] The second surface 60b can be an inclined surface connecting the first surface 60a and the third surface 60c.

[0193] As described above, the lower back metal pattern BMLa can completely penetrate the barrier layer 105 and can contact the base substrate 100. Accordingly, the thickness of the lower back metal pattern BMLa can be uniformly adjusted.

[0194] Furthermore, since the lower back metal pattern BMLa includes a groove RS, the step difference caused by the lower back metal pattern BMLa can be reduced more effectively.

[0195] According to an exemplary embodiment, the depth of the groove RS can be less than half the overall thickness of the lower back metal pattern BMLa (or the thickness of the barrier layer 105). Therefore, an increase in resistance caused by the groove RS can be prevented, and a reduction in step difference can be achieved. In several embodiments, the depth of the groove RS can be less than one-third, one-quarter, or one-fifth of the overall thickness of the lower back metal pattern BMLa (or the thickness of the barrier layer 105).

[0196] Figures 12 to 15 This is a schematic cross-sectional view illustrating a method of manufacturing a display device according to an exemplary embodiment.

[0197] Reference Figure 12 It can be executed and referenced. Figures 4 to 6 The processes described are substantially the same or similar. Accordingly, a barrier layer 105 can be formed on the base substrate 100, and trenches TH1 and TH2 (see reference) can be formed. Figure 5 ).

[0198] Subsequently, the lower back metal layer BML and the sacrificial layer PR of the filling trenches TH1 and TH2 can be sequentially formed on the barrier layer 105.

[0199] Reference Figure 13 The upper part of the sacrificial layer PR can be planarized using a reverse etching process. For example... Figure 13 As shown, while the upper part of the sacrificial layer PR is planarized, the upper surface of the lower back metal layer BML can be exposed.

[0200] Reference Figure 14As the etching process continues, a height difference can be created between the upper surface of the lower back metal layer BML and the upper surface of the sacrificial layer PR. According to an exemplary embodiment, the etching rate of the lower back metal layer BML (e.g., the etching rate of the metal layer) can be adjusted to be less than the etching rate of the sacrificial layer PR (e.g., the etching rate of the organic layer such as a photoresist layer).

[0201] Therefore, the amount of etching of the lower back metal layer BML around the sacrificial layer PR can be relatively reduced, and the pre-groove PRS can be formed while the sacrificial layer PR is being removed.

[0202] Reference Figure 15 As the etching process continues, the upper surface of the barrier layer 105 can be exposed. The groove RS can be formed by pre-grooving PRS as the underlying back metal layer BML is further etched.

[0203] Then, as per reference Figure 2 This indicates that transistors, storage capacitors, light-emitting elements, etc., can be formed on the barrier layer 105 and the lower back metal patterns BML1_a and BML2_a.

[0204] Figure 16 This is an exploded perspective view illustrating an electronic device according to an exemplary embodiment.

[0205] According to exemplary embodiments, the electronic device ED can be implemented in the form of a mobile phone (smartphone), tablet computer, PC, etc., which includes the display device described above.

[0206] Reference Figure 16 The electronic device ED may include a window structure WS, a display device DD, and a housing HS. The display device DD may also include a display panel DP containing the aforementioned transistors and light-emitting elements. Along the third direction, the housing HS, the display device DD, and the window structure WS may be stacked sequentially.

[0207] For example, a window structure WS can provide a user-identifiable external display surface, such as the visible surface of an electronic device (e.g., a mobile phone), and can include a transparent material film. For example, the window structure WS can include glass (e.g., ultra-thin glass (UTG)), a hard-coated film, a plastic film, etc.

[0208] The outer surface of the window structure WS may include an active area AA and a peripheral area PA. The active area AA provides a surface that substantially displays the image of the display device DD and allows for user touch / command input. The peripheral area PA may substantially correspond to the border area of ​​the electronic device ED.

[0209] The display device DD or display panel DP may include a display area DA and a non-display area NDA. The display area DA of the display panel DP may substantially correspond to or overlap with the effective area AA of the window structure WS. The non-display area NDA of the display panel DP may substantially correspond to or overlap with the peripheral area PA of the window structure WS. In some embodiments, the peripheral area PA of the window structure WS may further include an edge area that does not overlap with the non-display area NDA of the display panel DP.

[0210] In several embodiments, functional element regions E1 and E2 may be included within the effective area AA of the window structure WS. For example, the first functional element region E1 may be included at one end of the effective area AA, and may be implemented in the form of a camera hole. The second functional element region E2 may be configured as a fingerprint sensing area.

[0211] For example, a sensor structure for touch sensing or fingerprint sensing can be arranged within the display panel DP or between the window structure WS and the display panel DP.

[0212] The housing HS can be configured as a support frame or rear housing for the display device DD or electronic device ED. A cover panel can also be arranged between the housing HS and the display panel DP. The housing HS or the cover panel can include a plate (e.g., an SUS plate) supporting the display panel DP. The housing HS or the cover panel can also include an elastomer for absorbing impacts from the display device DD.

[0213] Figure 17 This is a block diagram of an electronic device according to an embodiment.

[0214] Reference Figure 17 According to one embodiment, the electronic device 10 may include a display module 11, a processor 12, a memory 13, and a power module 14.

[0215] The processor 12 may include a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and / or a controller.

[0216] The memory 13 may store data information required for the operation of the processor 12 or the display module 11. If the processor 12 executes the application stored in the memory 13, the image data signal and / or input control signal may be transmitted to the display module 11, and the display module 11 may process the received signal and output image information through the display screen.

[0217] The power module 14 may include a power supply module such as a power adapter or battery device and a power conversion module that generates the power required for the operation of the electronic device 10 by converting the power supplied by the power supply module.

[0218] At least one of the various components of the electronic device 10 described above may be included within the display device according to the above embodiments. Furthermore, a portion of an individual module that is functionally included within a single module may also be included within the display device, while another portion may be disposed separately from the display device. For example, the display device may include a display module 11, and the processor 12, memory 13, and power module 14 may be configured as other non-display devices within the electronic device 10.

[0219] Figure 18 This is a schematic diagram of an electronic device according to various embodiments.

[0220] Reference Figure 18 Non-limiting examples of various electronic devices that utilize the display device according to the above embodiments may include image display electronic devices (smartphones 10_1a, tablet PCs 10_1b, laptop computers 10_1c, televisions (TVs) 10_1d, desktop displays 10_1e, etc.), wearable electronic devices including display modules (such as smart glasses 10_2a, head-mounted displays 10_2b, smartwatches 10_2c, etc.), and vehicle electronic devices 10_3 including display modules (such as vehicle dashboards, center consoles, central information displays (CIDs) arranged on the dashboard, room mirror displays, etc.). The electronic devices may also include virtual reality glasses or augmented reality glasses.

Claims

1. A display device, comprising: Basic substrate; A barrier layer is formed on the base substrate; The lower back metal pattern extends through the barrier layer and includes protrusions or grooves; The lower transistor is stacked on the lower back metal pattern and includes a lower active layer and a lower gate electrode stacked on the lower active layer. as well as The light-emitting element is electrically connected to the lower transistor.

2. The display device according to claim 1, further comprising: The lower contact electrode is electrically connected to the lower active layer; as well as The lower back contact element is electrically connected to the lower back metal pattern. The lower back contact and the lower contact electrode are connected to each other.

3. The display device according to claim 1, further comprising: The lower gate contact is electrically connected to the lower gate electrode; as well as The lower back contact element is electrically connected to the lower back metal pattern. The lower back contact and the lower gate contact are connected to each other.

4. The display device according to claim 1, wherein, The base substrate has a display area and a peripheral circuit area. The lower back metal pattern includes: a first lower back metal pattern disposed in the display area of ​​the base substrate; and a second lower back metal pattern disposed in the peripheral circuit area of ​​the base substrate. Each of the first lower back metal pattern and the second lower back metal pattern includes the protrusion or the groove.

5. The display device according to claim 4, wherein, The lower transistor includes: a first lower transistor disposed in the display area of ​​the base substrate; and a second lower transistor disposed in the peripheral circuit area of ​​the base substrate.

6. The display device according to claim 5, further comprising: The first lower back contact connects the first lower transistor to the first lower back metal pattern. as well as The second lower back contact electrically connects the second lower transistor to the second lower back metal pattern.

7. The display device according to claim 5, further comprising: Storage capacitors are stacked on the first lower transistor in the display area of ​​the base substrate.

8. The display device according to claim 7, further comprising: A first upper back metal pattern is arranged between the first lower transistor and the storage capacitor.

9. The display device according to claim 5, further comprising: The second upper transistor is stacked on the second lower transistor in the peripheral circuit region of the base substrate.

10. The display device according to claim 9, further comprising: Contact electrodes are used to electrically connect the second upper transistor and the second lower transistor to each other.

11. The display device according to claim 9, further comprising: The second upper back metal pattern is arranged between the second lower transistor and the second upper transistor.

12. The display device according to claim 1, wherein, The bottom surface of the lower back metal pattern is in contact with the base substrate.

13. The display device according to claim 1, wherein, The lower back metal pattern has the protrusion, the thickness of which is less than the thickness of the peripheral portion of the lower back metal pattern excluding the protrusion.

14. The display device according to claim 1, wherein, The lower back metal pattern has the groove, the depth of which is less than 1 / 2 of the overall thickness of the lower back metal pattern.

15. The display device according to claim 1, wherein, The upper surface of the periphery of the protrusion of the lower back metal pattern or the upper surface of the periphery of the groove is on the same plane as the upper surface of the barrier layer.

16. A method for manufacturing a display device, comprising the following steps: A barrier layer is formed on the base substrate; A trench penetrating the barrier layer is formed by locally etching the barrier layer; A lower back metal layer and a sacrificial layer are sequentially formed on the base substrate to fill the trench; The sacrificial layer and the lower back metal layer are planarized by a back etching process to form a lower back metal pattern in the trench. A lower transistor is formed on the lower back metal pattern; as well as A light-emitting element is formed that is electrically connected to the lower transistor.

17. The method of manufacturing a display device according to claim 16, wherein, The etching process is performed under the condition that the etching rate of the lower back metal layer is greater than the etching rate of the sacrificial layer. A protrusion is formed on the upper part of the metal pattern on the lower back.

18. The method of manufacturing a display device according to claim 16, wherein, The etching process is performed under the condition that the etching rate of the lower back metal layer is less than the etching rate of the sacrificial layer. A groove is formed on the upper part of the metal pattern on the lower back.

19. An electronic device comprising: Display device; Memory; as well as The processor controls the operation of the display device by executing data included in the memory. The display device is the display device according to any one of claims 1 to 15.

20. The electronic device according to claim 19, wherein, The electronic devices include virtual reality or augmented reality glasses, smartphones, tablet computers, laptops, televisions, desktop monitors, smart glasses, head-mounted displays, smartwatches, or vehicle displays.

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