Display panel and display device

Abstract

The application provides a display panel and a display device; the display panel comprises a display area, a binding area, a first wiring area and a second wiring area, the display panel comprises a substrate, an array layer and a first planar layer, the array layer comprises a plurality of first fan-out lines in the first wiring area and a plurality of second fan-out lines in the second wiring area, the first planar layer is located at a first boundary of the binding area side in the first wiring area, and the first fan-out lines comprise at most two metal layers, and the second fan-out lines comprise at least two metal layers; by making the first boundary of the first planar layer fall in the first wiring area, and the first fan-out lines in the first wiring area comprise at most two metal layers, the boundary of the planar layer falls in the area where the first fan-out lines with less metal layers are located, the height of the boundary of the planar layer is reduced, and the technical problem that the upper touch metal lines are disconnected in the lap area is improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) are a new type of current-driven semiconductor light-emitting device that displays light by controlling the charge carriers in the device and exciting organic materials.

[0003] In the current OLED display panel manufacturing process, since the array layer contains multiple metal layers, multiple organic layers are required to ensure the flatness of the film structure. In the area where the bezel of the display panel is located, the boundaries of the multiple flat layers overlap with the fan-out traces. Since the fan-out traces are usually the overlapping areas of multiple metal layers, the terrain in the overlapping area is higher, causing the upper touch metal lines to break in this overlapping area. Summary of the Invention

[0004] This application provides a display panel and display device to solve the technical problem that there are errors in the low-level source signals received by the pixel driving circuit in existing display panels.

[0005] This application provides a display panel, which includes a display area, a bonding area, a first wiring area and a second wiring area located between the display area and the bonding area, wherein the second wiring area is located between the first wiring area and the display area, or between the first wiring area and the bonding area. The display panel includes: Substrate; An array layer is disposed on one side of the substrate. The array layer includes multiple first-type fan-out lines located in the first wiring area and multiple second-type fan-out lines located in the second wiring area. The first-type fan-out lines include at most two metal layers, and the second-type fan-out lines include at least two metal layers. A first planarization layer is disposed on the side of the array layer away from the substrate. The first boundary of the first flat layer near the bonding area is located within the first wiring area.

[0006] Optionally, the display panel includes: A first source-drain layer is disposed on the side of the array layer away from the substrate. The first source-drain layer includes a first signal portion of the signal line, and the boundary of the first signal portion away from the bonding region is the second boundary. The second planarization layer is disposed on the side of the first planarization layer away from the substrate. The second planarization layer covers the first boundary and the second boundary, and the boundary of the second planarization layer near the bonding area is located on the surface of the first signal section away from the substrate.

[0007] Optionally, the display panel includes: A first source-drain layer is disposed on the side of the array layer away from the substrate, and the first source-drain layer includes a first signal portion of the signal line; A second source / drain layer is disposed on the side of the first source / drain layer away from the substrate. The second source / drain layer includes a second signal portion of the signal line. The edge of the second signal portion covers the edge of the first signal portion. The boundary of the second signal portion on the side away from the bonding region is the second boundary. The second planarization layer is disposed on the side of the first planarization layer away from the substrate. The second planarization layer covers the first boundary and the second boundary, and the boundary of the second planarization layer near the bonding area is located on the surface of the second signal section away from the substrate.

[0008] Optionally, in a top view of the display panel, the first boundary and a first type of fan-out line overlap; Or / and, the two boundaries overlap with another first type of fan-out line.

[0009] Optionally, in a top view of the display panel, the first boundary is located between two adjacent fan-out lines of the first type; Or / and, between the two boundaries and another adjacent two first-type fan-out lines.

[0010] Optionally, in a top view of the display panel, and within the first wiring area, a portion of the first boundary overlaps with a first type of fan-out line, and another portion of the first boundary is located between two adjacent first type of fan-out lines. Or / and, a portion of the second boundary overlaps with a first type of fan-out line, and another portion of the second boundary lies between two adjacent first type of fan-out lines.

[0011] Optionally, within the first wiring area, at least a portion of the first boundary is parallel to the first type of fan-out line; Or / and, at least a portion of the second boundary is parallel to the first type of fan-out line.

[0012] Optionally, the array layer includes: A first gate layer is disposed on one side of the substrate. The second gate layer is disposed on the side of the first gate layer away from the substrate. A third gate layer is disposed on the side of the second gate layer away from the substrate. The thickness of the third gate layer is greater than the thickness of the first gate layer, and the thickness of the third gate layer is greater than the thickness of the second gate layer. The first type of fan-out line includes the material of at least one of the first gate layer and the second gate layer.

[0013] Optionally, the display panel further includes: The second wiring area is located between the first wiring area and the display area, and multiple type II fan-out lines are provided in the second wiring area; The third wiring area is located between the first wiring area and the bonding area, and the third wiring area is provided with multiple Class 3 fan-out lines; The third type of fan-out line includes at least two metal layers.

[0014] Optionally, the number of metal layers in the second type of fan-out line and / or the third type of fan-out line is greater than the number of metal layers in the first type of fan-out line.

[0015] This application provides a display device, which includes the display panel as described above.

[0016] This application improves the technical problem of broken lines in the upper touch metal wires in the overlapping area by making the first boundary of the first flat layer fall within the first wiring area, and the first type of fan-out line in the first wiring area includes at most two metal layers. This makes the boundary of the flat layer fall in the area where the first type of fan-out line with fewer metal layers is located, reducing the elevation of the boundary of the flat layer and improving the technical problem of broken lines in the upper touch metal wires in the overlapping area.

[0017] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0020] Figure 1 This is a simplified structural diagram of the display panel of this application.

[0021] Figure 2This is a diagram of the film structure in the display panel of this application.

[0022] Figure 3 for Figure 1 A magnified view of region M in the middle.

[0023] Figure 4 for Figure 3 Cross-sectional view of the mid-section AA. Detailed Implementation

[0024] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0025] Please see Figures 1 to 4 This application proposes a display panel 100, which includes a display area AA, a bonding area 400, and a first wiring area 310 and a second wiring area 320 located between the display area AA and the bonding area 400. The second wiring area 320 is located between the first wiring area 310 and the display area AA, or between the first wiring area 310 and the bonding area 400. The display panel 100 includes a substrate 110, an array layer 120 disposed on one side of the substrate 110, and a first planarization layer 130 disposed on the side of the array layer 120 away from the substrate 110.

[0026] In this embodiment, the array layer 120 includes multiple first-type fan-out lines 311 located in the first wiring area 310 and multiple second-type fan-out lines 321 located in the second wiring area 320. The first boundary 130A of the first flat layer 130 near the bonding area 400 is located in the first wiring area 310. The first-type fan-out lines 311 include at most two metal layers, and the second-type fan-out lines 321 include at least two metal layers.

[0027] This application improves the technical problem of broken lines in the upper touch metal wires in the overlapping area by making the first boundary 130A of the first flat layer 130 fall within the first wiring area 310, and the first type of fan-out line 311 in the first wiring area 310 includes at most two metal layers, so that the boundary of the flat layer falls in the area where the first type of fan-out line 311 with fewer metal layers is located.

[0028] The technical solution of this application will now be described in conjunction with specific embodiments.

[0029] Please see Figure 1The display panel 100 includes a display area AA and a non-display area NA adjacent to the display area AA. The display area AA contains multiple sub-pixels. Optionally, the non-display area NA surrounds the display area AA, so that the display area AA is surrounded by the non-display area NA. The display area AA is the area within the display panel 100 used for display functions, and it contains multiple display units that implement its display functions. The non-display area NA may be a border area of ​​the display panel 100, and it may contain functional components that assist the display units within the display area AA in displaying information.

[0030] Please see Figure 1 One side of the display area AA is provided with a bonding area 400 and a fan-out routing area 300 located between the display area and the bonding area 400. The bonding terminals in the bonding area 400 can be connected to external circuits. The bonding terminals transmit the signals input from the external circuits to the data routing lines, thereby driving the display panel to display the image. For example, the bonding terminals can be bonded to chips or flip-chip films to provide power and drive signals to the display panel 100.

[0031] In this embodiment, multiple light-emitting devices and pixel driving circuits for driving the light-emitting devices can be set in the display area AA. The pixel driving circuit PC can be nTmC, where n and m are positive integers, such as 6T1C, 7T1C, 7T2C, 8T2C, 8T3C, 8T4C, etc.

[0032] Please see Figure 2 The display panel 100 may have a substrate 110 and an array layer 120 disposed on the substrate 110 in the display area AA and the non-display area NA. In the display area AA, the display panel 100 may also have a pixel definition layer PDL disposed on the array layer 120, a light-emitting device layer disposed on the same layer as the pixel definition layer PDL, and an encapsulation layer TFE disposed on the pixel definition layer PDL. The following mainly describes the film layer structure of the display panel 100.

[0033] In this embodiment, the substrate 110 supports various layers disposed on the substrate 110. When the display panel 100 is a bottom-emitting light-emitting display device or a double-sided light-emitting display device, a transparent substrate is used. When the display panel 100 is a top-emitting light-emitting display device, a semi-transparent or opaque substrate, as well as a transparent substrate, can be used.

[0034] In this embodiment, the substrate 110 is used to support the various film layers disposed on the substrate 110. The substrate 110 may be made of an insulating material such as glass, quartz, or polymer resin. The substrate 110 may be a rigid substrate or a flexible substrate that can be bent, folded, rolled, etc. Examples of flexible materials used for flexible substrates include, but are not limited to, polyimide (PI).

[0035] Please see Figure 2 The array layer 120 may include multiple thin-film transistors. The thin-film transistors may be etch-block type, back-channel etch type, or classified into bottom-gate thin-film transistors, top-gate thin-film transistors, etc., according to the position of the gate and the active layer, or classified into N-type thin-film transistors and P-type thin-film transistors according to their performance.

[0036] Please see Figure 2 The array layer 120 may include a light-shielding layer 121 disposed on the substrate 110, a buffer layer 122 disposed on the light-shielding layer 121, an active layer 123 disposed on the buffer layer 122, a first gate insulating layer 124 disposed on the active layer 123, a first gate layer 125 disposed on the first gate insulating layer 124, a second gate insulating layer 126 disposed on the first gate layer 125, a second gate layer 127 disposed on the second gate insulating layer 126, a first inter-insulating layer IL1 disposed on the second gate layer 127, a third gate layer 128 disposed on the first inter-insulating layer IL1, and a second inter-insulating layer IL2 disposed on the third gate layer 128.

[0037] Please see Figure 2 The display panel 100 further includes a first source-drain layer 129 disposed on the second insulating layer IL2, a first planarization layer 130 disposed on the first source-drain layer 129, a second source-drain layer 131 disposed on the first planarization layer 130, a second planarization layer 132 disposed on the second source-drain layer 131, a third source-drain layer 133 disposed on the second planarization layer 132, a third planarization layer 134 disposed on the third source-drain layer 133, a light-emitting device layer and a pixel definition layer PDL disposed on the third planarization layer 134, and a packaging layer TFE disposed on the pixel definition layer PDL.

[0038] Please see Figure 2 The light-shielding layer 121 is used to block external light from entering the thin-film transistor from the bottom. The material of the light-shielding layer 121 can be made of black light-shielding material, such as black light-shielding metal or black organic material.

[0039] Please see Figure 2 A buffer layer 122 is disposed on the light-shielding layer 121. The buffer layer 122 is used to isolate the light-shielding layer 121 from the upper metal material. The material of the buffer layer 122 may be composed of a compound consisting of nitrogen, silicon and oxygen elements, such as a single layer of silicon oxide film or a stacked structure of silicon oxide and silicon nitride.

[0040] In this embodiment, the light-shielding layer 121 can also be embedded within the buffer layer 122.

[0041] Please see Figure 2The active layer 123 can be made of silicon semiconductor, for example, in this application the active layer 123 can be made of low-temperature polycrystalline silicon.

[0042] Please see Figure 2 The first gate insulating layer 124, the second gate insulating layer 126, the first interlayer insulating layer IL1, and the second interlayer insulating layer IL2 are respectively disposed on the corresponding metal layer or semiconductor layer, and are disposed separately with different metal layers or semiconductor layers; and the materials of the first gate insulating layer 124, the second gate insulating layer 126, the first interlayer insulating layer IL1, and the second interlayer insulating layer IL2 can be inorganic materials composed of at least two elements in silicon oxynitride or organic materials with planarity, or can be stacked single or multiple film layers, such as silicon oxide, silicon nitride, aluminum oxide, etc. stacked structure.

[0043] Please see Figure 2 The first gate layer 125, the second gate layer 127, and the third gate layer 128 are respectively disposed on the corresponding insulating layer. The materials of the first gate layer 125, the second gate layer 127, and the third gate layer 128 can be metals such as Cr, W, Ti, Ta, Mo, Al, and Cu, or single-layer or multi-layer metal structures composed of at least two of the above metals.

[0044] Please see Figure 2 The materials of the first source-drain layer 129, the second source-drain layer 131, and the third source-drain layer 133 can be metals such as Cr, W, Ti, Ta, Mo, Al, Cu, or single-layer or multi-layer metal structures composed of at least two of the above metals.

[0045] Please see Figure 2 The first planarization layer 130, the second planarization layer 132, and the third planarization layer 134 are laid in a whole layer to ensure the flatness of the film layer of the array layer 120. The materials of the first planarization layer 130 and the second planarization layer 132 can be inorganic materials composed of silicon oxynitride, or organic materials with flatness, such as flexible materials such as polytetrafluoroethylene.

[0046] It should be noted that the number of source and drain layers can be set according to the wiring space requirements. For example, the source and drain layers in this application can be three layers. At the same time, the number of gate layers can be set according to the wiring space and capacitance requirements. For example, the gate layers in this application can be three layers.

[0047] It should be noted that the planarization layer in this application is set to ensure the flatness of the film layer. The number of planarization layers is set according to the flatness requirements. For example, the number of planarization layers in this application can be three.

[0048] It should be noted that this application only uses a low-temperature polycrystalline silicon semiconductor transistor as an example, but it can also be an oxide transistor, or have both silicon semiconductor transistor and oxide transistor.

[0049] Please see Figure 2 The light-emitting device layer may include multiple light-emitting devices EL, each of which has an anode AN, a light-emitting unit, and a cathode CA connected to the pixel circuit.

[0050] Please see Figure 2 The encapsulation layer TFE covers the pixel definition layer PDL and continuously covers multiple pixel openings and multiple light-emitting devices EL; the encapsulation layer TFE may include a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer stacked in sequence.

[0051] Please see Figure 3 , Figure 3 for Figure 1 A magnified view of region M, i.e. Figure 3 This is an enlarged view of the inner part of the fan-out wiring area 300 in this application.

[0052] Please see Figure 3 The fan-out wiring area 300 includes a first wiring area 310, a second wiring area 320 and a third wiring area 330. The second wiring area 320 may be located between the first wiring area 310 and the display area AA, and the third wiring area 330 may be located between the first wiring area 310 and the bonding area 400. The second wiring area 320, the first wiring area 310 and the third wiring area 330 are arranged sequentially along the second direction Y.

[0053] In this embodiment, the first direction X can be parallel to the arrangement direction of the binding terminals in the binding area 400, and the second direction Y can be at a 90-degree angle to the first direction X.

[0054] In this embodiment, multiple fan-out lines are provided in the first wiring area 310, the second wiring area 320 and the third wiring area 330. Due to the narrow bezel design, the wires transmitting different signals in the fan-out wiring area 300 need to be overlapped, or the impedance of the wires needs to be reduced by paralleling multiple metal layers. This results in the boundary of the flat layer being in a higher area, causing the boundary of the source and drain metal layers in this area to form a protruding structure. When the organic material of the thin film encapsulation layer TFE cannot fill this area, the subsequent touch wiring may experience a breakage problem in the area where the protrusion is located.

[0055] This application improves the technical problem of broken upper touch metal wires in the overlapping area by adjusting the number of metal layers of the first type of fan-out line 311 in the first wiring area 310 within the fan-out wiring area 300, for example, changing from the original three metal layers to two or one metal layer, and making the first boundary 130A of the first flat layer 130 fall within the first wiring area 310. This reduces the elevation of the boundary of the first flat layer 130 and improves the technical problem of broken upper touch metal wires in the overlapping area.

[0056] Please see Figure 3 The first wiring area 310 has multiple Class I fan-out lines 311, the second wiring area 320 has multiple Class II fan-out lines 321, and the third wiring area 330 has multiple Class III fan-out lines 331. The Class I fan-out lines 311 include at most two metal layers, and the Class II fan-out lines 321 and Class III fan-out lines 331 each include at least two metal layers.

[0057] In this embodiment, the first type of fan-out line 311 can be the start signal line of the gate driving circuit or the clock signal line of the gate driving circuit with a small output load, such as the clock signal line of the gate driving circuit that outputs the light emission control signal to the light emission control transistor in the pixel driving circuit; the second type of fan-out line 321 and the third type of fan-out line 331 can be high-level lines, low-level lines, reset lines and clock signal lines of the gate driving circuit with a large output load, such as the clock signal line of the gate driving circuit that outputs the switch control signal to the switch transistor, and the clock signal line of the gate driving circuit that outputs the reset control signal to the reset transistor.

[0058] In this embodiment, the number of metal layers in the second type of fan-out line 321 or / and the third type of fan-out line 331 is greater than the number of metal layers in the first type of fan-out line 311.

[0059] For example, please see Figure 4 , Figure 4 for Figure 3 In the cross-sectional view of the mid-section AA, the second wiring area 320, the first wiring area 310 and the third wiring area 330 are arranged sequentially along the second direction Y. The second type fan-out line 321 in the second wiring area 320 and the third type fan-out line 331 in the third wiring area 331 are both composed of three layers of metal, and the first type fan-out line 311 in the first wiring area 310 is composed of one layer of metal. Adjacent first type fan-out lines 311 are spaced apart.

[0060] Please see Figure 4The second type of fan-out line 321 in the second wiring region 320 and the third type of fan-out line 331 in the third wiring region 330 are both made of metal materials in the first gate layer 125, the second gate layer 127 and the third gate layer 128. The first type of fan-out line 311 are all made of metal materials in the first gate layer 125 or the second gate layer 127. For example, some of the first type of fan-out lines 311 are made of metal materials in the first gate layer 125 and some of the first type of fan-out lines 311 are made of metal materials in the second gate layer 127.

[0061] In this embodiment, since the third gate layer 128 is typically formed by stacking molybdenum and titanium, and the first gate layer 125 and the second gate layer 127 are typically formed by a single layer of molybdenum, the thickness of the third gate layer 128 is greater than the thickness of the first gate layer 125, and the thickness of the third gate layer 128 is greater than the thickness of the second gate layer 127. Therefore, in order to avoid increasing the terrain height of the region where the boundary of the first flattening layer 130 is located, this application makes the first type of fan-out line 311 include the material of at least one of the first gate layer 125 and the second gate layer 127.

[0062] Alternatively, the second type fan-out line 321 in the second wiring area 320 is composed of two metal layers, and the third type fan-out line 331 in the third wiring area 330 is composed of three metal layers; or, the second type fan-out line 321 in the second wiring area 320 is composed of three metal layers, and the third type fan-out line 331 in the third wiring area 330 is composed of two metal layers.

[0063] Please see Figure 4 In the top view of the display panel 100, the first boundary 130A overlaps with a first type of fan-out line 311, that is, the cut-off position of the first flattening layer 130 can overlap with a first type of fan-out line 311.

[0064] exist Figure 4 In the structure, the first planarization layer 130 extends from the second wiring region 320 into the first wiring region 310 and terminates within the first wiring region 310. The multiple first-type fan-out lines 311 within the first wiring region 310 are all made of the metal material in the first gate layer 125 or the second gate layer 127. Therefore, the terrain of the first wiring region 310 is lower than that of the second wiring region 320. Consequently, the terrain of the boundary area of ​​the first planarization layer 130 after leveling is lower, allowing the upper second planarization layer 132 to level out when it overlaps with the metal of the source and drain layers. This avoids the formation of a protruding structure at the boundary of the source and drain layer metal in this area, thus improving the technical problem of broken lines in the upper touch metal lines in this overlap area.

[0065] In one embodiment, in a top view of the display panel 100, the first boundary 130A is located between two adjacent first-type fan-out lines 311, which means that the cutoff position of the first leveling layer 130 is located between two adjacent first-type fan-out lines 311, further reducing the terrain at the location of the first boundary 130A.

[0066] In one embodiment, in a top view of the display panel 100, and within the first wiring area 310, a portion of the first boundary 130A overlaps with a first type fan-out line 311, and another portion of the first boundary 130A is located between two adjacent first type fan-out lines 311; due to a certain error in controlling the cutoff position of the first flattening layer 130 leveling, and in the attached... Figure 3 In the first wiring area 310, a broken line area is formed. A part of the first boundary 130A of this application may overlap with a first type fan-out line 311, and another part of the first boundary 130A may be located between two adjacent first type fan-out lines 311.

[0067] In one embodiment, within the first wiring area 310, at least a portion of the first boundary 130A is parallel to the first type of fan-out line 311. For example, in the attached... Figure 3 In the first wiring area 310, there may be a continuous first sub-area 310A, a second sub-area 310B and a third sub-area 310C. The first sub-area 310A and the third sub-area 310C extend along a first direction X. The extension direction of the second sub-area 310B is set at an angle to the first direction X, that is, the first wiring area 310 is a broken line. The first boundary 130A located in the first sub-area 310A may be parallel to the first type of fan-out line 311 located in the first sub-area 310A; or / and, the first boundary 130A located in the third sub-area 310C may be parallel to the first type of fan-out line 311 located in the third sub-area 310C; or / and, the first boundary 130A located in the third sub-area 310C may be parallel or non-parallel to the first type of fan-out line 311 located in the third sub-area 310C.

[0068] Please see Figure 4 The display panel 100 also includes a signal line SL disposed on the side of the array layer 120 away from the substrate 110. The signal line SL can be a high-level power line or a low-level power line. The signal line SL includes a second boundary SLA on the side away from the bonding area 400. The second boundary SLA is located within the first wiring area 310, and the first boundary 130A and the second boundary SLA are spaced apart.

[0069] Because the output load of high-level and low-level power lines is relatively large, they are usually made of materials with at least one source-drain layer. When the boundary of the first planarization layer 130 overlaps with the boundary of the signal line SL, the terrain in the area where the boundary of the first planarization layer 130 is located is relatively high due to the presence of three gate layers and one source-drain layer in the overlapping area. This causes the second planarization layer 132 to be unable to flow level in this area, resulting in a raised structure at the boundary of the upper source-drain layer metal in this area. This can lead to a technical problem where the touch trace may break in the area where the raised structure is located.

[0070] This application, by indenting the first boundary 130A of the first planarization layer 130 and spacing the first boundary 130A of the first planarization layer 130 and the second boundary SLA of the signal line SL, effectively prevents the first planarization layer 130 and the signal line SL from overlapping. As a result, the area where the boundary of the first planarization layer 130 is located is at a lower elevation. The second planarization layer 132 located on the first planarization layer 130 can level across the first boundary 130A and overlap with the boundary of the signal line, thus avoiding the formation of a protruding structure at the boundary of the upper source and drain metal layers in this area and improving the technical problem of broken touch traces.

[0071] In this embodiment, the first source-drain layer 129 includes a first signal section SL1 of the signal line SL, and the boundary of the first signal section SL1 away from the bonding region 400 is the second boundary SLA; the second planarization layer 132 covers the first boundary 130A and the second boundary SLA, and the boundary of the second planarization layer 132 near the bonding region 400 is located on the surface of the first signal section SL1 away from the substrate 110.

[0072] That is, the signal line SL of this application can be composed of a single metal layer of the first source-drain layer 129, or composed of the metal of the first source-drain layer 129 and the third source-drain layer 133 connected in parallel. The second planarization layer 132 spans the first boundary 130A and the second boundary SLA, and fills the area between the first boundary 130A and the second boundary SLA. The boundary of the second planarization layer 132 can be located on the surface of the first signal section SL1 away from the substrate 110.

[0073] Please see Figure 4The first source-drain layer 129 includes a first signal portion SL1 of the signal line SL, and the second source-drain layer 131 includes a second signal portion SL2 of the signal line SL. The edge of the second signal portion SL2 covers the edge of the first signal portion SL1, and the boundary of the second signal portion SL2 away from the bonding region 400 is the second boundary SLA. The second planarization layer 132 covers the first boundary 130A and the second boundary SLA, and the boundary of the second planarization layer 132 near the bonding region 400 is located on the surface of the second signal portion SL2 away from the substrate 110.

[0074] That is, the signal line SL of this application can be formed by two metal layers in parallel, namely the first source-drain layer 129 and the second source-drain layer 131, or by the metal layers in parallel of the first source-drain layer 129, the second source-drain layer 131 and the third source-drain layer 133. The second planarization layer 132 spans the first boundary 130A and the second boundary SLA and fills the area between the first boundary 130A and the second boundary SLA. The boundary of the second planarization layer 132 can be located on the surface of the second signal section SL2 away from the substrate 110.

[0075] exist Figure 4 The third source-drain layer 133 also includes a third signal section SL3 of the signal line SL. The third signal section SL3, the second signal section SL2 and the first signal section SL1 are connected in parallel to reduce the impedance of the third signal section SL3.

[0076] In this embodiment, the boundary of the second flattening layer 132 is located within the first wiring area 310.

[0077] In this embodiment, in a top view of the display panel 100, the second boundary SLA and a first type of fan-out line 311 overlap. Figure 4 In the structure, some signal lines SL are located in the first wiring area 310, and the multiple first-type fan-out lines 311 in the first wiring area 310 are all made of metal materials in the first gate layer 125 or the second gate layer 127. Therefore, the terrain of the first wiring area 310 is lower than that in the third wiring area 330. Thus, the terrain of the boundary area after the second flattening layer 132 is leveled is lower, which avoids the formation of a protruding structure at the boundary of the source and drain metal in this area and improves the technical problem of broken lines in the upper touch metal lines in this overlapping area.

[0078] Optionally, the second boundary SLA is located between two adjacent first-class fan-out lines 311, which is equivalent to the boundary of the signal line SL being located between two adjacent first-class fan-out lines 311, further reducing the terrain at the location of the second boundary SLA.

[0079] Optionally, in a top view of the display panel 100, a portion of the second boundary SLA overlaps with a first-type fan-out line 311, and another portion of the second boundary SLA lies between two adjacent first-type fan-out lines 311; Figure 3 In the structure, the first wiring area 310 is a broken line area. Therefore, in order to make the second boundary SLA fall within the first wiring area 310, a part of the second boundary SLA can overlap with a first type fan-out line 311, and the other part of the second boundary SLA can be located between two adjacent first type fan-out lines 311.

[0080] In this embodiment, within the first wiring area 310, the second boundary SLA is similar, and at least a portion of the second boundary SLA can be parallel to the first type of fan-out line 311.

[0081] It should be noted that this application also proposes a display device, which includes the aforementioned display panel, and the display device of this application can be any product or component with display function, such as a vehicle screen, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0082] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0083] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0084] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0085] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display panel, characterized in that, The display panel includes a display area, a bonding area, a first wiring area and a second wiring area located between the display area and the bonding area, wherein the second wiring area is located between the first wiring area and the display area, or between the first wiring area and the bonding area. Substrate; An array layer is disposed on one side of the substrate. The array layer includes multiple first-type fan-out lines located in the first wiring area and multiple second-type fan-out lines located in the second wiring area. The first-type fan-out lines include at most two metal layers, and the second-type fan-out lines include at least two metal layers. A first planarization layer is disposed on the side of the array layer away from the substrate. The first boundary of the first flat layer near the bonding area is located within the first wiring area.

2. The display panel according to claim 1, characterized in that, The display panel also includes: Signal lines are located on the side of the array layer away from the substrate. The signal line includes a second boundary on the side away from the bonding area, the second boundary being located within the first wiring area, and the first boundary and the second boundary being spaced apart.

3. The display panel according to claim 2, characterized in that, The display panel includes: A first source-drain layer is disposed on the side of the array layer away from the substrate. The first source-drain layer includes a first signal portion of the signal line, and the boundary of the first signal portion away from the bonding region is the second boundary. The second planarization layer is disposed on the side of the first planarization layer away from the substrate. The second planarization layer covers the first boundary and the second boundary, and the boundary of the second planarization layer near the bonding area is located on the surface of the first signal section away from the substrate.

4. The display panel according to claim 2, characterized in that, The display panel includes: A first source-drain layer is disposed on the side of the array layer away from the substrate, and the first source-drain layer includes a first signal portion of the signal line; A second source / drain layer is disposed on the side of the first source / drain layer away from the substrate. The second source / drain layer includes a second signal portion of the signal line. The edge of the second signal portion covers the edge of the first signal portion. The boundary of the second signal portion on the side away from the bonding region is the second boundary. The second planarization layer is disposed on the side of the first planarization layer away from the substrate. The second planarization layer covers the first boundary and the second boundary, and the boundary of the second planarization layer near the bonding area is located on the surface of the second signal section away from the substrate.

5. The display panel according to any one of claims 1 to 4, characterized in that, In a top view of the display panel, the first boundary and a first type of fan-out line overlap; Or / and, the two boundaries overlap with another first type of fan-out line.

6. The display panel according to any one of claims 1 to 4, characterized in that, In a top view of the display panel, the first boundary is located between two adjacent fan-out lines of the first type; Or / and, between the two boundaries and another adjacent two first-type fan-out lines.

7. The display panel according to any one of claims 1 to 4, characterized in that, In a top view of the display panel, and within the first wiring area, a portion of the first boundary overlaps with a first type of fan-out line, and another portion of the first boundary lies between two adjacent first type of fan-out lines. Or / and, a portion of the second boundary overlaps with a first type of fan-out line, and another portion of the second boundary lies between two adjacent first type of fan-out lines.

8. The display panel according to any one of claims 1 to 4, characterized in that, Within the first wiring area, at least a portion of the first boundary is parallel to the first type of fan-out line; Or / and, at least a portion of the second boundary is parallel to the first type of fan-out line.

9. The display panel according to any one of claims 1 to 4, characterized in that, The array layer includes: A first gate layer is disposed on one side of the substrate. The second gate layer is disposed on the side of the first gate layer away from the substrate. A third gate layer is disposed on the side of the second gate layer away from the substrate. The thickness of the third gate layer is greater than the thickness of the first gate layer, and the thickness of the third gate layer is greater than the thickness of the second gate layer. The first type of fan-out line includes the material of at least one of the first gate layer and the second gate layer.

10. The display panel according to any one of claims 1 to 4, characterized in that, The display panel also includes: The second wiring area is located between the first wiring area and the display area, and multiple type II fan-out lines are provided in the second wiring area; The third wiring area is located between the first wiring area and the bonding area, and the third wiring area is provided with multiple Class 3 fan-out lines; The third type of fan-out line includes at least two metal layers.

11. The display panel according to claim 10, characterized in that, The number of metal layers in the second type of fan-out line and / or the third type of fan-out line is greater than the number of metal layers in the first type of fan-out line.

12. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 11.

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