Integrated chip and method of forming the same

Abstract

An integrated chip and a method of forming the same are provided. In some embodiments, the disclosure relates to an integrated chip including a dielectric structure. The dielectric structure includes a plurality of surfaces defining one or more capacitor openings. A conductive interconnect is in the dielectric structure and laterally adjacent to the one or more capacitor openings. An upper etch stop layer extends over a top surface of the dielectric structure and contacts a top surface of the conductive interconnect. A capacitor structure lines the plurality of surfaces. The capacitor structure includes a first electrode, a second electrode, and a capacitor dielectric disposed between the first and second electrodes. A top surface of the capacitor structure is vertically offset from a bottom surface of the upper etch stop layer by a first distance in a direction toward the substrate. A bottom surface of the capacitor structure is substantially aligned with a bottom surface of the conductive interconnect. The present disclosure can mitigate damage to the capacitor structure.

Description

Technical Field

[0001] This invention relates to an integrated chip and a method for forming the same. Background Technology

[0002] Integrated circuits are formed on semiconductor dies containing millions or billions of transistors. These transistors are configured to act as switches and / or generate power increases to enable the integrated circuit to perform logic functions (e.g., forming a processor configured to perform logic functions). Integrated circuits also include passive components such as capacitors, resistors, inductors, and transformers. Passive components are widely used to control characteristics of integrated circuits, such as gain and time constant. Summary of the Invention

[0003] An integrated chip according to an embodiment of the present invention includes: a dielectric structure overlaid on a substrate and including a plurality of surfaces defining one or more capacitor openings; a conductive interconnect located in the dielectric structure and laterally adjacent to the one or more capacitor openings; an upper etch stop layer extending above the top surface of the dielectric structure and contacting the top surface of the conductive interconnect; and a capacitor structure lining the plurality of surfaces defining the one or more capacitor openings, wherein the capacitor structure includes a first electrode, a second electrode, and a capacitor dielectric disposed between the first electrode and the second electrode, wherein the top surface of the capacitor structure is perpendicularly offset from the bottom surface of the upper etch stop layer by a first distance in a direction toward the substrate, and wherein the bottom surface of the capacitor structure is substantially aligned with the bottom surface of the conductive interconnect.

[0004] An embodiment of the present invention provides a method for forming an integrated chip, comprising: forming a dielectric structure over a substrate; performing a first patterning process on the dielectric structure to form one or more capacitor openings extending through the dielectric structure; forming a capacitor structure in the one or more capacitor openings, wherein the capacitor structure includes a first electrode, a second electrode, and a capacitor dielectric located between the first electrode and the second electrode; performing a second patterning process on the dielectric structure to form interconnect openings extending through the dielectric structure, wherein the interconnect openings are laterally adjacent to the capacitor structure, wherein the second patterning process is performed after forming the capacitor structure; and forming conductive interconnects in the interconnect openings, wherein a first height of the conductive interconnects is greater than a second height of the capacitor structure, wherein the bottom surface of the conductive interconnects is substantially aligned with the bottom surface of the capacitor structure.

[0005] An embodiment of the present invention provides a method for forming an integrated chip, comprising: forming a plurality of lower conductive interconnects above a substrate; forming a dielectric structure above the plurality of lower conductive interconnects, wherein the dielectric structure includes a first etch stop layer, a first dielectric layer, a second etch stop layer, and a second dielectric layer, wherein the first dielectric layer is located between the first etch stop layer and the second etch stop layer, and the second dielectric layer covers the second etch stop layer; etching the dielectric structure to form one or more capacitor openings extending through the dielectric structure, wherein the one or more capacitor openings expose the plurality of lower conductive interconnects. The upper surface of the first lower conductive internal connector is exposed and the upper surface of the second etch stop layer is exposed; a capacitor structure is formed in the one or more capacitor openings, wherein the capacitor structure contacts the upper surface of the first lower conductive internal connector and the upper surface of the second etch stop layer; a third dielectric layer is deposited on the second dielectric layer and the capacitor structure, wherein the top surface of the third dielectric layer is directly above the top surface of the capacitor structure; and a conductive internal connector is formed extending through the dielectric structure and the third dielectric layer, wherein the top surface of the conductive internal connector is aligned with the top surface of the third dielectric layer. Attached Figure Description

[0006] The various aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the different features are not drawn to scale. In fact, for clarity of explanation, the sizes of the various features may be arbitrarily increased or decreased.

[0007] Figure 1 Cross-sectional views are shown of some embodiments of an integrated chip including a capacitor structure and conductive interconnects according to the present disclosure.

[0008] Figure 2A Cross-sectional views are shown of some embodiments of an integrated chip including a capacitor structure and conductive interconnects according to the present disclosure.

[0009] Figure 2B Show Figure 2A Top view of some embodiments of the integrated chip.

[0010] Figures 3A-3C Show Figure 2A Cross-sectional views of various other embodiments of the integrated chip.

[0011] Figure 4A Cross-sectional views are shown of some embodiments of an integrated chip including a capacitor structure and conductive interconnects according to the present disclosure.

[0012] Figure 4B and 4C Show Figure 4ATop views of some different embodiments of the integrated chip.

[0013] Figures 5A-5C Show Figure 4A Cross-sectional views of various other embodiments of the integrated chip.

[0014] Figure 6 Cross-sectional views are shown of some embodiments of an image sensor integrated chip including a capacitor structure and conductive interconnects according to the present disclosure.

[0015] Figure 7-21 Cross-sectional views are shown of some embodiments of a method for forming an integrated chip including a capacitor structure and conductive interconnects according to the present disclosure.

[0016] Figure 22 The flowcharts illustrate some embodiments of a method for forming an integrated chip including a capacitor structure and conductive interconnects according to the present disclosure. Detailed Implementation

[0017] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these components and arrangements are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features are formed between the first and second features such that the first and second features are not in direct contact. Additionally, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0018] Furthermore, for ease of description, spatially related terms such as “underlying,” “below,” “lower,” “overlying,” and “upper” may be used herein to describe the relationship between one element or feature and another element(s) as shown in the figures. In addition to the orientations depicted in the figures, spatially related terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptive terms used herein shall be interpreted accordingly. Unless otherwise expressly stated, it is assumed that each device having the same reference numerals has the same material composition and a thickness within the same thickness range. In some embodiments, the terms “about” and / or “approximately” may be interpreted as meaning + / - 10% or + / - 5%, while in other embodiments, the terms “about” and / or “approximately” may be interpreted as meaning within normal manufacturing tolerances of a given wafer fabrication process.

[0019] MIM (Metal-Insulator-Metal) capacitors are passive components typically configured within back-end process (BEOL) interconnect stacks of integrated circuits. An MIM capacitor includes a first electrode layer, a second electrode layer, and a capacitor dielectric between the first and second electrode layers. An MIM capacitor may include one or more vertical segments extending through the inter-level dielectric (ILD) structure. Since the capacitance of an MIM capacitor is proportional to the overlap area between the first and second electrode layers, a MIM capacitor with one or more vertical segments increases the capacitance compared to a planar capacitor. MIM capacitors may be configured adjacent to conductive internal interconnects within the ILD structure.

[0020] A method for forming an integrated chip including a MIM capacitor may include depositing an ILD structure on a plurality of lower conductive interconnects. The conductive interconnects (e.g., including interconnect vias and / or interconnect wires) are formed in the ILD structure above a first lower conductive interconnect. An upper etch stop layer and a first upper dielectric layer are deposited on the conductive interconnects. An etching process is performed on the first upper dielectric layer, the upper etch stop layer, and the ILD structure to form one or more capacitor openings above a second lower conductive interconnect. The MIM capacitor is formed as a liner within the one or more capacitor openings and laterally adjacent to the conductive interconnect. An etch stop layer is deposited over the MIM capacitor, and a second upper dielectric layer is formed above the MIM capacitor and the first upper dielectric layer. Furthermore, the plurality of upper conductive interconnects are formed to extend through the first and second upper dielectric layers and the upper etch stop layer above the conductive interconnects and the MIM capacitor.

[0021] Forming a MIM capacitor after a conductive interconnect can present challenges. For example, the height of the conductive interconnect is limited by the height of the MIM capacitor. Furthermore, the MIM capacitor may have a greater height than the conductive interconnect. Simultaneous formation of the upper conductive interconnect (e.g., via single or dual damascene) can result in a larger MIM capacitor height that may damage the top electrode layer of the MIM capacitor during the etching process used to form the upper conductive interconnect. Additionally, reducing the power of the etching process can mitigate damage to the MIM capacitor, but this may prevent the etching process from exposing the conductive interconnect, leading to an open circuit between the conductive interconnect and the overlying upper conductive interconnect. Covering with an etch stop layer can mitigate damage to the MIM capacitor; however, forming such a layer increases manufacturing costs. For example, forming an etch stop layer may utilize one or more additional deposition and / or etching processes. Therefore, forming the MIM capacitor before the conductive interconnect increases manufacturing costs and complexity and / or may reduce the yield of the integrated chip.

[0022] This disclosure relates, in some embodiments, to an integrated chip including a metal-insulator-metal (MIM) capacitor with reduced manufacturing complexity. In some embodiments, a method for forming the integrated chip includes depositing a dielectric structure on a plurality of lower conductive interconnects. A MIM capacitor is formed in the dielectric structure. The MIM capacitor includes one or more vertical segments extending through the dielectric structure. A dielectric layer is formed above the MIM capacitor. Conductive interconnects are formed laterally adjacent to the MIM capacitor in the dielectric structure. An upper etch stop layer is formed above the top surface of the dielectric structure and the top surface of the conductive interconnects. The top surface of the MIM capacitor is perpendicularly offset from the top surface of the conductive interconnects such that the height of the MIM capacitor is less than the height of the conductive interconnects. A plurality of upper conductive interconnects are formed above the MIM capacitor and the conductive interconnects. By forming the MIM capacitor in the dielectric structure prior to the conductive interconnects, manufacturing complexity is reduced and damage to the MIM capacitor is minimized. For example, the top surface of the MIM capacitor located below the upper etch stop layer mitigates damage to the MIM capacitor during the fabrication of the upper conductive interconnect (e.g., during the etching process used to form the upper conductive interconnect), and the formation of an overlying etch stop layer on the MIM capacitor can be omitted. Furthermore, the height and / or configuration of the conductive interconnect can be defined independently of the height and / or configuration of the MIM capacitor, thereby increasing manufacturing flexibility.

[0023] Figure 1 Cross-sectional view 100 shows some embodiments of an integrated chip including a capacitor structure and conductive interconnects according to the present disclosure.

[0024] The integrated chip includes a lower interlayer dielectric (ILD) structure 104 above a substrate 102. In some embodiments, a plurality of lower conductive interconnects 106a-106b are disposed within the lower ILD structure 104. A dielectric structure 109 is disposed above the lower ILD structure 104. In some embodiments, the dielectric structure 109 is referred to as an ILD structure, a middle ILD structure, etc. The dielectric structure 109 includes a first etch stop layer 108, a first dielectric layer 110, a second etch stop layer 112, a second dielectric layer 114, and a third dielectric layer 115. The first etch stop layer 108 is disposed above the lower ILD structure 104. The first dielectric layer 110 is disposed between the first etch stop layer 108 and the second etch stop layer 112. The second dielectric layer 114 is disposed above the second etch stop layer 112, and the third dielectric layer 115 is disposed above the second dielectric layer 114.

[0025] Dielectric structure 109 includes a plurality of surfaces defining one or more capacitor openings extending through first and second etch stop layers 108, 112 and first and second dielectric layers 110, 114. Capacitor structure 125 is lined to one or more surfaces of dielectric structure 109 to define one or more capacitor openings. Capacitor structure 125 includes a plurality of vertical segments disposed in one or more capacitor openings and extending vertically from the top surface of second dielectric layer 114 to a first lower conductive interconnect 106a among a plurality of lower conductive interconnects 106a-106b. Capacitor structure 125 includes a first electrode 132, a second electrode 136, and a capacitor dielectric 134 between the first electrode 132 and the second electrode 136. Sidewall spacers 140 are clad on the capacitor dielectric 134 and surround the sidewalls of the second electrode 136. In some embodiments, the first electrode 132 includes a diffusion barrier layer 126 and a conductive layer 128. In various embodiments, the second electrode 136 includes a plurality of protrusions extending downward toward substrate 102. The vertical segments of the first electrode 132 are spaced between adjacent protrusions in a plurality of protrusions. In various embodiments, the plurality of protrusions of the second electrode 136 may each include an inner surface defining the cavity 138. The capacitor structure 125 having a plurality of vertical segments increases the overlap area between the first electrode 132 and the second electrode 136, thereby increasing the capacitance of the capacitor structure 125, for example, compared to another capacitor (e.g., a planar capacitor).

[0026] A conductive internal connector 113 is disposed in the dielectric structure 109 and laterally adjacent to the capacitor structure 125. In some embodiments, the conductive internal connector 113 extends continuously vertically from the top surface of the third dielectric layer 115 to a second lower conductive internal connector 106b among a plurality of lower conductive internal connectors 106a-106b. In some embodiments, the conductive internal connector 113 is a single continuous interconnect via. In various embodiments, the top surface of the capacitor structure 125 is perpendicularly offset from the top surface of the conductive internal connector 113 by a first vertical distance 135 in the direction toward the substrate 102.

[0027] The upper ILD structure 117 covers the capacitor structure 125 and the conductive internal connector 113. In some embodiments, the upper ILD structure 117 includes a first upper etch stop layer 116, a first upper dielectric layer 118, a second upper etch stop layer 120, and a second upper dielectric layer 122. The first upper etch stop layer 116 is disposed above the dielectric structure 109. The first upper dielectric layer 118 is disposed between the first upper etch stop layer 116 and the second upper etch stop layer 120. The second upper dielectric layer 122 is disposed above the second upper etch stop layer 120. A plurality of upper conductive internal connectors 142, 144 are disposed in the upper ILD structure 117. The first upper conductive internal connector 142 of the plurality of upper conductive internal connectors 142, 144 extends through the upper ILD structure 117 to contact the second electrode 136 of the capacitor structure 125. A second upper conductive internal connector 144, one of a plurality of upper conductive internal connectors 142, 144, extends through the upper ILD structure 117 to contact the conductive internal connector 113. In some embodiments, the first upper conductive internal connector 142 and / or the second upper conductive internal connector 144 may respectively include interconnect wires and / or interconnect vias. In various embodiments, the first upper conductive internal connector 142 extends vertically through the entire thickness of the first upper etch stop layer 116 and at least a portion of the third dielectric layer 115, such that the bottom surface of the first upper conductive internal connector 142 is located below the bottom surface of the first upper etch stop layer 116.

[0028] During the fabrication of the integrated circuit, a capacitor structure 125 is formed extending through first and second etch stop layers 108, 112 and first and second dielectric layers 110, 114. In some embodiments, after the capacitor structure 125 is formed, a third dielectric layer 115 is deposited over the second dielectric layer 114, and conductive interconnects 113 are formed extending from the third dielectric layer 115 to the first etch stop layer 108. An upper ILD structure 117 is deposited over the dielectric structure 109 and the conductive interconnects 113. A plurality of upper conductive interconnects 142, 144 are then formed in the upper ILD structure 117. Therefore, in some embodiments, the capacitor structure 125 is formed before the formation of adjacent conductive interconnects 113. This reduces fabrication complexity and prevents or mitigates damage to the capacitor structure 125. For example, the conductive interconnects 113 can be formed in a varied configuration in the dielectric structure 109 using a fabrication process not limited by the height of the capacitor structure 125. In one example, the height of the conductive interconnect 113 may be greater than the height of the capacitor structure 125 and defined independently of the height of the capacitor structure 125, thereby increasing design flexibility. Furthermore, the top surface of the capacitor structure 125 is directly overlaid with the first upper etch stop layer 116 to mitigate damage to the capacitor structure 125 during the fabrication of the upper conductive interconnects 142, 144 (e.g., mitigating damage during the etching process used to form the upper conductive interconnects). The close proximity between the first upper etch stop layer 116 and the capacitor structure 125 promotes increased capacitance of the capacitor structure 125 and enhances the ability of the first upper etch stop layer 116 to protect the capacitor structure. As a result, the formation of an overlay etch stop layer (not shown) on the second electrode 136 can be omitted, thereby saving one or more deposition processes and / or one or more patterning processes.

[0029] Figure 2A Cross-sectional view 200a shows some other embodiments of an integrated chip including a capacitor structure according to this disclosure.

[0030] The integrated chip includes a lower ILD structure 104 disposed above a substrate 102. The substrate 102 may be, for example, or include a bulk substrate (e.g., a bulk silicon substrate), a silicon-on-insulator (SOI) substrate, a silicon-germanium substrate, a semiconductor wafer, or another suitable semiconductor substrate. A plurality of lower conductive interconnects 106a-106b are disposed in the lower ILD structure 104. In some embodiments, the plurality of lower conductive interconnects 106a-106b may be, for example, one or more of conductive contacts, interconnect wires, and interconnect vias. The plurality of lower conductive interconnects 106a-106b may be, for example, one or more of copper, tungsten, ruthenium, aluminum, and copper.

[0031] A dielectric structure 109 is disposed above the lower ILD structure 104. In some embodiments, the dielectric structure 109 includes a first etch stop layer 108 on the lower ILD structure 104, a first dielectric layer 110 on the first etch stop layer, a second etch stop layer 112 on the first dielectric layer 110, a second dielectric layer 114 on the second etch stop layer 112, and a third dielectric layer 115 on the second dielectric layer 114. In various embodiments, the first etch stop layer 108 directly contacts the top surface of the lower conductive interconnects 106a-106b. The first etch stop layer 108 and the second etch stop layer 112 may be, for example, one or more of silicon nitride, silicon carbide, etc. In some embodiments, the thickness of the first etch stop layer 108 and the second etch stop layer 112 may be, for example, in the range of about 300 to 1,500 angstroms or some other suitable value. In a further embodiment, the thicknesses of the first, second, and third dielectric layers 110, 114, and 115 are each greater than the thickness of one or more of the first and second etch stop layers 108 and 112. The first, second, and third dielectric layers 110, 114, and 115 may be, for example, or include one or more of oxides (e.g., silicon dioxide), low-k (low dielectric constant) dielectric materials, etc.

[0032] The dielectric structure 109 includes a plurality of surfaces defining one or more capacitor openings extending through a first etch stop layer 108, a first dielectric layer 110, a second etch stop layer 112, and a second dielectric layer 114. A capacitor structure 125 is lining one or more surfaces of the dielectric structure 109 to define one or more capacitor openings. The capacitor structure 125 includes a plurality of vertical segments disposed in the dielectric structure 109 and extending vertically from the second dielectric layer 114 to a first lower conductive inner interconnect 106a. The capacitor structure 125 includes a first electrode 132, a second electrode 136, and a capacitor dielectric 134 disposed between the first electrode 132 and the second electrode 136. In various embodiments, the first electrode 132 includes a diffusion barrier layer 126 and a conductive layer 128, wherein the diffusion barrier layer 126 is disposed between the conductive layer 128 and the dielectric structure 109.

[0033] The diffusion barrier layer 126 may be, for example, one or more of tantalum, tantalum nitride, and tungsten nitride. The conductive layer 128 and the second electrode 136 may be, for example, one or more of copper, aluminum, titanium nitride, and tungsten. In some embodiments, the conductive layer 128 and the second electrode 136 comprise the same material (e.g., titanium nitride). In some embodiments, the capacitor dielectric 134 comprises a first capacitor dielectric layer 201 and a second capacitor dielectric layer 203. The first capacitor dielectric layer 201 is disposed between the second capacitor dielectric layer 203 and the first electrode 132. The first capacitor dielectric layer 201 may be, for example, one or more of titanium oxide and tantalum oxide. The second capacitor dielectric layer 203 may be, for example, one or more of zirconium oxide, hafnium oxide, aluminum oxide, and lead oxide. In some embodiments, the first capacitor dielectric layer 201 comprises a material different from the second capacitor dielectric layer 203. The second electrode 136 includes one or more internal surfaces defining the cavity 138. In some embodiments, cavity 138 comprises air and may be referred to as an air gap. In other embodiments, cavity 138 may comprise, for example, one or more of oxides (e.g., silicon dioxide), silicon, and germanium. Sidewall spacers 140 are disposed on the opposite sidewalls of the second electrode 136.

[0034] In various embodiments, the capacitor structure 125 includes a plurality of elongated vertical segments 222 and a peripheral ring structure 220. In some embodiments, the plurality of elongated vertical segments 222 may be circular when viewed in a top view (e.g., as shown in the figure). Figure 2B As seen in the diagram, the peripheral ring structure 220 extends laterally continuously around a plurality of elongated vertical segments 222. In various embodiments, the second electrode 136 includes a plurality of protrusions extending downward toward the first lower conductive inner connector 106a. The plurality of protrusions are disposed in the elongated vertical segments 222 and the peripheral ring structure 220. In some embodiments, the peripheral ring structure 220 is configured as a guard ring or protective ring to increase the structural integrity of the capacitor structure 125, wherein the peripheral ring structure 220 reduces delamination between layers of the capacitor structure 125 and promotes an increase in capacitance of the capacitor structure 125. In some embodiments, the first electrode 132, when viewed in cross-sectional view, includes a U-shaped segment extending along the side and lower surface of the protrusions of the second electrode 136. Furthermore, the capacitor structure 125 includes shorter vertical segments disposed between the plurality of elongated vertical segments 222. The shorter vertical segments contact the top surface of the second etch stop layer 112. In some embodiments, the height 209 of the capacitor structure 125 is, for example, in the range of 4,500 to 24,500 angstroms or some other suitable value.

[0035] A conductive internal connector 113 is disposed within the dielectric structure and laterally adjacent to the capacitor structure 125. In some embodiments, the conductive internal connector 113 extends continuously and vertically from the top surface of the third dielectric layer 115 to the second lower conductive internal connector 106b. In various embodiments, the conductive internal connector 113 is a single continuous interconnect via. In other embodiments, the conductive internal connector 113 includes conductive wires and conductive vias. The conductive internal connector 113 may be, for example, or include one or more of copper, tungsten, ruthenium, aluminum, and copper. In some embodiments, the top surface of the conductive internal connector 113 is aligned with the top surface of the third dielectric layer 115. The top surface of the capacitor structure 125 is perpendicularly offset from the top surface of the conductive internal connector 113 by a first vertical distance 135 in the direction toward the substrate 102. In some embodiments, the first vertical distance 135 is, for example, in the range of approximately 200 to 500 angstroms, approximately 200 to 350 angstroms, approximately 350 to 500 angstroms, or some other suitable value. In various embodiments, the height 211 of the conductive inner connector 113 is, for example, in the range of approximately 5,000 to 25,000 angstroms or some other suitable value. In some embodiments, the height 209 of the capacitor structure 125 is smaller than the height 211 of the conductive inner connector 113. In some embodiments, the bottom surface of the capacitor structure 125 is aligned with the bottom surface of the conductive inner connector 113.

[0036] In some embodiments, it should be understood that, as used herein, vias (e.g., conductive vias or interconnect vias) are configured to facilitate vertical electrical interconnections between two or more vertically spaced conductive structures (e.g., two or more vertically spaced conductive interconnects). The vias (e.g., conductive vias or interconnect vias) may extend in a direction substantially perpendicular to the top surface of substrate 102 and may have a height, for example, greater than the length and / or width of the via. In various embodiments, it should be understood that, as used herein, wires (e.g., conductive wires or interconnect wires) are configured to facilitate lateral electrical interconnections between laterally spaced conductive structures (e.g., between two or more laterally spaced vias). The wires (e.g., conductive wires or interconnect wires) may extend in a direction substantially parallel to the top surface of the substrate and may have a length or width, for example, greater than the height of the wire.

[0037] In some embodiments, a first ratio between the first vertical distance 135 and the height 209 of the capacitor structure 125 is in the range of approximately 0.008 to 0.11 or some other suitable value. In various embodiments, a first ratio greater than approximately 0.008 promotes increased capacitance of the capacitor structure 125 and promotes good electrical connection (e.g., ohmic contact) with the capacitor structure 125 and the overlying conductive structure (e.g., the first upper conductive inner connector 142). In yet another embodiment, a first ratio less than approximately 0.11 promotes substantially large capacitance of the capacitor structure 125 and promotes the capacitor structure 125 being configured in the same conductive interconnect level as the conductive inner connector 113. In yet another embodiment, a second ratio between the height 209 of the capacitor structure 125 and the conductive inner connector 113 is approximately 0.9, in the range of approximately 0.85 to 0.95, or some other suitable value. In some embodiments, a second ratio of approximately 0.9 promotes the capacitor structure 125 to be recessed below the first upper etch stop layer 116 and configured in the same conductive interconnect level as the conductive internal interconnect 113. As a result, manufacturing costs and complexity can be reduced and damage to the capacitor structure 125 can be prevented or mitigated.

[0038] The upper ILD structure 117 covers the dielectric structure 109 and the conductive internal connector 113. In some embodiments, the upper ILD structure 117 includes a first upper etch stop layer 116, a first upper dielectric layer 118 on the first upper etch stop layer 116, a second upper etch stop layer 120 on the first upper dielectric layer 118, and a second upper dielectric layer 122 on the second upper etch stop layer 120. In various embodiments, the first upper etch stop layer 116 covers and directly contacts the top surface of the dielectric structure 109 and the top surface of the conductive internal connector 113. The first upper etch stop layer 116 and the second upper etch stop layer 120 may be, for example, or include one or more of silicon nitride, silicon carbide, or the like. The first upper dielectric layer 118 and the second upper dielectric layer 122 may be, for example, or include one or more of oxides (e.g., silicon dioxide), low-k dielectric materials, or the like. In some embodiments, the thicknesses of the first upper etch stop layer 116 and the second upper etch stop layer 120 may be, for example, in the range of about 300 to 1,500 angstroms or some other suitable value. In a further embodiment, the thicknesses of the first and second upper dielectric layers 118, 122 are each greater than the thickness of one or more of the first and second upper etch stop layers 116, 120.

[0039] A plurality of upper conductive internal connectors 142, 144 are disposed in the upper ILD structure 117. A first upper conductive internal connector 142 of the plurality of upper conductive internal connectors 142, 144 extends through the upper ILD structure 117 to contact the upper surface 137 of the second electrode 136 of the capacitor structure 125. A second upper conductive internal connector 144 of the plurality of upper conductive internal connectors 142, 144 extends through the upper ILD structure 117 to contact a conductive internal connector 113. In some embodiments, the first upper conductive internal connector 142 and / or the second upper conductive internal connector 144 may respectively include an interconnect wire 208 and an interconnect via 206. In various embodiments, the first upper conductive internal connector 142 extends vertically through the entire thickness of the first upper etch stop layer 116 and at least a portion of the third dielectric layer 115, such that the bottom surface of the first upper conductive internal connector 142 is below the bottom surface of the first upper etch stop layer 116. The plurality of upper conductive inner connectors 142, 144 may be, for example, one or more of copper, tungsten, ruthenium, aluminum, copper or the like.

[0040] In various embodiments, the height 202 of the first upper conductive inner connector 142 is greater than the height 204 of the second upper conductive inner connector 144. In some embodiments, the difference between heights 202 and 204 is based on a first vertical distance 135 and / or the distance between the upper surface 137 of the second electrode 136 and the bottom surface of the first upper etch stop layer 116. In further embodiments, the heights 202 and 204 of the first and second upper conductive inner connectors 142 and 144 are each less than the height 209 of the capacitor structure 125 and / or the height 211 of the conductive inner connector 113. In some embodiments, the height 204 of the second upper conductive inner connector 144 is, for example, in the range of about 2,500 to 12,500 angstroms or some other suitable value. In some embodiments, the height 202 of the first upper conductive inner connector 142 is, for example, in the range of about 2,750 to 13,250 angstroms or some other suitable value.

[0041] In some embodiments, during the fabrication of the integrated chip, a capacitor structure 125 is formed in the dielectric structure 109 prior to the formation of conductive interconnects 113. After the formation of conductive interconnects 113, a plurality of upper conductive interconnects 142, 144 are formed in an upper ILD structure 117 above the conductive interconnects 113 and the capacitor structure 125. By forming the capacitor structure 125 first, the conductive interconnects 113 can be formed using a fabrication process not limited by the height of the capacitor structure 125, thereby increasing design flexibility. Furthermore, the height difference between the capacitor structure 125 and the conductive interconnects 113 is substantially small (e.g., less than about 500 angstroms), such that damage to the capacitor structure 125 from etching processes (e.g., dry etching) used to form the openings of the plurality of upper conductive interconnects 142, 144 is prevented or mitigated. Additionally, the height difference between the first upper conductive interconnect 142 and the second upper conductive interconnect 144 is substantially small (e.g., less than about 500 to 650 angstroms). This partially mitigates the break in the circuit between the multiple upper conductive internal connectors 142, 144 and the lower conductive layer (e.g., conductive internal connector 113).

[0042] In various embodiments, a first vertical distance 135 greater than about 200 angstroms facilitates the formation of conductive interconnects 113 in the dielectric structure 109 following the capacitor structure 125, while mitigating damage to the capacitor structure 125. For example, a planarization process (e.g., chemical mechanical planarization (CMP) process) used to form the conductive interconnects 113 may not adversely affect the layers of the capacitor structure 125. In a further embodiment, a first vertical distance 135 less than about 500 angstroms facilitates increased capacitance of the capacitor structure 125 while allowing the top surface of the capacitor structure 125 to be sufficiently close to the bottom surface of the first etch stop layer 116. As a result, the first etch stop layer 116 can be sufficiently close to the capacitor structure 125 to mitigate damage to the second electrode 136 during the fabrication of the plurality of upper conductive interconnects 142, 144.

[0043] Figure 2B Show Figure 2A Top view 200b of some embodiments of the integrated chip. Figure 2B The top view 200b can be viewed along Figure 2A The line A-A' is intercepted.

[0044] like Figure 2BAs shown, the multiple elongated vertical segments 222 appear circular when viewed from above. It should be understood that the multiple elongated vertical segments 222 may have other shapes when viewed from above, such as rectangular, polygonal, elliptical, etc. A portion of the second electrode 136 extends continuously around the multiple elongated vertical segments 222. Furthermore, the peripheral ring structure 220 extends continuously laterally around the multiple elongated vertical segments 222.

[0045] Figure 3A Show Figure 2A A cross-sectional view 300a of some other embodiments of the integrated chip shows that the upper ILD structure 117 further includes a third etch stop layer 302 and a third upper dielectric layer 304. The third etch stop layer 302 extends over a plurality of upper conductive interconnects 142, 144. The third upper dielectric layer 304 is disposed over the third etch stop layer 302. Furthermore, a second plurality of upper conductive interconnects 306 extend through the third upper dielectric layer 304 and the third etch stop layer 302 to contact the plurality of upper conductive interconnects 142, 144. In some embodiments, the second plurality of upper conductive interconnects each include interconnect vias and / or interconnect wires. The third etch stop layer 302 may be, for example, silicon nitride, silicon carbide, etc. The third upper dielectric layer 304 may be, for example, an oxide (e.g., silicon dioxide), a low-k dielectric material, etc.

[0046] Figure 3B Show Figure 3A Cross-sectional view 300b of some other embodiments of the integrated chip, wherein the first upper conductive inner connector 142 and the second upper conductive inner connector 144 are each configured as a single interconnect via. In various embodiments, the height 202 of the first upper conductive inner connector 142 and the height 204 of the second upper conductive inner connector 144 are each less than the height 211 of the conductive inner connector 113. In a further embodiment, the height 204 of the second upper conductive inner connector 144 may be approximately equal to or equal to the height 211 of the conductive inner connector 113. In various embodiments, the height 202 of the first upper conductive inner connector 142 may be greater than the height 211 of the conductive inner connector 113. In various embodiments, the second plurality of upper conductive inner connectors 306 may each include or be configured to have interconnect wires having a width greater than that of one of the underlying first and second upper conductive inner connectors 142, 144.

[0047] Figure 3C Show Figure 3BA cross-sectional view 300c of some other embodiments of the integrated chip shows that the conductive interconnect 113 includes a first interconnect via 308 and a first interconnect wire 310. In some embodiments, the first interconnect wire 310 extends continuously and vertically from the third dielectric layer 115 through the second etch stop layer 112. In various embodiments, the bottom surface of the first interconnect wire 310 is below the bottom surface of the second etch stop layer. In a further embodiment, the conductive interconnect 113 includes a single interconnect via and a single interconnect wire, such as... Figure 3C As shown in the diagram. The height of the first interconnect via 308 may, for example, be less than the height of the first interconnect conductor 310. It should be understood that although the conductive inner connector 113 is in Figure 3C It includes a first interconnect via 308 and a first interconnect wire 310, but Figure 1 , Figure 2A and Figures 3A-3B The conductive internal connector 113 of any one of them may include a first interconnecting via 308 and a first interconnecting wire 310.

[0048] Figure 4A Show Figure 2A Cross-sectional view 400a of some other embodiments of the integrated chip.

[0049] In some embodiments, capacitor structure 125 includes a plurality of vertical segments 125vs extending through dielectric structure 109 and laterally separated from each other through second dielectric layer 114. In some embodiments, the plurality of vertical segments 125vs extend vertically from the top surface of second dielectric layer 114 to a first lower conductive inner connector 106a, respectively. In various embodiments, the top surface of capacitor structure 125 is vertically offset from the top surface of conductive inner connector 113 by a first vertical distance 135. In some embodiments, the first vertical distance 135 is less than about 500 angstroms, in the range of about 200 to 500 angstroms, or some other suitable value. In various embodiments, the top surface of capacitor structure 125 is defined by the top surface of second electrode 136.

[0050] Figure 4B Show Figure 4A Top view 400b of some embodiments of the integrated chip. Figure 4B The top view 400b can be viewed along Figure 4A The line A-A' is intercepted.

[0051] like Figure 4BAs shown, the plurality of vertical segments 125vs appear circular when viewed from above. It should be understood that the plurality of vertical segments 125vs may have other shapes when viewed from above, such as rectangular, polygonal, elliptical, or similar shapes. A second dielectric layer 114 extends laterally continuously between adjacent vertical segments of the plurality of vertical segments 125vs. In various embodiments, the plurality of vertical segments 125vs have a cylindrical shape.

[0052] Figure 4C Show Figure 4A Top view 400c of some other embodiments of the integrated chip. Figure 4C The top view of 400c can be along Figure 4A The line A-A' is intercepted.

[0053] like Figure 4C As shown, a plurality of vertical segments 125vs are configured in a plurality of capacitor trenches, which extend laterally in a first direction (e.g., in the y-direction). In some embodiments, each of the vertical segments 125vs has an elongated sidewall extending in the first direction and a shorter sidewall extending in a second direction (e.g., in the x-direction) that is substantially orthogonal to the first direction.

[0054] Figure 5A Show Figure 4A A cross-sectional view 500a of some other embodiments of the integrated chip, wherein the second electrode 136 includes one or more inner surfaces defining the cavity 138.

[0055] Figure 5B Show Figure 5A Cross-sectional view 500b of some other embodiments of the integrated chip, wherein the heights 202, 204 of the first and second upper conductive inner connectors 142, 144 are greater than the heights 209, 211 of the capacitor structure 125 and the conductive inner connector 113. In various embodiments, the bottom surface of the second upper conductive inner connector 144 extends below the top surface of the conductive inner connector 113.

[0056] Figure 5C Show Figure 5A A cross-sectional view 500c of some further embodiments of the integrated chip shows that a plurality of lower conductive interconnects 106a-106b, conductive interconnect 113, and a plurality of upper conductive interconnects 142, 144 each include a conductive body structure 502 and a barrier layer 504. In various embodiments, the barrier layer 504 extends along opposite sidewalls and a lower surface of the conductive body structure 502. The barrier layer 504 may be, for example, or include one or more of titanium nitride, tantalum nitride, or the like. The conductive body structure 502 may be, for example, or include one or more of aluminum, copper, tungsten, ruthenium, or the like.

[0057] Figure 6 A cross-sectional view 600 shows some embodiments of an image sensor integrated chip including a capacitor structure and conductive interconnects according to the present disclosure.

[0058] The image sensor integrated chip includes a lower ILD structure 602 disposed along a first surface 102a of a substrate 102. In some embodiments, the lower ILD structure 602 includes a plurality of lower dielectric layers 615 and a plurality of lower etch stop layers 616. The lower dielectric layers 615 may be, for example, or include oxides (e.g., silicon dioxide), low-k dielectric materials, or the like. The plurality of lower etch stop layers 616 may be, for example, or include silicon nitride, silicon carbide, or the like. A plurality of conductive contacts 618, a plurality of lower interconnect wires 620, and a plurality of lower interconnect vias 622 are disposed in the lower ILD structure 602. The plurality of lower interconnect vias 622 are disposed between adjacent layers of the plurality of lower interconnect wires 620. A plurality of gate structures 606g, 610g, 612g, and 614g are disposed on the first surface 102a of the substrate 102.

[0059] A dielectric structure 109 is disposed on the lower ILD structure 602. In some embodiments, the dielectric structure 109 includes a first etch stop layer 108, a first dielectric layer 110 on the first etch stop layer 108, a second etch stop layer 112 on the first dielectric layer 110, a second dielectric layer 114 on the second etch stop layer 112, and a third dielectric layer 115 on the second dielectric layer 114. A capacitor structure 125 is disposed in the dielectric structure 109. The capacitor structure 125 includes a first electrode 132, a second electrode 136, and a capacitor dielectric 134 disposed between the first electrode 132 and the second electrode 136. In various embodiments, the first electrode 132 includes a conductive layer on a diffusion barrier layer. Furthermore, a conductive internal connector 113 is disposed in the dielectric structure 109. The conductive internal connector 113 is adjacent to the capacitor structure 125. The capacitor structure 125 and the conductive internal connector 113 may be configured as follows: Figure 1 The shown and / or described, but alternatively configured as follows: Figure 2A-2B Any one or a combination of 3A-3C, 4A-4C, and 5A-5C. In some embodiments, capacitor structure 125 is configured as a lateral overflow integration capacitor (LOFIC). In some embodiments, dielectric structure 109 is referred to as a middle-of-line (MOL) structure or the like.

[0060] The upper ILD structure 117 covers the dielectric structure 109. In some embodiments, the upper ILD structure 117 includes a first upper etch stop layer 116, a first upper dielectric layer 118 on the first upper etch stop layer 116, a second upper etch stop layer 120 on the first upper dielectric layer 118, and a second upper dielectric layer 122 on the second upper etch stop layer 120. A plurality of upper conductive internal connectors 142, 144 are disposed above the capacitor structure 125 and the conductive internal connectors 113 in the upper ILD structure 117.

[0061] An image sensing element 604, a floating diffusion well 608, and a plurality of transistors 610, 612, 614 are disposed on and / or within a substrate 102. An isolation structure 624 is disposed between the transistors 610, 612, 614 in the substrate 102. In some embodiments, the image sensing element 604 includes a first region having a first doping type (e.g., n-type doping), the first region being adjacent to a second region having a second doping type different from the first doping type (e.g., p-type doping). The image sensing element 604 may be, for example, a photodiode. A plurality of gate structures 606g, 610g, 612g, 614g have a gate dielectric layer disposed along a first surface 102a of the substrate 102 and gate electrodes disposed on the gate dielectric layer. In some embodiments, sidewall spacers are disposed on opposite sides of the gate electrodes.

[0062] In some embodiments, a transfer transistor gate structure 606g is laterally disposed between an image sensing element 604 and a floating diffusion well 608. The transfer transistor gate structure 606g is configured to control charge transfer from the image sensing element 604 to the floating diffusion well 608. The floating diffusion well 608 is coupled to a first source / drain region of a source follower transistor gate structure 612g and a capacitor switching transistor 610. The source / drain region may refer to either a source or a drain, depending on whether the context is individual or collective. In some embodiments, a source follower transistor 612 is coupled between a row select transistor 614 and a voltage node (e.g., a node coupled to a power supply), wherein the source follower transistor 612 is configured to buffer and amplify the voltage at the floating diffusion well 608. The column select transistor 614 is configured to selectively deliver the buffered and amplified voltage from the source follower transistor 612 to an output terminal. A second source / drain region of the capacitor switching transistor 610 is coupled to a capacitor structure 125. Furthermore, in some embodiments, the conductive internal connector 113 is directly coupled to the source / drain region of the column select transistor 614, providing an output signal corresponding to the charge accumulated at the image sensing element 604. In various embodiments, the conductive internal connector 113 may be referred to as an in-pixel via, a pixel output internal connector, etc.

[0063] In some embodiments, the capacitor switching transistor 610 is configured to switch the image sensing element 604 between a low conversion gain mode and a high conversion gain mode. For example, when operating in a low conversion gain mode, the capacitor switching transistor 610 is closed (e.g., ON), causing the capacitor structure 125 to couple to the floating diffusion well 608. In this case, charge at the floating diffusion well 608 overflows into the capacitor structure 125. When operating in a high conversion gain mode, the capacitor switching transistor 610 is turned on (e.g., OFF), isolating the capacitor structure 125 from the floating diffusion well 608. The plurality of gate structures 606g, 610g, 612g, 614g, the source / drain regions of the plurality of transistors 610, 612, 614, and the capacitor structure 125 are operably coupled to each other via a plurality of conductive contacts 618, a plurality of interconnect wires 620, and a plurality of lower interconnect vias 622.

[0064] Figure 7-21 Cross-sectional views are shown of some embodiments of a method for forming an integrated chip including a capacitor structure and conductive interconnects according to the present disclosure. Although Figure 7-21 It concerns the method description; it should be understood. Figure 7-21 The structure revealed in the paper is not limited to this method, but can exist independently of the method.

[0065] like Figure 7 As shown in cross-sectional view 700, a plurality of lower conductive internal interconnects 106a-106b are formed within a lower ILD structure 104 above a substrate 102. The substrate 102 may be, for example, or include a bulk substrate (e.g., a bulk silicon substrate), a silicon-on-insulator (SOI) substrate, a silicon-germanium substrate, a semiconductor wafer, or another suitable semiconductor substrate. In some embodiments, the plurality of lower conductive internal interconnects 106a-106b may be, or include, one or more of conductive contacts, interconnect wires, and / or interconnect vias.

[0066] In some embodiments, a plurality of lower conductive interconnects 106a-106b may be formed using a damascene process (e.g., a single damascene process or a dual damascene process). In various embodiments, the plurality of lower conductive interconnects 106a-106b may be formed by: depositing a lower ILD structure 104 over a substrate 102; selectively etching the lower ILD structure 104 to define vias and / or wire trenches within the lower ILD structure 104; depositing one or more conductive materials (e.g., copper, aluminum, etc.) within the vias and / or wire trenches; and performing a planarization process (e.g., a chemical mechanical planarization (CMP) process) to remove excess portions of one or more conductive materials from over the lower ILD structure 104.

[0067] like Figure 8 As shown in cross-sectional view 800, a dielectric structure 109 is formed above the lower ILD structure 104. In some embodiments, the dielectric structure 109 includes a first etch stop layer 108, a first dielectric layer 110, a second etch stop layer 112, and a second dielectric layer 114. The first etch stop layer 108 is formed above the lower ILD structure 104. The first dielectric layer 110 is formed above the first etch stop layer 108. The second etch stop layer 112 is formed above the first dielectric layer 110. The second dielectric layer 114 is formed above the second etch stop layer 112. The first etch stop layer 108 and the second etch stop layer 112 may, for example, be or comprise silicon nitride, silicon carbide, or similar materials. The first dielectric layer 110 and the second dielectric layer 114 may, for example, be or comprise oxides (e.g., silicon dioxide), low-k dielectric materials, or similar materials. The first etch stop layer, the first dielectric layer 110, the second etch stop layer 112, and the second dielectric layer 114 can each be formed by a deposition process, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or similar processes.

[0068] like Figure 9 As shown in cross-sectional view 900, a first patterning process is performed on dielectric structure 109 to form a plurality of first capacitor openings 904 within dielectric structure 109. The plurality of first capacitor openings 904 extend through a second dielectric layer 114, a second etch stop layer 112, a first dielectric layer 110, and a first etch stop layer 108. In some embodiments, the first patterning process includes: forming a first mask 902 on dielectric structure 109; performing an etching process (e.g., reactive ion etching, plasma etching, etc.) on dielectric structure 109 with the first mask 902 in place; and removing the first mask 902. The first mask 902 may be, for example, or include photoresist, a hard mask, or a similar material. In various embodiments, the plurality of first capacitor openings 904 expose the upper surface of a first lower conductive internal interconnect 106a.

[0069] like Figure 10 As shown in cross-sectional view 1000, a diffusion barrier layer 126 and a conductive layer 128 are formed as liners within a plurality of first capacitor openings 904. In some embodiments, the diffusion barrier layer 126 is formed along one or more surfaces of the dielectric structure 109 to define the plurality of first capacitor openings 904, and the conductive layer 128 is formed over the diffusion barrier layer 126. The diffusion barrier layer 126 and the conductive layer 128 may each be formed by a deposition process, such as PVD, CVD, ALD, or similar processes. The diffusion barrier layer 126 may be, for example, or include tantalum, tantalum nitride, tungsten nitride, or similar materials. The conductive layer 128 may be, for example, or include copper, aluminum, titanium, titanium nitride, tungsten, or similar materials.

[0070] like Figure 11 As shown in cross-sectional view 1100, a second patterning process is performed on the diffusion barrier layer 126 and the conductive layer 128 to expose the upper surface of one or more segments 1104 of the dielectric structure 109 between the plurality of first capacitor openings 904. In some embodiments, the second patterning process includes: forming a second mask 1102 on a region of the conductive layer 128 laterally offset from the plurality of first capacitor openings 904; performing an etching process (e.g., RIE process, plasma etching process, etc.) on the conductive layer 128 and the diffusion barrier layer 126 with the second mask 1102 in place; and removing the second mask 1102. In various embodiments, the second patterning process is performed such that the diffusion barrier layer 126 and the conductive layer 128 are removed from the upper surface of one or more segments 1104 without being removed from one or more surfaces of the dielectric structure 109 defining the plurality of first capacitor openings 904. The second mask 1102 may be, for example, or include photoresist, a hard mask, or a similar material.

[0071] like Figure 12 As shown in cross-sectional view 1200, a third patterning process is performed on the second dielectric layer 114 to remove a portion of the second dielectric layer 114 from above the second etch stop layer 112, thereby defining one or more second capacitor openings 1202. In some embodiments, the third patterning process includes performing a wet etching process on the portion of the second dielectric layer 114 above the second etch stop layer 112. In some embodiments, the wet etching process includes exposing the second dielectric layer 114 to one or more wet etchants (e.g., hydrofluoric acid, or similar etchants).

[0072] like Figure 13 As shown in the cross-sectional view 1300, a first capacitor dielectric layer 201, a second capacitor dielectric layer 203, and a second electrode layer 1302 are formed in a plurality of first capacitor openings ( Figure 12 The first capacitor opening 904) and one or more second capacitor openings ( Figure 12The second capacitor opening 1202 is located within the second capacitor. A first capacitor dielectric layer 201 is formed over and lining the conductive layer 128. A second capacitor dielectric layer 203 is formed over the first capacitor dielectric layer 201. A second electrode layer 1302 is formed over the second capacitor dielectric layer 203. In some embodiments, the second electrode layer 1302 includes one or more inner surfaces to define one or more cavities 138. In some embodiments, the one or more cavities 138 are air gaps including air. In other embodiments, the one or more cavities 138 include silicon dioxide, silicon germanium, or similar materials. The first capacitor dielectric layer 201 may be, for example, titanium oxide, tantalum oxide, or similar materials. The second capacitor dielectric layer 203 may be, for example, zirconium oxide, hafnium oxide, aluminum oxide, lead oxide, or similar materials. The second electrode layer 1302 may be, for example, copper, aluminum, titanium, titanium nitride, tungsten, or similar materials.

[0073] like Figure 14 As shown in the cross-sectional view 1400, in the second electrode layer ( Figure 13 A fourth patterning process is performed on the second electrode layer 1302 to define the second electrode 136. Furthermore, sidewall spacers 140 are formed along the opposing sidewalls of the second electrode 136. In some embodiments, the fourth patterning process includes: on the second electrode layer (… Figure 13 A third mask 1402 is formed above the second electrode layer 1302; with the third mask 1402 in place, the second electrode layer ( Figure 13 The etching process (e.g., RIE process, plasma etching process, etc.) is performed on the second electrode layer 1302; and the third mask 1402 is removed. The third mask 1402 may be, for example, photoresist, a hard mask, or a similar material. In various embodiments, the sidewall spacers 140 are formed after the third mask 1402 is removed.

[0074] like Figure 15As shown in cross-sectional view 1500, a fifth patterning process is performed on the second capacitor dielectric layer 203, the first capacitor dielectric layer 201, the conductive layer 128, and the diffusion barrier layer 126 to define a capacitor structure 125. The capacitor structure 125 includes a first electrode 132, a capacitor dielectric 134, and a second electrode 136. The capacitor dielectric 134 includes the first and second capacitor dielectric layers 201 and 203. The first electrode 132 includes the diffusion barrier layer 126 and the conductive layer 128. In some embodiments, the fifth patterning process includes: forming a fourth mask 1502 on the second electrode 136; performing one or more etching processes (e.g., one or more RIE processes, one or more plasma etching processes, etc.) on the second capacitor dielectric layer 203, the first capacitor dielectric layer 201, the conductive layer 128, and the diffusion barrier layer 126 with the fourth mask 1502 in place; and removing the fourth mask 1502. The fourth mask 1502 may be, for example, or include photoresist, a hard mask, or a similar material.

[0075] like Figure 16 As shown in cross-sectional view 1600, a third dielectric layer 115 is formed above capacitor structure 125. In various embodiments, the third dielectric layer 115 is the top layer of dielectric structure 109. The third dielectric layer 115 may be, for example, an oxide (e.g., silicon dioxide), a low-k dielectric material, or a similar material. The third dielectric layer 115 may be formed, for example, by a CVD process, a PVD process, an ALD process, or a similar process. In various embodiments, the top surface of capacitor structure 125 is perpendicularly offset from the top surface of third dielectric layer 115 by a first vertical distance 135. In some embodiments, the first vertical distance 135 is less than about 500 angstroms, in the range of about 200 to 500 angstroms, or some other suitable value. In some embodiments, the first dielectric layer 110, the second dielectric layer 114, and the third dielectric layer 115 may comprise the same material (e.g., silicon dioxide).

[0076] like Figure 17 As shown in cross-sectional view 1700, a sixth patterning process is performed on dielectric structure 109 to form an interconnect opening 1704 extending through dielectric structure 109 and adjacent to capacitor structure 125. In various embodiments, interconnect opening 1704 exposes the upper surface of second lower conductive inner interconnect 106b. In some embodiments, the sixth patterning process includes: forming a fifth mask 1702 on dielectric structure 109; performing an etching process (e.g., RIE process, plasma etching process, etc.) on dielectric structure 109 with fifth mask 1702 in place; and removing fifth mask 1702. Fifth mask 1702 may be, for example, or include photoresist, hard mask, or similar materials.

[0077] like Figure 18As shown in the cross-sectional view 1800, the conductive inner connector 113 is formed in the interconnect opening ( Figure 17 Within the interconnect opening 1704. The conductive inner connector 113 is laterally adjacent to the capacitor structure 125 and extends through the dielectric structure 109 to contact the second lower conductive inner connector 106b. In some embodiments, the conductive inner connector 113 is formed within the interconnect opening ( Figure 17 One or more conductive materials are formed (e.g., by CVD, PVD, electroplating, electroless plating, etc.) in the interconnect opening 1704 and over the dielectric structure 109, and a planarization process (e.g., CMP process) is performed on the one or more conductive materials. In some embodiments, the one or more conductive materials may be, for example, aluminum, copper, tungsten, titanium nitride, tantalum nitride, or similar materials. Furthermore, forming one or more conductive materials may include forming a liner in the interconnect opening (…). Figure 17 A barrier layer (e.g., including titanium nitride, tantalum nitride, etc.) is formed on the interconnect opening 1704, and a conductive substrate (e.g., including copper, aluminum, tungsten, etc.) is formed on the barrier layer and the interconnect opening is filled. Figure 17 The remaining portion of the interconnect opening 1704. In some embodiments, the top surface of the conductive inner connector 113 is located above the top surface of the capacitor structure 125, for example, at a first vertical distance 135. In a further embodiment, the height of the capacitor structure 125 is less than the height of the conductive inner connector 113. In yet another further embodiment, the top surface of the conductive inner connector 113 is coplanar with the top surface of the third dielectric layer 115.

[0078] In some embodiments, the process of forming the capacitor structure 125 includes Figure 9-15 The steps shown and / or described herein, and the process for forming the conductive internal interconnect 113 includes Figure 17-18 The steps shown and / or described are as follows. In various embodiments, the capacitor structure 125 is formed in the dielectric structure 109 prior to the formation of the conductive internal interconnect 113. As a result, manufacturing complexity is reduced. For example, the conductive internal interconnect can be formed in the dielectric structure 109 in various configurations and through manufacturing steps and / or processes not limited by the manufacturing of the capacitor structure 125. In some embodiments, the height of the conductive internal interconnect 113 is greater than the height of the capacitor structure 125, thereby increasing design flexibility. In various embodiments, the conductive internal interconnect 113 includes a single interconnect via. In another embodiment, the conductive internal interconnect 113 includes a single interconnect wire above the single interconnect via. The bottom surface of the capacitor structure 125 may be substantially aligned with the bottom surface of the conductive internal interconnect 113.

[0079] like Figure 19As shown in cross-sectional view 1900, an upper ILD structure 117 is formed above the dielectric structure 109 and the conductive internal interconnect 113. In some embodiments, the upper ILD structure 117 includes a first upper etch stop layer 116, a first upper dielectric layer 118, a second upper etch stop layer 120, and a second upper dielectric layer 122. The first upper etch stop layer 116 is formed on the top surface of the third dielectric layer 115 and the top surface of the conductive internal interconnect 113. The first upper dielectric layer 118 is formed on the first upper etch stop layer 116. The second upper etch stop layer 120 is formed on the first upper dielectric layer 118. The second upper dielectric layer 122 is formed on the second upper etch stop layer 120. The first upper etch stop layer 116 and the second upper etch stop layer 120 may, for example, respectively include silicon nitride, silicon carbide, or the like. The first upper dielectric layer 118 and the second upper dielectric layer 122 may, for example, be or comprise oxides (e.g., silicon dioxide), low-k dielectric materials, or the like. The first upper etch stop layer 116, the first upper dielectric layer 118, the second upper etch stop layer 120, and the second upper dielectric layer 122 may each be formed by a deposition process, such as PVD, CVD, ALD, or the like.

[0080] like Figure 20 As shown in cross-sectional view 2000, a seventh patterning process is performed on the upper ILD structure 117 to form a plurality of upper interconnect openings 2004. The plurality of upper interconnect openings 2004 extend through the upper ILD structure 117 and / or the third dielectric layer 115 to expose the upper surface 137 of the second electrode 136 and the upper surface of the conductive internal interconnect 113. In some embodiments, the seventh patterning process includes: forming a sixth mask 2002 on the upper ILD structure 117; performing an etching process (e.g., RIE process, plasma etching process, etc.) on the upper ILD structure 117 with the sixth mask 2002 in place; and removing the sixth mask 2002. The sixth mask 2002 may be, for example, or include photoresist, a hard mask, or the like. In various embodiments, the plurality of upper interconnect openings 2004 each include a wire trench above a via. The etching process may include, for example, exposing the unmasked portion of the upper ILD structure 117 to one or more etchants (e.g., one or more of fluorine, tetrafluoromethane, ozone, etc.).

[0081] In some embodiments, the top surface of the capacitor structure 125 is directly overlaid with the first upper etch stop layer 116 to mitigate damage to the second electrode 136 during the seventh patterning process. In various embodiments, the first vertical distance 135 is relatively short (e.g., less than about 500 angstroms), thereby increasing the ability of the first upper etch stop layer 116 to protect the capacitor structure 125 during the seventh patterning process. This facilitates the omission of forming an overlay etch stop layer (not shown) on the second electrode 136, thereby saving one or more deposition processes and / or one or more patterning processes and reducing fabrication complexity.

[0082] like Figure 21 As shown in cross-sectional view 2100, multiple upper conductive inner connectors 142, 144 are formed in multiple upper interconnecting openings ( Figure 20 The upper interconnect opening 2004 is located within the upper interconnect opening. A plurality of upper conductive inner connectors 142, 144 include a first upper conductive inner connector 142 disposed on the second electrode 136 and a second upper conductive inner connector 144 disposed on the conductive inner connector 113. In some embodiments, the plurality of upper conductive inner connectors 142, 144 are formed within the upper interconnect opening ( Figure 20 One or more conductive materials are formed (e.g., by CVD, PVD, electroplating, electroless plating, etc.) in the upper interconnect opening 2004 and above the upper ILD structure 117, and a planarization process (e.g., CMP process) is performed on the one or more conductive materials. In some embodiments, the one or more conductive materials may be, for example, aluminum, copper, tungsten, titanium nitride, tantalum nitride, or the like. Furthermore, forming one or more conductive materials may include forming a liner in the upper interconnect opening (2004). Figure 20 The upper interconnect opening 2004) has a barrier layer (e.g., including titanium nitride, tantalum nitride, etc.) and a conductive host structure (e.g., including copper, aluminum, tungsten, etc.) formed on the barrier layer and filled with the upper interconnect opening. Figure 20 The remaining portion of the upper interconnection opening (2004).

[0083] In various embodiments, a plurality of upper conductive inner connectors 142, 144 each include an upper interconnect wire 208 located above the upper interconnect via 206. Furthermore, the height 202 of the first upper conductive inner connector 142 is greater than the height 204 of the second upper conductive inner connector 144. In some embodiments, the plurality of upper conductive inner connectors 142, 144 are formed simultaneously with each other.

[0084] Figure 22 Flowcharts are shown for some embodiments of a method 2200 for forming an integrated chip including a capacitor structure and conductive interconnects according to the present disclosure.

[0085] Although the disclosed method 2200 is shown and described herein as a series of steps or events, it should be understood that the order in which such steps or events are shown should not be interpreted in a limiting sense. For example, in addition to the steps or events shown and / or described herein, some steps may occur in a different order and / or simultaneously with other steps or events. Furthermore, not all of the steps shown may be necessary to implement one or more of the states or embodiments described herein. Moreover, one or more of the steps depicted herein may be performed as one or more separate steps and / or stages.

[0086] In step 2202, a lower conductive internal connector is formed within a lower interlayer dielectric (ILD) structure above the substrate. Figure 7 A cross-sectional view 700 is shown, corresponding to some embodiments of step 2202.

[0087] In step 2204, a dielectric structure is formed above the lower ILD structure. Figure 8 A cross-sectional view 800 is shown, corresponding to some embodiments of step 2204.

[0088] In step 2206, a capacitor structure is formed along the surface of the dielectric structure to define one or more capacitor openings. Figure 9-15 Cross-sectional views 900-1500 are shown for some embodiments corresponding to step 2206.

[0089] In step 2208, a conductive internal connector is formed in the dielectric structure and laterally adjacent to the capacitor structure. Figure 17-18 Cross-sectional views 1700-1800 are shown for some embodiments corresponding to step 2208.

[0090] In step 2210, an upper ILD structure is formed having a first upper etch stop layer above the dielectric structure and the conductive internal interconnect, wherein the top surface of the capacitor structure is recessed below the first upper etch stop layer. Figure 19 Cross-sectional view 1900 shows some embodiments corresponding to step 2210.

[0091] In step 2212, a plurality of upper conductive internal connectors are formed within the upper ILD structure and above the capacitor structure and the conductive internal connectors. Figure 20-21 Cross-sectional views 2000-2100 are shown for some embodiments corresponding to step 2212.

[0092] Therefore, in some embodiments, this disclosure relates to an integrated chip and a method of forming the same, which includes forming a capacitor structure in a dielectric structure and forming a conductive internal interconnect in the dielectric structure adjacent to the capacitor structure, wherein the capacitor structure is formed prior to the conductive internal interconnect.

[0093] In some embodiments, an integrated chip includes: a dielectric structure overlaid on a substrate and including a plurality of surfaces defining one or more capacitor openings; a conductive interconnect located in the dielectric structure and laterally adjacent to the one or more capacitor openings; an upper etch stop layer extending above the top surface of the dielectric structure and contacting the top surface of the conductive interconnect; and a capacitor structure lining the plurality of surfaces defining the one or more capacitor openings, wherein the capacitor structure includes a first electrode, a second electrode, and a capacitor dielectric disposed between the first electrode and the second electrode, wherein the top surface of the capacitor structure is perpendicularly offset from the bottom surface of the upper etch stop layer by a first distance in a direction toward the substrate, and wherein the bottom surface of the capacitor structure is substantially aligned with the bottom surface of the conductive interconnect.

[0094] In some embodiments, the upper segment of the dielectric structure extends continuously from the top surface of the capacitor structure to the bottom surface of the upper etch stop layer, wherein the thickness of the upper etch stop layer is greater than the first distance. In some embodiments, it further includes: a first upper conductive inner connector contacting the capacitor structure and extending through the upper etch stop layer and the dielectric structure, wherein the first upper conductive inner connector has a first height; and a second upper conductive inner connector contacting the conductive inner connector and extending through the upper etch stop layer, wherein the second upper conductive inner connector has a second height less than the first height. In some embodiments, the top surface of the first upper conductive inner connector is aligned with the top surface of the second upper conductive inner connector. In some embodiments, the first upper conductive inner connector and the second upper conductive inner connector each include an interconnect conductor located above an interconnect via, wherein the conductive inner connector is a single interconnect via continuously extending through the dielectric structure. In some embodiments, the height of the interconnect via of the first upper conductive inner connector is greater than the height of the interconnect via of the second upper conductive inner connector. In some embodiments, a first vertical distance between the bottom surface of the dielectric structure and the top surface of the capacitor structure is less than a second vertical distance between the bottom surface of the dielectric structure and the top surface of the conductive interconnect, wherein the ratio between the first vertical distance and the second vertical distance is in the range of approximately 0.85 to 0.95. In some embodiments, the dielectric structure includes a first etch stop layer, a first dielectric layer on the first etch stop layer, a second etch stop layer on the first dielectric layer, a second dielectric layer on the second etch stop layer, and a third dielectric layer on the second dielectric layer, wherein the conductive interconnect extends continuously through the first etch stop layer, the first dielectric layer, the second etch stop layer, the second dielectric layer, and the third dielectric layer, and wherein the top surface of the conductive interconnect is aligned with the top surface of the third dielectric layer. In some embodiments, the capacitor structure includes one or more first vertical segments extending through the first etch stop layer, the first dielectric layer, the second etch stop layer, and the second dielectric layer, wherein the capacitor structure includes one or more second vertical segments disposed in the second dielectric layer and located on the top surface of the second etch stop layer, wherein a first height of the one or more first vertical segments is greater than a second height of the one or more second vertical segments.

[0095] In some embodiments, a method for forming an integrated chip includes: forming a dielectric structure over a substrate; performing a first patterning process on the dielectric structure to form one or more capacitor openings extending through the dielectric structure; forming a capacitor structure in the one or more capacitor openings, wherein the capacitor structure includes a first electrode, a second electrode, and a capacitor dielectric located between the first electrode and the second electrode; performing a second patterning process on the dielectric structure to form interconnect openings extending through the dielectric structure, wherein the interconnect openings are laterally adjacent to the capacitor structure, wherein the second patterning process is performed after forming the capacitor structure; and forming conductive interconnects in the interconnect openings, wherein a first height of the conductive interconnects is greater than a second height of the capacitor structure, wherein the bottom surface of the conductive interconnects is substantially aligned with the bottom surface of the capacitor structure.

[0096] In some embodiments, the ratio between the second height and the first height is in the range of 0.85 to 0.95. In some embodiments, the method further includes depositing a dielectric layer over the capacitor structure prior to performing the second patterning process, wherein the dielectric layer contacts the top surface of the capacitor structure. In some embodiments, the method further includes depositing an upper etch stop layer over the capacitor structure, wherein the upper etch stop layer directly contacts the top surface of the dielectric layer and the top surface of the conductive interconnect, wherein the top surface of the capacitor structure is recessed below the bottom surface of the upper etch stop layer. In some embodiments, the method further includes forming an upper dielectric structure over the dielectric structure; forming a first upper conductive interconnect in the upper dielectric structure and over the capacitor structure; and forming a second upper conductive interconnect in the upper dielectric structure and over the conductive interconnect, wherein the top surface of the first upper conductive interconnect is aligned with the top surface of the second upper conductive interconnect, wherein a third height of the first upper conductive interconnect is greater than a fourth height of the second upper conductive interconnect. In some embodiments, the second patterning process is performed after the capacitor structure is formed, and the interconnect openings extend through the entire thickness of the dielectric structure.

[0097] In some embodiments, a method of forming an integrated chip includes: forming a plurality of lower conductive interconnects over a substrate; forming a dielectric structure over the plurality of lower conductive interconnects, wherein the dielectric structure includes a first etch stop layer, a first dielectric layer, a second etch stop layer, and a second dielectric layer, wherein the first dielectric layer is located between the first etch stop layer and the second etch stop layer, and the second dielectric layer covers the second etch stop layer; etching the dielectric structure to form one or more capacitor openings extending through the dielectric structure, wherein the one or more capacitor openings expose the plurality of lower conductive interconnects. The upper surface of the first lower conductive internal connector is exposed and the upper surface of the second etch stop layer is exposed; a capacitor structure is formed in the one or more capacitor openings, wherein the capacitor structure contacts the upper surface of the first lower conductive internal connector and the upper surface of the second etch stop layer; a third dielectric layer is deposited on the second dielectric layer and the capacitor structure, wherein the top surface of the third dielectric layer is directly above the top surface of the capacitor structure; and a conductive internal connector is formed extending through the dielectric structure and the third dielectric layer, wherein the top surface of the conductive internal connector is aligned with the top surface of the third dielectric layer.

[0098] In some embodiments, the method further includes: forming a first upper conductive inner connector above the capacitor structure, wherein the bottom surface of the first upper conductive inner connector is located below the top surface of the third dielectric layer; and forming a second upper conductive inner connector above the conductive inner connector, wherein the bottom surface of the second upper conductive inner connector is located above the top surface of the capacitor structure. In some embodiments, the first upper conductive inner connector and the second upper conductive inner connector are formed simultaneously. In some embodiments, the third dielectric layer directly contacts the opposite sidewall of the first upper conductive inner connector, and the second upper conductive inner connector is separated from the third dielectric layer through the conductive inner connector. In some embodiments, the vertical offset between the top surface of the capacitor structure and the top surface of the third dielectric layer is in the range of 200 to 500 angstroms.

[0099] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. An integrated chip, comprising: A dielectric structure, overlaid on a substrate and including multiple surfaces defining one or more capacitor openings; A conductive internal connector is located in the dielectric structure and laterally adjacent to the one or more capacitor openings; An upper etching stop layer extends above the top surface of the dielectric structure and contacts the top surface of the conductive internal connector; as well as A capacitor structure lining a plurality of surfaces defining one or more capacitor openings, wherein the capacitor structure includes a first electrode, a second electrode, and a capacitor dielectric disposed between the first electrode and the second electrode, wherein the top surface of the capacitor structure is perpendicularly offset from the bottom surface of the upper etch stop layer by a first distance in a direction toward the substrate, and wherein the bottom surface of the capacitor structure is aligned with the bottom surface of the conductive internal interconnect.

2. The integrated chip according to claim 1, wherein the upper segment of the dielectric structure extends continuously from the top surface of the capacitor structure to the bottom surface of the upper etch stop layer, wherein the thickness of the upper etch stop layer is greater than the first distance.

3. The integrated chip according to claim 1, further comprising: A first upper conductive inner connector contacts the capacitor structure and extends through the upper etch stop layer and the dielectric structure, wherein the first upper conductive inner connector has a first height; as well as A second upper conductive inner connector contacts the conductive inner connector and extends through the upper etch stop layer, wherein the second upper conductive inner connector has a second height that is less than the first height.

4. The integrated chip of claim 1, wherein the first vertical distance between the bottom surface of the dielectric structure and the top surface of the capacitor structure is less than the second vertical distance between the bottom surface of the dielectric structure and the top surface of the conductive internal interconnect, wherein the ratio between the first vertical distance and the second vertical distance is in the range of approximately 0.85 to 0.

95.

5. The integrated chip of claim 1, wherein the dielectric structure comprises a first etch stop layer, a first dielectric layer on the first etch stop layer, a second etch stop layer on the first dielectric layer, a second dielectric layer on the second etch stop layer, and a third dielectric layer on the second dielectric layer, wherein the conductive interconnect extends continuously through the first etch stop layer, the first dielectric layer, the second etch stop layer, the second dielectric layer, and the third dielectric layer, and wherein the top surface of the conductive interconnect is aligned with the top surface of the third dielectric layer.

6. A method for forming an integrated chip, comprising: A dielectric structure is formed above the substrate; The dielectric structure is subjected to a first patterning process to form one or more capacitor openings extending through the dielectric structure; A capacitor structure is formed in one or more capacitor openings, wherein the capacitor structure includes a first electrode, a second electrode, and a capacitor dielectric located between the first electrode and the second electrode; A second patterning process is performed on the dielectric structure to form interconnect openings extending through the dielectric structure, wherein the interconnect openings laterally abut the capacitor structure, and wherein the second patterning process is performed after the capacitor structure is formed; and A conductive internal connector is formed in the interconnection opening, wherein a first height of the conductive internal connector is greater than a second height of the capacitor structure, and wherein the bottom surface of the conductive internal connector is aligned with the bottom surface of the capacitor structure.

7. The method according to claim 6, further comprising: Prior to the second patterning process, a dielectric layer is deposited over the capacitor structure, wherein the dielectric layer contacts the top surface of the capacitor structure.

8. The method according to claim 6, further comprising: An upper dielectric structure is formed above the dielectric structure; A first upper conductive inner connector is formed in the upper dielectric structure and above the capacitor structure; as well as A second upper conductive inner connector is formed in the upper dielectric structure and above the conductive inner connector, wherein the top surface of the first upper conductive inner connector is aligned with the top surface of the second upper conductive inner connector, and wherein the third height of the first upper conductive inner connector is greater than the fourth height of the second upper conductive inner connector.

9. A method for forming an integrated chip, comprising: Multiple lower conductive internal interconnects are formed above the substrate; A dielectric structure is formed above the plurality of lower conductive internal connectors, wherein the dielectric structure includes a first etch stop layer, a first dielectric layer, a second etch stop layer and a second dielectric layer, wherein the first dielectric layer is located between the first etch stop layer and the second etch stop layer, and the second dielectric layer covers the second etch stop layer. The dielectric structure is etched to form one or more capacitor openings extending through the dielectric structure, wherein the one or more capacitor openings expose the upper surface of the first lower conductive interconnect of the plurality of lower conductive interconnects and expose the upper surface of the second etch stop layer. A capacitor structure is formed in one or more capacitor openings, wherein the capacitor structure contacts the upper surface of the first lower conductive inner connector and the upper surface of the second etch stop layer. A third dielectric layer is deposited on the second dielectric layer and the capacitor structure, wherein the top surface of the third dielectric layer is directly above the top surface of the capacitor structure; as well as A conductive internal connector is formed extending through the dielectric structure and the third dielectric layer, wherein the top surface of the conductive internal connector is aligned with the top surface of the third dielectric layer.

10. The method of claim 9, further comprising: A first upper conductive inner connector is formed above the capacitor structure, wherein the bottom surface of the first upper conductive inner connector is located below the top surface of the third dielectric layer; as well as A second upper conductive inner connector is formed above the conductive inner connector, wherein the bottom surface of the second upper conductive inner connector is located above the top surface of the capacitor structure.

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