Photoelectric conversion device and apparatus

Abstract

The present disclosure relates to a photoelectric conversion device and apparatus. The photoelectric conversion device includes: a first photoelectric conversion unit; a floating diffusion region; a first transfer transistor configured to transfer electric charges from the first photoelectric conversion unit to the floating diffusion region; a first wiring connected to a gate electrode of the first transfer transistor; a second wiring connected to the floating diffusion region; a third wiring to which a predetermined potential is applied; a fourth wiring arranged at least partially side by side with the third wiring and generating a capacitance with the third wiring; and a capacitance addition transistor having a first main electrode connected to the floating diffusion region and a second main electrode connected to the fourth wiring. In a plan view of a semiconductor substrate, the fourth wiring is arranged between the first wiring and the second wiring.

Description

Technical Field

[0001] This disclosure relates to photoelectric conversion devices. Background Technology

[0002] International Publication No. WO2016 / 098624 discloses a photoelectric conversion device including a photodiode and a transfer gate that transfers charge from the photodiode to a floating diffusion region. Summary of the Invention

[0003] According to one aspect of this disclosure, a photoelectric conversion device is provided, comprising: a semiconductor substrate; a first photoelectric conversion unit formed in the semiconductor substrate; a floating diffusion region formed in the semiconductor substrate; a first transfer transistor formed in the semiconductor substrate and configured to transfer charge from the first photoelectric conversion unit to the floating diffusion region; a first wiring connected to the gate electrode of the first transfer transistor; a second wiring connected to the floating diffusion region; a third wiring to which a predetermined potential is applied; a fourth wiring arranged at least partially alongside the third wiring and forming a capacitance with the third wiring; and a capacitor-attached transistor formed in the semiconductor substrate and having a first main electrode connected to the floating diffusion region and a second main electrode connected to the fourth wiring. In a plan view of the semiconductor substrate, the fourth wiring is arranged between the first and second wirings.

[0004] The features of this disclosure will become apparent from the following description of embodiments with reference to the accompanying drawings. The following description of the embodiments is given by way of example. Attached Figure Description

[0005] Figure 1 This is a block diagram illustrating an example of the overall configuration of the photoelectric conversion device according to the first embodiment.

[0006] Figure 2 This is a circuit diagram illustrating an example of pixel configuration according to the first embodiment.

[0007] Figure 3 This is a plan view illustrating an example of pixel configuration according to the first embodiment.

[0008] Figure 4 This is a cross-sectional view illustrating an example of pixel configuration according to the first embodiment.

[0009] Figure 5 This is a cross-sectional view illustrating an example of pixel configuration according to the first embodiment.

[0010] Figure 6 This is a circuit diagram illustrating an example of pixel configuration according to the second embodiment.

[0011] Figure 7This is a plan view illustrating an example of pixel configuration according to the second embodiment.

[0012] Figure 8 This is a plan view illustrating an example of pixel configuration according to the third embodiment.

[0013] Figure 9 This is a circuit diagram illustrating an example of pixel configuration according to the fourth embodiment.

[0014] Figure 10 This is a plan view illustrating an example of pixel configuration according to the fourth embodiment.

[0015] Figure 11 This is a plan view illustrating an example of pixel configuration according to the fifth embodiment.

[0016] Figure 12 This is a plan view illustrating an example of pixel configuration according to the sixth embodiment.

[0017] Figure 13 This is a circuit diagram illustrating an example of pixel configuration according to the seventh embodiment.

[0018] Figure 14 This is a plan view illustrating an example of pixel configuration according to the seventh embodiment.

[0019] Figure 15 This is a circuit diagram illustrating an example of pixel configuration according to the eighth embodiment.

[0020] Figure 16 This is a plan view illustrating an example of pixel configuration according to the eighth embodiment.

[0021] Figure 17 This is a plan view illustrating an example of pixel configuration according to the eighth embodiment.

[0022] Figure 18 This is a plan view illustrating an example arrangement of the color filter according to the eighth embodiment.

[0023] Figure 19 This is a cross-sectional view illustrating an example of pixel configuration according to the eighth embodiment.

[0024] Figure 20 This is a circuit diagram illustrating an example of pixel configuration according to the ninth embodiment.

[0025] Figure 21 This is a plan view illustrating an example of pixel configuration according to the ninth embodiment.

[0026] Figure 22 This is a plan view illustrating an example arrangement of the color filter according to the ninth embodiment.

[0027] Figure 23This is a plan view illustrating an example of pixel configuration according to the tenth embodiment.

[0028] Figure 24 This is a block diagram illustrating a schematic configuration of the device according to the eleventh embodiment.

[0029] Figure 25A and Figure 25B This is a block diagram illustrating a schematic configuration of the device according to the twelfth embodiment. Detailed Implementation

[0030] In the photoelectric conversion device disclosed in International Publication No. WO2016 / 098624, the settling time of the potential in the floating diffusion region may affect the operating speed. The following disclosure relates to a photoelectric conversion device with improved operating speed.

[0031] The embodiments will be described in detail below with reference to the accompanying drawings. Note that the following embodiments do not limit the technology claimed. Although multiple features are described in the embodiments, not all of the multiple features are necessary for the claimed technology. Furthermore, multiple features may be suitably combined. Throughout the drawings, the same or corresponding elements are indicated by the same reference numerals, and their redundant descriptions may be omitted or simplified.

[0032] In the embodiments described below, the camera device will be primarily described as an example of a photoelectric conversion device. However, the photoelectric conversion device in the various embodiments is not limited to a camera device and can be applied to other light detection devices based on photoelectric conversion. Examples of other light detection devices include rangefinders and photometers. A rangefinder may be, for example, a focus detection device or a distance measurement device using time-of-flight (TOF). A photometer may be a device that measures the amount of light incident on the device.

[0033] In the following text, the semiconductor region of the first conductivity type, having the same charge carriers as the signal carriers as the majority carriers, is an N-type semiconductor region, and the semiconductor region of the second conductivity type is a P-type semiconductor region. That is, the signal carriers are electrons. Furthermore, the anode of the photodiode constituting the photoelectric conversion unit is N-type, and the cathode of the photodiode is P-type. The polarity and conductivity type can be reversed. That is, the signal carriers can be holes, the semiconductor region of the first conductivity type can be a P-type semiconductor region, and the semiconductor region of the second conductivity type can be an N-type semiconductor region. The anode of the photodiode constituting the photoelectric conversion unit can be P-type, and the cathode of the photodiode can be N-type. In this case, the voltage relationship is also reversed. First Embodiment

[0034] Figure 1This is a block diagram illustrating an example of the overall configuration of the photoelectric conversion device 1 according to this embodiment. The photoelectric conversion device 1 includes a pixel array 10, a vertical scanning circuit 20, a column circuit 30, a horizontal scanning circuit 40, an output circuit 50, and a control circuit 60. The pixel array 10 includes a plurality of pixels 11 arranged in the x and y directions and forming a plurality of rows and a plurality of columns. The vertical scanning circuit 20, the column circuit 30, the horizontal scanning circuit 40, the output circuit 50, and the control circuit 60 are driving circuits for the photoelectric conversion device 1.

[0035] In the pixel array 10, scan lines 13 are arranged for each row, and output signal lines 12 are arranged for each column. The scan lines 13 are connected to the vertical scan circuit 20, and the output signal lines 12 are connected to the column circuit 30. Although in Figure 1 In this example, a single signal line is illustrated as scan line 13 in a row, but scan lines 13 in a row can include multiple signal lines. Multiple signal lines supply different control signals to pixel 11. Although in Figure 1 One output signal line 12 is illustrated in a column, but multiple output signal lines 12 can be arranged in a column.

[0036] exist Figure 1 In this configuration, the driving circuitry is arranged around the pixel array 10. However, the location of the driving circuitry is not limited to this. For example, in the case where the photoelectric conversion device 1 is a stacked type with multiple semiconductor substrates stacked, the driving circuitry units can be arranged in the area overlapping with the pixel array 10 in the plan view. Note that in this specification, a plan view refers to the plane of the substrate including the photoelectric conversion units that is parallel to the light incident plane, viewed from the normal direction of the plane parallel to the light incident plane.

[0037] Each pixel in the plurality of pixels 11 converts light into an electrical signal. Each pixel in the plurality of pixels 11 outputs the generated electrical signal to the column circuit 30 via the output signal line 12 of the corresponding column.

[0038] The control circuit 60 supplies control signals to the vertical scanning circuit 20, the column circuit 30, and the horizontal scanning circuit 40 for controlling the operating timing of each unit. The vertical scanning circuit 20 outputs control signals for controlling the pixels 11 in each row via the scan line 13. The vertical scanning circuit 20 scans to sequentially select the pixels 11 in each row and outputs the signal from the selected pixel 11 to the output signal line 12.

[0039] The column circuit 30 performs signal processing on the electrical signals input from the pixel 11 for each column pair. This signal processing may include, for example, noise removal and signal amplification.

[0040] The horizontal scanning circuit 40 supplies control signals to the column circuit 30 to sequentially output the processed signals from the column circuit 30 to the output circuit 50 for each column. The output circuit 50 outputs the signals from the column circuit 30 to the outside of the photoelectric conversion device 1. The device for inputting the signals output from the photoelectric conversion device 1 can be, for example, a storage device or a signal processing device.

[0041] Figure 2 This is a circuit diagram illustrating an example configuration of pixel 11 according to this embodiment. Pixel 11 includes a photoelectric conversion unit PD, a capacitor element C1, a transmission transistor M1, a reset transistor M2, an amplification transistor M3, a selection transistor M4, and a capacitor-attached transistor M5. The transmission transistor M1, reset transistor M2, amplification transistor M3, selection transistor M4, and capacitor-attached transistor M5 are N-type metal-oxide-semiconductor (MOS) transistors. The drain and source of each transistor can be collectively referred to as the main electrode.

[0042] A photoelectric conversion unit (PD, or first photoelectric conversion unit) is a photoelectric conversion element that generates and accumulates charges corresponding to incident light through photoelectric conversion. A typical photoelectric conversion unit (PD) is a photodiode.

[0043] The anode of the photoelectric conversion unit PD is connected to a ground wire with a ground potential. The cathode of the photoelectric conversion unit PD is connected to the source of the transfer transistor M1 (the first transfer transistor). The drain of the transfer transistor M1 is connected to the source of the reset transistor M2, the drain of the capacitor-attached transistor M5, and the gate of the amplification transistor M3. The connection node between the drain of the transfer transistor M1, the source of the reset transistor M2, the drain of the capacitor-attached transistor M5, and the gate of the amplification transistor M3 is a floating diffusion region FD. The floating diffusion region FD has parasitic capacitances in the semiconductor regions constituting these transistors, and retains the charge transferred from the photoelectric conversion unit PD.

[0044] Capacitor element C1 is an inter-line capacitor formed in the wiring layer and has a first terminal and a second terminal. The source of capacitor-attached transistor M5 is connected to the first terminal of capacitor element C1. The second terminal of capacitor element C1 is connected to a ground wire with a ground potential.

[0045] The drains of reset transistor M2 and amplification transistor M3 are connected to a power supply line with power supply potential VDD. The source of amplification transistor M3 is connected to the drain of selection transistor M4. The source of selection transistor M4 is connected to output signal line 12.

[0046] The vertical scanning circuit 20 supplies a control signal PTX to the gate of the transmission transistor M1 via a signal line constituting the scan line 13. When the transmission transistor M1 is turned on according to the control signal PTX, the charge accumulated in the photoelectric conversion unit PD is transferred to the floating diffusion region FD.

[0047] The vertical scanning circuit 20 supplies a control signal PRES to the gate of the reset transistor M2 via a signal line constituting the scan line 13. When the reset transistor M2 is turned on according to the control signal PRES, the charge transferred to the floating diffusion region FD is discharged, and the potential of the floating diffusion region FD is reset.

[0048] The vertical scanning circuit 20 supplies a control signal PSEL to the gate of the selection transistor M4 via a signal line constituting the scan line 13. When the selection transistor M4 is turned on according to the control signal PSEL, a signal is output from the amplifying transistor M3 in the corresponding row to the output signal line 12. At this time, the amplifying transistor M3 and the current source (not shown) connected to the output signal line 12 constitute a source follower circuit for outputting a signal corresponding to the charge transferred to the floating diffusion region FD, thereby serving as an amplification unit.

[0049] The vertical scanning circuit 20 supplies a control signal PFDINC to the gate of the capacitor-added transistor M5 via a signal line constituting the scan line 13. When the capacitor-added transistor M5 is turned on according to the control signal PFDINC, the capacitance of the capacitor element C1 is connected in parallel with the capacitance of the floating diffusion region FD, and the substantial capacitance of the floating diffusion region FD increases. At this time, compared with the case where the capacitor-added transistor M5 is in the off state, the charge-to-voltage conversion efficiency in the floating diffusion region FD decreases. Therefore, for example, whiteout in images when photographing bright objects can be suppressed. As described above, the capacitor element C1 and the capacitor-added transistor M5 have the function of changing the charge-to-voltage conversion efficiency in the floating diffusion region FD.

[0050] Figure 3 This is a plan view illustrating an example configuration of pixel 11 according to this embodiment. Figure 3 The semiconductor regions, gate electrodes, vias, and wiring that constitute the photoelectric conversion unit PD, capacitor element C1, and transistor are schematically illustrated in a plan view.

[0051] Figure 3The arrangement of gate electrodes GM1 to GM5, N-type semiconductor region S11, vias V11 to V16, and wirings W11 to W14 is illustrated. Gate electrodes GM1, GM2, GM3, GM4, and GM5 are the gates of transfer transistor M1, reset transistor M2, amplification transistor M3, select transistor M4, and capacitor-attached transistor M5, respectively. N-type semiconductor region S11 is the drain of transfer transistor M1 and also the drain (first main electrode) of capacitor-attached transistor M5. Via V11 is electrically connected to gate electrode GM3 via wiring W13 (second wiring), and via V12 is electrically connected to gate electrode GM3 via wiring (not illustrated). These connection nodes correspond to... Figure 2 The floating diffusion region FD is illustrated in the example. Note that this embodiment is not limited to this arrangement. That is, as shown in the example... Figure 13 As illustrated, the reset transistor M2, the capacitor-attached transistor M5, and the floating diffusion region FD can be connected in series. This configuration can be achieved via wiring (not shown). Figure 3 The illustrated via V12 is connected to the configuration of wiring W11. Vias V13 and V14 are connected to the power supply voltage nodes. Via V15 is connected to the output signal line 12. The gate electrode GM1 is connected via via V16 to wiring W14 (the first wiring) which is supplied with the control signal PTX.

[0052] Wiring W11 (fourth wiring) is connected to the source (second main electrode) of capacitor-attached transistor M5 via a via. Wiring W12 (third wiring) is connected to a ground wire (not shown), thereby applying a predetermined potential to wiring W12. Wiring W11 and wiring W12 are arranged in the same layer, and a portion of wiring W11 and a portion of wiring W12 are arranged side by side and close to each other. Wiring W11 and wiring W12 serve as capacitor elements C1 because inter-line capacitance due to electrostatic coupling is generated in the portions of the wirings that are close to each other. Note that wiring W11 and wiring W12 can be arranged in different layers.

[0053] Figure 4 This is a cross-sectional view illustrating an example configuration of pixel 11 according to this embodiment. Figure 4 Example edge Figure 3 The cross section intercepted by line A-A' in the diagram. For example... Figure 4 As illustrated, isolation region IS1, N-type semiconductor regions S11, 111 and 112, and P-type semiconductor region 113 are arranged in the semiconductor substrate. Gate electrode GM1, vias V11 and V16, and wirings W11, W13 and W14 are arranged above the semiconductor substrate.

[0054] The isolation section IS1 is, for example, a device isolation structure formed by shallow trench isolation (STI), localized silicon oxide (LOCOS), or a P-type semiconductor region. The N-type semiconductor region S11 corresponds to... Figure 2The illustrated floating diffusion region FD, N-type semiconductor regions 111 and 112 correspond to Figure 2 The illustrated photoelectric conversion unit (PD) has an N-type semiconductor region 111 positioned closer to the front side (wiring layer side) of the semiconductor substrate than the N-type semiconductor region 112. The peak concentration of impurities in the N-type semiconductor region 111 is higher than that in the N-type semiconductor region 112. The P-type semiconductor region 113 suppresses dark current generated on the front side of the semiconductor substrate.

[0055] When the transmission transistor M1 is turned on, the potential of the floating diffusion region FD can fluctuate due to the parasitic capacitance between the transmission transistor M1 and the floating diffusion region FD. The settling time of the potential fluctuation can be a factor that reduces the operating speed of the photoelectric conversion device 1. In particular, when the capacitor-attached transistor M5 is turned off, the reduction in operating speed may be significant because the capacitance of the floating diffusion region FD is small. On the other hand, in this embodiment, in the plan view, the wiring W11 constituting the capacitor element C1 is arranged between the wiring W13 connected to the floating diffusion region FD and the wiring W14 connected to the gate electrode GM1 of the transmission transistor M1. Therefore, the parasitic capacitance between the transmission transistor M1 and the floating diffusion region FD is reduced, and the potential fluctuation of the floating diffusion region FD is reduced, thereby improving the reduction in the operating speed of the photoelectric conversion device 1 caused by the settling time of the potential fluctuation. Therefore, according to this embodiment, the operating speed of the photoelectric conversion device 1 can be improved.

[0056] like Figure 4 As illustrated in this embodiment, wirings W11, W13, and W14 are arranged in the same layer. However, two of wirings W11, W13, and W14 can be arranged in different layers, or each of wirings W11, W13, and W14 can be arranged in different layers. However, when wiring W11 is arranged in the same layer as wirings W13 and W14, wiring W11 can more appropriately shield the capacitive coupling between wirings W13 and W14. Therefore, the parasitic capacitance between the transfer transistor M1 and the floating diffusion region FD is appropriately reduced. Alternatively, wiring W11 can be arranged in a layer closer to the semiconductor substrate than wirings W13 and W14. Therefore, wiring W11 can shield the capacitive coupling caused by the pattern (e.g., gate electrode) beneath wirings W13 and W14, and thus the parasitic capacitance between the transfer transistor M1 and the floating diffusion region FD can be appropriately reduced.

[0057] Figure 5 This is a cross-sectional view illustrating an example configuration of pixel 11 according to this embodiment. Figure 5 Example edge Figure 3The cross-section is taken by line B-B'. Wiring layer 116 and microlens ML are arranged above the first surface F1, which is the front side of the semiconductor substrate on which the photoelectric conversion device 1 is formed. The second surface F2, opposite to the first surface F1, is the back side of the semiconductor substrate. That is, the photoelectric conversion device 1 of this embodiment is a front-side illumination type that receives light incident from the first surface F1. However, the structure of the photoelectric conversion device 1 of this embodiment can be modified to a back-side illumination type that receives light incident from the second surface F2. N-type semiconductor regions 111 and 112 are formed in portions of the photoelectric conversion unit PD in the semiconductor substrate.

[0058] P-type semiconductor region 113 is disposed on a first surface F1 of the semiconductor substrate, and P-type semiconductor region 114 is disposed on a second surface F2 of the semiconductor substrate. The peak concentration of impurities in P-type semiconductor region 113 is higher than the peak concentration of impurities in P-type semiconductor region 114. P-type semiconductor region 113 suppresses dark current generated on the first surface F1, and P-type semiconductor region 114 suppresses dark current generated on the second surface F2.

[0059] P-type semiconductor region 115 and isolation portion IS1 are arranged outside N-type semiconductor regions 111 and 112. P-type semiconductor region 115 and isolation portion IS1 electrically isolate adjacent pixels from each other.

[0060] As described above, the photoelectric conversion device 1 of this embodiment has a wiring structure that can reduce the parasitic capacitance between the transmission transistor M1 and the floating diffusion region FD. Therefore, according to this embodiment, a photoelectric conversion device 1 that can improve operating speed is provided. Second Embodiment

[0061] In this embodiment, a modified example of pixel 11 including two photoelectric conversion units and two transmission transistors will be described. In this embodiment, the description of elements common to those in the first embodiment may be omitted or simplified.

[0062] Figure 6 This is a circuit diagram illustrating an example configuration of pixel 11 according to this embodiment. Pixel 11 in this embodiment includes two photoelectric conversion units PDA and PDB (a first photoelectric conversion unit and a second photoelectric conversion unit) and two transmission transistors M1A and M1B (a first transmission transistor and a second transmission transistor). This difference between pixel 11 in this embodiment and that of the first embodiment is significant. Figure 2Pixel 11. The anodes of photoelectric conversion units PDA and PDB are connected to a ground wire with a ground potential. The cathode of photoelectric conversion unit PDA is connected to the source of transmission transistor M1A, and the cathode of photoelectric conversion unit PDB is connected to the source of transmission transistor M1B. The drains of transmission transistors M1A and M1B are connected to the source of reset transistor M2, the drain of capacitor-added transistor M5, and the gate of amplification transistor M3. The connection node between the drains of transmission transistors M1A and M1B, the source of reset transistor M2, the drain of capacitor-added transistor M5, and the gate of amplification transistor M3 is the floating diffusion region FD.

[0063] The vertical scanning circuit 20 supplies a control signal PTXA to the gate of the transfer transistor M1A via a signal line constituting scan line 13. When the transfer transistor M1A is turned on according to the control signal PTXA, the charge accumulated in the photoelectric conversion unit PDA is transferred to the floating diffusion region FD. Additionally, the vertical scanning circuit 20 supplies a control signal PTXB to the gate of the transfer transistor M1B via another signal line constituting scan line 13. When the transfer transistor M1B is turned on according to the control signal PTXB, the charge accumulated in the photoelectric conversion unit PDB is transferred to the floating diffusion region FD.

[0064] As described above, in this embodiment, the two photoelectric conversion units PDA and PDB share the reset transistor M2, the amplification transistor M3, the selection transistor M4, and the capacitor-attached transistor M5. That is, the number of transistors in each photoelectric conversion unit (the ratio of the number of transistors to the number of photoelectric conversion units) is reduced. Therefore, for example, pixel 11 can be miniaturized.

[0065] Figure 7 This is a plan view illustrating an example configuration of pixel 11 according to this embodiment. Figure 7 The diagram schematically illustrates the arrangement of semiconductor regions, gate electrodes, vias, and wiring constituting the photoelectric conversion units PDA and PDB, capacitor element C1, and transistors in a plan view. Gate electrode GM1A is the gate of transfer transistor M1A, and gate electrode GM1B is the gate of transfer transistor M1B. The N-type semiconductor region S11 is the drain of both transfer transistor M1A and transfer transistor M1B, and is shared by both transistors. Transfer transistors M1A and M1B are arranged symmetrically about a line segment L1 parallel to the x-direction, which passes between gate electrodes GM1A and GM1B. That is, gate electrodes GM1A and GM1B are also arranged symmetrically about line segment L1. However, transfer transistors M1A and M1B can be arranged asymmetrically.

[0066] Gate electrode GM1A is connected to wiring W14, which supplies control signal PTXA, via a via, and gate electrode GM1B is connected to wiring W16 (the fifth wiring), which supplies control signal PTXB, via a via. Wiring W15 (the sixth wiring) is arranged between wiring W14 and wiring W16 in the plan view and is connected to the power supply voltage node.

[0067] In this embodiment, as in the first embodiment, the wiring W11 for configuring the capacitor element C1 is arranged between the wiring W13 connected to the floating diffusion region FD and the wiring W14 connected to the gate electrode GM1A of the transmission transistor M1A. Therefore, as in the first embodiment, the parasitic capacitance between the transmission transistor M1A and the floating diffusion region FD is reduced, and the operating speed of the photoelectric conversion device 1 can be improved.

[0068] Wiring W11 is not arranged between wiring W13 and wiring W16, which is connected to the gate electrode GM1B of the transmission transistor M1B. However, in this embodiment, wiring W15 is arranged between wiring W13 and wiring W16. Therefore, the parasitic capacitance between the transmission transistor M1B and the floating diffusion region FD is reduced, and the operating speed of the photoelectric conversion device 1 can be improved.

[0069] Similarly, in this embodiment, as in the first embodiment, a photoelectric conversion device 1 that can improve operating speed is provided. Third Embodiment

[0070] In this embodiment, a variation of the wiring between the transmission transistor M1B and the floating diffusion region FD will be described. In this embodiment, the description of elements common to both the first and second embodiments may be omitted or simplified.

[0071] Figure 8 This is a plan view illustrating an example configuration of pixel 11 according to this embodiment. Figure 8 In the middle, W17 is used to replace the wiring. Figure 7 Wiring W15 is used in the circuit. Wiring W17 is connected to the N-type semiconductor region S12 through a via. The N-type semiconductor region S12 is the source of the amplifying transistor M3 and also the drain of the selecting transistor M4.

[0072] In this embodiment, wiring W17 is further arranged between wiring W13 and wiring W16 connected to the gate electrode GM1B of the transmission transistor M1B. Therefore, as in the second embodiment, the parasitic capacitance between the transmission transistor M1B and the floating diffusion region FD is reduced, and the operating speed of the photoelectric conversion device 1 can be improved.

[0073] Similarly, in this embodiment, as in the first and second embodiments, a photoelectric conversion device 1 that can improve the operating speed is provided. Fourth embodiment

[0074] In this embodiment, a variation of pixel 11 including two selection transistors will be described. In this embodiment, the description of elements common to the first to third embodiments may be omitted or simplified.

[0075] Figure 9 This is a circuit diagram illustrating an example configuration of pixel 11 according to this embodiment. Pixel 11 in this embodiment has two selection transistors M4A and M4B (a first selection transistor and a second selection transistor). This difference between pixel 11 in this embodiment and that of the second embodiment is significant. Figure 6 Pixel 11. Furthermore, in the photoelectric conversion device 1 of this embodiment, two output signal lines 12A and 12B (first output signal line and second output signal line) are arranged for each column.

[0076] The drains of selector transistors M4A and M4B are connected to the source of amplifier transistor M3. The source of selector transistor M4A is connected to output signal line 12A, and the source of selector transistor M4B is connected to output signal line 12B.

[0077] The vertical scanning circuit 20 supplies a control signal PSELA to the gate of the selection transistor M4A via a signal line constituting scan line 13. When the selection transistor M4A is turned on according to the control signal PSELA, a signal is output from the amplifying transistor M3 in the corresponding row to the output signal line 12A. Furthermore, the vertical scanning circuit 20 supplies a control signal PSELB to the gate of the selection transistor M4B via another signal line constituting scan line 13. When the selection transistor M4B is turned on according to the control signal PSELB, a signal is output from the amplifying transistor M3 in the corresponding row to the output signal line 12B.

[0078] As described above, in this embodiment, a signal can be output from one pixel 11 to two output signal lines 12A and 12B. Therefore, multiple signal readout methods can be performed in parallel. For example, a readout method that outputs signals from each pixel via output signal line 12A and a readout method that adds and outputs the signals of multiple pixels of the same color via output signal line 12B can be performed in parallel. In this case, since the time required to read out the signals can be reduced, the speed of camera operation can be improved.

[0079] Figure 10 This is a plan view illustrating an example configuration of pixel 11 according to this embodiment. Figure 10The diagram schematically illustrates the arrangement of semiconductor regions, gate electrodes, vias, and wiring constituting the photoelectric conversion units PDA and PDB, capacitor element C1, and transistors in a plan view. Gate electrode GM4A is the gate of selection transistor M4A, and gate electrode GM4B is the gate of selection transistor M4B. N-type semiconductor region S13 is the source of amplifying transistor M3, N-type semiconductor region S14 is the drain of selection transistor M4A, and N-type semiconductor region S15 is the drain of selection transistor M4B. N-type semiconductor regions S13, S14, and S15 are connected to each other vias and wiring W18. Furthermore, as in the second and third embodiments, since a portion of wiring W18 is arranged between wiring W13 and wiring W16, the same effect as in the second and third embodiments can be obtained.

[0080] Similarly, in this embodiment, as in the first to third embodiments, a photoelectric conversion device 1 capable of improving operating speed is provided. Fifth Embodiment

[0081] In this embodiment, a variation of the configuration in the fourth embodiment will be described in which the source of the amplifying transistor M3 is configured with two N-type semiconductor regions. In this embodiment, the description of elements common to the first to fourth embodiments may be omitted or simplified.

[0082] Figure 11 This is a plan view illustrating an example configuration of pixel 11 according to this embodiment. Figure 11 In the middle, wiring W19 and W20 are used to replace Figure 10 The wiring W18 is used, and N-type semiconductor regions S16, S17, and S18 are arranged to replace it. Figure 10 N-type semiconductor regions S13, S14, and S15 are included. N-type semiconductor region S17 (first semiconductor region) serves as the source of amplifying transistor M3 and the drain of selecting transistor M4A. N-type semiconductor region S17 is connected to wiring W19 via a via. N-type semiconductor region S18 (second semiconductor region) serves as the source of amplifying transistor M3 and the drain of selecting transistor M4B. N-type semiconductor region S18 is connected to wiring W20 via a via. N-type semiconductor region S16 is the drain of amplifying transistor M3. Wiring W19 and wiring W20 are connected to each other via upper-layer wiring (not illustrated). Since a portion of wiring W20 is arranged between wiring W13 and wiring W16 as in the second and third embodiments, the same effect as in the second to fourth embodiments can be obtained.

[0083] Furthermore, unlike the fourth embodiment, in this embodiment, the wiring connecting the source of the amplifying transistor M3 to the drains of the selection transistors M4A and M4B is not necessary. Therefore, the wiring density in pixel 11 is reduced, and the possibility of accidental short circuits between wirings during the wiring manufacturing process is decreased. Thus, the yield of the photoelectric conversion device 1 can be improved.

[0084] Similarly, in this embodiment, as in the first to fourth embodiments, a photoelectric conversion device 1 capable of improving signal quality is provided. Sixth Embodiment

[0085] In this embodiment, a variation will be described in which the source of the reset transistor M2 and the drain of the capacitor-attached transistor M5 are composed of a single semiconductor region. In this embodiment, the description of elements common to the first through fifth embodiments may be omitted or simplified.

[0086] Figure 12 This is a plan view illustrating an example configuration of pixel 11 according to this embodiment. Figure 12 In the process, the N-type semiconductor region S19 (the third semiconductor region) serves as the source of the reset transistor M2 and the drain of the capacitor-attached transistor M5, and also functions as the floating diffusion region FD.

[0087] exist Figure 11 In the configuration of the illustrated fifth embodiment, an isolation section is arranged between the source of the reset transistor M2 and the drain of the capacitor-attached transistor M5. However, in this embodiment, since this isolation section is unnecessary, area efficiency is improved, and pixel 11 can be miniaturized.

[0088] Similarly, in this embodiment, as in the first to fifth embodiments, a photoelectric conversion device 1 capable of improving signal quality is provided. Seventh Embodiment

[0089] In this embodiment, variations relating to the connection relationships in the reset transistor M2, the capacitor-attached transistor M5, and the capacitor element C1 will be described. In this embodiment, the description of elements common to the first through sixth embodiments may be omitted or simplified.

[0090] Figure 13 This is a circuit diagram illustrating an example configuration of pixel 11 according to this embodiment. The description will be... Figure 9The differences are as follows: The source of capacitor-added transistor M5 is connected to the drain of transfer transistors M1A and M1B and the gate of amplification transistor M3. The connection node between the drain of transfer transistors M1A and M1B, the source of capacitor-added transistor M5, and the gate of amplification transistor M3 is the floating diffusion region FD. The drain of capacitor-added transistor M5 is connected to the first terminal of capacitor element C1 and the source of reset transistor. The second terminal of capacitor element C1 is connected to a ground wire with a ground potential.

[0091] Figure 14 This is a plan view illustrating an example configuration of pixel 11 according to this embodiment. Figure 14 In the middle, wiring W21 is used to replace Figure 11 Wiring W11 is shown in the diagram. Wiring W21 is connected via vias to the N-type semiconductor region S21, which serves as the source of the reset transistor M2, and the N-type semiconductor region S20, which serves as the drain of the capacitor-attached transistor M5. A portion of wiring W21 and a portion of wiring W12 are arranged side-by-side and close to each other, and serve as a capacitor element C1.

[0092] By arranging the wiring W21 as described above, the parasitic capacitance between the gate electrode GM2 of the reset transistor and the N-type semiconductor region S11 can be reduced. Therefore, the capacitance of the floating diffusion region FD is reduced, and the charge-to-voltage conversion efficiency in the floating diffusion region FD can be increased.

[0093] Similarly, in this embodiment, as in the first to sixth embodiments, a photoelectric conversion device 1 capable of improving signal quality is provided. Eighth embodiment

[0094] In this embodiment, a modified example of pixel 11 including four photoelectric conversion units and four transmission transistors will be described. Furthermore, in this embodiment, the microlens ML is not arranged on the first surface F1 side, but rather on the second surface F2 side. In this embodiment, the description of elements common to the first through seventh embodiments may be omitted or simplified.

[0095] Figure 15 This is a circuit diagram illustrating an example configuration of pixel 11 according to this embodiment. Pixel 11 in this embodiment includes four photoelectric conversion units PDA, PDB, PDC, and PDD, and four transmission transistors M1A, M1B, M1C, and M1D. This difference between pixel 11 in this embodiment and that of the seventh embodiment is significant. Figure 13 Pixel 11. In the following description, the seventh embodiment will be primarily described. Figure 13 The photoelectric conversion units PDC and PDD, and the transmission transistors M1C and M1D.

[0096] The anodes of photoelectric conversion units PDC and PDD are connected to a grounding wire with a ground potential. The cathode of photoelectric conversion unit PDC (the third photoelectric conversion unit) is connected to the source of transmission transistor M1C (the third transmission transistor), and the cathode of photoelectric conversion unit PDD is connected to the source of transmission transistor M1D. The drains of transmission transistors M1C and M1D are connected to the source of capacitor-added transistor M5 and the gate of amplifying transistor M3. The connection node between the drains of transmission transistors M1A, M1B, M1C, and M1D, the source of capacitor-added transistor M5, and the gate of amplifying transistor M3 is the floating diffusion region FD.

[0097] The vertical scanning circuit 20 supplies a control signal PTXC to the gate of the transfer transistor M1C via a signal line constituting scan line 13. When the transfer transistor M1C is turned on according to the control signal PTXC, the charge accumulated in the photoelectric conversion unit PDC is transferred to the floating diffusion region FD. Additionally, the vertical scanning circuit 20 supplies a control signal PTXD to the gate of the transfer transistor M1D via another signal line constituting scan line 13. When the transfer transistor M1D is turned on according to the control signal PTXD, the charge accumulated in the photoelectric conversion unit PDD is transferred to the floating diffusion region FD.

[0098] As described above, in this embodiment, the four photoelectric conversion units PDA, PDB, PDC, and PDD share a reset transistor M2, an amplification transistor M3, selection transistors M4A and M4B, and a capacitor-attached transistor M5. That is, the number of transistors in each photoelectric conversion unit is further reduced.

[0099] Figure 16 This is a plan view illustrating an example configuration of pixel 11 according to this embodiment. Figure 16 The diagram schematically illustrates the arrangement of semiconductor regions, gate electrodes, vias, and wiring constituting the photoelectric conversion units PDA, PDB, PDC, and PDD, capacitor element C1, and transistors in a plan view. Gate electrode GM1C is the gate of transfer transistor M1C, and gate electrode GM1D is the gate of transfer transistor M1D. The N-type semiconductor region S11 is the drain of transfer transistors M1A, M1B, M1C, and M1D, and is shared by all four transfer transistors. Via V17 connects the P-type semiconductor region used for isolating the photoelectric conversion unit and wiring W22, and supplies ground potential to the P-type semiconductor region.

[0100] Gate electrode GM1A is connected to wiring W23 supplying control signal PTXA via a via, and gate electrode GM1B is connected to wiring W24 supplying control signal PTXB via a via. Gate electrode GM1C is connected to wiring W25 supplying control signal PTXC via a via, and gate electrode GM1D is connected to wiring W26 supplying control signal PTXD via a via. In the plan view, wiring W21 is arranged between wiring W23 and wiring W13, and between wiring W25 and wiring W13. In the plan view, wiring W20 is arranged between wiring W24 and wiring W13, and between wiring W26 and wiring W13. Therefore, the parasitic capacitance between each transfer transistor and the floating diffusion region FD can be reduced.

[0101] Photoelectric conversion units PDA and PDC are arranged symmetrically about line segment L2, which is parallel to the y-direction. Therefore, focus detection of the phase difference detection method in the x-direction can be performed using signals based on the charge accumulated in photoelectric conversion unit PDA and signals based on the charge accumulated in photoelectric conversion unit PDC. Photoelectric conversion units PDB and PDD are arranged symmetrically about line segment L2. Therefore, focus detection of the phase difference detection method in the x-direction can be performed using signals based on the charge accumulated in photoelectric conversion unit PDB and signals based on the charge accumulated in photoelectric conversion unit PDD.

[0102] Figure 17 This is a plan view illustrating an example configuration of pixel 11 according to this embodiment. Figure 17 The diagram schematically illustrates the arrangement of wiring W13 and wirings W19 to W26, wirings W27 and W28 arranged in a layer above wirings W13 and wirings W19 to W26, and the via V18 connecting these two layers of wiring.

[0103] Wiring W27 is arranged to overlap at least a portion of wiring W21 in the plan view. Similarly, wiring W28 is also arranged to overlap at least a portion of wiring W21 in the plan view. Wirings W27 and W28 are connected to wiring W22 via via V18, thus ground potential is supplied to wirings W27 and W28. Therefore, due to the inter-line capacitance generated between wirings W21 and W27, and between W21 and W28 due to electrostatic coupling, the group including wirings W21, W27, and W28 (the third wiring) functions as part of the capacitive element C1.

[0104] Figure 18 This is a plan view illustrating an example arrangement of the color filters according to this embodiment. Figure 18 Schematic example and Figure 16 and Figure 17 The example shown illustrates the arrangement of three color filters corresponding to the four pixels 11. Figure 18 In this diagram, a red color filter is arranged in region R1. A blue color filter is arranged in region R2. Green color filters are arranged in regions R3 and R4, respectively. That is, the photoelectric conversion unit in region R1 is sensitive to red (first wavelength) light, the photoelectric conversion unit (fourth photoelectric conversion unit) in region R2 is sensitive to blue (second wavelength) light, and the photoelectric conversion units in regions R3 and R4 are sensitive to green light. Here, by comparison... Figure 17 and Figure 18 It is understandable that the wiring density in region R1, which receives relatively long wavelength light, is higher than that in region R2, which receives relatively short wavelength light.

[0105] Figure 19 This is a cross-sectional view illustrating an example configuration of pixel 11 according to this embodiment. Figure 19 Example edge Figure 16 The cross-section is taken by line C-C'. Wiring layer 116 is arranged above the first surface F1, which is the front side of the semiconductor substrate on which the photoelectric conversion device 1 is formed. The second surface F2, opposite to the first surface F1, is the back side of the semiconductor substrate. Red color filter CFR, green color filter CFG, and microlens ML are arranged above the second surface F2. That is, the photoelectric conversion device 1 of this embodiment is a back-side illumination type that receives light incident from the second surface F2.

[0106] N-type semiconductor regions 111A and 111C, and N-type semiconductor regions 112A and 112C are formed in portions of photoelectric conversion units (PDA and PDC) in a semiconductor substrate. N-type semiconductor region 111A is arranged closer to the first surface F1 than N-type semiconductor region 112A, and N-type semiconductor region 111C is arranged closer to the first surface F1 than N-type semiconductor region 112C. The peak concentration of impurities in N-type semiconductor regions 111A and 111C is higher than the peak concentration of impurities in N-type semiconductor regions 112A and 112C. A P-type semiconductor region 117 is arranged between N-type semiconductor regions 111A and 111C, and between N-type semiconductor regions 112A and 112C. The P-type semiconductor region 117 is an isolation portion that separates N-type semiconductor regions 111A and 111C, and also separates N-type semiconductor regions 112A and 112C.

[0107] A common microlens ML is arranged above each of the photoelectric conversion units PDA and PDC, and light that has passed through different pupil regions of the optical system enters each of the photoelectric conversion units PDA and PDC. Additionally, another common microlens is arranged above the photoelectric conversion units PDB and PDD, and light that has passed through different pupil regions of the optical system enters each of the photoelectric conversion units PDB and PDD. Using these configurations, a signal suitable for focus detection by a phase difference detection method is generated.

[0108] In this embodiment, a back-side illumination type is used where a photoelectric conversion device receives incident light from a second surface F2, which is different from the first surface F1 where the wiring layer 116 is arranged. Therefore, incident light directed towards the second surface F2 enters the photoelectric conversion units PDA, PDB, PDC, and PDD without being reflected by the wiring in the wiring layer 116, and generates a signal corresponding to the incident light. Thus, the photosensitivity of the photoelectric conversion units PDA, PDB, PDC, and PDD can be improved.

[0109] In this embodiment, the wiring density in region R1, where the red filter is arranged, is higher than the wiring density in region R2, where the blue filter is arranged. Typically, in the visible light wavelength range, light with longer wavelengths penetrates deeper into semiconductor substrates such as silicon. Therefore, since longer wavelength light is transmitted through a surface opposite to the incident surface, losses may occur. In this embodiment, because the wiring layer 116 on the first surface F1 side of region R1, where the red filter is arranged, has a high wiring density, incident light transmitted through the semiconductor substrate can be reflected towards the photoelectric conversion section side, thus further improving the photosensitivity of the red pixel.

[0110] Similarly, in this embodiment, as in the first to seventh embodiments, a photoelectric conversion device 1 capable of improving signal quality is provided. Ninth Embodiment

[0111] In this embodiment, a modified example of pixel 11 including eight photoelectric conversion units and eight transmission transistors will be described. In this embodiment, the description of elements common to the first to seventh embodiments may be omitted or simplified.

[0112] Figure 20 This is a circuit diagram illustrating an example configuration of pixel 11 according to this embodiment. Pixel 11 in this embodiment includes eight photoelectric conversion units PDA, PDB, PDC, PDD, PDE, PDF, PTG, and PDH, and eight transmission transistors M1A, M1B, M1C, M1D, M1E, M1F, M1G, and M1H. This difference in pixel 11 from that of the eighth embodiment is significant. Figure 15 Pixel 11. In the following description, the eighth embodiment will be primarily described. Figure 15The photoelectric conversion units PDE, PDF, PTG and PDH, and the transmission transistors M1E, M1F, M1G and M1H.

[0113] The anodes of photoelectric conversion units PDE, PDF, PTG, and PDH are connected to a grounding wire with a ground potential. The cathodes of photoelectric conversion units PDE, PDF, PTG, and PDH (the fourth photoelectric conversion unit) are connected to the sources of transmission transistors M1E, M1F, M1G, and M1H (the fourth transmission transistor), respectively. The drains of transmission transistors M1E, M1F, M1G, and M1H are connected to the source of capacitor-added transistor M5 and the gate of amplifying transistor M3. The connection node between the drains of transmission transistors M1A, M1B, M1C, M1D, M1E, M1F, M1G, and M1H, the source of capacitor-added transistor M5, and the gate of amplifying transistor M3 is the floating diffusion region FD.

[0114] The vertical scanning circuit 20 supplies control signals PTXE, PTXF, PTXG, and PTXH to the gates of the transmission transistors M1E, M1F, M1G, and M1H via signal lines constituting scan lines 13. When the transmission transistors M1E, M1F, M1G, and M1H are turned on according to the control signals PTXE, PTXF, PTXG, and PTXH, the charge accumulated in the photoelectric conversion units PDE, PDF, PTG, and PDH is transferred to the floating diffusion region FD.

[0115] As described above, in this embodiment, the eight photoelectric conversion units PDA, PDB, PDC, PDD, PDE, PDF, PTG, and PDH share a reset transistor M2, an amplification transistor M3, selection transistors M4A and M4B, and a capacitor-attached transistor M5. That is, the number of transistors in each photoelectric conversion unit is further reduced.

[0116] Figure 21 This is a plan view illustrating an example configuration of pixel 11 according to this embodiment. Figure 21 The diagram schematically illustrates the arrangement of semiconductor regions, gate electrodes, vias, and wiring constituting the photoelectric conversion units PDE, PDF, PTG, and PDH, capacitor element C1, and transistors in a plan view. Gate electrodes GM1E, GM1F, GM1G, and GM1H are the gates of transmission transistors M1E, M1F, M1G, and M1H, respectively. N-type semiconductor region S11 is the drain of transmission transistors M1A, M1B, M1C, and M1D, and is shared by all four transmission transistors. N-type semiconductor region S22 is the drain of transmission transistors M1E, M1F, M1G, and M1H, and is shared by all four transmission transistors. N-type semiconductor regions S11 and S22 are connected to each other vias and wiring W13.

[0117] Gate electrode GM1E is connected to wiring W29, which supplies control signal PTXE, via a via, and gate electrode GM1F is connected to wiring W30, which supplies control signal PTXF, via a via. Gate electrode GM1G is connected to wiring W31, which supplies control signal PTXG, via a via, and gate electrode GM1H is connected to wiring W32, which supplies control signal PTXH, via a via. Wirings W20 and W21 extend from the area where photoelectric conversion units PDA, PDB, PDC, and PDD are arranged to the area where photoelectric conversion units PDE, PDF, PTG, and PDH are arranged. In the plan view, wiring W21 is arranged between wiring W29 and wiring W13, and between wiring W31 and wiring W13. In the plan view, wiring W20 is arranged between wiring W30 and wiring W13, and between wiring W32 and wiring W13. Therefore, the parasitic capacitance between each transmission transistor and the floating diffusion region FD can be reduced.

[0118] Figure 22 This is a plan view illustrating an example arrangement of the color filters according to this embodiment. Figure 22 Schematic example and Figure 21 The example shown illustrates the arrangement of three color filters correspondingly arranged in two pixels 11. Figure 22 In this diagram, a red color filter is arranged in region R1. A blue color filter is arranged in region R2. Green color filters are arranged in regions R3 and R4, respectively. The photoelectric conversion units PDA and PDC in region R1 are sensitive to red light; the photoelectric conversion units PDF and PDH in region R2 are sensitive to blue light; and the photoelectric conversion units PDB, PDD, PDE, and PDG in regions R3 and R4 are sensitive to green light. Here, a comparison is made... Figure 21 and Figure 22 It is understood that the wiring density in region R1, which receives relatively long wavelength light, is higher than any wiring density in regions R2, R3, and R4, which receive relatively short wavelength light. Therefore, for the same reasons described in the eighth embodiment, the photosensitivity of the red pixel can be further improved.

[0119] Similarly, in this embodiment, as in the first to eighth embodiments, a photoelectric conversion device 1 capable of improving signal quality is provided. Tenth Embodiment

[0120] In this embodiment, variations relating to the arrangement of wiring connected to the drain of the capacitor-added transistor M5 and the gate electrode GM5 of the capacitor-added transistor M5 will be described. In this embodiment, the description of elements common to the first to ninth embodiments may be omitted or simplified.

[0121] Figure 23 This is a plan view illustrating an example configuration of pixel 11 according to this embodiment. Figure 23 The diagram schematically illustrates the arrangement of wiring W33 connected to the gate electrode GM5 of capacitor-attached transistor M5, wiring W34 (seventh wiring) arranged in a layer above wiring W33, and via V19 connecting wiring W33 and wiring W34 in a plan view. Figure 23 The configuration of other elements is similar to Figure 17 The configuration in [the document] is omitted here, therefore its description is omitted.

[0122] Wiring W33 and wiring W34 are supplied with a constant potential during the signal readout period. In the plan view, wiring W34 and wiring W21 connected to the drain of capacitor-attached transistor M5 are arranged to at least partially overlap each other.

[0123] Wiring W34 functions as part of capacitor element C1 because inter-line capacitance due to electrostatic coupling is generated between wiring W21 and wiring W34. Since the capacitance of capacitor element C1 is greater than that without wiring W34, the charge-to-voltage conversion efficiency in the floating diffusion region FD is reduced when capacitor-attached transistor M5 is on. Therefore, for example, whitening of images when photographing bright objects can be suppressed.

[0124] Since wiring W21 is connected to the drain of capacitor-added transistor M5 and wiring W33 is connected to the gate electrode GM5 of capacitor-added transistor M5, wiring W21 and wiring W33 are arranged close to each other. Therefore, compared to the case where wiring W33 is connected to the gate electrode GM5 of capacitor-added transistor M5 as in this embodiment, the wiring length of wiring W34 can be shortened. This increases the flexibility in the layout of other wiring.

[0125] Similarly, in this embodiment, as in the first to ninth embodiments, a photoelectric conversion device 1 capable of improving signal quality is provided. Eleventh Embodiment

[0126] Reference Figure 24 The device according to the eleventh embodiment is described. Figure 24 This is a block diagram illustrating a schematic configuration of the device according to this embodiment.

[0127] Figure 24This is a schematic diagram illustrating a device EQP including a photoelectric conversion device APR. The photoelectric conversion device APR has the functions of the photoelectric conversion device 1 according to the first to tenth embodiments. All or part of the photoelectric conversion device APR is a semiconductor device IC. The photoelectric conversion device APR of this example can be used as, for example, an image sensor, an autofocus (AF) sensor, a light metering sensor, or a rangefinder sensor. The semiconductor device IC has a pixel region PX, in which pixel circuits PXC, each including a photoelectric conversion unit, are arranged in a matrix. The semiconductor device IC may have a peripheral region PR surrounding the pixel region PX. Circuitry other than the pixel circuits may be arranged in the peripheral region PR.

[0128] The photoelectric conversion device APR can have a stacked structure (stacked chip structure) of a first semiconductor chip having multiple photoelectric conversion units and a second semiconductor chip having peripheral circuits. Each peripheral circuit in the second semiconductor chip can be a column circuit corresponding to a pixel column of the first semiconductor chip. Each peripheral circuit in the second semiconductor chip can also be a matrix circuit corresponding to a pixel or pixel block in the first semiconductor chip. The connection between the first and second semiconductor chips can be achieved using through-electrode (TSV), inter-chip wiring via direct bonding through a conductor such as copper, connections via microbumps between chips, or connections via wire bonding, etc.

[0129] In addition to a semiconductor device IC, an APR (Agent Photovoltaic Power Regulator) may also include a package PKG (Package Box) for mounting the semiconductor device IC. The package PKG may include: a substrate to which the semiconductor device IC is fixed; a cover such as glass facing the semiconductor device IC; and connecting members such as bonding wires or bumps for connecting terminals disposed on the substrate and terminals disposed on the semiconductor device IC.

[0130] The device EQP may also include at least one of an optical device OPT, a control device CTRL, a processing device PRCS, a display device DSPL, a storage device MMRY, and a mechanical device MCHN. The optical device OPT corresponds to the photoelectric conversion device APR and is, for example, a lens, shutter, or mirror. The control device CTRL controls the photoelectric conversion device APR and is, for example, a semiconductor device such as an ASIC.

[0131] The processing unit PRCS processes the signal output from the photoelectric conversion device APR and forms an analog front-end (AFE) or digital front-end (DFE). The processing unit PRCS is a semiconductor device such as a central processing unit (CPU) or an application-specific integrated circuit (ASIC). The display device DSPL is an EL display device or liquid crystal display device that displays information (images) obtained from the photoelectric conversion device APR. The storage device MMRY is a magnetic device or semiconductor device that stores information (images) obtained from the photoelectric conversion device APR. The storage device MMRY is a volatile memory such as SRAM or DRAM, or a non-volatile memory such as flash memory or a hard disk drive.

[0132] The mechanical device MCHN may include a movable or propulsion unit such as a motor or engine. In the device EQP, the signal output from the photoelectric conversion device APR is displayed on the display device DSPL or transmitted to the outside via a communication device (not shown) included in the device EQP. Therefore, separate from the storage circuit unit and the arithmetic circuit unit included in the photoelectric conversion device APR, the device EQP may also include a storage device MMRY and a processing device PRCS. The mechanical device MCHN can be controlled based on the signal output from the photoelectric conversion device APR.

[0133] Figure 24 The illustrated device EQP can be an electronic device such as an information terminal with shooting capabilities (e.g., smartphones and wearable devices) or a camera (e.g., interchangeable lens cameras, compact cameras, camcorders, and surveillance cameras). The mechanical device MCHN in the camera can drive components of the optical device OPT for zooming, focusing, and shutter operation. Furthermore, the device EQP can be a transportation device (mobile body) such as a vehicle, ship, drone, or aircraft. The device EQP can be a medical device such as an endoscope or CT scanner. The device EQP can be a measuring device such as a range sensor, an analytical device such as an electron microscope, an office device such as a copier, or an industrial device such as a robot.

[0134] The mechanical device MCHN in the transport device can be used as a mobile device. The equipment EQP as a transport device is suitable for transporting the photoelectric conversion device APR, or suitable for assisted and / or automated driving (manipulation) using camera functions. The processing device PRCS for assisted and / or automated driving (manipulation) can perform processing for operating the mechanical device MCHN as a mobile device based on information obtained from the photoelectric conversion device APR.

[0135] According to the first to tenth embodiments, signal acquisition can be satisfactorily achieved. Therefore, the photoelectric conversion device APR according to the first to tenth embodiments can provide high value to its designers, manufacturers, distributors, purchasers, and / or users. Therefore, when the photoelectric conversion device APR is installed on the device EQP, the value of the device EQP can also be increased. Therefore, when manufacturing and selling the device EQP, it is advantageous to install the photoelectric conversion device APR of this embodiment on the device EQP to increase the value of the device EQP. Here, increased value corresponds to at least one of adding functionality, improving performance, improving characteristics, improving reliability, increasing manufacturing yield, reducing environmental impact, reducing cost, reducing size, and reducing weight.

[0136] For example, by installing the photoelectric conversion device (APR) in a transport device, excellent performance can be obtained when photographing or measuring the external environment outside the transport device. Therefore, when manufacturing and selling transport devices, it is advantageous to install the photoelectric conversion device (APR) according to this embodiment on the transport device to improve the performance of the transport device itself. In particular, the photoelectric conversion device (APR) is suitable for transport devices that use information obtained by the photoelectric conversion device (APR) to provide driving support and / or automatic driving. Twelfth Embodiment

[0137] Figure 25A and Figure 25B This is a block diagram of a device related to a vehicle-mounted camera according to this embodiment. Figure 25A and Figure 25B An example of applying a photoelectric conversion device to a movable body such as a vehicle is illustrated. Device 80 includes an imaging device 800 (an example of a photoelectric conversion device) and a signal processing device (processing unit) for processing signals from the imaging device 800. Device 80 includes: an image processing unit 801 for performing image processing on multiple image data acquired by the imaging device 800; and a disparity calculation unit 802 for calculating disparity (phase difference of a disparity image) based on the multiple image data acquired by device 80.

[0138] Here, device 80 may include an optical system (not illustrated) for guiding light to imaging device 800. The optical system may include, for example, a lens, a shutter, and a mirror. Multiple photoelectric conversion units, substantially conjugate to the pupil of the optical system, may be arranged among the pixels included in imaging device 800. For example, multiple photoelectric conversion units may be arranged corresponding to a microlens. The multiple photoelectric conversion units can receive light beams transmitted through different positions of the pupil of the optical system. Therefore, imaging device 800 outputs multiple image data corresponding to the different positions of the light beams transmitted through the pupil of the optical system. Then, parallax calculation unit 802 can use the output multiple image data to calculate parallax.

[0139] Device 80 includes: a distance measurement unit 803 for calculating the distance to an object based on the calculated parallax; and a collision determination unit 804 for determining the likelihood of a collision based on the calculated distance. Here, the parallax calculation unit 802 and the distance measurement unit 803 are examples of distance information acquisition units used to acquire distance information to an object. That is, the distance information is information related to parallax, defocus, and the distance to the object. The collision determination unit 804 can use any of this distance information to determine the likelihood of a collision. Note that time-of-flight (ToF) technology can be used to acquire the distance information. The distance information acquisition unit can be implemented using specially designed hardware or software modules. Furthermore, the distance information acquisition unit can be implemented using a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), or a combination thereof.

[0140] Device 80 is connected to vehicle information acquisition device 810 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. Furthermore, device 80 is connected to control ECU 820, which is a control device for outputting control signals to generate braking force on the vehicle based on the judgment result of collision judgment unit 804. Device 80 is also connected to alarm device 830 for issuing warnings to the driver based on the judgment result of collision judgment unit 804. For example, when the collision judgment unit 804 determines that the probability of a collision is high, control ECU 820 performs vehicle control to avoid a collision or reduce damage by braking, returning the accelerator to its original position, or suppressing engine output. Alarm device 830 alerts the user by issuing warnings such as sounds, displaying warning information on a screen such as a car navigation system, or vibrating the seat belt or steering wheel. Device 80 functions as a control unit that controls the operation of the vehicle as described above.

[0141] In this embodiment, the device 80 captures images of the vehicle's surroundings (e.g., the front or rear). Figure 25B An example of a device that captures an image in front of the vehicle (camera range 850). The vehicle information acquisition device 810, which acts as a camera control unit, sends instructions to the device 80 or the camera device 800 to perform camera operation. With this configuration, the accuracy of distance measurement can be further improved.

[0142] While examples of controls for avoiding collisions with other vehicles have been described above, this embodiment is applicable to autonomous driving controls for following other vehicles or for autonomous driving controls that prevent vehicles from leaving their traffic lanes. Furthermore, the device is not limited to vehicles such as automobiles, and can be applied to mobile bodies (mobile appliances) such as ships, aircraft, satellites, industrial robots, or consumer robots. Additionally, the device can be widely applied to devices utilizing object recognition or biometric authentication, such as intelligent transportation systems (ITS) or monitoring systems, and is not limited to mobile bodies. Other embodiments

[0143] This disclosure is not limited to the embodiments described above, and various modifications can be made. For example, examples of adding some configurations of any embodiment to examples of other embodiments, or replacing some configurations of any embodiment with some configurations of other embodiments, are also embodiments of this disclosure.

[0144] The above embodiments can be appropriately modified without departing from the technical concept. Note that the disclosure of this specification includes not only the matters described herein, but also all matters that can be understood from this specification and the accompanying drawings. Furthermore, the disclosure of this specification includes a supplementary set of concepts described herein. In other words, for example, when a description of "A is greater than B" exists in this specification, it can be considered that even if the description of "A is not greater than B" is omitted, the description of "A is not greater than B" is still disclosed in this specification. This is because it is assumed that the case of "A is not greater than B" is considered when "A is greater than B" is described.

[0145] Embodiments of the present invention can also be implemented by providing software (including computer program products of computer programs) that performs the functions of the above embodiments to a system or device via a network or various storage media, and the computer (central processing unit (CPU) or microprocessor unit (MPU) of the system or device) reads and executes the computer program.

[0146] It should be noted that the above embodiments are merely specific examples for implementing this disclosure, and the technical scope of this disclosure should not be interpreted as limiting by these embodiments. That is, this disclosure can be implemented in various forms without departing from the technical concept or main features of this disclosure.

[0147] While this disclosure has been described with reference to embodiments, it should be understood that this disclosure is not limited to the disclosed embodiments. The scope of the appended claims should be given the broadest interpretation to cover all such modifications and equivalent structures and functions.

Claims

1. A photoelectric conversion device, comprising: Semiconductor substrate; A first photoelectric conversion unit is formed in the semiconductor substrate; A floating diffusion region is formed in the semiconductor substrate; A first transfer transistor is formed in the semiconductor substrate and configured to transfer charge from the first photoelectric conversion unit to the floating diffusion region; A first wiring is connected to the gate electrode of the first transmitting transistor; A second wiring is connected to the floating diffusion region; The third wiring is subjected to a predetermined potential; A fourth wiring is arranged at least partially alongside the third wiring and forms a capacitance with the third wiring; as well as A capacitor-attached transistor is formed in the semiconductor substrate and has a first main electrode connected to the floating diffusion region and a second main electrode connected to the fourth wiring. In a plan view of the semiconductor substrate, the fourth wiring is arranged between the first wiring and the second wiring.

2. The photoelectric conversion device according to claim 1, wherein, The first wiring, the second wiring, and the fourth wiring are arranged in the same layer.

3. The photoelectric conversion device according to claim 1, wherein, The third wiring and the fourth wiring are arranged on the same layer.

4. The photoelectric conversion device according to claim 1, wherein, At least a portion of the third wiring is arranged in a different layer than the fourth wiring.

5. The photoelectric conversion device according to claim 4, wherein, In the plan view, the third wiring overlaps at least partially with the fourth wiring.

6. The photoelectric conversion device according to claim 1, wherein, The fourth wiring is disposed in a layer closer to the semiconductor substrate than the first wiring and the second wiring.

7. The photoelectric conversion device according to claim 1, further comprising: A second photoelectric conversion unit is formed in the semiconductor substrate; A second transfer transistor is formed in the semiconductor substrate and configured to transfer charge from the second photoelectric conversion unit to the floating diffusion region; The fifth wiring is connected to the gate electrode of the second transmission transistor; as well as The sixth wiring is arranged between the second wiring and the fifth wiring in the plan view.

8. The photoelectric conversion device according to claim 7, wherein, In the plan view, the fourth wiring is not arranged between the second wiring and the fifth wiring.

9. The photoelectric conversion device according to claim 7, further comprising an amplifying transistor configured to output a signal corresponding to the potential of the floating diffusion region. in, The sixth wiring is connected to the main electrode of the amplifying transistor.

10. The photoelectric conversion device according to claim 7, further comprising: An amplifying transistor is configured to output a signal corresponding to the potential of the floating diffusion region; First output signal line and second output signal line; A first selection transistor is configured to output a signal from the amplifying transistor to the first output signal line by being turned on; as well as A second selection transistor is configured to output a signal from the amplifying transistor to the second output signal line when turned on. The sixth wiring is connected to the main electrodes of the amplifying transistor, the first selection transistor, and the second selection transistor.

11. The photoelectric conversion device according to claim 7, further comprising: An amplifying transistor is configured to output a signal corresponding to the potential of the floating diffusion region; First output signal line and second output signal line; A first selection transistor is configured to output a signal from the amplifying transistor to the first output signal line by being turned on; A second selection transistor is configured to output a signal from the amplifying transistor to the second output signal line by being turned on; as well as A first semiconductor region and a second semiconductor region are each disposed in the semiconductor substrate. The first semiconductor region constitutes the main electrode of the first selection transistor and the main electrode of the amplification transistor. Wherein, the second semiconductor region constitutes the main electrode of the second selection transistor and the main electrode of the amplification transistor, and The sixth wiring is connected to at least one of the first semiconductor region and the second semiconductor region.

12. The photoelectric conversion device according to claim 1, further comprising: A third photoelectric conversion unit is formed in the semiconductor substrate; A third transfer transistor is formed in the semiconductor substrate and configured to transfer charge from the third photoelectric conversion unit to the floating diffusion region; as well as Microlenses are arranged to guide incident light to the first photoelectric conversion unit and the third photoelectric conversion unit.

13. The photoelectric conversion device according to claim 1, in, The semiconductor substrate has a first side and a second side opposite to the first side. The first wiring, the second wiring, the third wiring, and the fourth wiring are arranged on the first surface side, and The first photoelectric conversion unit is sensitive to light incident on the second surface.

14. The photoelectric conversion device according to claim 13 further includes a fourth photoelectric conversion unit formed in the semiconductor substrate. in, The first photoelectric conversion unit has photosensitivity to light with a first wavelength. The fourth photoelectric conversion unit is sensitive to light with a second wavelength shorter than the first wavelength, and The wiring density in the area where the first photoelectric conversion unit is located is higher than the wiring density in the area where the fourth photoelectric conversion unit is located.

15. The photoelectric conversion device according to claim 14, in, The first photoelectric conversion unit has photosensitivity to red light, and The fourth photoelectric conversion unit is sensitive to blue light.

16. The photoelectric conversion device of claim 14, further comprising a fourth transfer transistor formed in the semiconductor substrate and configured to transfer charge from the fourth photoelectric conversion unit to the floating diffusion region.

17. The photoelectric conversion device of claim 1, further comprising a reset transistor configured to reset the potential of the floating diffusion region by being turned on. in, The fourth wiring is connected to the main electrode of the reset transistor.

18. The photoelectric conversion device according to claim 1, further comprising: A reset transistor, configured to reset the potential of the floating diffusion region by being turned on; as well as A third semiconductor region is disposed in the semiconductor substrate. The third semiconductor region constitutes the first main electrode of the capacitor-attached transistor and the main electrode of the reset transistor.

19. The photoelectric conversion device according to claim 1, further comprising a seventh wiring connected to the gate electrode of the capacitor-attached transistor. in, In the plan view, the seventh wiring overlaps with at least a portion of the fourth wiring.

20. An apparatus comprising a photoelectric conversion device according to any one of claims 1 to 19, The device also includes at least one of the following: Optical device, adapted for use with the photoelectric conversion device, A control device configured to control the photoelectric conversion device. A processing device configured to process the signal output from the photoelectric conversion device. A display device configured to display the information obtained by the photoelectric conversion device. A storage device configured to store information obtained by the photoelectric conversion device, and A mechanical device configured to operate based on information obtained from the photoelectric conversion device.

21. The device according to claim 20, wherein, The processing device acquires information related to the distance from the photoelectric conversion device to the object.

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