Image sensor and imaging system

Abstract

The present disclosure relates to an image sensor and an imaging system. The image sensor includes a substrate and a plurality of buried transfer gates. The substrate includes a floating diffusion region and a plurality of pixel cells. The plurality of buried transfer gates are disposed within the substrate and surround the floating diffusion region. Each buried gate is coupled to a corresponding pixel cell to control charge transfer between the pixel cell and the floating diffusion region.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, specifically to an image sensor and imaging system. Background Technology

[0002] An image sensor is a semiconductor device that converts optical information into electrical signals. For example, an image sensor can convert the variable attenuation of light waves into a signal (i.e., a small burst of current that transmits information). Such image sensors can include charge-coupled device (CCD) image sensors and complementary metal-oxide-semiconductor (CMOS) image sensors.

[0003] The structural design of an image sensor determines its space utilization and full well capacity (FWC), both of which are key indicators for evaluating image sensor performance. With technological advancements, pixel size is decreasing, and improvements in full well capacity are limited by size constraints. Simultaneously, the coupling capacitance between metal wirings also increases. Therefore, it is necessary to provide a new image sensor structure that can achieve size reduction while maintaining performance improvement. Summary of the Invention

[0004] To overcome the problems existing in related technologies, this disclosure provides an image sensor and an imaging system.

[0005] According to a first aspect of the present disclosure, an image sensor is provided, the image sensor comprising:

[0006] The substrate includes a floating diffusion region and multiple pixel units;

[0007] Multiple buried transfer gates are spaced apart inside the substrate and surround the floating diffusion region. Each buried gate is coupled to a pixel unit to control charge transfer between the pixel unit and the floating diffusion region.

[0008] In some embodiments of this disclosure, along a direction parallel to the substrate, the bottom surface of the buried transfer gate is flush with the bottom surface of the floating diffusion region and the top surface of the pixel unit; or, the bottom surface of the buried transfer gate is located between the bottom surface of the floating diffusion region and the top surface of the pixel unit.

[0009] In some embodiments of this disclosure, the projection of the buried transfer gate is located between the projection of the pixel cell and the projection of the floating diffusion region along a direction perpendicular to the substrate.

[0010] In some embodiments of this disclosure, a first contact hole is provided above the floating diffusion region, and the floating diffusion region is electrically connected to the first contact hole.

[0011] In some embodiments of this disclosure, the embedded transfer gate extends in a direction away from the first contact hole and is connected to the second contact hole, and a first isolation structure is provided between the embedded transfer gate and the first contact hole.

[0012] In some embodiments of this disclosure, a conductive layer is disposed above the buried transfer gate, the conductive layer extends in a direction away from the first contact hole and is connected to the second contact hole, and a first isolation structure is disposed between the buried transfer gate and the conductive layer and the first contact hole.

[0013] In some embodiments of this disclosure, the image sensor further includes a wiring layer, and the floating diffusion region and the buried transfer gate are connected to the wiring layer through the first contact hole and the second contact hole, respectively.

[0014] In some embodiments of this disclosure, a plurality of functional transistors are disposed on the substrate surface, and each of the functional transistors overlaps with a projection portion of a pixel unit in a direction perpendicular to the substrate.

[0015] In some embodiments of this disclosure, a second isolation structure is provided between the functional transistor and the pixel unit along a direction perpendicular to the substrate.

[0016] In some embodiments of this disclosure, the buried transfer gate is disposed between the second isolation structure and the floating diffusion region.

[0017] In some embodiments of this disclosure, a contact structure is provided above the functional transistor, and each functional transistor is connected to the wiring layer through the corresponding contact structure.

[0018] In some embodiments of this disclosure, the functional transistor is at least one of a source follower transistor, a reset transistor, a select transistor, and a double-conversion gain transistor.

[0019] According to a second aspect of the present disclosure, an imaging system is provided, comprising:

[0020] Processor and memory;

[0021] A camera, the camera including a lens and an image sensor as described in the first aspect.

[0022] The technical solutions provided by the embodiments of this disclosure may include the following beneficial effects: setting an embedded transfer gate, since the embedded transfer gate is set inside the substrate, improves the effective area and gate control capability of the transfer gate on the basis of realizing charge transfer, which is conducive to ensuring the full-well capacity of the image sensor and improving the overall performance of the image sensor. At the same time, it frees up space on the substrate surface, so that other structures can be set on the substrate surface, making the structure of the image sensor more compact, reducing the number of wafers, reducing the thickness of the image sensor and reducing the production cost of the image sensor.

[0023] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0024] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0025] Figure 1 This is a top view of an image sensor according to an exemplary embodiment.

[0026] Figure 2 This is illustrated according to an exemplary embodiment. Figure 2 Cross-sectional view in the a-a' direction.

[0027] Figure 3 This is illustrated according to an exemplary embodiment. Figure 2 Cross-sectional view in the a-a' direction.

[0028] Figure 4 This is a circuit diagram of an image sensor according to an exemplary embodiment.

[0029] Figure 5 This is illustrated according to an exemplary embodiment. Figure 2 Cross-sectional view in the b-b' direction.

[0030] Figure 6 This is illustrated according to an exemplary embodiment. Figure 5 Cross-sectional view in the c-c' direction.

[0031] Figure 7 This is illustrated according to another exemplary embodiment. Figure 2 Cross-sectional view in the b-b' direction.

[0032] Figure 8 This is illustrated according to another exemplary embodiment. Figure 5 Cross-sectional view in the c-c' direction.

[0033] Figure 9This is a schematic diagram of an image sensor according to another exemplary embodiment.

[0034] Figure 10 This is a block diagram of an imaging system according to an exemplary embodiment. Detailed Implementation

[0035] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the invention as detailed in the appended claims.

[0036] As technology advances, the size of pixel units is getting smaller and smaller. The increase in pixel full-well capacity will be limited by size. At the same time, the coupling capacitance between the conductive lines connecting the transistors in the image sensor also increases. Therefore, it is necessary to provide a new image sensor structure to achieve size reduction while ensuring performance improvement.

[0037] Based on this, an exemplary embodiment of this disclosure provides an image sensor, such as a CMOS image sensor. (Reference) Figures 1 to 3 As shown, the image sensor includes a substrate 10 and a plurality of buried transfer gates 40. The substrate 10 includes a floating diffusion region 20 and a plurality of pixel units 30. The plurality of buried transfer gates 40 are spaced apart inside the substrate 10 and surround the floating diffusion region 20. Each buried gate is coupled to a pixel unit 30 to control the charge transfer between the pixel unit 30 and the floating diffusion region 20.

[0038] The substrate 10 can be, for example, an epitaxial layer on a wafer substrate, and the material of the substrate 10 can include semiconductor materials such as silicon (Si), germanium (Ge), gallium phosphide (GaP), and gallium arsenide (GaAs). A floating diffusion region 20 and multiple pixel units 30 are disposed in the substrate 10. Each pixel unit 30 is used to generate a charge proportional to the amount of external incident light, and the floating diffusion region 20 is used to convert the charge into a voltage signal and store the charge. For example, the pixel unit 30 can be a photodiode, and the floating diffusion region 20 is formed by an ion implantation process. One floating diffusion region 20 can correspond to multiple pixel units 30, that is, one floating diffusion region 20 is coupled to multiple pixel units 30 to achieve multiple pixel units 30 sharing one floating diffusion region 20. Multiple pixel units 30 are arranged around the floating diffusion region 20, for example, as shown in... Figure 2As shown, one floating diffusion area 20 corresponds to four pixel units 30, and the four pixel units 30 are arranged in an array, with the floating diffusion area 20 located at the center of the four pixel units 30.

[0039] like Figure 1 , Figure 2 and Figure 3 As shown, multiple buried transfer gates 40 (BTGs) are spaced apart inside the substrate 10 and surround the floating diffusion region 20, such that the multiple buried transfer gates 40 are arranged at intervals along the circumferential outer side of the floating diffusion region 20. For example, the multiple buried transfer gates 40 are located on a circle or polygon (e.g., square) centered on the floating diffusion region 20. The intervals between adjacent buried transfer gates 40 can be equal or unequal. The material of the buried transfer gates 40 can be, for example, polysilicon or metal oxide.

[0040] like Figure 4 As shown, each buried transfer gate 40 is coupled to a pixel unit 30. The buried transfer gate 40 can transfer the charge in the corresponding pixel unit 30 to the floating diffusion region 20 according to the predetermined bias voltage, i.e., the transfer signal, thereby realizing the conversion of photoelectric signals and the transfer of charge, so that the image sensor can subsequently generate and process image data.

[0041] The image sensor provided in this embodiment controls the charge transfer between the corresponding pixel unit 30 and the floating diffusion region 20 by arranging multiple buried transfer gates 40 at intervals around the floating diffusion region 20 inside the substrate 10. Since the buried transfer gates 40 are located inside the substrate 10, the effective area and gate control capability of the transfer gates are effectively increased while achieving charge transfer, saving space on the surface of the image sensor on the substrate 10, thereby expanding the image sensor's capabilities in the direction perpendicular to the substrate 10. Figure 2 or Figure 3 The available space in the Y direction. The saving of surface space on the substrate 10 and the expansion of available space can be used to increase the size of each pixel unit 30 in this direction to ensure full-well pixel capacity. It can also be used to set other transistors or devices on the surface of the substrate 10 to reduce the number of bonding wafers, all of which are beneficial to improving the overall performance of the image sensor.

[0042] In some embodiments, since the embedded transfer gate 40 is disposed inside the substrate 10, space for the image sensor on the surface of the substrate 10 is saved, and the image sensor's range in the direction perpendicular to the substrate 10 is expanded. Figure 2 or Figure 3The available space in the Y direction, and at the same time, the length of the pixel unit 30 in the direction perpendicular to the substrate 10 is also extended. For example, in the first cross section passing through the central axis of the floating diffusion region 20, the central axis of the pixel unit 30, and the buried transfer gate 40 (i.e., Figure 2 or Figure 3 On the cross-section shown, the aspect ratio of the pixel unit 30 is set to be greater than 8, so that the pixel unit 30 has a larger size in the direction perpendicular to the substrate 10, that is, the pixel unit 30 is "stretched", realizing the depth extension of the pixel unit 30, thereby ensuring the full-well capacity of the pixel. For example, when the width of the cross-section of the pixel unit 30 is less than 0.5 micrometers, the height of the cross-section of the pixel unit 30 can be set to be greater than 4 micrometers, and the cross-sectional area of ​​the pixel unit 30 is 1.9 to 2.1 square micrometers.

[0043] In some embodiments, along a direction parallel to the substrate 10, the bottom surface of the buried transfer gate 40 is flush with the bottom surface of the floating diffusion region 20 and the top surface of the pixel unit 30.

[0044] like Figure 2 As shown, along the X direction parallel to the substrate 10, the bottom surface of the buried transfer gate 40 is flush with the bottom surface of the floating diffusion region 20 and the top surface of the pixel unit 30. The bottom surface of the buried transfer gate 40 is the surface closer to the pixel unit 30, and the top surface of the pixel unit 30 is the surface closer to the floating diffusion region 20 and the buried transfer gate 40. This makes the bottom surfaces of the floating diffusion region 20 and the buried transfer gate 40 and the top surface of the pixel unit 30 at the same height, thereby shortening the charge transfer path between the pixel unit 30 and the floating diffusion region 20, reducing charge transfer resistance, forming a stable and continuous potential between the pixel unit 30 and the floating diffusion region 20, reducing leakage risk, improving the efficiency and stability of charge transfer, and thus improving the overall performance of the image sensor.

[0045] In other embodiments, the bottom surface of the buried transfer gate 40 is located between the bottom surface of the floating diffusion region 20 and the top surface of the pixel unit 30 along a direction parallel to the substrate 10.

[0046] like Figure 3As shown, along the X direction parallel to the substrate 10, the bottom surface of the buried transfer gate 40 is located between the bottom surface of the floating diffusion region 20 and the top surface of the pixel unit 30. The bottom surface of the buried transfer gate 40 is the surface closer to the pixel unit 30, and the top surface of the pixel unit 30 is the surface closer to both the floating diffusion region 20 and the buried transfer gate 40. This ensures that the bottom surface of the buried transfer gate 40 is within the height range between the bottom surface of the floating diffusion region 20 and the top surface of the pixel unit 30, guaranteeing that as much charge as possible is transferred from the pixel unit 30 to the floating diffusion region 20. This creates a stable and continuous potential between the pixel unit 30 and the floating diffusion region 20, avoids leakage problems, improves the efficiency and stability of charge transfer, and enhances the overall performance of the image sensor.

[0047] In some embodiments, the projection of the buried transfer gate 40 is located between the projections of the pixel unit 30 and the floating diffusion region 20 along a direction perpendicular to the substrate 10.

[0048] like Figure 1 , Figure 2 and Figure 3 As shown, the projection of the buried transfer gate 40 in the direction perpendicular to the substrate 10, i.e., the Y direction, is located between the projections of the pixel unit 30 and the floating diffusion region 20. For example, from Figure 1 As shown in the top view, the buried transfer gate 40 is located between the pixel unit 30 and the floating diffusion region 20, so that the buried transfer gate 40 is between the starting position and the ending position of the charge transfer path, thereby forming a stable and continuous potential between the floating diffusion region 20, the buried transfer gate 40 and the pixel unit 30, and further improving the gate control capability of the buried transfer gate 40, thereby improving the efficiency and stability of charge transfer.

[0049] In some embodiments, reference Figure 2 , Figure 5 and Figure 6 As shown, a first contact hole 50 is provided above the floating diffusion area 20, and the floating diffusion area 20 is electrically connected to the first contact hole 50.

[0050] like Figure 2 and Figure 6 As shown, a first contact hole 50 is disposed above the floating diffusion region 20. The floating diffusion region 20 is electrically connected to the first contact hole 50 to transmit the charge and signal of the floating diffusion region 20 to other devices or circuits outside the substrate 10 through the first contact hole 50. For example, the first contact hole 50 may be a contact hole filled with a conductive material, and the conductive material of the first contact hole 50 may include tungsten (W) for example.

[0051] In this embodiment, by providing a first contact hole 50 above the floating diffusion region 20 and electrically connecting the floating diffusion region 20 to the first contact hole 50, the transmission of charge or signal from the floating diffusion region 20 to external devices or circuits of the substrate 10 can be achieved through the first contact hole 50, which is beneficial to improving the overall performance and process compatibility of the image sensor. In some embodiments, refer to Figure 1 , Figure 2 , Figure 5 and Figure 6 As shown, the buried transfer gate 40 extends in a direction away from the first contact hole 50 and is connected to the second contact hole 60, and a first isolation structure 70 is provided between the buried transfer gate 40 and the first contact hole 50.

[0052] In this embodiment, the embedded transfer gate 40 extends in a direction away from the first contact hole 50, and one end of the extended gate is connected to the second contact hole 60, thereby making the second contact hole 60 located away from the first contact hole 50. By increasing the distance between the second contact hole 60 and the first contact hole 50, capacitive coupling caused by their close proximity is avoided, reducing the risk of signal coupling.

[0053] For example, such as Figure 5 and Figure 6 As shown, the buried transfer gate 40 includes a body portion 41 and an extension portion 42 connected to the body portion 41. The body portion 41 extends in a direction perpendicular to the substrate 10. One end of the extension portion 42 is connected to the top end of the body portion 41. The extension portion 42 extends from the top end of the body portion 41 in a direction parallel to the substrate 10 away from the first contact hole 50. The other end of the extension portion 42 is connected to the second contact hole 60. Along the direction perpendicular to the substrate 10, the projection of the extension portion 42 is located between the projections of the pixel units 30. One extension portion 42 is correspondingly disposed between every two adjacent pixel units 30, such that multiple extension portions 42 are radially spaced apart. For example, in... Figure 6 In the illustrated embodiment, four arrayed pixel units 30 form a cross-shaped spacing space. A first contact hole 50 is located at the center of the cross, and extensions 42 of four buried transfer gates 40 extend along the four sides of the cross. By radially spacing the extensions 42 of the multiple buried transfer gates 40, the multiple second contact holes 60 are dispersed, thereby avoiding capacitive coupling caused by the second contact holes 60 being too close together, and further reducing the risk of signal coupling.

[0054] Continue to refer to Figure 5 and Figure 6The second contact hole 60 is electrically connected to the buried transfer gate 40 to transmit control signals to the buried transfer gate 40, thereby enabling the buried transfer gate 40 to control charge transfer. For example, the second contact hole 60 may be a contact hole filled with a conductive material, and the material of the second contact hole 60 may include tungsten.

[0055] like Figure 1 , Figure 2 , Figure 5 and Figure 6 As shown, a first isolation structure 70 is provided between the buried transfer gate 40 and the first contact hole 50. The first isolation structure 70 may include, for example, a shallow trench isolation (STI) structure. The buried transfer gate 40 and the first contact hole 50 are isolated by the first isolation structure 70 to reduce the risk of leakage and short circuit, thereby improving the reliability of the image sensor.

[0056] For example, such as Figure 6 As shown, four pixel units 30 arranged in an array form a cross-shaped space. A first isolation structure 70 is disposed in the space. A first contact hole 50 is located at the center of the first isolation structure 70. Four embedded transfer gates 40 extend from the center of the first isolation structure 70 to the four sides.

[0057] In some embodiments, along a direction perpendicular to the substrate 10, the projection of the body portion 41 of the buried transfer gate 40 is curved or bent, and the projection of the extension portion 42 of the buried transfer gate 40 is straight, such that the overall projection of the buried transfer gate 40 is a bent curve or a broken line. For example, as... Figure 6 As shown, the body portion 41 of the buried transfer gate 40 is fan-shaped, so that in the direction perpendicular to the substrate 10, the buried transfer gate 40 can partially surround the floating diffusion region 20 and extend to the second contact hole 60, thereby effectively increasing the facing area between the buried transfer gate 40 and the floating diffusion region 20, further improving the gate control capability and charge transfer efficiency of the buried transfer gate, and realizing electrical connection with the second contact hole 60.

[0058] In this embodiment, the buried transfer gate 40 extends in a direction away from the first contact hole 50 and is connected to the second contact hole 60. A first isolation structure 70 is provided between the buried transfer gate 40 and the first contact hole 50. The distance between the first contact hole 50 and the second contact hole 60 is increased by flexible wiring, avoiding coupling capacitance caused by the first contact hole 50 and the second contact hole 60 being too close, reducing the risk of signal coupling, and realizing the isolation between the buried transfer gate 40 and the first contact hole 50, further improving the overall performance of the image sensor.

[0059] For example, the buried transfer gate 40 can be made of polysilicon, which makes the wiring in the pixel area more flexible and has a lower coupling capacitance compared to metal wiring, avoiding signal coupling caused by dense wiring in small-sized pixels, especially affecting the source follower transistor more significantly.

[0060] In other embodiments, reference is made to... Figure 1 , Figure 2 , Figure 7 and Figure 8 As shown, a conductive layer 80 is disposed above the buried transfer gate 40. The conductive layer 80 extends in a direction away from the first contact hole 50 and is connected to the second contact hole 60. A first isolation structure 70 is disposed between the buried transfer gate 40, the conductive layer 80 and the first contact hole 50.

[0061] In this embodiment, a conductive layer 80 is disposed above the buried transfer gate 40. The conductive layer 80 extends in a direction away from the first contact hole 50 and connects to the second contact hole 60, thereby making the second contact hole 60 located away from the first contact hole 50. By increasing the distance between the second contact hole 60 and the first contact hole 50, capacitive coupling caused by their close proximity is avoided, reducing the risk of signal coupling.

[0062] For example, such as Figure 7 and Figure 8 As shown, a conductive layer 80 is disposed above the buried transfer gate 40. The material of the conductive layer 80 can be, for example, polysilicon. By setting the shape of the polysilicon material, such as a linear shape, the wiring in the pixel area becomes more flexible. Compared with metal wiring, it has a lower coupling capacitance, avoiding signal coupling caused by dense wiring in small-sized pixels, especially affecting the source follower transistor. One end of the conductive layer 80 is connected to the top of the buried transfer gate 40. The conductive layer 80 extends from the top of the buried transfer gate 40 away from the first contact hole 50 in a direction parallel to the substrate 10. The other end of the conductive layer 80 is connected to the second contact hole 60. Along the direction perpendicular to the substrate 10, the projection of the conductive layer 80 is located between the projections of the pixel units 30. One conductive layer 80 is disposed between every two adjacent pixel units 30, so that multiple conductive layers 80 are arranged radially at intervals. For example, in Figure 8 In the illustrated embodiment, four arrayed pixel units 30 form a cross-shaped spacing space, with a first contact hole 50 located at the center of the cross, and four conductive layers 80 extending along the four sides of the cross. By arranging the multiple conductive layers 80 radially at intervals, the multiple second contact holes 60 are dispersed, thereby avoiding capacitive coupling caused by the second contact holes 60 being too close together, and further reducing the risk of signal coupling.

[0063] Continue to refer to Figure 7 and Figure 8 The conductive layer 80 is electrically connected to the buried transfer gate 40 and the second contact hole 60, respectively, so as to transmit control signals to the buried transfer gate 40 through the second contact hole 60, thereby realizing the control of charge transfer by the buried transfer gate 40. For example, the second contact hole 60 can be a contact hole filled with conductive material, and the material of the second contact hole 60 can include tungsten, for example.

[0064] like Figure 1 , Figure 2 , Figure 7 and Figure 8 As shown, a first isolation structure 70 is provided between the buried transfer gate 40 and the first contact hole 50, and between the conductive layer 80 and the first contact hole 50. The first isolation structure 70 may include, for example, a shallow trench isolation structure. The first isolation structure 70 isolates the buried transfer gate 40 and the first contact hole 50, and isolates the conductive layer 80 and the first contact hole 50, thereby reducing the risk of leakage and short circuit and improving the reliability of the image sensor.

[0065] In some embodiments, the projection of the buried transfer gate 40 along a direction perpendicular to the substrate 10 is curved or bent, for example, as shown in the figure. Figure 8 As shown, the buried transfer gate 40 is fan-shaped, so that in the direction perpendicular to the substrate 10, the buried transfer gate 40 can partially surround the floating diffusion region 20 and extend to the second contact hole 60 through the linearly extending conductive layer 80, thereby effectively increasing the facing area between the buried transfer gate 40 and the floating diffusion region 20, further improving the gate control capability and charge transfer efficiency of the buried transfer gate, and realizing the electrical connection with the second contact hole 60.

[0066] In this embodiment, a conductive layer 80 is disposed above the buried transfer gate 40. The conductive layer 80 extends in a direction away from the first contact hole 50 and connects to the second contact hole 60. A first isolation structure 70 is disposed between the buried transfer gate 40, the conductive layer 80, and the first contact hole 50. The flexible wiring increases the distance between the first contact hole 50 and the second contact hole 60, avoiding coupling capacitance caused by the first contact hole 50 and the second contact hole 60 being too close, reducing the risk of signal coupling, and achieving isolation between the buried transfer gate 40 and the first contact hole 50, as well as between the conductive layer 80 and the first contact hole 50, further improving the overall performance of the image sensor.

[0067] In some embodiments, reference Figure 9 As shown, the image sensor also includes a wiring layer 90, a floating diffusion region 20 and a buried transfer gate 40, which are connected to the wiring layer 90 through a first contact hole 50 and a second contact hole 60, respectively.

[0068] like Figure 9 As shown, the image sensor also includes a wiring layer 90, which is disposed on the side of the substrate 10 away from the pixel unit 30. The wiring layer 90 may include, for example, a wafer and contacts and metal layers disposed in the wafer and between the wafer and the substrate for signal transmission. The floating diffusion region 20 is electrically connected to the wiring layer 90 through a first contact hole 50 disposed above it, and the buried transfer gate 40 is electrically connected to the wiring layer 90 through a second contact hole 60. The first contact hole 50 and the second contact hole 60 respectively realize the connection between the floating diffusion region 20 and the buried transfer gate 40 and the wiring layer 90, i.e., the external wiring of the substrate 10.

[0069] In this embodiment, by setting the wiring layer 90, wiring outside the substrate 10 can be realized through the wiring layer 90, and the floating diffusion region 20 and the buried transfer gate 40 are connected to the wiring layer 90 through the first contact hole 50 and the second contact hole 60 respectively, providing a basis for signal transfer and transmission and ensuring the functional integrity of the image sensor.

[0070] In some embodiments, reference Figure 1 and Figure 2 As shown, a plurality of functional transistors 100 are disposed on the surface of the substrate 10, and each functional transistor 100 overlaps with the projection portion of a pixel unit 30 in a direction perpendicular to the substrate 10.

[0071] like Figure 1 and Figure 2 As shown, a plurality of functional transistors 100 are disposed on the surface of the substrate 10. Each functional transistor 100 includes, for example, a gate 101 and an active region 102. The plurality of functional transistors 100 can be electrically connected to the floating diffusion region 20 to transmit charge and signals from the floating diffusion region 20 to the functional transistors 100. Figure 4 As shown, the plurality of functional transistors 100 may include, for example, at least one of a source follower transistor SF, a reset transistor RST, a select transistor RS, and a dual-conversion gain transistor DCG, for implementing signal processing functions such as voltage buffering, providing gain, resetting, and selecting. For example, as... Figure 4As shown, the image sensor includes a pixel unit 30, a buried transfer gate 40, a floating diffusion region 20, a source follower transistor SF, a reset transistor RST, a select transistor RS, and a dual conversion gain transistor DCG. The pixel unit 30, the buried transfer gate 40, and the floating diffusion region 20 are connected in sequence. The dual conversion gain transistor DCG and the reset transistor RST are sequentially disposed between the floating diffusion region 20 and the power supply terminal of the circuit. The source follower transistor SF and the select transistor RS are sequentially disposed between the floating diffusion region 20 and the output terminal of the circuit. The source follower transistor SF amplifies the potential change of the floating diffusion region 20 that receives charge from the pixel unit 30 and outputs the amplified change to the output line Vout to output the signal of the floating diffusion region 20. When the source follower transistor SF is turned on, a predetermined potential is provided to the drain of the source follower transistor SF, for example, the power supply voltage VDD can be transferred to the drain region of the select transistor RS. The reset transistor RST can periodically reset the floating diffusion region 20 by applying a predetermined bias voltage to reset the floating diffusion region 20. The selector transistor RS can select the pixel unit 30 to be read row by row or column by column, so as to selectively output the signal output by the source follower transistor SF to the corresponding row line or column line. The dual conversion gain transistor DCG is connected between the reset transistor RST and the floating diffusion region 20 to enhance the full-well capacity of the pixel.

[0072] like Figure 9 As shown, multiple functional transistors 100 may be located, for example, between the surface of the substrate 10 and the wiring layer 90.

[0073] like Figure 2 As shown, in the direction perpendicular to the substrate 10, i.e. the Y direction, the projection of each functional transistor 100 in this direction overlaps with the projection of a pixel unit 30 in this direction, so that each functional transistor 100 corresponds to a pixel unit 30 in the position of the substrate 10. This facilitates the arrangement of more functional transistors 100 in the direction parallel to the substrate 10 and reduces the distance between each functional transistor 100 and the floating diffusion region 20 and the pixel unit 30 in this direction, thereby improving the stability and response speed of subsequent signal processing.

[0074] For the image sensor described above in this disclosure, when the transfer gate is configured as an embedded transfer gate 40 disposed inside the substrate 10, the functional transistor 100 can be disposed on the surface of the substrate 10. Therefore, it is not necessary to provide a separate wafer for the functional transistor 100, which effectively reduces the number of wafers.

[0075] In this embodiment, by setting multiple functional transistors 100 on the surface of the substrate 10, and making each functional transistor 100 overlap with the projection portion of a pixel unit 30 in a direction perpendicular to the substrate 10, multiple signal processing functions can be realized through the functional transistors 100 to improve the stability and response speed of subsequent signal processing, and reduce the number of wafers, thereby further improving the overall performance of the image sensor.

[0076] In some embodiments, a second isolation structure 110 is provided between the functional transistor 100 and the pixel unit 30 along a direction perpendicular to the substrate 10.

[0077] like Figure 2 As shown, a second isolation structure 110 is provided between the functional transistor 100 and the pixel unit 30 along the Y direction perpendicular to the substrate 10. The second isolation structure 110 may include, for example, a pin region. The second isolation structure 110 and the end of the pixel unit 30 near the functional transistor 100 have different doping types, and can form a PN junction with the end of the pixel unit 30 near the functional transistor 100, thereby isolating the functional transistor 100 and the pixel unit 30 to ensure the stability and efficiency of charge transfer and improve the signal-to-noise ratio of the image sensor. For example, the active region of the functional transistor 100 is a P-type doped P-well, the end of the pixel unit 30 near the functional transistor 100 is N-type doped, and the second isolation structure 110 can be a P-type doped pin region, i.e., a P-pin.

[0078] In this embodiment, a second isolation structure 110 is provided between the functional transistor 100 and the pixel unit 30 along a direction perpendicular to the substrate 10. The second isolation structure 110 can isolate the functional transistor 100 and the pixel unit 30, thereby ensuring the stability and efficiency of charge transfer and further improving the overall performance of the image sensor.

[0079] In some embodiments, the buried transfer gate 40 is disposed between the second isolation structure 110 and the floating diffusion region 20.

[0080] like Figure 2 As shown, when the second isolation structure 110 is disposed between the functional transistor 100 and the pixel unit 30, the buried transfer gate 40 is disposed between the second isolation structure 110 and the floating diffusion region 20. This allows for full utilization of the space perpendicular to the substrate 10 for the arrangement of the pixel unit 30, the second isolation structure 110, and the functional transistor 100, and also makes full use of the space parallel to the substrate 10 for the arrangement of the second isolation structure 110, the buried transfer gate 40, and the floating diffusion region 20. This makes the arrangement of each device in the substrate 10 more compact and reasonable, further improving the space utilization rate in the substrate 10 and contributing to the improvement of the overall performance of the image sensor.

[0081] In some embodiments, a contact structure 120 is provided above the functional transistor 100, and each functional transistor 100 is connected to the wiring layer 90 through the corresponding contact structure 120.

[0082] like Figure 9 As shown, a contact structure 120 is provided above the functional transistor 100. The contact structure 120 may include contact holes or wires, etc. Each functional transistor 100 can be connected to the wiring layer 90 through the corresponding contact structure 120, and the signal can be transmitted between the functional transistor 100 and the wiring layer 90 through the contact structure 120.

[0083] In this embodiment, by providing a contact structure 120 above the functional transistor 100 and connecting each functional transistor 100 to the wiring layer 90 through the corresponding contact structure 120, signal transmission between the functional transistor 100 and the wiring layer 90 can be achieved through the contact structure 120, which is beneficial to improving the overall performance of the image sensor.

[0084] In some embodiments, the functional transistor 100 is at least one of a source follower transistor, a reset transistor, a select transistor, and a double-conversion gain transistor.

[0085] The functional transistor 100 disposed on the surface of the substrate 10 can be any one or any combination of a source follower transistor SF, a reset transistor RST, a select transistor RS, and a dual-conversion gain transistor DCG. The source follower transistor SF amplifies the potential change of the floating diffusion region 20 receiving charge from the pixel cell 30 and outputs the amplified change to an output line to output the signal of the floating diffusion region 20. The reset transistor RST can periodically reset the floating diffusion region 20 by applying a predetermined bias voltage to reset the floating diffusion region 20. The select transistor RS can select the pixel cell 30 to be read row by row or column by column to selectively output the signal output by the source follower transistor SF to the corresponding row or column line. The dual-conversion gain transistor DCG is connected between the reset transistor RST and the floating diffusion region 20 to enhance the full-well capacity of the pixel.

[0086] In this embodiment, at least one of the source follower transistor SF, reset transistor RST, select transistor RS, and dual conversion gain transistor DCG is used as the functional transistor 100. The functional transistor 100 can realize signal processing functions such as voltage buffering, providing gain, reset, and selection, ensuring the diversity of image sensor functions, providing a basis for image generation and processing, and further improving the overall performance of the image sensor.

[0087] For example, in Figure 1 In the illustrated embodiment, each floating diffusion region 20 corresponds to four pixel units 30. Above each of the four pixel units 30, a source follower transistor SF, a reset transistor RST, a select transistor RS, and a dual conversion gain transistor DCG are respectively arranged. Each functional transistor 100 overlaps with the projected portion of the pixel unit 30 below it. In this way, the space on the top surface of the substrate 10 can be effectively utilized to arrange the functional transistors 100, eliminating the need to arrange functional transistors 100 in other locations, making the structure of the image processor more compact.

[0088] In some embodiments, such as Figure 1 As shown, for each floating diffusion region 20, four buried transfer gates 40 can be surrounding it. Each buried transfer gate 40 is coupled to a pixel unit 30, so that one floating diffusion region 20, four buried transfer gates 40, and four pixel units 30 form a shared pixel group, through which the shared floating diffusion region 20 receives the charge transferred from the four pixel units 30. In this case, a source follower transistor SF, a reset transistor RST, a select transistor RS, and a dual conversion gain transistor DCG are disposed on the substrate surface corresponding to a shared pixel group. The four functional transistors 100 are all corresponding to the floating diffusion region 20, so that each pixel unit 30 in a shared pixel group can correspond to four different functional transistors 100.

[0089] In some embodiments, such as Figure 2 As shown, the substrate 10 also includes a third isolation structure 130, which may include a deep trench isolation (DTI) structure. The third isolation structure 130 is used to isolate adjacent shared pixel groups to reduce the coupling risk of adjacent shared pixel groups.

[0090] In some embodiments, the substrate 10 further includes a filter structure 140 and a lens 150.

[0091] It should be noted that the formation of the buried transfer gate 40 and the trench isolation structure requires passivation using high-energy ion implantation (PLAD) and repair of damage to the substrate 10 using rapid thermal annealing (RTA) to ensure the reliability of the image sensor.

[0092] In some embodiments, the image sensor substrate 10, pixel unit 30 disposed within the substrate 10, floating diffusion region 20, buried transfer gate 40, and functional transistor 100 disposed on the surface of the substrate 10 constitute a first wafer, and the image sensor wiring layer 90 is disposed on a second wafer. The first wafer and the second wafer are bonded together to form a two-layer wafer stack structure, which can be used as the pixel wafer and wiring wafer of the image sensor, respectively.

[0093] The image sensor provided in this disclosure has an embedded transfer gate 40 disposed inside the substrate 10. This effectively improves the effective area and gate control capability of the transfer gate while achieving charge transfer, which helps to ensure the full-well capacity of the image sensor pixels and improves the overall performance of the image sensor. At the same time, it frees up space on the surface of the substrate 10, so that other structures can be disposed on the surface of the substrate 10, making the structure of the image sensor more compact, reducing the number of wafers, reducing the thickness of the image sensor, and reducing the production cost of the image sensor.

[0094] In one exemplary embodiment, an imaging system is provided, which can be applied, for example, to terminal devices with shooting functions such as mobile phones, cameras, and video recorders. (Reference) Figure 10 As shown, the imaging system 200 includes a processor 210, a memory 220, and a camera 230. The camera 230 refers to a lens module used to realize image generation functions. The camera 230 includes a lens 231 and an image sensor 232 as described above. Through this imaging system 200, photoelectric signal conversion and charge transfer can be realized, providing a basis for image generation and processing. It also improves the effective area and gate control capability of the transfer gate, saves space on the surface of the substrate 10, helps to ensure the full-well pixel capacity of the image sensor 232 and reduces the number of wafers, thereby improving the overall performance of the imaging system 200.

[0095] Other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of the invention are indicated by the claims.

[0096] It should be understood that the present invention is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. An image sensor, characterized in that, The image sensor includes: The substrate includes a floating diffusion region and multiple pixel units; Multiple buried transfer gates are spaced apart inside the substrate and surround the floating diffusion region. Each buried gate is coupled to a pixel unit to control charge transfer between the pixel unit and the floating diffusion region.

2. The image sensor according to claim 1, characterized in that, Along a direction parallel to the substrate, the bottom surface of the buried transfer gate is flush with the bottom surface of the floating diffusion region and the top surface of the pixel unit; or, the bottom surface of the buried transfer gate is located between the bottom surface of the floating diffusion region and the top surface of the pixel unit.

3. The image sensor according to claim 1, characterized in that, Along a direction perpendicular to the substrate, the projection of the embedded transfer gate is located between the projection of the pixel cell and the projection of the floating diffusion region.

4. The image sensor according to claim 1, characterized in that, A first contact hole is provided above the floating diffusion area, and the floating diffusion area is electrically connected to the first contact hole.

5. The image sensor according to claim 4, characterized in that, The embedded transfer gate extends in a direction away from the first contact hole and is connected to the second contact hole, and a first isolation structure is provided between the embedded transfer gate and the first contact hole.

6. The image sensor according to claim 4, characterized in that, A conductive layer is disposed above the embedded transfer gate. The conductive layer extends in a direction away from the first contact hole and is connected to the second contact hole. A first isolation structure is disposed between the embedded transfer gate, the conductive layer and the first contact hole.

7. The image sensor according to claim 5 or 6, characterized in that, The image sensor further includes a wiring layer, and the floating diffusion region and the buried transfer gate are connected to the wiring layer through the first contact hole and the second contact hole, respectively.

8. The image sensor according to claim 7, characterized in that, The substrate surface is provided with a plurality of functional transistors, and in a direction perpendicular to the substrate, each functional transistor overlaps with a projection portion of a pixel unit.

9. The image sensor according to claim 8, characterized in that, A second isolation structure is provided between the functional transistor and the pixel unit along a direction perpendicular to the substrate.

10. The image sensor according to claim 9, characterized in that, The embedded transfer gate is disposed between the second isolation structure and the floating diffusion region.

11. The image sensor according to claim 8, characterized in that, A contact structure is provided above the functional transistor, and each functional transistor is connected to the wiring layer through the corresponding contact structure.

12. The image sensor according to claim 8, characterized in that, The functional transistor is at least one of a source follower transistor, a reset transistor, a select transistor, and a double-conversion gain transistor.

13. An imaging system, characterized in that, include: Processor and memory; A camera, the camera comprising a lens and an image sensor as described in any one of claims 1-12.

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