Method for manufacturing topcon solar cell and solar cell

Abstract

The application relates to the technical field of solar cells, and particularly provides a manufacturing method of a TOPCon solar cell and the solar cell, and aims to solve the problem of how to guarantee the conversion efficiency of the cell while reducing the parasitic absorption of doped polysilicon. The method comprises the following steps: sequentially forming a tunnel oxide layer, a doped polysilicon layer and a phosphosilicate glass on the back light surface of a substrate; removing the phosphosilicate glass in the non-grid line area along the extension direction of the non-grid line area at intervals, so that exposed areas and channel areas are alternately arranged in the extension direction; removing the doped polysilicon layer of the exposed areas to expose the tunnel oxide layer; removing the phosphosilicate glass of the grid line area and the phosphosilicate glass of the channel areas to expose the doped polysilicon layer, remove the tunnel oxide layer of the exposed areas to expose the back light surface, and electrically connect the doped polysilicon layer in the channel areas to the doped polysilicon layer in the adjacent grid line areas. The application provides a horizontal transmission channel for carriers, guarantees the conversion efficiency of the cell, and reduces the parasitic absorption.

Description

Technical Field

[0001] This application relates to the field of solar cell technology, specifically to a method for manufacturing a TOPCon solar cell and the solar cell itself. Background Technology

[0002] TOPCon (Tunnel Oxide Passivated Contact) cells are currently the mainstream technology for crystalline silicon cells. Their core lies in the passivation contact structure on the back side, namely the tunnel oxide layer and the doped polycrystalline silicon layer. The doped polycrystalline silicon layer provides excellent field passivation and improves the contact of the metal grid lines; however, parasitic absorption in the doped polycrystalline silicon layer reduces the cell's conversion efficiency. Existing solutions, such as the back-side polyfin structure, while reducing optical parasitic absorption by the doped polycrystalline silicon, weaken the lateral transport capability of charge carriers on the back side, lowering the cell's fill factor and hindering the improvement of cell conversion efficiency.

[0003] Accordingly, there is a need in the field for a new fabrication method for TOPCon solar cells to solve the above problems. Summary of the Invention

[0004] In order to overcome the above-mentioned defects, this application is made to solve, or at least partially solve, the technical problem of how to reduce parasitic absorption of doped polycrystalline silicon while ensuring cell conversion efficiency.

[0005] In a first aspect, a method for fabricating a TOPCon solar cell is provided, wherein the back surface of the solar cell includes multiple grid line regions and non-grid line regions between the grid line regions. The method includes: sequentially forming a tunnel oxide layer, a doped polysilicon layer, and a phosphosilicate glass layer on the back surface of a substrate; periodically removing the phosphosilicate glass layer along its extension direction in the non-grid line regions, thereby forming alternating exposed regions and channel regions in the extension direction, wherein the exposed regions are regions where the phosphosilicate glass has been removed, and the channel regions are regions where the phosphosilicate glass has not been removed; removing the doped polysilicon layer in the exposed regions to expose the tunnel oxide layer; removing the phosphosilicate glass in the grid line regions and the phosphosilicate glass in the channel regions to expose the doped polysilicon layer, and simultaneously removing the tunnel oxide layer in the exposed regions to expose the back surface, wherein the doped polysilicon layer in the channel region is electrically connected to the doped polysilicon layer in the adjacent grid line regions.

[0006] In one technical solution of the above-mentioned TOPCon solar cell manufacturing method, the removal of phosphorus silicon glass includes: removing phosphorus silicon glass using a laser process, wherein the laser wavelength is 355nm-1064nm, the power is 30W-500W, and the spot size is 80μm-500μm.

[0007] In one technical solution of the above-mentioned TOPCon solar cell manufacturing method, the exposed area accounts for no more than 50% of the non-grid area.

[0008] In one technical solution of the above-mentioned TOPCon solar cell manufacturing method, the removal of the doped polycrystalline silicon layer in the exposed area includes: alkaline washing to remove the doped polycrystalline silicon layer in the exposed area.

[0009] In one technical solution of the above-mentioned TOPCon solar cell manufacturing method, the removal of the phosphorus silicon glass in the grid area and the phosphorus silicon glass in the channel area to expose the doped polycrystalline silicon layer, and the removal of the tunnel oxide layer in the exposed area to expose the backlight surface, includes: acid washing to remove the phosphorus silicon glass in the grid area, the phosphorus silicon glass in the channel area and the tunnel oxide layer in the exposed area.

[0010] In a second aspect, a TOPCon solar cell is provided, the solar cell comprising: a substrate; a plurality of grid line regions located on the back surface of the substrate and non-grid line regions between the grid line regions, wherein the grid line regions include a tunnel oxide layer and a doped polysilicon layer sequentially stacked from the back surface toward the direction away from the substrate, the non-grid line regions include alternately arranged exposed regions and channel regions in the extension direction, wherein the exposed regions expose the back surface, the channel regions include a tunnel oxide layer and a doped polysilicon layer disposed on the same layer as the non-grid line regions from the back surface toward the direction away from the substrate, wherein the doped polysilicon layer in the channel region is electrically connected to the doped polysilicon layer in the adjacent grid line regions.

[0011] In one technical solution of the TOPCon solar cell mentioned above, the exposed area accounts for no more than 50% of the non-grid area.

[0012] In one technical solution of the TOPCon solar cell described above, the tunnel oxide layer and the doped polycrystalline silicon layer stacked in sequence include a first tunnel oxide layer and a first doped polycrystalline silicon layer stacked in sequence from the back light surface toward the direction away from the substrate, as well as a second tunnel oxide layer and a second doped polycrystalline silicon layer stacked in sequence.

[0013] In one technical solution of the TOPCon solar cell mentioned above, the solar cell further includes: a doped polycrystalline silicon layer located in the grid region, a backlight surface exposed in the exposed region, and a passivation antireflection layer on the doped polycrystalline silicon layer in the channel region.

[0014] In one technical solution of the TOPCon solar cell described above, the solar cell further includes: a groove, the groove penetrating the passivation and antireflection layer on the doped polycrystalline silicon layer of the grid region, at least exposing the doped polycrystalline silicon layer; and a metal electrode, filling the groove and forming an ohmic contact with the doped polycrystalline silicon layer.

[0015] The above-described technical solutions of this application have at least one or more of the following beneficial effects: In the technical solution provided in this application, a tunneling oxide layer, a doped polysilicon layer, and a phosphosilicate glass are sequentially formed on the backlight surface of the substrate. The phosphosilicate glass is then removed intermittently along its extension direction in the non-gateline region, resulting in alternating exposed regions and channel regions in the extension direction. Next, the doped polysilicon layer in the exposed region is removed to expose the tunneling oxide layer. The phosphosilicate glass in the gateline and channel regions is then removed to expose the doped polysilicon layer, and the tunneling oxide layer in the exposed region is also removed to expose the backlight surface. This achieves the electrical connection between the doped polysilicon layer in the channel region and the doped polysilicon layer in the adjacent gateline region, thereby providing a lateral transport channel for charge carriers. This improves the open-film ratio of the doped polysilicon while ensuring cell conversion efficiency and reducing parasitic absorption. Attached Figure Description

[0016] The disclosure of this application will become more readily understood with reference to the accompanying drawings. It will be readily understood by those skilled in the art that these drawings are for illustrative purposes only and are not intended to limit the scope of protection of this application. Wherein:

[0017] Figure 1 This is a schematic flowchart of the main steps of a method for manufacturing a TOPCon solar cell according to an embodiment of this application;

[0018] Figure 2a This is a schematic diagram showing the distribution of the grid line area and non-grid line area on the back surface of a solar cell;

[0019] Figure 2b This is a schematic diagram of a portion of the backlight surface according to an embodiment of this application;

[0020] Figure 2c This is a schematic cross-sectional view of a reference section according to an embodiment of this application;

[0021] Figure 3 This is a schematic diagram of the battery structure after method step S2 according to an embodiment of this application;

[0022] Figure 4a This is a schematic diagram of the battery structure after step S4 of a method according to an embodiment of this application;

[0023] Figure 4b This is a schematic diagram of the battery structure after step S4 of a method according to an embodiment of this application;

[0024] Figure 4c This is a schematic diagram of the battery structure in section b-b' of part B after method step S4 according to an embodiment of this application;

[0025] Figure 4d This is a schematic diagram of the battery structure in section b-b' of part A after method step S4 according to an embodiment of this application;

[0026] Figure 5a This is a schematic diagram of the battery structure after step S6 of a method according to an embodiment of this application;

[0027] Figure 5b This is a schematic diagram of the battery structure in section b-b' of part B after method step S6 according to an embodiment of this application;

[0028] Figure 6a This is a schematic diagram of the battery structure after step S8 of a method according to an embodiment of this application;

[0029] Figure 6b This is a schematic diagram of the battery structure in section b-b' of part B after method step S8 according to an embodiment of this application.

[0030] Figure 6c This is a schematic diagram of the battery structure in section b-b' of part A after method step S8 according to an embodiment of this application;

[0031] Figure 6d This is a schematic diagram of the battery structure in section a-a' of part A after method step S8 according to an embodiment of this application;

[0032] Figure 7 This is a schematic diagram of the back structure of a polyfin in related technologies;

[0033] Figure 8a This is a schematic diagram of the back structure of a solar cell according to an embodiment of this application;

[0034] Figure 8b This is a schematic diagram of the structure of the C portion of the back of a solar cell according to an embodiment of this application;

[0035] Figure 9a This is a schematic diagram of the battery structure in section b-b' of part B of the double passivated contact structure according to an embodiment of this application;

[0036] Figure 9b This is a schematic diagram of the battery structure in section b-b' of part A of the double passivated contact structure according to an embodiment of this application;

[0037] Figure 9c This is a schematic diagram of the battery structure in section a-a' of part A of the double passivated contact structure according to an embodiment of this application;

[0038] Figure 10aThis is a schematic diagram of the battery structure in section b-b' of part B of the double passivated contact structure according to another embodiment of this application;

[0039] Figure 10b This is a schematic diagram of the battery structure in section b-b' of part A of the double passivated contact structure according to another embodiment of this application;

[0040] Figure 10c This is a schematic diagram of the battery structure in section a-a' of part A of the double passivated contact structure according to another embodiment of this application;

[0041] Figure 11a This is a schematic diagram of the passivation and antireflection layer in section b-b' of part B according to an embodiment of this application;

[0042] Figure 11b This is a schematic diagram of the passivation and antireflection layer in section b-b' of part A according to an embodiment of this application;

[0043] Figure 11c This is a schematic diagram of the passivation and antireflection layer in section a-a' of part A according to an embodiment of this application;

[0044] Figure 12a This is a schematic diagram of the structure of the slot in section a-a' of part A according to an embodiment of this application;

[0045] Figure 12b This is a schematic diagram of the structure of a metal electrode in section a-a' of part A according to an embodiment of this application;

[0046] Figure 12c This is a schematic diagram of the structure of a metal electrode in section a-a' of part A according to another embodiment of this application.

[0047] Figure label:

[0048] 1: Gate line region; 2: Non-gate line region; 3: Substrate; 31: Backlight surface; 32: Light-facing surface; 4: Tunnel oxide layer; 41: First tunnel oxide layer; 42: Second tunnel oxide layer; 5: Doped polysilicon layer; 51: First doped polysilicon layer; 52: Second doped polysilicon layer; 6: Phosphosilicate glass; 7: Exposed area; 8: Channel region; 9: Passivation antireflection layer; 10: Groove; 11: Metal electrode. Detailed Implementation

[0049] Some embodiments of this application are described below with reference to the accompanying drawings. Those skilled in the art should understand that these embodiments are merely illustrative of the technical principles of this application and are not intended to limit the scope of protection of this application.

[0050] In the description of this application, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus. The terms "installed," "connected," and "linked" should be interpreted broadly; for example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection or an indirect connection via an intermediate medium; a connection within two elements; a wireless connection or a wired connection.

[0051] Furthermore, if the term "and / or" appears in this application, it includes three parallel solutions. Taking "A and / or B" as an example, it includes solution A, solution B, or a solution that simultaneously satisfies A and B. Additionally, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of a person skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed in this application. The terms "at least one A or B" or "at least one of A and B" have a similar meaning to "A and / or B," and can include only A, only B, or A and B. The singular forms of the terms "a" and "this" can also include plural forms.

[0052] TOPCon (Tunnel Oxide Passivated Contact) cells are currently the mainstream technology for crystalline silicon cells. Their core component is the passivated contact structure on the back side, which consists of an ultra-thin tunnel oxide layer and a layer of doped polycrystalline silicon. The doped polycrystalline silicon layer provides excellent field passivation and improves the contact of the metal grid lines. However, due to the infiltration of dopants (such as phosphorus) into the doped polycrystalline silicon layer, parasitic absorption of light in the long wavelength range is severe, resulting in significant optical losses on the back side of the cell, a decrease in short-circuit current density, and ultimately a decrease in cell conversion efficiency. To improve the parasitic absorption problem of long wavelength light in TOPCon cells, the following solutions are generally used:

[0053] 1) The overall thickness of the back-side doped polysilicon layer is reduced to improve the parasitic absorption problem. This approach can reduce the thickness of the doped polysilicon to 100nm-120nm. However, further thinning cannot guarantee good ohmic contact, which in turn affects the battery fill factor and ultimately results in no gain in battery efficiency.

[0054] 2) The parasitic absorption problem can be improved by carbon doping, but the carbon doping technology is not mature and the overall passivation effect on the back side is not as good as that of phosphorus-doped polycrystalline silicon, so the improvement effect is limited.

[0055] 3) The back-side polyfin structure involves using laser patterning or mask patterning, followed by wet etching, to thin the doped polysilicon layer in the non-gate area while retaining the doped polysilicon layer in the gate area. This reduces parasitic optical absorption in the back-side polysilicon layer and ensures metal contact in the gate area. However, the polyfin structure weakens the lateral transport capability of charge carriers on the back side, reducing the fill factor of the cell and hindering the improvement of TOPCon cell efficiency.

[0056] 4) By directly depositing a phosphorus diffusion-doped layer on the silicon substrate and the tunneling oxide layer in combination with a backside polyfin structure, the lateral current transport capability on the backside can be improved through the phosphorus diffusion layer, thereby ensuring the fill factor. However, this approach increases the corresponding cost, and the phosphorus diffusion layer will introduce corresponding recombination, reducing the passivation effect.

[0057] To address the aforementioned problems, this embodiment provides a method for manufacturing TOPCon solar cells, see attached figure. Figure 1 , Figure 1 This is a schematic flowchart of the main steps of a method for manufacturing a TOPCon solar cell according to an embodiment of this application. The method mainly includes the following steps S2 to S8:

[0058] like Figure 2a As shown, the back surface of a solar cell typically includes multiple grid line regions 1 and non-grid line regions 2 located between the grid line regions. The grid line regions are areas covering metal electrodes and are used to collect photogenerated carriers (electron-hole pairs) generated inside the solar cell. In this embodiment, using... Figure 2b Taking part A of the solar cell as an example, which consists of a non-grid region 2 and two adjacent grid regions 1, the manufacturing method is the same for any part of the solar cell that is the same as part A.

[0059] It should be noted that, Figure 2a This is a bottom view of the solar cell, showing the back side of the cell. For a clearer illustration, please refer to the appendix. Figure 2cAssuming that reference sections a-a' and b-b' are used to cut through part A or part B, the structure of part A at sections a-a' and b-b' or the structure of part B at sections a-a' and b-b' can be obtained, thus more clearly showing the structure and shape of the battery. Sections a-a' and b-b' can represent the front view and side view, respectively.

[0060] In step S2, a tunnel oxide layer 4, a doped polycrystalline silicon layer 5, and a phosphosilicate glass 6 are sequentially formed on the back surface 31 of the substrate 3.

[0061] In this embodiment, this step is performed on the substrate (such as a silicon wafer) using LPCVD (Low Pressure Chemical Vapor Deposition) to obtain the following result: Figure 3 The battery structure shown, in which Figure 3 This is a view of part A of the solar cell across section a-a'.

[0062] In one embodiment, step S2 can first use a standard wet cleaning process (RCA) to clean and remove contaminants from the surface of the silicon wafer, i.e., substrate 3. Then, an ultrathin (e.g., 1-2 nm) SiO2 tunnel oxide layer 4 is grown using LPCVD, followed by deposition of amorphous silicon, annealing and crystallization into polycrystalline silicon, and formation of n through phosphorus doping diffusion. + -poly-Si, i.e., doped polycrystalline silicon layer 5, and obtained phosphorosilicate glass (PSG) 6.

[0063] Step S4: In the non-gate region 2, the phosphosilicate glass 6 is removed at intervals along its extension direction, so that alternating exposed regions 7 and channel regions 8 are formed in the extension direction, wherein the exposed regions 7 are the regions where the phosphosilicate glass 6 has been removed, and the channel regions 8 are the regions where the phosphosilicate glass 6 has not been removed.

[0064] In this embodiment, the extension direction of the non-gate region refers to the direction perpendicular to the array arrangement formed by the gate region, the non-gate region, and the gate region. The battery structure obtained in step S4 is as follows: Figure 4a As shown, part B corresponds to the part where the non-gate region 2 is located. By removing the phosphor bronze glass 6 at intervals along its extension direction in the non-gate region 2, the following can be obtained: Figure 4a The alternating arrangement of exposed areas 7 and channel areas 8 is shown.

[0065] In one implementation, Figure 4b This is a schematic diagram of the battery structure in part A after step S4. Since step S4 only removes the phosphorus glass 6 on the non-grid area 2 at intervals, the grid area 1 still contains the phosphorus glass 6.

[0066] In one implementation, Figure 4cThis is a schematic diagram of the battery structure in section b-b' of part B after step S4. Figure 4c It can be seen that the phosphosilicate glass 6 in exposed area 7 has been removed, while the phosphosilicate glass 6 in channel area 8 has not been removed.

[0067] In one implementation, Figure 4d This is a schematic diagram of the battery structure in section b-b' of part A after step S4. Since the phosphorus-silicon glass 6 on grid region 1 was not removed in step S4, there is a continuous and uninterrupted layer of phosphorus-silicon glass 6 on grid region 1. Figure 4d The gray area. This is understandable. Figure 4d The phosphorus-silicon glass 6 on the non-gate region 2 partially obscures the phosphorus-silicon glass 6 on the gate region 1.

[0068] In one embodiment of this application, a laser process can be used to remove the phosphosilicate glass. For example, a laser can be used to remove the phosphosilicate glass at intervals along its extension direction in the non-gate region 2, that is, the phosphosilicate glass in the non-gate region can be locally opened or locally modified according to a certain proportion. The parameters of the laser are as follows: wavelength 355nm-1064nm, power 30W-500W, spot size 80μm-500μm, and output frequency 300KHz-2000KHz.

[0069] In one embodiment, a laser with a wavelength of 532nm, a power of 100W, and a spot size of 200μm is used to remove the phosphosilicate glass.

[0070] In one embodiment, the phosphosilicate glass can be removed at multiple identical distance intervals, or it can be removed at multiple different distance intervals. Generally, the exposed area 7 obtained after removing the phosphosilicate glass accounts for no more than 50% of the corresponding non-gateline area 2. (See reference...) Figure 4a For each part B, the ratio of the total area of ​​exposed region 7 to the area of ​​its corresponding non-grid region 2 is less than or equal to 50%.

[0071] In one embodiment, the exposed area 7 accounts for 5%-50% of the corresponding non-gate area 2.

[0072] Step S6: Remove the doped polysilicon layer 5 from the exposed region 7 to expose the tunnel oxide layer 4.

[0073] In this embodiment, an alkaline solution (such as KOH or NaOH) is used to remove the doped polysilicon layer 5 in the exposed region 7, exposing the tunnel oxide layer 4. Figure 5a As shown, the battery structure before removal can be referenced. Figure 4b It should be noted that since there is phosphosilicate glass on the gate region 1 and the channel region 8, it will not be washed away by the alkaline solution. This is equivalent to using the phosphosilicate glass as a mask, so that only the doped polysilicon layer 5 in the exposed region 7 is removed.

[0074] In one implementation, Figure 5b This is a schematic diagram of the battery structure at section b-b' in part B after step S6. From... Figure 5b As can be seen, the doped polysilicon layer 5 in exposed region 7 has been removed.

[0075] Step S8: Remove the phosphorus silicon glass 6 of the gate region 1 and the phosphorus silicon glass 6 of the channel region 8 to expose the doped polysilicon layer 5. At the same time, remove the tunnel oxide layer 4 of the exposed region 7 to expose the backlight surface 31. The doped polysilicon layer in the channel region 8 is electrically connected to the doped polysilicon layer 5 in the adjacent gate region 1.

[0076] In this embodiment, hydrofluoric acid (HF) is used to clean and remove the phosphosilicate glass 6 on the gate region 1 and the channel region 8, exposing the doped polysilicon layer 5. Simultaneously, hydrofluoric acid (HF) can also remove the tunnel oxide layer 4 on the exposed region 7, exposing the backlight surface 31, resulting in the following... Figure 6a The structure shown is such that the doped polysilicon layer in channel region 8 is electrically connected to the doped polysilicon layer 5 in the adjacent gate region 1.

[0077] In one implementation, Figure 6b This is a schematic diagram of the battery structure in section b-b' of part B after step S8. (See diagram below.) Figure 6b As shown, the tunnel oxide layer 4 in exposed region 7 is removed, exposing the backlight surface 31, and the phosphosilicate glass 6 in channel region 8 is removed, exposing the doped polysilicon layer 5.

[0078] In one implementation, Figure 6c This is a schematic diagram of the battery structure in section b-b' of part A after step S8. The phosphorus silicon glass 6 in the gate region 1 is removed, exposing the doped polycrystalline silicon layer 5. It should be noted that the stacked structure of the tunneling oxide layer 4 and the doped polycrystalline silicon layer 5 in the non-gate region 2 is arranged in an array along the extension direction; while the stacked structure of the tunneling oxide layer 4 and the doped polycrystalline silicon layer 5 in the gate region 1 is continuous and uninterrupted, i.e. Figure 6c The medium gray area is continuous in grid area 1.

[0079] In one implementation, Figure 6d This is a schematic diagram of the battery structure in section a-a' of part A after step S8. In this view, the extension direction is perpendicular to the paper and inwards. The stacked structure of the tunneling oxide layer 4 and the doped polysilicon layer 5 in the non-gate region 2 is arranged in an array along the extension direction, and the stacked structure of the tunneling oxide layer 4 and the doped polysilicon layer 5 in the gate region 1 is continuous and uninterrupted along the extension direction. Therefore, the doped polysilicon layers 5 in adjacent gate regions 1 can be electrically connected by the doped polysilicon layers in the channel region 8, thereby providing a lateral transport channel for charge carriers. While ensuring the battery conversion efficiency, the open-film ratio can be further improved, thereby reducing parasitic absorption.

[0080] In one embodiment, the above method can also be used on the sunlit surface, and this embodiment does not limit this.

[0081] In one application scenario example of this application, Figure 7 This is a schematic diagram of the back structure of a polyfinger in related technologies. The green vertical bars represent non-gateline areas, and the gray vertical bars represent gateline areas. The polyfin structure selectively removes the poly layer in the non-gateline areas, retaining only the poly layer in the gateline areas. The schematic diagram of the battery back structure in this embodiment is as follows. Figure 8a As shown, a laser is used to locally open the film in each non-gate region 2 according to a certain proportion. The multiple green boxes in each column represent the laser area, which is the area where the Poly layer is ultimately removed. The gray areas represent the non-laser areas, which are the areas where the Poly layer is ultimately retained. Finally, the Poly layers of the multiple gate regions 1 can be electrically connected through multiple lateral channels, i.e., channel areas (red dashed box areas). Figure 8a Taking part C in the example, such as Figure 8b As shown, the laser region is the exposed area 7 in the non-gate region 2 in the above embodiment; the non-laser region includes the gate region 1 and the channel region 8 in the non-gate region 2.

[0082] The main steps of the above method are as follows:

[0083] a) From the TOPCon process to the LPCVD + phosphorus diffusion process or the PECVD + annealing process.

[0084] Optionally, a SiO2 layer and a Poly layer are formed on the back surface of the battery in step a), and PSG is generated simultaneously.

[0085] b) Using laser technology (wavelength 532nm, power 100W, spot size 200μm laser), the PSG in the non-gate area of ​​the Poly layer on the backlight is locally opened or locally modified in a certain proportion.

[0086] Optionally, in step b), a portion of the PSG is removed at intervals in the non-grid area 2.

[0087] c) HF cleaning is used to remove the PSG coating on the light-facing and side surfaces, and alkaline cleaning is used to remove the Poly layer coating on the light-facing and side surfaces.

[0088] d) The Poly layer in the laser region of the backlight is removed by alkaline washing, and the PSG layer in the non-laser region (gate line region and channel region) and the SiO2 layer in the laser region are removed by HF cleaning.

[0089] e) Deposit aluminum oxide passivation layers on the back and front surfaces using atomic layer deposition (ALD).

[0090] f) Deposit an antireflection layer on the alumina passivation layer by PECVD.

[0091] g) Screen printing process.

[0092] In this embodiment, the PSG in the non-gateline area of ​​the backlight poly layer is partially opened up according to a certain proportion. Subsequently, the poly layer in the non-gateline area is removed by a corresponding wet process, while the gridline area (width 50μm-500μm) is retained. This achieves a higher opening ratio (above 60%), i.e., a higher backlight poly removal ratio. This achieves the effect of reducing parasitic absorption of backlight poly to a greater extent and further improving battery efficiency without reducing the FF.

[0093] In one embodiment of this application, a stacked structure of a first tunneling oxide layer and a first doped polysilicon layer, and a stacked structure of a second tunneling oxide layer and a second doped polysilicon layer, i.e., a double passivation contact structure, can be sequentially formed on the backlight surface of the substrate. Referring to the method in the above embodiment, the stacked structure of the second tunneling oxide layer and the second doped polysilicon layer, and the stacked structure of the first tunneling oxide layer and the first doped polysilicon layer are removed at intervals along their extension direction in the non-gate line region to form alternating exposed regions and channel regions. The exposed regions expose the backlight surface, the first doped polysilicon layer in the channel region is electrically connected to the first doped polysilicon layer in the adjacent gate line region, and the second doped polysilicon layer in the channel region is electrically connected to the second doped polysilicon layer in the adjacent gate line region.

[0094] In one embodiment, the channel region may also remove the stacked structure of the second tunnel oxide layer and the second doped polysilicon layer, retaining only the first doped polysilicon layer and the first tunnel oxide layer.

[0095] The above method can maximize the passivation effect of solar cells while ensuring battery conversion efficiency and reducing parasitic absorption. At the same time, the double passivation contact structure can also avoid the increase in series resistance caused by an excessively thick tunneling layer.

[0096] It should be noted that although the steps in the above embodiments are described in a specific order, those skilled in the art will understand that in order to achieve the effect of this application, different steps do not necessarily have to be executed in such an order. They can be executed simultaneously (in parallel) or in other orders. These adjusted solutions are equivalent to the technical solutions described in this application and therefore will also fall within the protection scope of this application.

[0097] Another aspect of this application provides a TOPCon solar cell, see attached figure. Figures 6b to 6dThe battery includes: a substrate 3; multiple grid line regions 1 and non-grid line regions 2 located on the backlight surface 31 of the substrate 3, wherein the grid line regions 1 include a tunnel oxide layer 4 and a doped polysilicon layer 5 sequentially stacked from the backlight surface 31 away from the substrate, and the non-grid line regions 2 include alternately arranged exposed regions 7 and channel regions 8 in the extending direction, wherein the exposed regions 7 expose the backlight surface 31, and the channel regions 8 include a tunnel oxide layer 4 and a doped polysilicon layer 5 disposed on the same layer as the non-grid line regions 2 from the backlight surface 31 away from the substrate, wherein the doped polysilicon layer 5 in the channel regions 8 is electrically connected to the doped polysilicon layer 5 in the adjacent grid line regions 1.

[0098] In one implementation, the exposed area 7 accounts for no more than 50% of the non-gate area 2 to which it belongs.

[0099] In one embodiment, the exposed area 7 accounts for 5%-50% of the corresponding non-gate area 2.

[0100] In one implementation, such as Figures 9a to 9c As shown, the tunnel oxide layer 4 and the doped polysilicon layer 5 are stacked sequentially, including a first tunnel oxide layer 41 and a first doped polysilicon layer 51 stacked structure and a second tunnel oxide layer 42 and a second doped polysilicon layer 52 stacked structure, which are stacked sequentially from the backlight surface toward the direction away from the substrate.

[0101] In one embodiment, the channel region 8 may also have the second doped polysilicon layer and the second tunnel oxide layer removed, leaving only the first doped polysilicon layer and the first tunnel oxide layer, such as... Figures 10a to 10c As shown in the figure. It is understandable that the structure in Figure 9 has better lateral transmission capability on the backlight side compared to Figure 10, and the battery conversion efficiency is higher.

[0102] In one embodiment, the solar cell further includes: a doped polysilicon layer 5 located in the grid region 1, a backlight surface 31 exposed in the exposed region 7, and a passivation antireflection layer 9 on the doped polysilicon layer 5 in the channel region 8.

[0103] In other words Figures 6b to 6d The solar cell shown has a passivation and antireflection layer (such as aluminum oxide and silicon nitride thin film) laid entirely on the back surface. (See attached image.) Figures 11a to 11c .

[0104] In one embodiment, the sun-facing side of the solar cell can also be entirely covered with a passivation and anti-reflection layer. In addition, the back and sun-facing sides of the dual-passivation contact structure cell can also include passivation and anti-reflection layers.

[0105] In one embodiment, the solar cell further includes: a slot 10 that penetrates the passivation and antireflection layer 9 on the doped polysilicon layer 5 of the gate region 1, exposing at least the doped polysilicon layer 5; and a metal electrode 11 that fills the slot 10 and forms an ohmic contact with the first doped polysilicon layer 5.

[0106] In this embodiment, Figure 12a This shows a schematic diagram of the structure of slot 10 at section a-a' in part A. Figure 12b This is a schematic diagram showing the structure of the metal electrode 11 at section a-a' in part A.

[0107] In one implementation, such as Figure 12c As shown, the metal electrode 11 can penetrate the doped polysilicon layer 5 and make better contact with the doped polysilicon layer 5.

[0108] In one embodiment, the light-facing surface may also include a slot and a metal electrode, the metal electrode penetrating the passivation and antireflection layer of the light-facing surface, and interacting with n. + An ohmic contact is formed at the emitter.

[0109] The technical solution of this application has been described above with reference to one embodiment shown in the accompanying drawings. However, it will be readily understood by those skilled in the art that the scope of protection of this application is obviously not limited to these specific embodiments. Without departing from the principles of this application, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will all fall within the scope of protection of this application.

Claims

1. A method for manufacturing a TOPCon solar cell, wherein the back surface of the solar cell includes multiple grid line regions (1) and non-grid line regions (2) between the grid line regions, characterized in that, The method includes: A tunnel oxide layer (4), a doped polycrystalline silicon layer (5), and a phosphosilicate glass (6) are sequentially formed on the back surface (31) of the substrate (3); In the non-gate region (2), the phosphosilicate glass (6) is removed at intervals along its extension direction, so that alternating exposed regions (7) and channel regions (8) are formed in the extension direction, wherein the exposed regions (7) are the regions where the phosphosilicate glass (6) has been removed, and the channel regions (8) are the regions where the phosphosilicate glass (6) has not been removed. Remove the doped polysilicon layer (5) from the exposed area (7) to expose the tunnel oxide layer (4); Remove the phosphosilicate glass (6) from the gate region (1) and the phosphosilicate glass (6) from the channel region (8) to expose the doped polysilicon layer (5). At the same time, remove the tunnel oxide layer (4) from the exposed region (7) to expose the backlight surface (31). Among them, the doped polysilicon layer in the channel region (8) is electrically connected to the doped polysilicon layer (5) in the adjacent gate region (1).

2. The method according to claim 1, characterized in that, The removal of the phosphosilicate glass (6) includes: Laser technology is used to remove phosphosilicate glass, with laser wavelengths ranging from 355nm to 1064nm, power from 30W to 500W, and spot sizes from 80μm to 500μm.

3. The method according to claim 1 or 2, characterized in that, The exposed area (7) accounts for no more than 50% of the non-grid area (2) to which it belongs.

4. The method according to claim 1, characterized in that, The removal of the doped polysilicon layer (5) from the exposed region (7) includes: Alkali washing removes the doped polysilicon layer (5) from the exposed area (7).

5. The method according to claim 1, characterized in that, The removal of the phosphorus silicate glass (6) in the gate region (1) and the phosphorus silicate glass (6) in the channel region (8) to expose the doped polycrystalline silicon layer (5), and the removal of the tunnel oxide layer (4) in the exposed region (7) to expose the backlight surface (31), includes: Pickling removes the phosphosilicate glass (6) in the gate area (1), the phosphosilicate glass (6) in the channel area (8), and the tunnel oxide layer (4) in the exposed area (7).

6. A TOPCon solar cell, characterized in that, The solar cell includes: Base (3); The multiple gate line regions (1) and the non-gate line regions (2) between the gate line regions are located on the backlight surface (31) of the substrate (3). The gate region (1) includes a tunnel oxide layer (4) and a doped polysilicon layer (5) stacked sequentially from the backlight surface (31) away from the substrate. The non-gate region (2) includes alternating exposed regions (7) and channel regions (8) in the extension direction. The exposed regions (7) expose the backlight surface (31). The channel regions (8) include a tunnel oxide layer (4) and a doped polysilicon layer (5) stacked on the same layer as the non-gate region (2) from the backlight surface (31) away from the substrate. The doped polysilicon layer (5) in the channel region (8) is electrically connected to the doped polysilicon layer (5) in the adjacent gate region (1).

7. The solar cell according to claim 6, characterized in that, The exposed area (7) accounts for no more than 50% of the non-grid area (2) to which it belongs.

8. The solar cell according to claim 6, characterized in that, The tunnel oxide layer (4) and the doped polysilicon layer (5) stacked sequentially include a first tunnel oxide layer (41) and a first doped polysilicon layer (51) stacked sequentially from the backlight surface toward the direction away from the substrate, as well as a second tunnel oxide layer (42) and a second doped polysilicon layer (52) stacked sequentially.

9. The solar cell according to claim 6, characterized in that, The solar cell also includes: Passivation and antireflection layer (9) on the doped polysilicon layer (5) in the gate region (1), the backlight surface (31) exposed in the exposed region (7), and the doped polysilicon layer (5) in the channel region (8).

10. The solar cell according to claim 9, characterized in that, The solar cell also includes: A slot (10) is made that penetrates the passivation and antireflection layer (9) on the doped polysilicon layer (5) of the gate region (1), exposing at least the doped polysilicon layer (5). A metal electrode (11) is filled in the groove (10) and forms an ohmic contact with the doped polycrystalline silicon layer (5).

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