Display device including a spacer between cathode electrodes and electronic device including the same

Abstract

A display device including a spacer between cathode electrodes and an electronic device including the display device are provided. The display device includes a substrate, a first light emitting element in a first emission area, a second light emitting element in a second emission area, and a spacer. The first light emitting element includes a first anode electrode electrically connected to a first pixel circuit, a first emission layer on the first anode electrode, and a first cathode electrode on the first emission layer and to which a first low power voltage is applied. The second light emitting element includes a second anode electrode spaced apart from the first anode electrode and electrically connected to a second pixel circuit, a second emission layer on the second anode electrode, and a second cathode electrode on the second emission layer, spaced apart from the second cathode electrode, and to which a second low power voltage is applied. The spacer is between the first cathode electrode and the second cathode electrode.

Description

Technical Field

[0001] This disclosure relates to a display device, and more specifically, to a display device including a spacer between cathode electrodes and an electronic device including the display device. Background Technology

[0002] Flat panel displays are replacing cathode ray tube displays due to their lightweight and thin profile. Examples of such flat panel displays include liquid crystal displays (LCDs) and organic light-emitting diode (OLED) displays.

[0003] A flat panel display device may include light-emitting elements that emit light of different colors, and the driving voltages required to drive the light-emitting elements that emit different colors of light may be different from each other. If the same power voltage of the same level is applied to all the pixels included in the display device, the power consumption of the display device may increase because some light-emitting elements may receive more power than they require. Summary of the Invention

[0004] The display device includes: a substrate including a first emitting region and a second emitting region; a first pixel circuit and a second pixel circuit disposed on the substrate; a first light-emitting element disposed in the first emitting region of the substrate; a second light-emitting element disposed in the second emitting region of the substrate; and a spacer. The first light-emitting element includes: a first anode electrode electrically connected to the first pixel circuit; a first emitting layer disposed on the first anode electrode; and a first cathode electrode disposed on the first emitting layer and subjected to a first low electrical voltage. The second light-emitting element includes: a second anode electrode spaced apart from the first anode electrode and electrically connected to the second pixel circuit; a second emitting layer disposed on the second anode electrode; and a second cathode electrode disposed on the second emitting layer, spaced apart from the first cathode electrode, and subjected to a second low electrical voltage. The spacer is disposed between the first cathode electrode and the second cathode electrode.

[0005] The first cathode electrode and the second cathode electrode can be electrically insulated from each other.

[0006] The second low power voltage can have a different voltage level than the first low power voltage.

[0007] The same high electrical voltage can be applied to both the first and second pixel circuits.

[0008] The display device may further include: a third pixel circuit disposed on a substrate; and a third light-emitting element disposed in a third emitting region of the substrate. The third light-emitting element may include: a third anode electrode spaced apart from each of the first and second anode electrodes and electrically connected to the third pixel circuit; a third emitting layer disposed on the third anode electrode; and a second cathode electrode. A first portion of the second cathode electrode may be disposed on the second emitting layer, and a second portion of the second cathode electrode may be disposed on the third emitting layer.

[0009] The first light-emitting element can emit blue light, the second light-emitting element can emit red light, and the third light-emitting element can emit green light.

[0010] Each of the first and second emission regions can be configured as multiple. Multiple first cathode electrodes can also be configured. In a plan view, a second cathode electrode can be spaced apart from and surrounding multiple first cathode electrodes.

[0011] In a plan view, each of the plurality of first cathode electrodes may be superimposed on two or more of the plurality of first emission regions. In a plan view, a second cathode electrode may be superimposed on all of the plurality of second emission regions.

[0012] In the plan view, each of the plurality of first cathode electrodes may be spaced apart from the second emission region. In the plan view, the second cathode electrode may be spaced apart from the plurality of first emission regions.

[0013] Multiple spacers can be configured. In a plan view, each of the multiple spacers can surround two or more first launch regions within a plurality of first launch regions.

[0014] The display device may further include: vertical transmission lines spaced apart from each other in a first direction and each extending in a second direction intersecting the first direction; and horizontal transmission lines disposed on a different layer from the vertical transmission lines, spaced apart from each other in the second direction, and each extending in the first direction. The horizontal transmission lines may include: a first horizontal power transmission line applied with a first low power voltage; and a second horizontal power transmission line spaced apart from the first horizontal power transmission line and applied with a second low power voltage. The vertical transmission lines may include: a first vertical power transmission line electrically connected to the first horizontal power transmission line and transmitting the first low power voltage to a first cathode electrode; and a second vertical power transmission line spaced apart from the first vertical power transmission line, electrically connected to the second horizontal power transmission line, and transmitting the second low power voltage to a second cathode electrode.

[0015] The plurality of first cathode electrodes may include: a first-first cathode electrode corresponding to a first vertical power transmission line; and a first-second cathode electrode corresponding to a second vertical power transmission line. The first-first cathode electrode may be electrically connected to the first vertical power transmission line. The first-second cathode electrode may be electrically connected to a first horizontal power transmission line.

[0016] The first cathode electrode can directly contact the first vertical power transmission line.

[0017] The display device may further include a first connecting electrode disposed on the same layer as the second vertical power transmission line. The first connecting electrode may be adjacent to and spaced apart from the second vertical power transmission line in a plan view. The first connecting electrode can electrically connect the first horizontal power transmission line and the first-second cathode electrodes to each other.

[0018] The first and second cathode electrodes can directly contact the first connecting electrode.

[0019] The second cathode electrode can directly contact the second vertical power transmission line.

[0020] The display device may further include a second connecting electrode disposed on the same layer as the first vertical power transmission line. The second connecting electrode may be adjacent to or spaced apart from the first vertical power transmission line in a plan view. The second connecting electrode can electrically connect the second horizontal power transmission line and the second cathode electrode to each other.

[0021] The second cathode electrode can directly contact the second connecting electrode.

[0022] The display device includes: a substrate including a first emitting region emitting light of a first color, a second emitting region emitting light of a second color, and a third emitting region emitting light of a third color; a first cathode electrode disposed on the substrate; a second cathode electrode disposed on the substrate; and a spacer. In a plan view, the first cathode electrode is superimposed on two or more first emitting regions within the first emitting region and spaced apart from the second and third emitting regions. A first low-power voltage is applied to the first cathode electrode. In a plan view, the second cathode electrode is superimposed on all of the second and third emitting regions and spaced apart from the first emitting region. In a plan view, the second cathode electrode is spaced apart from and surrounds the first cathode electrode. A second low-power voltage having a voltage level different from the first low-power voltage is applied to the second cathode electrode. The spacer is disposed between the first and second cathode electrodes and surrounds the first cathode electrode in the plan view.

[0023] An electronic device includes: a display device including a light-emitting element; and a processor configured to transmit image data signals and input control signals to the display device. The display device includes: a substrate including a first emitting region and a second emitting region; a first pixel circuit and a second pixel circuit disposed on the substrate; a first light-emitting element disposed in the first emitting region of the substrate; a second light-emitting element disposed in the second emitting region of the substrate; and a spacer. The first light-emitting element includes: a first anode electrode electrically connected to the first pixel circuit; a first emitting layer disposed on the first anode electrode; and a first cathode electrode disposed on the first emitting layer and subjected to a first low electrical voltage. The second light-emitting element includes: a second anode electrode spaced apart from the first anode electrode and electrically connected to the second pixel circuit; a second emitting layer disposed on the second anode electrode; and a second cathode electrode disposed on the second emitting layer, spaced apart from the first cathode electrode, and subjected to a second low electrical voltage. The spacer is disposed between the first cathode electrode and the second cathode electrode. Attached Figure Description

[0024] The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and form part of this specification. The drawings illustrate embodiments of the invention and, together with the specification, serve to explain the invention.

[0025] Figure 1 This is a plan view showing a display device according to an embodiment.

[0026] Figure 2A , Figure 2B , Figure 2C and Figure 2D This is a schematic diagram illustrating the equivalent circuit diagram of a pixel according to an embodiment.

[0027] Figure 3 It is shown Figure 1 A plan view of the emission area of ​​the display device.

[0028] Figure 4 , Figure 5 and Figure 6 It is shown Figure 1 A floor plan of an example of a magnified portion of a display device.

[0029] Figure 7 It is along Figure 4 A sectional view taken by line I-I'.

[0030] Figure 8 It is shown Figure 4 An enlarged plan view of the area surrounding the first connection portion of the display device.

[0031] Figure 9 It is along Figure 8 The sectional view taken from line II-II'.

[0032] Figure 10 It is shown Figure 4 An enlarged plan view of the area surrounding the second connection portion of the display device.

[0033] Figure 11 It is along Figure 10 The sectional view taken from line III-III'.

[0034] Figure 12 It is shown Figure 4 An enlarged plan view of the area surrounding the third connection portion of the display device.

[0035] Figure 13 It is along Figure 12 A sectional view taken from line IV-IV'.

[0036] Figure 14 It is shown Figure 1 A floor plan of an example of a magnified portion of a display device.

[0037] Figure 15 It is shown Figure 14 An enlarged plan view of the area surrounding the fourth connection portion of the display device.

[0038] Figure 16 It is along Figure 15 A sectional view taken by line V-V'.

[0039] Figure 17 This is a block diagram illustrating an electronic device according to an embodiment.

[0040] Figure 18 This is a schematic diagram illustrating an electronic device according to various embodiments. Detailed Implementation

[0041] Various exemplary embodiments will be described more fully below with reference to the accompanying drawings, in which some exemplary embodiments are illustrated. However, the inventive concept can be embodied in many different forms and should not necessarily be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concept to those skilled in the art. While each drawing may represent one or more specific embodiments of this disclosure drawn to scale so that relative lengths, thicknesses, and angles can be inferred from them, it should be understood that the invention is not necessarily limited to the relative lengths, thicknesses, and angles shown. These values ​​may be varied within the spirit and scope of this disclosure, for example, to allow for manufacturing limitations, etc.

[0042] Various modifications and forms may be made in this disclosure, and specific embodiments will be shown in the accompanying drawings and described in detail in the text. However, this is not intended to limit the disclosure to the specific forms disclosed, and it will be understood that all changes, equivalents, or substitutions falling within the spirit and technical scope of the disclosure should be included.

[0043] It will be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not necessarily be limited by these terms. These terms are used to distinguish one element from another. Therefore, without departing from the teachings of the inventive concept, the first element discussed below may be referred to as the second element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0044] It will be understood that when an element is referred to as "connected" or "joined" to another element, the element may be directly connected or directly joined to the other element, or an intermediary element may be present. Conversely, when an element is referred to as "directly connected" or "directly joined" to another element, no intermediary element is present. Other terms used to describe the relationship between elements (e.g., "between" and "directly between," "adjacent to" and "directly adjacent to") should be interpreted in a similar manner.

[0045] The terminology used herein is for the purpose of describing particular exemplary embodiments and is not necessarily intended to limit the inventive concept. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well. It will also be understood that when the terms “comprising” and / or “including” are used in this specification, it indicates the presence of the stated features, integrals, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0046] Furthermore, relative terms such as “below” or “bottom” and “above” or “top” may be used here to describe the relationship between one element and another, as shown in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the drawings, the relative terms are intended to cover different orientations of the device. For example, if a device in one of the drawings is flipped, an element described as being “below” the other element will subsequently be oriented to be “above” the other element. Thus, the term “below” can cover both “below” and “above” orientations depending on the specific orientation of the drawing. Similarly, if a device in one of the drawings is flipped, an element described as being “below” or “under” another element will subsequently be oriented to be “above” the other element. Thus, the term “below” or “under” can cover both above and below orientations.

[0047] In the following, embodiments will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals may be used for the same components, and unless an element is described in detail with respect to the drawings, it will be understood that the element is at least similar to a corresponding element already described elsewhere in this disclosure.

[0048] Embodiments of this disclosure relate to a display device, specifically an OLED display designed to improve power efficiency by applying different low power voltages to the light-emitting elements based on their color requirements. The device includes a substrate divided into multiple emission regions for red, green, and blue light, each emission region having corresponding pixel circuitry and a light-emitting element. Each light-emitting element includes an anode electrode, an emission layer, and a cathode electrode. Unlike conventional displays that apply the same cathode voltage across all pixels, this embodiment introduces separate cathode electrodes for the groups of emission regions, enabling the application of different low power voltages optimized for specific colors. For example, blue pixels, which typically require higher drive voltages, receive different voltages than red and green pixels that share a second voltage level.

[0049] To achieve this separation, the device employs a unique structural configuration including insulating spacers arranged between the cathode electrodes. These spacers electrically isolate the cathode electrodes of different color groups and also segment the functional layers during deposition, resulting in distinct electrode regions without cross-connections. This design allows multiple cathode electrodes to coexist within the same display panel while maintaining proper electrical isolation. Transmission lines are strategically positioned to deliver appropriate low-power voltages to the correct cathode electrodes via horizontal and vertical wiring, while providing a common high-power voltage to all pixel circuitry. This layered and segmented architecture ensures a stable voltage supply and prevents electrical interference between adjacent color groups.

[0050] As a result, by adapting the cathode voltage level to the actual requirements of each color channel, the display significantly reduces total power consumption compared to conventional designs. This approach not only improves energy efficiency but also maintains image quality and uniform brightness across the entire panel. Furthermore, because this approach utilizes existing thin-film transistor structures and organic layer stacking processes, the design allows for integration into a variety of electronic devices without increasing panel thickness or complexity. Therefore, this embodiment addresses the growing demand for energy-efficient, high-resolution OLED displays used in modern portable electronic devices.

[0051] In this document, the terms "low power voltage" and "high power voltage" are used. Here, these two terms refer to two different voltage levels applied to different parts of an OLED display system. For example, high power voltage (ELVDD) can be the main driving voltage supplied to pixel circuitry (e.g., thin-film transistor circuitry). It is applied to control the transistors and capacitors within the pixel circuitry to generate and regulate the current used to drive the light-emitting elements. Therefore, high power voltage can power the active matrix drive components, rather than the emitter layer itself.

[0052] A low power voltage (ELVSS) can be applied to the cathode electrode of the light-emitting element. It can determine the potential of the emitting layer where electroluminescence occurs. In this disclosure, different low power voltages can be applied to different sets of cathode electrodes (e.g., blue versus red / green) because these colors require different forward voltages to achieve appropriate brightness. By individually optimizing these voltages, the system can reduce unnecessary power consumption.

[0053] High power voltage can be larger than low power voltage. For example, high power voltage can be in the range of 4V to 10V, and low power voltage can be about 0V and can even be a slightly negative voltage (e.g., in the range of 1V to -3V).

[0054] Figure 1 This is a plan view showing a display device according to an embodiment.

[0055] Reference Figure 1 The display device DD may include a display surface for displaying an image. In an embodiment, the display surface may be substantially parallel to a plane defined by a first direction DR1 and a second direction DR2 intersecting the first direction DR1. For example, the second direction DR2 may be perpendicular to the first direction DR1. The display device DD may display an image on a third direction DR3 extending through the display surface. The third direction DR3 may be substantially parallel to the normal direction of the display surface. The third direction DR3 may be perpendicular to each of the first direction DR1 and the second direction DR2. The display surface may correspond to the upper surface (or front surface) of the display device DD. In an embodiment, the display surface may be curved.

[0056] Display device DD (or Figure 7 The base (SUB) may include a display area DA for displaying images and a peripheral area PA located around the display area DA.

[0057] Multiple pixels used to generate an image can be arranged in the display area DA. For example, each pixel can emit one of red, green, and blue light, but the invention is not limited to this.

[0058] The peripheral area PA can be located outside the display area DA. For example, the peripheral area PA can surround at least a portion of the display area DA in a plan view. Drivers for driving the display area DA (e.g., scan drivers, data drivers, etc.), transmission lines for transmitting various signals or voltages to the display area DA, etc., can be provided in the peripheral area PA.

[0059] Figure 2A , Figure 2B , Figure 2C and Figure 2D This is a schematic diagram illustrating the equivalent circuit diagram of a pixel according to an embodiment.

[0060] Each pixel may include a pixel circuit PC and a light-emitting element LE. The pixel circuit PC may include at least one thin-film transistor and at least one capacitor. The pixel circuit PC can generate a drive current and can provide the generated drive current to the light-emitting element LE. The light-emitting element LE can emit light based on the drive current. For example, the light-emitting element LE may include an organic light-emitting diode, an inorganic light-emitting diode, a quantum dot light-emitting diode, a micro light-emitting diode, etc.

[0061] Reference Figure 2A In an embodiment, the pixel circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a first capacitor C1, and a second capacitor C2.

[0062] The first transistor T1 may include a gate electrode electrically connected to a first node N1, a first electrode, and a second electrode electrically connected to a second node N2. In an embodiment, the first transistor T1 may further include a back gate electrode electrically connected to the second node N2.

[0063] The second transistor T2 may include a gate electrode to which a write gate signal GW is applied, a first electrode electrically connected to a data line DL, and a second electrode electrically connected to a first node N1.

[0064] The third transistor T3 may include a gate electrode to which a reference gate signal GR is applied, a first electrode to which a reference voltage VREF is applied, and a second electrode electrically connected to the first node N1.

[0065] The fourth transistor T4 may include a gate electrode to which an initialization gate signal GI is applied, a first electrode to which an initialization voltage VINT is applied, and a second electrode electrically connected to the second node N2.

[0066] The fifth transistor T5 may include a gate electrode to which a transmit control signal EM is applied, a first electrode to which a first power voltage ELVDD is applied, and a second electrode electrically connected to the first electrode of the first transistor T1. The first power voltage ELVDD may be a high power voltage.

[0067] The first capacitor C1 may include a first electrode electrically connected to the first node N1 and a second electrode electrically connected to the second node N2 and the fourth transistor T4.

[0068] The second capacitor C2 may include a first electrode to which a first electrical voltage ELVDD is applied, and a second electrode electrically connected to the back gate electrode of the first transistor T1 and the second node N2.

[0069] In an embodiment, such as Figure 2A As shown, each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 may include an NMOS. For example, the active pattern of each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 may include an oxide semiconductor material, but the invention is not limited thereto.

[0070] The light-emitting element LE may include a first electrode electrically connected to the second node N2 and a second electrode to which a second electrical voltage ELVSS is applied. The first electrode may be an anode electrode, and the second electrode may be a cathode electrode. The second electrical voltage ELVSS may be a low electrical voltage.

[0071] Reference Figure 2B In an embodiment, the pixel circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a first capacitor C1, and a second capacitor C2.

[0072] The first transistor T1 may include a gate electrode electrically connected to a first node N1, a first electrode, and a second electrode electrically connected to a second node N2. In an embodiment, the first transistor T1 may further include a back gate electrode electrically connected to the second node N2.

[0073] The second transistor T2 may include a gate electrode to which a write gate signal GW is applied, a first electrode electrically connected to a data line DL, and a second electrode electrically connected to a first node N1.

[0074] The third transistor T3 may include a gate electrode to which a reference gate signal GR is applied, a first electrode to which a reference voltage VREF is applied, and a second electrode electrically connected to the first node N1.

[0075] The fourth transistor T4 may include a gate electrode to which an initialization gate signal GI is applied, a first electrode to which an initialization voltage VINT is applied, and a second electrode electrically connected to the third node N3.

[0076] The fifth transistor T5 may include a gate electrode to which a first transmit control signal EM is applied, a first electrode to which a first power voltage ELVDD is applied, and a second electrode electrically connected to the first electrode of the first transistor T1. The first power voltage ELVDD may be a high power voltage.

[0077] The sixth transistor T6 may include a gate electrode to which a second transmit control signal EMB is applied, a first electrode electrically connected to the second node N2, and a second electrode electrically connected to the third node N3.

[0078] The first capacitor C1 may include a first electrode electrically connected to a first node N1 and a second electrode electrically connected to a second node N2.

[0079] The second capacitor C2 may include a first electrode to which a first electrical voltage ELVDD is applied, and a second electrode electrically connected to the back gate electrode of the first transistor T1 and the second node N2.

[0080] In an embodiment, such as Figure 2B As shown, each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may include an NMOS. For example, the active pattern of each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may include an oxide semiconductor material, but the invention is not limited thereto.

[0081] The light-emitting element LE may include a first electrode electrically connected to a third node N3 and a second electrode to which a second electrical voltage ELVSS is applied. The first electrode may be an anode electrode, and the second electrode may be a cathode electrode. The second electrical voltage ELVSS may be a low electrical voltage.

[0082] Reference Figure 2C In an embodiment, the pixel circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a first capacitor C1.

[0083] The first transistor T1 may include a gate electrode electrically connected to a first node N1, a first electrode electrically connected to a second node N2, and a second electrode electrically connected to a third node N3. In an embodiment, the first transistor T1 may further include a back gate electrode to which a first power voltage ELVDD is applied. The first power voltage ELVDD may be a high power voltage.

[0084] The second transistor T2 may include a gate electrode to which a write gate signal GW is applied, a first electrode electrically connected to a data line DL, and a second electrode electrically connected to a second node N2.

[0085] The third transistor T3 may include a gate electrode to which a compensation gate signal GC is applied, a first electrode electrically connected to the first node N1, and a second electrode electrically connected to the third node N3.

[0086] The fourth transistor T4 may include a gate electrode to which an initialization gate signal GI is applied, a first electrode to which a first initialization voltage VINT is applied, and a second electrode electrically connected to the first electrode of the first node N1 and the third transistor T3.

[0087] The fifth transistor T5 may include a gate electrode to which a transmit control signal EM is applied, a first electrode to which a first power voltage ELVDD is applied, and a second electrode electrically connected to the second node N2.

[0088] The sixth transistor T6 may include a gate electrode to which an emission control signal EM is applied, a first electrode electrically connected to the third node N3, and a second electrode electrically connected to the fourth node N4.

[0089] The seventh transistor T7 may include a gate electrode to which a bias gate signal GB is applied, a first electrode to which a second initialization voltage VAINT is applied, and a second electrode electrically connected to the fourth node N4.

[0090] The first capacitor C1 may include a first electrode to which a first electrical voltage ELVDD is applied and a second electrode electrically connected to the first node N1.

[0091] In an embodiment, such as Figure 2C As shown, each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may include a P-type metal-oxide-semiconductor (PMOS), and each of the third transistor T3 and the fourth transistor T4 may include an N-type metal-oxide-semiconductor (NMOS). For example, the active pattern of each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may include a silicon semiconductor material, and the active pattern of each of the third transistor T3 and the fourth transistor T4 may include an oxide semiconductor material, but the invention is not limited thereto.

[0092] The light-emitting element LE may include a first electrode electrically connected to the fourth node N4 and a second electrode to which a second electrical voltage ELVSS is applied. The first electrode may be an anode electrode, and the second electrode may be a cathode electrode. The second electrical voltage ELVSS may be a low electrical voltage.

[0093] Reference Figure 2D In an embodiment, the pixel circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a first capacitor C1.

[0094] The first transistor T1 may include a gate electrode electrically connected to a first node N1, a first electrode electrically connected to a second node N2, and a second electrode electrically connected to a third node N3. In an embodiment, the first transistor T1 may further include a back gate electrode to which a first power voltage ELVDD is applied. The first power voltage ELVDD may be a high power voltage.

[0095] The second transistor T2 may include a gate electrode to which a write gate signal GW is applied, a first electrode electrically connected to a data line DL, and a second electrode electrically connected to a second node N2.

[0096] The third transistor T3 may include a gate electrode to which a compensation gate signal GC is applied, a first electrode electrically connected to the first node N1, and a second electrode electrically connected to the third node N3.

[0097] The fourth transistor T4 may include a gate electrode to which an initialization gate signal GI is applied, a first electrode to which a first initialization voltage VINT is applied, and a second electrode electrically connected to the first electrode of the first node N1 and the third transistor T3.

[0098] The fifth transistor T5 may include a gate electrode to which a transmit control signal EM is applied, a first electrode to which a first power voltage ELVDD is applied, and a second electrode electrically connected to the second node N2.

[0099] The sixth transistor T6 may include a gate electrode to which an emission control signal EM is applied, a first electrode electrically connected to the third node N3, and a second electrode electrically connected to the fourth node N4.

[0100] The seventh transistor T7 may include a gate electrode to which a bias gate signal GB is applied, a first electrode to which a second initialization voltage VAINT is applied, and a second electrode electrically connected to the fourth node N4.

[0101] The eighth transistor T8 may include a gate electrode to which a bias gate signal GB is applied, a first electrode to which a conduction bias voltage VOBS is applied, and a second electrode electrically connected to the second node N2.

[0102] The first capacitor C1 may include a first electrode to which a first electrical voltage ELVDD is applied and a second electrode electrically connected to the first node N1.

[0103] In an embodiment, such as Figure 2D As shown, each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may include a PMOS, and each of the third transistor T3 and the fourth transistor T4 may include an NMOS. For example, the active pattern of each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may include a silicon semiconductor material, and the active pattern of each of the third transistor T3 and the fourth transistor T4 may include an oxide semiconductor material, but the invention is not limited thereto.

[0104] The light-emitting element LE may include a first electrode electrically connected to the fourth node N4 and a second electrode to which a second electrical voltage ELVSS is applied. The first electrode may be an anode electrode, and the second electrode may be a cathode electrode. The second electrical voltage ELVSS may be a low electrical voltage.

[0105] Although the above has been referenced Figures 2A to 2D A pixel circuit PC according to an embodiment has been described, but this is only an example, and the invention is not necessarily limited thereto, and the structure of the pixel circuit PC can be changed differently.

[0106] Therefore, the display device may include a display surface, which may be flat or curved, oriented along two mutually perpendicular directions, and viewing the image in the normal direction (i.e., the third direction DR3). The display device may include a display area having pixels that generate images using red, green, or blue light, and a peripheral area housing drivers and transmission lines for controlling these pixels. Each pixel is characterized by pixel circuitry having multiple transistors and capacitors controlling a light-emitting element that operates with a high power voltage for driving and a low power voltage for emission; and, depending on the design, these circuits may vary in configuration using NMOS, PMOS, or hybrid transistor types.

[0107] Figure 3 It is shown Figure 1 A plan view of the emission area of ​​the display device.

[0108] Reference Figure 3In an embodiment, the display area DA may include a first emission area EAa, a second emission area EAb, a third emission area EAc, and a non-emission area NEA.

[0109] The first emission region EAa, the second emission region EAb, and the third emission region EAc can be spaced apart from each other in a plan view. Light-emitting elements can be respectively disposed in the first emission region EAa, the second emission region EAb, and the third emission region EAc. The first emission region EAa, the second emission region EAb, and the third emission region EAc can all be regions from which light is emitted. For example, the first light-emitting element LDa can be disposed in the first emission region EAa, and the first emission region EAa can be a region from which light is emitted. The second light-emitting element LDb can be disposed in the second emission region EAb, and the second emission region EAb can be a region from which light is emitted. The third light-emitting element LDc can be disposed in the third emission region EAc, and the third emission region EAc can be a region from which light is emitted.

[0110] In this embodiment, the first emission region EAa, the second emission region EAb, and the third emission region EAc can emit light of different colors. For example, the first emission region EAa can emit blue light, the second emission region EAb can emit red light, and the third emission region EAc can emit green light. However, this is just an example, and the invention is not necessarily limited thereto.

[0111] In this embodiment, the first light-emitting element LDa, the second light-emitting element LDb, and the third light-emitting element LDc can emit light of different colors. For example, the first light-emitting element LDa can emit blue light, the second light-emitting element LDb can emit red light, and the third light-emitting element LDc can emit green light. However, this is just an example, and the invention is not necessarily limited thereto.

[0112] The light-emitting element may not be located within the non-emitting region NEA. The non-emitting region NEA can be a region that does not emit light. The non-emitting region NEA can be located between the first emitting region EAa, the second emitting region EAb, and the third emitting region EAc. For example, the non-emitting region NEA can surround each of the first emitting region EAa, the second emitting region EAb, and the third emitting region EAc in a planar diagram.

[0113] In an embodiment, the first transmission region EAa, the second transmission region EAb, and the third transmission region EAc, which are adjacent to each other, can form a unit transmission region (first unit transmission region UEA1 or second unit transmission region UEA2). In an embodiment, as... Figure 3As shown, in each unit transmission region, the first transmission region EAa, the second transmission region EAb, and the third transmission region EAc can be arranged in an S-stripe pattern. For example, in each unit transmission region, the first transmission region EAa can be positioned relative to the second transmission regions EAb and the third transmission region EAc in a first direction DR1, and the third transmission region EAc can be positioned relative to the second transmission region EAb in a second direction DR2. However, this is an example, and the invention is not necessarily limited thereto, and the arrangement of the first transmission region EAa, the second transmission region EAb, and the third transmission region EAc can be varied according to embodiments.

[0114] In an embodiment, the first unit transmission area UEA1 and the second unit transmission area UEA2 can be defined as a matrix in the first direction DR1 and the second direction DR2. Although Figure 3 Four unit emission regions are shown, but the unit emission regions can be defined as a matrix in the display area DA along the first direction DR1 and the second direction DR2.

[0115] In an embodiment, the first unit emission region UEA1 and the second unit emission region UEA2 can be distinguished based on the arrangement of the first light-emitting element LDa, the second light-emitting element LDb, and the third light-emitting element LDc (or the arrangement of the first emission region EAa, the second emission region EAb, and the third emission region EAc). For example, for each first unit emission region UEA1, the arrangement of the first light-emitting element LDa, the second light-emitting element LDb, and the third light-emitting element LDc (or the arrangement of the first emission region EAa, the second emission region EAb, and the third emission region EAc) can be the same, and for each second unit emission region UEA2, the arrangement of the first light-emitting element LDa, the second light-emitting element LDb, and the third light-emitting element LDc (or the arrangement of the first emission region EAa, the second emission region EAb, and the third emission region EAc) can be the same.

[0116] like Figure 3 and Figure 4 As shown, in an embodiment, the first unit emission area UEA1 and the second unit emission area UEA2 can be alternately arranged in the first direction DR1 (i.e., the row direction) and the second direction DR2 (i.e., the column direction). However, the invention is not limited to this, and the number of different unit emission areas or the arrangement of the unit emission areas included in the display device DD can be varied according to different embodiments.

[0117] Figures 4 to 6 It is shown Figure 1 A floor plan of an example of a magnified portion of a display device. Figure 7 It is along Figure 4 A sectional view taken from line I-I'.

[0118] Figure 4 It shows Figure 1 It is a part of the display area DA of the display device DD. Figure 5 It shows Figure 4 The first cathode electrode CE1, Figure 6 It shows Figure 4 The second cathode electrode CE2. In the following text, reference will be made to... Figures 4 to 7 The planar and cross-sectional structures of the display area DA of the display device DD according to the embodiment are described in detail.

[0119] Reference Figures 4 to 7 In an embodiment, the display device DD may include a substrate SUB, a first pixel circuit PCa, a second pixel circuit PCb and a third pixel circuit PCc, a first insulating layer IL1, a second insulating layer IL2, a third insulating layer IL3 and a fourth insulating layer IL4, a first via insulating layer VIA1 and a second via insulating layer VIA2, a first anode connection electrode ACEa, a second anode connection electrode ACEb and a third anode connection electrode ACEc, a horizontal transmission line HL, a vertical transmission line VL, a first light-emitting element LDa, a second light-emitting element LDb and a third light-emitting element LDc, a pixel defining layer PDL, a spacer SPR and an encapsulation layer ENC.

[0120] The substrate SUB can form the base of the display device DD. In embodiments, examples of materials that can be used as the substrate SUB include glass, quartz, silicon, polymers, etc. These can be used alone or in combination with each other. Additionally, the substrate SUB can have a single-layer structure or a multi-layer structure in which multiple layers comprising different materials are stacked.

[0121] A first insulating layer IL1 may be disposed on a substrate SUB. In an embodiment, the first insulating layer IL1 may comprise an inorganic insulating material. Examples of insulating materials that can be used as the first insulating layer IL1 may include silicon oxide (SiO2). x Silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y These can be used individually or in combination with each other. The first insulating layer IL1 can have a single-layer structure or a multi-layer structure in which multiple insulating layers are stacked.

[0122] The first pixel circuit PCa, the second pixel circuit PCb, and the third pixel circuit PCc can be disposed on the first insulating layer IL1 in the display area DA. The first pixel circuit PCa, the second pixel circuit PCb, and the third pixel circuit PCc can be electrically connected to the first light-emitting element LDa, the second light-emitting element LDb, and the third light-emitting element LDc, respectively. In an embodiment, the same high electrical voltage can be applied to the first pixel circuit PCa, the second pixel circuit PCb, and the third pixel circuit PCc.

[0123] Each of the first pixel circuit PCa, the second pixel circuit PCb, and the third pixel circuit PCc may include at least one thin-film transistor and at least one capacitor. For example, each of the first pixel circuit PCa, the second pixel circuit PCb, and the third pixel circuit PCc may be Figures 2A to 2D One of the pixel circuits in a PC. For ease of description, in Figure 7 The diagram illustrates a first transistor TRa included in a first pixel circuit PCa, a second transistor TRb included in a second pixel circuit PCb, and a third transistor TRc included in a third pixel circuit PCc. For example, the first transistor TRa, the second transistor TRb, and the third transistor TRc could be... Figure 2A The first transistor T1, Figure 2B The sixth transistor T6, Figure 2C The sixth transistor T6 and Figure 2D One of the sixth transistors, T6.

[0124] In an embodiment, the first transistor TRa may include an active pattern AP, a gate electrode GE, a first contact electrode SE, and a second contact electrode DE.

[0125] An active patterned AP can be disposed on a first insulating layer IL1. The active patterned AP can include an oxide semiconductor material, a silicon semiconductor material, and / or an organic semiconductor material. The active patterned AP can include a first contact region S, a second contact region D, and a channel region CH between the first contact region S and the second contact region D. The first contact region S and the second contact region D can have a higher conductivity than the channel region CH.

[0126] In embodiments, the active patterned AP may include an oxide semiconductor material. Examples of oxide semiconductor materials that can be used as active patterned APs include indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), indium tin zinc oxide (ITZO), etc. These can be used alone or in combination with each other. However, the invention is not limited thereto, and the active patterned AP may include a silicon semiconductor material.

[0127] A second insulating layer IL2 may be disposed on the first insulating layer IL1. The second insulating layer IL2 may cover the active pattern AP. In an embodiment, the second insulating layer IL2 may include an inorganic insulating material. The second insulating layer IL2 may have a single-layer structure or a multilayer structure in which multiple insulating layers are stacked.

[0128] The gate electrode GE can be disposed on the second insulating layer IL2. The gate electrode GE can be stacked with the channel region CH of the active pattern AP. The gate electrode GE can include conductive materials, such as metals, alloys, conductive metal oxides (e.g., transparent conductive oxides), conductive metal nitrides, etc. The gate electrode GE can have a single-layer structure or a multilayer structure in which multiple conductive layers are stacked.

[0129] A third insulating layer IL3 may be disposed on the second insulating layer IL2. The third insulating layer IL3 may cover the gate electrode GE. In an embodiment, the third insulating layer IL3 may comprise an inorganic insulating material. The third insulating layer IL3 may have a single-layer structure or a multilayer structure in which multiple insulating layers are stacked.

[0130] In an embodiment, capacitor electrodes may be disposed on a third insulating layer IL3. The capacitor electrodes and a conductive pattern (e.g., a gate electrode GE) disposed between the second insulating layer IL2 and the third insulating layer IL3 and superimposed on the capacitor electrodes can form a capacitor.

[0131] A fourth insulating layer IL4 may be disposed on the third insulating layer IL3. The fourth insulating layer IL4 may cover the capacitor electrodes. In an embodiment, the fourth insulating layer IL4 may comprise an inorganic insulating material. The fourth insulating layer IL4 may have a single-layer structure or a multilayer structure in which multiple insulating layers are stacked.

[0132] The first contact electrode SE and the second contact electrode DE can be disposed on the fourth insulating layer IL4. The first contact electrode SE can contact the first contact area S of the active pattern AP, and the second contact electrode DE can contact the second contact area D of the active pattern AP. Each of the first contact electrode SE and the second contact electrode DE can include a conductive material, such as a metal, alloy, conductive metal oxide (e.g., transparent conductive oxide), conductive metal nitride, etc. Each of the first contact electrode SE and the second contact electrode DE can have a single-layer structure or a multilayer structure in which multiple conductive layers are stacked.

[0133] In an embodiment, the display device DD may further include a lower conductive pattern disposed between the substrate SUB and the first insulating layer IL1 and superimposed on the active pattern AP. For example, the lower conductive pattern may be electrically connected to one of the gate electrode GE, the first contact electrode SE, and the second contact electrode DE.

[0134] The description of the first transistor TRa described above can be applied substantially equivalently to the second transistor TRb included in the second pixel circuit PCb and the third transistor TRc included in the third pixel circuit PCc.

[0135] A first via insulating layer VIA1 may be disposed on a fourth insulating layer IL4. The first via insulating layer VIA1 may cover the first contact electrode SE and the second contact electrode DE. In embodiments, the first via insulating layer VIA1 may include an organic insulating material. Examples of organic insulating materials that can be used as the first via insulating layer VIA1 may include photoresists, acrylic resins (e.g., polyacrylic resins), polyimide resins, polyamide resins, siloxane resins, epoxy resins, etc. These may be used alone or in combination with each other. The first via insulating layer VIA1 may have a single-layer structure or a multilayer structure in which multiple insulating layers are stacked.

[0136] The first anode connecting electrode ACEa, the second anode connecting electrode ACEb, and the third anode connecting electrode ACEc can be disposed on the first via insulating layer VIA1. The first anode connecting electrode ACEa can electrically connect the first pixel circuit PCa and the first light-emitting element LDA. The first anode connecting electrode ACEa can contact the first contact electrode SE or the second contact electrode DE of the first transistor TRa of the first pixel circuit PCa. The second anode connecting electrode ACEb can electrically connect the second pixel circuit PCb and the second light-emitting element LDb. The second anode connecting electrode ACEb can contact the first contact electrode or the second contact electrode of the second transistor TRb of the second pixel circuit PCb. The third anode connecting electrode ACEc can electrically connect the third pixel circuit PCc and the third light-emitting element LDc. The third anode connecting electrode ACEc can contact the first contact electrode or the second contact electrode of the third transistor TRc of the third pixel circuit PCc.

[0137] Each of the first anode connecting electrode ACEa, the second anode connecting electrode ACEb, and the third anode connecting electrode ACEc may include a conductive material, such as a metal, an alloy, a conductive metal oxide (e.g., a transparent conductive oxide), a conductive metal nitride, etc. Each of the first anode connecting electrode ACEa, the second anode connecting electrode ACEb, and the third anode connecting electrode ACEc may have a single-layer structure or a multilayer structure in which multiple conductive layers are stacked.

[0138] A second via insulating layer VIA2 may be disposed on the first via insulating layer VIA1. The second via insulating layer VIA2 may cover the first anode connection electrode ACEa, the second anode connection electrode ACEb, and the third anode connection electrode ACEc. In an embodiment, the second via insulating layer VIA2 may include an organic insulating material. The second via insulating layer VIA2 may have a single-layer structure or a multilayer structure in which multiple insulating layers are stacked.

[0139] In an embodiment, such as Figure 4 As shown, horizontal transmission lines HL can extend generally in the first direction DR1 and can be spaced apart from each other in the second direction DR2. Vertical transmission lines VL can extend generally in the second direction DR2 and can be spaced apart from each other in the first direction DR1. Horizontal transmission lines HL and vertical transmission lines VL can cross each other.

[0140] Horizontal transmission lines (HL) can be placed on the same layer as each other. Vertical transmission lines (VL) can be placed on the same layer as each other. Vertical transmission lines (VL) can also be placed on different layers from horizontal transmission lines (HL).

[0141] In this embodiment, the horizontal transmission line HL can be disposed between the substrate SUB and the first insulating layer IL1, and the vertical transmission line VL can be disposed between the first via insulating layer VIA1 and the second via insulating layer VIA2 (see...). Figure 9 For example, the horizontal transmission line HL and the lower conductive pattern can be disposed on the same layer and can be formed substantially simultaneously with each other. The vertical transmission line VL and the first anode connection electrode ACEa, the second anode connection electrode ACEb, and the third anode connection electrode ACEc can be disposed on the same layer and can be formed substantially simultaneously with each other. However, this is an example, and the invention is not limited thereto, and each of the horizontal transmission line HL and the vertical transmission line VL can be disposed on the same layer as another conductive layer (e.g., gate electrode GE, capacitor electrode, first contact electrode SE, and second contact electrode DE, etc.) between the substrate SUB and the first light-emitting element LDa, the second light-emitting element LDb, and the third light-emitting element LDc.

[0142] In an embodiment, such as Figure 4 As shown, horizontal transmission lines HL and vertical transmission lines VL can correspond one-to-one with a unit transmission area. For example, one horizontal transmission line HL and one vertical transmission line VL can correspond to one unit transmission area. However, this is an example, and the invention is not limited thereto, and the number of horizontal transmission lines HL and vertical transmission lines VL corresponding to one unit transmission area can be varied.

[0143] In this embodiment, the horizontal transmission line HL may include a first horizontal power transmission line HSL1 and a second horizontal power transmission line HSL2. The first horizontal power transmission line HSL1 and the second horizontal power transmission line HSL2 may not be electrically connected to each other (or may be electrically insulated from each other).

[0144] In this embodiment, the vertical transmission line VL may include a first vertical power transmission line VSL1, a second vertical power transmission line VSL2, and a voltage transmission line VTL. The first vertical power transmission line VSL1, the second vertical power transmission line VSL2, and the voltage transmission line VTL may not be electrically connected to each other (or may be electrically insulated from each other).

[0145] In an embodiment, the first vertical power transmission line VSL1 can be electrically connected to the first horizontal power transmission line HSL1 (see...). Figure 9 A first low power voltage can be applied to the first vertical power transmission line VSL1 and the first horizontal power transmission line HSL1. For example, the first vertical power transmission line VSL1 or the first horizontal power transmission line HSL1 can be electrically connected to the peripheral area PA (see...). Figure 1 The first power line in the first power line can receive a first low power voltage. In an embodiment, the first vertical power transmission line VSL1 and the first horizontal power transmission line HSL1 can transmit the first low power voltage to the first light-emitting element LDa. This will be described in detail later.

[0146] In this embodiment, the second vertical power transmission line VSL2 can be electrically connected to the second horizontal power transmission line HSL2 (see...). Figure 13 A second low power voltage can be applied to the second vertical power transmission line VSL2 and the second horizontal power transmission line HSL2. In an embodiment, the second low power voltage may have a different voltage level than the first low power voltage. For example, the second vertical power transmission line VSL2 or the second horizontal power transmission line HSL2 may be electrically connected to the peripheral area PA (see...). Figure 1 The second power line in the system can receive a second low power voltage. In an embodiment, the second vertical power transmission line VSL2 and the second horizontal power transmission line HSL2 can transmit the second low power voltage to the second light-emitting element LDb and the third light-emitting element LDc. This will be described in detail later.

[0147] The voltage required to drive the display area DA (e.g., high power voltage, initialization voltage, reference voltage, etc.) can be applied to the voltage transmission line VTL.

[0148] Figure 4 The arrangement of the horizontal transmission line HL and the vertical transmission line VL shown is an example, and the invention is not necessarily limited thereto.

[0149] like Figure 7 As shown, the first light-emitting element LDa, the second light-emitting element LDb, and the third light-emitting element LDc can be disposed on the second via insulating layer VIA2. The first light-emitting element LDa, the second light-emitting element LDb, and the third light-emitting element LDc can be disposed in the first emission region EAa, the second emission region EAb, and the third emission region EAc, respectively.

[0150] The first light-emitting element LDa may include a first anode electrode AEa, a first intermediate layer MLA, and a first cathode electrode CE1. The first intermediate layer MLA may include a first lower functional layer BL1, a first emitting layer ELA, and a first upper functional layer UL1. For example, the first emitting layer ELA may include a first emitting material that emits blue light.

[0151] The second light-emitting element LDb may include a second anode electrode AEb, a second intermediate layer MLb, and a second cathode electrode CE2. The second intermediate layer MLb may include a second lower functional layer BL2, a second emitting layer ELb, and a second upper functional layer UL2. For example, the second emitting layer ELb may include a second emitting material that emits red light.

[0152] The third light-emitting element LDc may include a third anode electrode AEc, a third intermediate layer MLc, and a second cathode electrode CE2. The third intermediate layer MLc may include a second lower functional layer BL2, a third emitting layer ELc, and a second upper functional layer UL2. For example, the third emitting layer ELc may include a third emitting material that emits green light.

[0153] In this embodiment, the second light-emitting element LDb and the third light-emitting element LDc can share the second cathode electrode CE2. For example, as... Figure 6 As shown, the second cathode electrode CE2 can be entirely formed within the second emission region EAb and the third emission region EAc. A portion of the second cathode electrode CE2 can serve as the cathode of the second light-emitting element LDb, and another portion of the second cathode electrode CE2 can serve as the cathode of the third light-emitting element LDc. Furthermore, the second light-emitting element LDb and the third light-emitting element LDc can share the second lower functional layer BL2 and the second upper functional layer UL2.

[0154] The first anode electrode AEa, the second anode electrode AEb, and the third anode electrode AEc can be disposed on the second via insulating layer VIA2. The first anode electrode AEa, the second anode electrode AEb, and the third anode electrode AEc can be disposed in the first emission region EAa, the second emission region EAb, and the third emission region EAc, respectively. Each of the first anode electrode AEa, the second anode electrode AEb, and the third anode electrode AEc can include a conductive material, such as a metal, an alloy, a conductive metal oxide (e.g., a transparent conductive oxide), a conductive metal nitride, etc. Each of the first anode electrode AEa, the second anode electrode AEb, and the third anode electrode AEc can have a single-layer structure or a multilayer structure in which multiple conductive layers are stacked.

[0155] The first anode electrode AEa can contact the first anode connection electrode ACEa. Therefore, the first anode electrode AEa can be electrically connected to the first pixel circuit PCa through the first anode connection electrode ACEa.

[0156] The second anode electrode AEb can contact the second anode connection electrode ACEb. Therefore, the second anode electrode AEb can be electrically connected to the second pixel circuit PCb through the second anode connection electrode ACEb.

[0157] The third anode electrode AEc can contact the third anode connecting electrode ACEc. Therefore, the third anode electrode AEc can be electrically connected to the third pixel circuit PCc through the third anode connecting electrode ACEc.

[0158] A pixel defining layer (PDL) may be disposed on a second via insulating layer (VIA2). The PDL may cover the peripheral portions of each of the first anode electrode AEa, the second anode electrode AEb, and the third anode electrode AEc, such that the first anode electrode AEa, the second anode electrode AEb, and the third anode electrode AEc are spaced apart from each other. The PDL may define a first pixel opening POa that exposes the central portion of the first anode electrode AEa, a second pixel opening POb that exposes the central portion of the second anode electrode AEb, and a third pixel opening POc that exposes the central portion of the third anode electrode AEc. A first emission region EAa may be defined by the first pixel opening POa, a second emission region EAb may be defined by the second pixel opening POb, and a third emission region EAc may be defined by the third pixel opening POc.

[0159] In some embodiments, the pixel defining layer (PDL) may include an organic insulating material. For example, the pixel defining layer (PDL) may include a photosensitive resin. In some embodiments, the pixel defining layer (PDL) may also include a light-blocking material, such as a black dye, pigment, carbon black, etc.

[0160] Spacer spacers (SPRs) can be set on the pixel definition layer (PDL). For example... Figure 4 As shown, the spacer SPR can be positioned in the non-emission region NEA in the plan view. The spacer SPR may not overlap with the first emission region EAa, the second emission region EAb, and the third emission region EAc in the plan view. In an embodiment, the spacer SPRs may be spaced apart from each other in the plan view.

[0161] In an embodiment, each of the spacers SPRs may surround at least one of the first transmission regions EAa in a plan view. For example, each of the spacers SPRs may have a closed-loop shape in a plan view. For example, each of the spacers SPRs may surround two or more first transmission regions EAa that are adjacent to each other in the second direction DR2 in a plan view. For example, one spacer SPR may correspond to two or more first transmission regions EAa. The spacers SPRs may not surround the second transmission region EAb and the third transmission region EAc in a plan view.

[0162] All of the first emission regions EAa can be surrounded by spacers SPR in a plan view. Each of the first emission regions EAa can be surrounded by one of the spacers SPR in a plan view. For example, in a plan view, each of the first emission regions EAa can be located inside the corresponding spacer SPR, and the second emission region EAb and the third emission region EAc can be located outside the spacers SPR.

[0163] like Figures 4 to 7 As shown, the spacer SPR can separate (or disconnect) the cathode electrode layer CEL into a first cathode electrode CE1 and a second cathode electrode CE2. Additionally, the spacer SPR can separate (or disconnect) the lower functional layer into a first lower functional layer BL1 and a second lower functional layer BL2, and can separate (or disconnect) the upper functional layer into a first upper functional layer UL1 and a second upper functional layer UL2. This will be described in detail later.

[0164] In this embodiment, each of the spacers SPRs may include an organic electrically insulating material. For example, each of the spacers SPRs may include a photosensitive resin.

[0165] In an embodiment, such as Figure 7 As shown, the width of the upper part of the spacer SPR can be greater than the width of the lower part of the spacer SPR. For example, the side surface of the spacer SPR that connects the upper surface and the lower surface of the spacer SPR can be an inverted conical inclined surface. For example, the side surface of the spacer SPR can have multiple inverted conical inclined surfaces. For example, the spacer SPR can have a double inverted conical structure.

[0166] The first intermediate layer MLa can be disposed on the first anode electrode AEa and the pixel definition layer PDL. The second intermediate layer MLb can be disposed on the second anode electrode AEb and the pixel definition layer PDL. The third intermediate layer MLc can be disposed on the third anode electrode AEc and the pixel definition layer PDL.

[0167] In this embodiment, the first emitter layer ELa can be disposed on the first anode electrode AEa within the first pixel opening POa. The second emitter layer ELb can be disposed on the second anode electrode AEb within the second pixel opening POb. The third emitter layer ELc can be disposed on the third anode electrode AEc within the third pixel opening POc.

[0168] Each of the first lower functional layer BL1, the second lower functional layer BL2, the first upper functional layer UL1, and the second upper functional layer UL2 may include an organic material. The first lower functional layer BL1 and the second lower functional layer BL2 may have the same material and the same layer structure, and the first upper functional layer UL1 and the second upper functional layer UL2 may also have the same material and the same layer structure. The first lower functional layer BL1 and the second lower functional layer BL2 may be formed substantially simultaneously with each other, and the first upper functional layer UL1 and the second upper functional layer UL2 may also be formed substantially simultaneously with each other. For example, each of the first lower functional layer BL1 and the second lower functional layer BL2 may include a hole injection layer, a hole transport layer, etc., and each of the first upper functional layer UL1 and the second upper functional layer UL2 may include an electron transport layer, an electron injection layer, etc.

[0169] There may be shaded areas around the spacer SPR with its inverted conical inclined surface, making it difficult to deposit the lower functional layer. Therefore, in and / or around the shaded areas, the lower functional layer may have a structure that is separated (or disconnected) by the spacer SPR. For example, the lower functional layer can be separated (or disconnected) by the spacer SPR into a first lower functional layer BL1 and a second lower functional layer BL2 that are spaced apart from each other.

[0170] There may be shaded areas around the spacer SPR with its inverted conical inclined surface, making it difficult to deposit the upper functional layer. Therefore, in and / or around the shaded areas, the upper functional layer may have a structure that is separated (or disconnected) by the spacer SPR. For example, the upper functional layer can be separated (or disconnected) by the spacer SPR into a first upper functional layer UL1 and a second upper functional layer UL2 that are spaced apart from each other.

[0171] In the embodiment, the first lower functional layer BL1 and the first upper functional layer UL1 may have the same characteristics as... Figure 5 The first cathode electrode CE1 has a planar shape that is substantially the same as that of the second lower functional layer BL2 and the second upper functional layer UL2. Figure 6The second cathode electrode CE2 has a substantially the same planar shape. For example, in the plan view, each of the first lower functional layer BL1 and each of the first upper functional layer UL1 can be completely disposed inside the corresponding spacer SPR. In the plan view, the second lower functional layer BL2 and the second upper functional layer UL2 can be completely disposed outside the spacer SPR.

[0172] The cathode electrode layer (CEL) can be disposed on a first intermediate layer (MLa), a second intermediate layer (MLb), and a third intermediate layer (MLc). The cathode electrode layer (CEL) can include conductive materials such as metals, alloys, conductive metal oxides (e.g., transparent conductive oxides), conductive metal nitrides, etc. In embodiments, the cathode electrode layer (CEL) can have a single-layer structure. However, the invention is not limited thereto. In embodiments, the cathode electrode layer (CEL) can have a multilayer structure in which multiple conductive layers are stacked. For example, the cathode electrode layer (CEL) can have a two-layer structure comprising a first sub-electrode layer of metallic material and a first and second sub-electrode layer comprising transparent conductive oxides stacked on top of each other.

[0173] There may be shaded areas around the spacer SPR with its inverted conical inclined surface, making it difficult to deposit the cathode electrode layer CEL. Therefore, in and / or around the shaded areas, the cathode electrode layer CEL has a structure that is separated (or disconnected) by the spacer SPR. For example, the cathode electrode layer CEL can be separated (or disconnected) by the spacer SPR into a first cathode electrode CE1 and a second cathode electrode CE2 spaced apart from each other.

[0174] like Figures 4 to 6 As shown, the first cathode electrode CE1 and the second cathode electrode CE2 may be spaced apart from each other in a plan view. The first cathode electrode CE1 and the second cathode electrode CE2 may not be electrically connected to each other (or may be electrically insulated from each other). The first cathode electrode CE1 and the second cathode electrode CE2 may have the same material and the same layered structure. The first cathode electrode CE1 and the second cathode electrode CE2 may be formed substantially simultaneously with each other.

[0175] In one embodiment, each of the first cathode electrodes CE1 can be completely disposed within the corresponding spacer SPR in a plan view. Each of the spacers SPR can be disposed between the corresponding first cathode electrode CE1 and the second cathode electrode CE2 in a plan view.

[0176] In an embodiment, in a plan view, the second cathode electrode CE2 may be spaced apart from the first cathode electrode CE1 and may surround the first cathode electrode CE1. In an embodiment, the second cathode electrode CE2 may be completely disposed outside the spacer SPR in a plan view. For example, the second cathode electrode CE2 may have a generally grid shape in a plan view.

[0177] In an embodiment, when each of the spacers SPR surrounds two or more adjacent first emission regions EAa in the second direction DR2 in a plan view, each of the first cathode electrodes CE1 may be superimposed on two or more adjacent first emission regions EAa in the second direction DR2 in a plan view. For example, one first cathode electrode CE1 may correspond to two or more first emission regions EAa.

[0178] Each of the first cathode electrodes CE1 may not be superimposed on the second emission region EAb and the third emission region EAc in a plan view. For example, each of the first cathode electrodes CE1 may be spaced apart from the second emission region EAb and the third emission region EAc in a plan view.

[0179] In an embodiment, the second cathode electrode CE2 may be superimposed on all of the second emission region EAb and all of the third emission region EAc in a plan view.

[0180] The second cathode electrode CE2 may not overlap with the first emission region EAa in the plan view. For example, the second cathode electrode CE2 may be spaced apart from the first emission region EAa in the plan view.

[0181] A first low voltage can be applied to the first cathode electrode CE1. Each first cathode electrode CE1 can be disposed on the first emitting layer ELa and can be used as the cathode of the first light-emitting element LDa.

[0182] A second low voltage can be applied to the second cathode electrode CE2. A portion of the second cathode electrode CE2 can be disposed on the second emitting layer ELb and can serve as the cathode of the second light-emitting element LDb. Another portion of the second cathode electrode CE2 can be disposed on the third emitting layer ELc and can serve as the cathode of the third light-emitting element LDc.

[0183] Each of the first cathode electrodes CE1 can receive a first low power voltage through its corresponding first horizontal power transmission line HSL1 and its corresponding first vertical power transmission line VSL1.

[0184] In an embodiment, the first cathode electrode CE1 may include a first-first cathode electrode CE1-1, a first-second cathode electrode CE1-2, and a first-third cathode electrode CE1-3. For example... Figure 4As shown, the first-first cathode electrode CE1-1 may be an electrode configured to correspond to (e.g., superimposed) the first vertical power transmission line VSL1 in the vertical transmission line VL, the first-second cathode electrode CE1-2 may be an electrode configured to correspond to (e.g., superimposed) the second vertical power transmission line VSL2 in the vertical transmission line VL, and the first-third cathode electrode CE1-3 may be an electrode configured to correspond to (e.g., superimposed) the voltage transmission line VTL in the vertical transmission line VL.

[0185] The first cathode electrode CE1-1 can be electrically connected to the first connection portion CP1 of the first vertical power transmission line VSL1 (see...). Figure 8 and Figure 9 Each of the first-second cathode electrode CE1-2 and the first-third cathode electrode CE1-3 can be electrically connected to the second connection portion CP2 of the corresponding first connecting electrode CNE1, and the first connecting electrode CNE1 can be electrically connected to the first horizontal power transmission line HSL1 (see...) via the second bridge electrode BRE2. Figure 10 and Figure 11 ).

[0186] The second cathode electrode CE2 can receive a second low power voltage via the second horizontal power transmission line HSL2 and the second vertical power transmission line VSL2. The second cathode electrode CE2 can be electrically connected to the third connection portion CP3 of the second vertical power transmission line VSL2 (see...). Figure 12 and Figure 13 For example, the second cathode electrode CE2 can be electrically connected to multiple second vertical power transmission lines VSL2.

[0187] Please refer to later Figures 8 to 13 The connection structure of the first cathode electrode CE1, the first vertical power transmission line VSL1 and the first horizontal power transmission line HSL1 is described in detail, as well as the connection structure of the second cathode electrode CE2, the second vertical power transmission line VSL2 and the second horizontal power transmission line HSL2.

[0188] In an embodiment, the first dummy pattern DP1, the second dummy pattern DP2, and the third dummy pattern DP3 can be disposed on the spacer SPR. For example, the first dummy pattern DP1 can be formed from a lower functional layer separated (or disconnected) by the spacer SPR, the second dummy pattern DP2 can be formed from an upper functional layer separated (or disconnected) by the spacer SPR, and the third dummy pattern DP3 can be formed from a cathode electrode layer CEL separated (or disconnected) by the spacer SPR. For example, the first dummy pattern DP1 can be formed using the same process as the first lower functional layer BL1 and the second lower functional layer BL2, the second dummy pattern DP2 can be formed using the same process as the first upper functional layer UL1 and the second upper functional layer UL2, and the third dummy pattern DP3 can be formed using the same process as the first cathode electrode CE1 and the second cathode electrode CE2. In an embodiment, at least some of the first dummy pattern DP1, the second dummy pattern DP2, and the third dummy pattern DP3 can be omitted.

[0189] The encapsulation layer ENC can be disposed on the first cathode electrode CE1 and the second cathode electrode CE2. The encapsulation layer ENC can completely cover the spacer SPR, the first cathode electrode CE1, the second cathode electrode CE2, and the first dummy pattern DP1, the second dummy pattern DP2, and the third dummy pattern DP3. In an embodiment, the encapsulation layer ENC may include: a first inorganic encapsulation layer comprising an inorganic insulating material; an organic encapsulation layer disposed on the first inorganic encapsulation layer and comprising an organic insulating material; and a second inorganic encapsulation layer disposed on the organic encapsulation layer and comprising an inorganic insulating material.

[0190] In an embodiment, the touch sensing layer may be disposed on the encapsulation layer ENC. For example, the touch sensing layer may include a plurality of touch electrode arrays for capacitively detecting user input, a touch pad portion, and a plurality of touch wirings electrically connecting the touch pad portion and the touch electrode arrays. However, the invention is not limited thereto. In an embodiment, the touch sensing layer may be omitted.

[0191] The driving voltages required to drive the first light-emitting element LDa, the second light-emitting element LDb, and the third light-emitting element LDc, which emit different colors of light, can be different from each other. For example, the driving voltage required to drive the second light-emitting element LDb, which emits red light, can be similar to the driving voltage required to drive the third light-emitting element LDc, which emits green light. However, the difference between the driving voltage required to drive the first light-emitting element LDa, which emits blue light, and the driving voltage required to drive the second light-emitting element LDb, which emits red light (or the driving voltage required to drive the third light-emitting element LDc, which emits green light), can be relatively large. In this case, if the same high power voltage and the same low power voltage of the same voltage level are applied to all pixels (e.g., blue pixels, red pixels, and green pixels), the power consumption of the display device DD will increase.

[0192] In the display device DD, according to an embodiment, low power voltages with different voltage levels can be applied to at least some of the first light-emitting elements LDa, the second light-emitting element LDb, and the third light-emitting element LDc that emit light of different colors. For example, a first low power voltage can be applied to the first cathode electrode CE1 of the first light-emitting element LDa (e.g., a blue light-emitting element), and a second low power voltage with a different voltage level can be applied to the second cathode electrodes CE2 of the second light-emitting element LDb (e.g., a red light-emitting element) and the third light-emitting element LDc (e.g., a green light-emitting element), which require similar driving voltages. For example, in the display device DD according to an embodiment, a low power voltage optimized for each pixel can be applied to the light-emitting element compared to the case where the same low power voltage of the same voltage level is applied to all pixels (e.g., blue pixels, red pixels, and green pixels). Therefore, the power consumption of the display device DD can be reduced.

[0193] Therefore, the display area can be divided into a first emitting region, a second emitting region, and a third emitting region, each corresponding to a light-emitting element that generates blue, red, or green light, and these emitting regions are grouped into unit emitting regions arranged in an S-striped pattern. Spacers can be placed in the non-emitting areas to electrically isolate functional layers, thereby creating separate cathode electrodes for blue pixels and for red and green pixels. This structure allows different low-power voltages to be applied to different color groups, optimizing the voltage supply for each color, and significantly reducing power consumption compared to designs that apply the same voltage to all pixel types.

[0194] Figure 8 It is shown Figure 4 An enlarged plan view of the area surrounding the first connection portion of the display device. Figure 9 It is along Figure 8The sectional view taken from line II-II'.

[0195] In the following text, reference will be made to Figure 8 and Figure 9 A detailed description of the connection structure of the first-first cathode electrode CE1-1, the first vertical power transmission line VSL1, and the first horizontal power transmission line HSL1 is provided.

[0196] Reference Figure 4 , Figure 8 and Figure 9 In an embodiment, the first cathode electrode CE1-1 can be electrically connected to the first connection portion CP1 of the corresponding first vertical power transmission line VSL1.

[0197] In an embodiment, the first vertical power transmission line VSL1 may have a multilayer structure in which multiple conductive layers are stacked. For example, the first vertical power transmission line VSL1 may include a first conductive layer VSL1a, a second conductive layer VSL1b, and a third conductive layer VSL1c stacked in sequence.

[0198] In embodiments, the first conductive layer VSL1a may comprise a metal and / or a transparent conductive oxide. Examples of metals that can be used as the first conductive layer VSL1a include titanium (Ti), molybdenum (Mo), etc. Examples of transparent conductive oxides that can be used as the first conductive layer VSL1a include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), etc. x Indium oxide (InO) x Materials include indium gallium oxide (IGO) and zinc aluminum oxide (AZO). Compared to the second conductive layer VSL1b, the first conductive layer VSL1a can have a relatively small thickness.

[0199] The second conductive layer VSL1b may comprise a different material than the first conductive layer VSL1a. For example, the second conductive layer VSL1b may comprise a different metal than the first conductive layer VSL1a. Examples of metals that can be used as the second conductive layer VSL1b may include aluminum (Al), copper (Cu), etc. Compared to the first conductive layer VSL1a, the second conductive layer VSL1b may have a relatively large thickness.

[0200] The third conductive layer VSL1c can be made of a different material than the second conductive layer VSL1b. For example, the third conductive layer VSL1c can be made of a different metal and / or transparent conductive oxide than the second conductive layer VSL1b. Examples of metals that can be used as the third conductive layer VSL1c include Ti, Mo, etc. Examples of transparent conductive oxides that can be used as the third conductive layer VSL1c include ITO, IZO, ZnO. x InO xIGO, AZO, etc. Compared with the second conductive layer VSL1b, the third conductive layer VSL1c can have a relatively small thickness.

[0201] In this embodiment, the first conductive layer VSL1a and the third conductive layer VSL1c may comprise the same material. However, the invention is not limited thereto.

[0202] The side surface VSL1b-S of the second conductive layer VSL1b may be recessed in one direction relative to the side surface VSL1a-S of the first conductive layer VSL1a and the side surface VSL1c-S of the third conductive layer VSL1c, toward the center of the first vertical power transmission line VSL1. For example, the side surfaces VSL1a-S of the first conductive layer VSL1a and the side surface VSL1c-S of the third conductive layer VSL1c may protrude outward relative to the side surface VSL1b-S of the second conductive layer VSL1b. Therefore, due to the protruding portion of the third conductive layer VSL1c compared to the second conductive layer VSL1b, the first connection portion CP1 of the first vertical power transmission line VSL1 may have a pointed portion. For example, based on the same etching process, when etching the second conductive layer VSL1b using an etching material that has a higher etching rate than the first and third conductive layers VSL1a and VSL1c, the first vertical power transmission line VSL1 may be formed with a pointed portion.

[0203] Figure 9 The diagram illustrates a first vertical power transmission line VSL1 having a three-layer structure in which a first conductive layer VSL1a, a second conductive layer VSL1b, and a third conductive layer VSL1c are stacked. However, the invention is not limited to this, and the first vertical power transmission line VSL1 may have a two-layer structure in which a second conductive layer VSL1b and a third conductive layer VSL1c are stacked. For example, the first conductive layer VSL1a may be omitted.

[0204] The second via insulation layer VIA2 can define a first-first sub-opening OP1a that exposes a portion of the first vertical power transmission line VSL1. For example, the first-first sub-opening OP1a can expose the tip portion of the first connection portion CP1 of the first vertical power transmission line VSL1.

[0205] The pixel-defining layer (PDL) can define a first-second sub-aperture OP1b corresponding to the first-first sub-aperture OP1a. The first-second sub-aperture OP1b can be located on the first-first sub-aperture OP1a, and the first-first sub-aperture OP1a and the first-second sub-aperture OP1b can be spatially connected to each other. For example, the first-first sub-aperture OP1a and the first-second sub-aperture OP1b can be spatially connected to define a first opening OP1, and the first opening OP1 can expose the tip portion of the first connection portion CP1 of the first vertical power transmission line VSL1.

[0206] The lower functional layer, upper functional layer, and cathode electrode layer CEL can also be separated (or disconnected) through the tip portion of the first connection portion CP1 of the first vertical power transmission line VSL1. Because the lower and upper functional layers are separated (or disconnected) through the tip portion of the first connection portion CP1 of the first vertical power transmission line VSL1, at least a portion of the side surface VSL1b-S of the second conductive layer VSL1b of the first vertical power transmission line VSL1 is exposed. Therefore, the first cathode electrode CE1-1 can contact the side surface VSL1b-S of the second conductive layer VSL1b of the first vertical power transmission line VSL1.

[0207] The first-first cathode electrode CE1-1 can be electrically connected to the corresponding first vertical power transmission line VSL1. For example, the first-first cathode electrode CE1-1 can contact the side surface VSL1b-S of the second conductive layer VSL1b of the first vertical power transmission line VSL1. For example, when the deposition angle of the deposition process for forming the cathode electrode layer CEL is greater than the deposition angle of the deposition process for forming the lower functional layer and the deposition angle of the deposition process for forming the upper functional layer, the cathode electrode layer CEL (e.g., the first-first cathode electrode CE1-1) can be formed to overlap with discontinuous portions in the lower functional layer (e.g., the first lower functional layer BL1) and the upper functional layer (e.g., the first upper functional layer UL1) separated by a tip portion, and formed to contact the side surface VSL1b-S of the second conductive layer VSL1b of the first vertical power transmission line VSL1. For example, the first-first cathode electrode CE1-1 can directly contact the first vertical power transmission line VSL1. Therefore, the first cathode electrode CE1-1 can be electrically connected to the first vertical power transmission line VSL1.

[0208] In one embodiment, the first vertical power transmission line VSL1 can be electrically connected to the first horizontal power transmission line HSL1 via the first bridge electrode BRE1. For example... Figure 8As shown in the diagram, the first bridge electrode BRE1 can be positioned in the plan view at the intersection area where the first vertical power transmission line VSL1 and the first horizontal power transmission line HSL1 intersect each other.

[0209] In this embodiment, the first bridge electrode BRE1 can be connected to... Figure 7 The first contact electrode SE and the second contact electrode DE are disposed on the same layer. The first bridge electrode BRE1 can contact the first horizontal power transmission line HSL1 through the first contact hole CNT1 that penetrates the first insulating layer IL1, the second insulating layer IL2, the third insulating layer IL3, and the fourth insulating layer IL4. The first vertical power transmission line VSL1 can contact the first bridge electrode BRE1 through the first through hole VH1 that penetrates the first via insulating layer VIA1. However, this is an example, and the invention is not necessarily limited thereto.

[0210] Therefore, the first cathode electrode CE1-1 can be electrically connected to the first vertical power transmission line VSL1 and the first horizontal power transmission line HSL1. Thus, the first cathode electrode CE1-1 can receive a first low power voltage through the first vertical power transmission line VSL1 and the first horizontal power transmission line HSL1.

[0211] In an embodiment, such as Figure 4 As shown, the first-first cathode electrode CE1-1 can be electrically connected to two or more first connection portions CP1. Therefore, it is possible to reduce defects (e.g., dark spots, brightness degradation, etc.) in the first light-emitting element LDa caused by poor connection between the first-first cathode electrode CE1-1 and the first vertical power transmission line VSL1.

[0212] Figure 10 It is shown Figure 4 An enlarged plan view of the area surrounding the second connection portion of the display device. Figure 11 It is along Figure 10 The sectional view taken from line III-III'.

[0213] In the following text, reference will be made to Figure 10 and Figure 11 A detailed description of an example of the connection structure between the first-second cathode electrode CE1-2 (or the first-third cathode electrode CE1-3) and the first horizontal power transmission line HSL1.

[0214] Reference Figure 4 , Figure 10 and Figure 11 In an embodiment, the first-second cathode electrode CE1-2 (or the first-third cathode electrode CE1-3) can be electrically connected to the second connection portion CP2 of the first connection electrode CNE1.

[0215] In an embodiment, the first connecting electrode CNE1 can be disposed on the same layer as the second vertical power transmission line VSL2 (or voltage transmission line VTL). For example... Figure 10 As shown in the diagram, in the plan view, the first connecting electrode CNE1 may be adjacent to, and may be spaced apart from, the second vertical power transmission line VSL2 (or voltage transmission line VTL). The first connecting electrode CNE1 may electrically connect the first horizontal power transmission line HSL1 and the first-second cathode electrode CE1-2 (or the first-third cathode electrode CE1-3). The first connecting electrode CNE1 may not be electrically connected to the second vertical power transmission line VSL2 (or voltage transmission line VTL) (or may be electrically insulated from the second vertical power transmission line VSL2 (or voltage transmission line VTL)).

[0216] In an embodiment, the first connection electrode CNE1 may have a multilayer structure in which multiple conductive layers are stacked. For example, the first connection electrode CNE1 may include a first conductive layer CNE1a, a second conductive layer CNE1b, and a third conductive layer CNE1c stacked sequentially. For example, the first connection electrode CNE1 may be related to the above-referenced... Figure 8 and Figure 9 The first vertical power transmission line VSL1 described has a substantially identical layer structure. Therefore, repeated descriptions will be omitted or simplified.

[0217] The side surface CNE1b-S of the second conductive layer CNE1b may be recessed in one direction relative to the side surfaces CNE1a-S of the first conductive layer CNE1a and the third conductive layer CNE1c-S, toward the center of the first connecting electrode CNE1. For example, the side surfaces CNE1a-S of the first conductive layer CNE1a and the side surfaces CNE1c-S of the third conductive layer CNE1c may protrude outward relative to the side surface CNE1b-S of the second conductive layer CNE1b. Therefore, due to the protruding portion of the third conductive layer CNE1c compared to the second conductive layer CNE1b, the second connecting portion CP2 of the first connecting electrode CNE1 may have a pointed portion. For example, based on the same etching process, when etching the second conductive layer CNE1b using an etching material that has a higher etching rate than the first and third conductive layers CNE1a and CNE1c, the first connecting electrode CNE1 may be formed with a pointed portion.

[0218] The second via insulating layer VIA2 can define a second-first sub-opening OP2a that exposes a portion of the first connecting electrode CNE1. For example, the second-first sub-opening OP2a can expose the tip portion of the second connecting portion CP2 of the first connecting electrode CNE1.

[0219] The pixel-defining layer (PDL) can define a second-second sub-opening OP2b corresponding to the second-first sub-opening OP2a. The second-second sub-opening OP2b can be located on the second-first sub-opening OP2a, and the second-first sub-opening OP2a and the second-second sub-opening OP2b can be spatially connected to each other. For example, the second-first sub-opening OP2a and the second-second sub-opening OP2b can be spatially connected to define a second opening OP2, and the second opening OP2 can expose the tip portion of the second connection portion CP2 of the first connection electrode CNE1.

[0220] The lower functional layer, upper functional layer, and cathode electrode layer CEL can also be separated (or disconnected) through the tip of the second connection portion CP2 of the first connecting electrode CNE1. Because the lower and upper functional layers are separated (or disconnected) through the tip of the second connection portion CP2 of the first connecting electrode CNE1, the lower and upper functional layers can expose at least a portion of the side surface CNE1b-S of the second conductive layer CNE1b of the first connecting electrode CNE1. Therefore, the first-second cathode electrode CE1-2 (or the first-third cathode electrode CE1-3) can contact the side surface CNE1b-S of the second conductive layer CNE1b of the first connecting electrode CNE1.

[0221] The first-second cathode electrode CE1-2 (or the first-third cathode electrode CE1-3) can be electrically connected to the corresponding first connecting electrode CNE1. For example, the first-second cathode electrode CE1-2 (or the first-third cathode electrode CE1-3) can contact the side surface CNE1b-S of the second conductive layer CNE1b of the first connecting electrode CNE1. For example, when the deposition angle of the deposition process for forming the cathode electrode layer CEL is greater than the deposition angle of the deposition process for forming the lower functional layer and the deposition angle of the deposition process for forming the upper functional layer, the cathode electrode layer CEL (e.g., the first-second cathode electrode CE1-2 or the first-third cathode electrode CE1-3) can be formed to overlap with the discontinuous portions in the lower functional layer (e.g., the first lower functional layer BL1) and the upper functional layer (e.g., the first upper functional layer UL1) separated by the tip portion, and formed to contact the side surface CNE1b-S of the second conductive layer CNE1b of the first connecting electrode CNE1. For example, the first-second cathode electrode CE1-2 (or the first-third cathode electrode CE1-3) can directly contact the first connecting electrode CNE1. Therefore, the first-second cathode electrode CE1-2 (or the first-third cathode electrode CE1-3) can be electrically connected to the first connecting electrode CNE1.

[0222] In an embodiment, the first connection electrode CNE1 can be electrically connected to the first horizontal power transmission line HSL1 via the second bridge electrode BRE2. Figure 10 As shown, the second bridge electrode BRE2 can be stacked with each of the first horizontal power transmission line HSL1 and the first connection electrode CNE1 in the plan view.

[0223] In this embodiment, the second bridge electrode BRE2 can be connected with... Figure 7 The first contact electrode SE and the second contact electrode DE are disposed on the same layer. The second bridge electrode BRE2 can contact the first horizontal power transmission line HSL1 through the second contact hole CNT2 that penetrates the first insulating layer IL1, the second insulating layer IL2, the third insulating layer IL3, and the fourth insulating layer IL4. The first connecting electrode CNE1 can contact the second bridge electrode BRE2 through the second through hole VH2 that penetrates the first via insulating layer VIA1. However, this is an example, and the invention is not necessarily limited thereto.

[0224] Therefore, the first-second cathode electrode CE1-2 (or the first-third cathode electrode CE1-3) can be electrically connected to the first horizontal power transmission line HSL1 through the first connecting electrode CNE1 and the second bridge electrode BRE2. Therefore, the first-second cathode electrode CE1-2 (or the first-third cathode electrode CE1-3) can receive a first low power voltage through the first horizontal power transmission line HSL1.

[0225] In an embodiment, such as Figure 4 As shown, the first-second cathode electrode CE1-2 (or the first-third cathode electrode CE1-3) can be electrically connected to two or more second connection portions CP2. Therefore, it is possible to reduce defects (e.g., dark spots, brightness degradation, etc.) in the first light-emitting element LDa caused by poor connection between the first-second cathode electrode CE1-2 (or the first-third cathode electrode CE1-3) and the first horizontal power transmission line HSL1.

[0226] Figure 12 It is shown Figure 4 An enlarged plan view of the area surrounding the third connection portion of the display device. Figure 13 It is along Figure 12 A sectional view taken from line IV-IV'.

[0227] In the following text, reference will be made to Figure 12 and Figure 13 A detailed description of the connection structure of the second cathode electrode CE2, the second vertical power transmission line VSL2, and the second horizontal power transmission line HSL2.

[0228] Reference Figure 4 , Figure 12 and Figure 13 In this embodiment, the second cathode electrode CE2 can be electrically connected to the third connection portion CP3 of the corresponding second vertical power transmission line VSL2.

[0229] In an embodiment, the second vertical power transmission line VSL2 may have a multilayer structure in which multiple conductive layers are stacked. For example, the second vertical power transmission line VSL2 may include a first conductive layer VSL2a, a second conductive layer VSL2b, and a third conductive layer VSL2c stacked sequentially. For example, the second vertical power transmission line VSL2 may be related to the above-mentioned... Figure 8 and Figure 9 The first vertical power transmission line VSL1 described has a substantially identical layer structure. Therefore, repeated descriptions will be omitted or simplified.

[0230] The side surface VSL2b-S of the second conductive layer VSL2b may be recessed in one direction relative to the side surface VSL2a-S of the first conductive layer VSL2a and the side surface VSL2c-S of the third conductive layer VSL2c, toward the center of the second vertical power transmission line VSL2. For example, the side surfaces VSL2a-S of the first conductive layer VSL2a and the side surface VSL2c-S of the third conductive layer VSL2c may protrude outward relative to the side surface VSL2b-S of the second conductive layer VSL2b. Therefore, due to the protruding portion of the third conductive layer VSL2c compared to the second conductive layer VSL2b, the third connection portion CP3 of the second vertical power transmission line VSL2 may have a pointed portion. For example, based on the same etching process, when etching the second conductive layer VSL2b using an etching material that has a higher etching rate than the first and third conductive layers VSL2a and VSL2c, the second vertical power transmission line VSL2 may be formed with a pointed portion.

[0231] The second via insulation layer VIA2 can define a third-first sub-opening OP3a that exposes a portion of the second vertical power transmission line VSL2. For example, the third-first sub-opening OP3a can expose the tip portion of the third connection portion CP3 of the second vertical power transmission line VSL2.

[0232] The pixel-defining layer (PDL) can define a third-second sub-aperture OP3b corresponding to the third-first sub-aperture OP3a. The third-second sub-aperture OP3b can be located on the third-first sub-aperture OP3a, and the third-first sub-aperture OP3a and the third-second sub-aperture OP3b can be spatially connected to each other. For example, the third-first sub-aperture OP3a and the third-second sub-aperture OP3b can be spatially connected to define a third opening OP3, and the third opening OP3 can expose the tip portion of the third connection portion CP3 of the second vertical power transmission line VSL2.

[0233] The lower functional layer, upper functional layer, and cathode electrode layer CEL can also be separated (or disconnected) through the tip of the third connection portion CP3 of the second vertical power transmission line VSL2. Because the lower and upper functional layers are separated (or disconnected) through the tip of the third connection portion CP3 of the second vertical power transmission line VSL2, at least a portion of the side surface VSL2b-S of the second conductive layer VSL2b of the second vertical power transmission line VSL2 can be exposed. Therefore, the second cathode electrode CE2 can contact the side surface VSL2b-S of the second conductive layer VSL2b of the second vertical power transmission line VSL2.

[0234] The second cathode electrode CE2 can be electrically connected to the corresponding second vertical power transmission line VSL2. For example, the second cathode electrode CE2 can contact the side surface VSL2b-S of the second conductive layer VSL2b of the second vertical power transmission line VSL2. For example, when the deposition angle of the deposition process for forming the cathode electrode layer CEL is greater than the deposition angle of the deposition process for forming the lower functional layer and the deposition angle of the deposition process for forming the upper functional layer, the cathode electrode layer CEL (e.g., the second cathode electrode CE2) can be formed to overlap with discontinuous portions in the lower functional layer (e.g., the second lower functional layer BL2) and the upper functional layer (e.g., the second upper functional layer UL2) separated by a tip portion, and formed to contact the side surface VSL2b-S of the second conductive layer VSL2b of the second vertical power transmission line VSL2. For example, the second cathode electrode CE2 can directly contact the second vertical power transmission line VSL2. Therefore, the second cathode electrode CE2 can be electrically connected to the second vertical power transmission line VSL2.

[0235] In one embodiment, the second vertical power transmission line VSL2 can be electrically connected to the second horizontal power transmission line HSL2 via the third bridge electrode BRE3. Figure 12 As shown in the diagram, the third bridge electrode BRE3 can be positioned in the intersection area where the second vertical power transmission line VSL2 and the second horizontal power transmission line HSL2 intersect each other in the plan view.

[0236] In this embodiment, the third bridge electrode BRE3 can be connected with... Figure 7 The first contact electrode SE and the second contact electrode DE are disposed on the same layer. The third bridge electrode BRE3 can contact the second horizontal power transmission line HSL2 through the third contact hole CNT3 that penetrates the first insulating layer IL1, the second insulating layer IL2, the third insulating layer IL3, and the fourth insulating layer IL4. The second vertical power transmission line VSL2 can contact the third bridge electrode BRE3 through the third through hole VH3 that penetrates the first via insulating layer VIA1. However, this is an example, and the invention is not necessarily limited thereto.

[0237] Therefore, the second cathode electrode CE2 can be electrically connected to the second vertical power transmission line VSL2 and the second horizontal power transmission line HSL2. Thus, the second cathode electrode CE2 can receive a second low power voltage through the second vertical power transmission line VSL2 and the second horizontal power transmission line HSL2.

[0238] In an embodiment, such as Figure 4 As shown, the second cathode electrode CE2 can be electrically connected to two or more third connection portions CP3. Therefore, it is possible to reduce defects (e.g., dark spots, brightness degradation, etc.) in the second light-emitting element LDb and the third light-emitting element LDc caused by poor connection between the second cathode electrode CE2 and the second vertical power transmission line VSL2.

[0239] Figure 14 It is shown Figure 1 A floor plan of an example of a magnified portion of a display device. Figure 15 It is shown Figure 14 An enlarged plan view of the area surrounding the fourth connection portion of the display device. Figure 16 It is along Figure 15 A sectional view taken by line V-V'.

[0240] Reference Figures 14 to 16 In this embodiment, the second cathode electrode CE2 can be electrically connected to the fourth connection portion CP4 of the second connection electrode CNE2. The second cathode electrode CE2 can also be electrically connected to the second horizontal power transmission line HSL2 via the second connection electrode CNE2.

[0241] In an embodiment, the second connecting electrode CNE2 can be disposed on the same layer as the first vertical power transmission line VSL1 (or voltage transmission line VTL). For example... Figure 15 As shown in the diagram, in the plan view, the second connecting electrode CNE2 can be adjacent to, and can be spaced apart from, the first vertical power transmission line VSL1 (or voltage transmission line VTL). The second connecting electrode CNE2 can electrically connect the second horizontal power transmission line HSL2 and the second cathode electrode CE2. The second connecting electrode CNE2 may also not be electrically connected to the first vertical power transmission line VSL1 (or voltage transmission line VTL).

[0242] In an embodiment, the second connection electrode CNE2 may have a multilayer structure in which multiple conductive layers are stacked. For example, the second connection electrode CNE2 may include a first conductive layer CNE2a, a second conductive layer CNE2b, and a third conductive layer CNE2c stacked sequentially. For example, the second connection electrode CNE2 may be related to the above-mentioned... Figure 8 and Figure 9The first vertical power transmission line VSL1 described has a substantially identical layer structure. Therefore, repeated descriptions will be omitted or simplified.

[0243] The side surface CNE2b-S of the second conductive layer CNE2b may be recessed in one direction relative to the side surfaces CNE2a-S of the first conductive layer CNE2a and the third conductive layer CNE2c, toward the center of the second connecting electrode CNE2. For example, the side surfaces CNE2a-S of the first conductive layer CNE2a and the third conductive layer CNE2c may protrude outward relative to the side surface CNE2b-S of the second conductive layer CNE2b. Therefore, due to the protruding portion of the third conductive layer CNE2c compared to the second conductive layer CNE2b, the fourth connecting portion CP4 of the second connecting electrode CNE2 may have a pointed portion. For example, based on the same etching process, when etching the second conductive layer CNE2b using an etching material that has a higher etching rate than the first and third conductive layers CNE2a and CNE2c, the second connecting electrode CNE2 may be formed to have a pointed portion.

[0244] The second via insulating layer VIA2 can define a fourth-first sub-opening OP4a that exposes a portion of the second connection electrode CNE2. For example, the fourth-first sub-opening OP4a can expose the tip portion of the fourth connection portion CP4 of the second connection electrode CNE2.

[0245] The pixel-defining layer (PDL) can define a fourth-second sub-opening OP4b corresponding to the fourth-first sub-opening OP4a. The fourth-second sub-opening OP4b can be located on the fourth-first sub-opening OP4a, and the fourth-first sub-opening OP4a and the fourth-second sub-opening OP4b can be spatially connected to each other. For example, the fourth-first sub-opening OP4a and the fourth-second sub-opening OP4b can be spatially connected to define a fourth opening OP4, and the fourth opening OP4 can expose the tip portion of the fourth connection portion CP4 of the second connection electrode CNE2.

[0246] The lower functional layer, upper functional layer, and cathode electrode layer CEL can also be separated (or disconnected) through the tip of the fourth connection portion CP4 of the second connecting electrode CNE2. Because the lower and upper functional layers are separated (or disconnected) through the tip of the fourth connection portion CP4 of the second connecting electrode CNE2, at least a portion of the side surface CNE2b-S of the second conductive layer CNE2b of the second connecting electrode CNE2 can be exposed. Therefore, the second cathode electrode CE2 can contact the side surface CNE2b-S of the second conductive layer CNE2b of the second connecting electrode CNE2.

[0247] The second cathode electrode CE2 can be electrically connected to the corresponding second connecting electrode CNE2. For example, the second cathode electrode CE2 can contact the side surface CNE2b-S of the second conductive layer CNE2b of the second connecting electrode CNE2. For example, when the deposition angle of the deposition process for forming the cathode electrode layer CEL is greater than the deposition angle of the deposition process for forming the lower functional layer and the deposition angle of the deposition process for forming the upper functional layer, the cathode electrode layer CEL (e.g., the second cathode electrode CE2) can be formed to overlap with discontinuous portions in the lower functional layer (e.g., the second lower functional layer BL2) and the upper functional layer (e.g., the second upper functional layer UL2) separated by a tip portion, and formed to contact the side surface CNE2b-S of the second conductive layer CNE2b of the second connecting electrode CNE2. For example, the second cathode electrode CE2 can directly contact the second connecting electrode CNE2. Therefore, the second cathode electrode CE2 can be electrically connected to the second connecting electrode CNE2.

[0248] In an embodiment, the second connection electrode CNE2 can be electrically connected to the second horizontal power transmission line HSL2 via the fourth bridge electrode BRE4. Figure 15 As shown, the fourth bridge electrode BRE4 can be stacked with each of the second horizontal power transmission line HSL2 and the second connection electrode CNE2 in the plan view.

[0249] In this embodiment, the fourth bridge electrode BRE4 can be with Figure 7 The first contact electrode SE and the second contact electrode DE are disposed on the same layer. The fourth bridge electrode BRE4 can contact the second horizontal power transmission line HSL2 through the fourth contact hole CNT4 that penetrates the first insulating layer IL1, the second insulating layer IL2, the third insulating layer IL3, and the fourth insulating layer IL4. The second connection electrode CNE2 can contact the fourth bridge electrode BRE4 through the fourth through hole VH4 that penetrates the first via insulating layer VIA1. However, this is an example, and the invention is not necessarily limited thereto.

[0250] Therefore, the second cathode electrode CE2 can be electrically connected to the second horizontal power transmission line HSL2 via the second connecting electrode CNE2 and the fourth bridge electrode BRE4. Additionally, with... Figure 4 Compared to the previous embodiment, the second cathode electrode CE2 can also be directly connected to the second connection electrode CNE2, which is electrically connected to the second horizontal power transmission line HSL2. Therefore, it is possible to further reduce defects (e.g., dark spots, brightness degradation, etc.) in the second light-emitting element LDb and the third light-emitting element LDc caused by poor connection between the second cathode electrode CE2 and the second vertical power transmission line VSL2.

[0251] The display device according to the above embodiments can be applied to various electronic devices.

[0252] Therefore, in OLED displays, in the connection structure that delivers low electrical voltage to different cathode electrodes, each cathode electrode (such as the first cathode electrode CE1-1 for blue pixels or the second cathode electrode CE2 for red and green pixels) is connected to vertical and horizontal power transmission lines via multilayer connecting electrodes and bridge electrodes. This ensures reliable electrical contact regardless of the complex layer stacking and insulation structures. These connections are designed to maintain stable voltage delivery while minimizing defects such as dark spots, thereby achieving efficient power distribution for color-specific driving requirements.

[0253] Figure 17 This is a block diagram illustrating an electronic device according to an embodiment.

[0254] Reference Figure 17 The electronic device 10 according to the embodiment may include a display module 11, a processor 12, a memory 13 and a power module 14.

[0255] In an embodiment, the electronic device 10 may include Figures 1 to 16 The display device DD. In an embodiment, the electronic device 10 may also include modules or devices with additional functions in addition to the display device.

[0256] The processor 12 may include at least one of a central processing unit (“CPU”), an application processor (“AP”), a graphics processing unit (“GPU”), a communication processor (“CP”), an image signal processor (“ISP”), and a controller.

[0257] In an embodiment, the processor 12 may be configured to provide image data signals and / or input control signals to a display device.

[0258] The memory 13 can store the data information required for the operation of the processor 12 or the display module 11. When the processor 12 executes the application stored in the memory 13, image data signals and / or input control signals can be sent to the display module 11, and the display module 11 can process the received signals and output image information through the display screen.

[0259] The power module 14 may include a power module such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power module to generate the power required for the operation of the electronic device 10.

[0260] At least one of each component of the electronic device 10 described above may be included in the display device according to the embodiment. Furthermore, some of the various modules functionally included in the electronic device 10 may be included in the display device, and other components may be separately provided relative to the display device. For example, the display device may include a display module 11, and the processor 12, memory 13, and power module 14 may be provided within the electronic device 10 as other devices besides the display device.

[0261] Figure 18 This is a schematic diagram illustrating an electronic device according to various embodiments.

[0262] Reference Figure 17 and Figure 18 The various electronic devices 10 employing the display device according to the embodiments may include not only image display electronic devices (such as smartphones 10_1a, tablet computers 10_1b, laptops / notebook computers 10_1c, TVs 10_1d, and computer monitors 10_1e), but also wearable electronic devices (such as smart glasses 10_2a, head-mounted displays 10_2b, and smartwatches 10_2c) and automotive electronic devices 10_3 (such as vehicle dashboards, central dashboards, central information displays (“CIDs”) mounted on dashboards, and interior mirror displays) that include display modules. The electronic devices 10 are not necessarily limited to image display electronic devices, wearable electronic devices, and automotive electronic devices.

[0263] Although embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Therefore, the invention is not limited to such embodiments, but rather to the broader scope of the appended claims and various obvious modifications and equivalent arrangements that will be apparent to those skilled in the art.

Claims

1. A display device, the display device comprising: The substrate includes a first launch region and a second launch region; The first pixel circuit and the second pixel circuit are disposed on the substrate; A first light-emitting element is disposed in the first emitting region of the substrate and includes: a first anode electrode electrically connected to the first pixel circuit; a first emitting layer disposed on the first anode electrode; and a first cathode electrode disposed on the first emitting layer and subjected to a first low power voltage. A second light-emitting element, disposed in the second emitting region of the substrate, includes: a second anode electrode spaced apart from the first anode electrode and electrically connected to the second pixel circuit; a second emitting layer disposed on the second anode electrode; and a second cathode electrode disposed on the second emitting layer, spaced apart from the first cathode electrode, and subjected to a second low-voltage power supply; and A spacer is disposed between the first cathode electrode and the second cathode electrode.

2. The display device as claimed in claim 1, wherein, The first cathode electrode and the second cathode electrode are electrically insulated from each other.

3. The display device as claimed in claim 1, wherein, The second low power voltage has a different voltage level than the first low power voltage.

4. The display device as claimed in claim 3, wherein, The same high electrical voltage is applied to both the first pixel circuit and the second pixel circuit.

5. The display device as claimed in claim 1, further comprising: The third pixel circuit is disposed on the substrate; as well as A third light-emitting element, disposed in a third emitting region of the substrate, includes: a third anode electrode, spaced apart from each of the first and second anode electrodes and electrically connected to the third pixel circuit; a third emitting layer disposed on the third anode electrode; and a second cathode electrode. The first part of the second cathode electrode is disposed on the second emission layer, and the second part of the second cathode electrode is disposed on the third emission layer.

6. The display device as claimed in claim 5, wherein, The first light-emitting element emits blue light, the second light-emitting element emits red light, and the third light-emitting element emits green light.

7. The display device as claimed in claim 1, wherein, Each of the first and second transmission regions is configured as multiple. The first cathode electrode is configured as multiple electrodes, and In the plan view, the second cathode electrode is spaced apart from and surrounds the plurality of first cathode electrodes.

8. The display device as claimed in claim 7, wherein, In the plan view, each of the plurality of first cathode electrodes is superimposed on two or more first emission regions of the plurality of first emission regions, and In the plan view, the second cathode electrode is superimposed on all of the multiple second emission regions.

9. The display device as claimed in claim 8, wherein, In the plan view, each of the plurality of first cathode electrodes is spaced apart from the plurality of second emission regions, and In the plan view, the second cathode electrode is spaced apart from the plurality of first emission regions.

10. The display device as claimed in claim 7, wherein, The spacers are configured in multiple ways, and In the plan view, each of the multiple spacers surrounds two or more of the multiple first launch regions.

11. The display device of claim 7, further comprising: Vertical transmission lines are spaced apart from each other in a first direction and each extends in a second direction that intersects the first direction; as well as The horizontal transmission line, disposed on a different layer from the vertical transmission line, is spaced apart from each other in the second direction, and each extends in the first direction. The horizontal transmission line includes: a first horizontal power transmission line, to which the first low power voltage is applied; and a second horizontal power transmission line, spaced apart from the first horizontal power transmission line, to which the second low power voltage is applied. The vertical transmission line includes: a first vertical power transmission line electrically connected to the first horizontal power transmission line and transmitting the first low power voltage to the plurality of first cathode electrodes; and a second vertical power transmission line spaced apart from the first vertical power transmission line, electrically connected to the second horizontal power transmission line, and transmitting the second low power voltage to the second cathode electrode.

12. The display device as claimed in claim 11, wherein, The plurality of first cathode electrodes includes: The first cathode electrode corresponds to the first vertical power transmission line; and The first and second cathode electrodes correspond to the second vertical power transmission line. Wherein, the first cathode electrode is electrically connected to the first vertical power transmission line, and The first and second cathode electrodes are electrically connected to the first horizontal power transmission line.

13. The display device as claimed in claim 12, wherein, The first cathode electrode is in direct contact with the first vertical power transmission line.

14. The display device of claim 12, further comprising: The first connecting electrode is disposed on the same layer as the second vertical power transmission line. In the plan view, the first connecting electrode is adjacent to and spaced apart from the second vertical power transmission line. The first connecting electrode electrically connects the first horizontal power transmission line and the first-second cathode electrode to each other.

15. The display device as claimed in claim 14, wherein, The first and second cathode electrodes are in direct contact with the first connecting electrode.

16. The display device as claimed in claim 11, wherein, The second cathode electrode is in direct contact with the second vertical power transmission line.

17. The display device of claim 11, further comprising: The second connecting electrode is disposed on the same layer as the first vertical power transmission line. In the plan view, the second connecting electrode is adjacent to and spaced apart from the first vertical power transmission line. The second connecting electrode electrically connects the second horizontal power transmission line and the second cathode electrode to each other.

18. The display device as claimed in claim 17, wherein, The second cathode electrode is in direct contact with the second connecting electrode.

19. A display device, the display device comprising: The substrate includes a first emitting region that emits light of a first color, a second emitting region that emits light of a second color, and a third emitting region that emits light of a third color; A first cathode electrode is disposed on the substrate, the first cathode electrode being superimposed on two or more first emission regions in the first emission region in a plan view, and spaced apart from the second emission region and the third emission region, and a first low power voltage is applied to the first cathode electrode; A second cathode electrode is disposed on the substrate. In a plan view, the second cathode electrode overlaps with all of the second emission region and all of the third emission region and is spaced apart from the first emission region. In a plan view, the second cathode electrode is spaced apart from and surrounds the first cathode electrode. A second low power voltage having a voltage level different from the first low power voltage is applied to the second cathode electrode. as well as A spacer is disposed between the first cathode electrode and the second cathode electrode, the spacer surrounding the first cathode electrode in a plan view.

20. An electronic device, the electronic device comprising: Display device, including light-emitting elements; as well as The processor is configured to send image data signals and input control signals to the display device. The display device includes: The substrate includes a first launch region and a second launch region; The first pixel circuit and the second pixel circuit are disposed on the substrate; A first light-emitting element is disposed in the first emitting region of the substrate and includes: a first anode electrode electrically connected to the first pixel circuit; a first emitting layer disposed on the first anode electrode; and a first cathode electrode disposed on the first emitting layer and subjected to a first low power voltage. A second light-emitting element, disposed in the second emitting region of the substrate, includes: a second anode electrode spaced apart from the first anode electrode and electrically connected to the second pixel circuit; a second emitting layer disposed on the second anode electrode; and a second cathode electrode disposed on the second emitting layer, spaced apart from the first cathode electrode, and subjected to a second low-voltage power supply; and A spacer is disposed between the first cathode electrode and the second cathode electrode.

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