Display device and electronic device including the same

Abstract

A display device and an electronic device including the same are provided. In a display device having a display area and a non-display area, the display device includes a plurality of pad units in the non-display area, at least one dummy pattern unit between adjacent pad units among the plurality of pad units, and an adjacent insulating layer between at least the plurality of pad units and the at least one dummy pattern unit and disposed not to cover at least one region among regions of the plurality of pad units.

Description

Technical Field

[0001] One or more aspects of the embodiments relate to a display device and an electronic device including the display device. Background Technology

[0002] Recently, the applications of display devices have diversified. Display devices are becoming relatively thinner and lighter, which has gradually broadened their range of uses. Therefore, various designs are being explored to relatively improve the quality of display devices.

[0003] These display devices are being used in a variety of fields. For example, they are not only used in televisions and monitors for user visual activities, but also in mobile phones, tablets, digital watches, indoor and outdoor information displays for transportation devices, and other wearable devices.

[0004] Therefore, consumer demand for display devices with relatively improved electrical reliability in various environments is increasing.

[0005] The information disclosed in this background section is only intended to enhance the understanding of the background art, and therefore the information discussed in this background section does not necessarily constitute prior art. Summary of the Invention

[0006] Some embodiments include a display device with relatively improved electrical reliability and an electronic device including the display device.

[0007] The aspects of embodiments according to this disclosure are not limited to the features described above, and other features not mentioned in the embodiments according to this disclosure will be understood from the following description and will be more clearly understood from the disclosed embodiments. Furthermore, it will be readily understood that the features of embodiments according to this disclosure can be implemented by the features set forth in the appended claims, their equivalents, and combinations thereof.

[0008] According to one or more embodiments, a display device having a display area and a non-display area includes: a plurality of pad units disposed in the non-display area; at least one dummy pattern unit disposed between adjacent pad units among the plurality of pad units; and an adjacent insulating layer disposed at least between the plurality of pad units and at least one dummy pattern unit, and arranged to not cover at least one area among the areas of the plurality of pad units.

[0009] According to some embodiments, the display device may further include: a circuit component arranged to be electrically connected to a plurality of pad units; and a plurality of lead units arranged on the circuit component, electrically connected to at least one area of ​​the region of the plurality of pad units that is not covered by an adjacent insulating layer, and spaced apart from at least one dummy pattern unit.

[0010] According to some embodiments, at least one dummy pattern unit can be arranged to be spatially superimposed on adjacent lead units among a plurality of lead units.

[0011] According to some embodiments, the display device may also include an intermediate insulating layer disposed between a plurality of pad units and circuit components.

[0012] According to some embodiments, the regions of each of the plurality of lead units and the corresponding pad unit can be arranged to contact each other.

[0013] According to some embodiments, each of the plurality of pad units may include at least one protrusion projecting toward a circuit member, and a region of the at least one protrusion may be arranged to contact a corresponding lead unit.

[0014] According to some embodiments, each of the plurality of pad units may include: a substrate conductive layer; at least one connecting conductive layer electrically connected to the substrate conductive layer; and a raised pattern corresponding to at least one raised portion and disposed between the substrate conductive layer and the at least one connecting conductive layer.

[0015] According to some embodiments, the raised pattern may include organic materials.

[0016] According to some embodiments, at least one dummy pattern unit may include: at least one dummy conductive layer; and a dummy insulating layer covering at least one dummy conductive layer.

[0017] According to some embodiments, at least one dummy pattern unit and a plurality of pad units may have a height based on the thickness direction of the display device, and the height of at least one dummy pattern unit may not be greater than the height of each of the plurality of pad units.

[0018] According to some embodiments, adjacent insulating layers and multiple pad units may have a height based on the thickness direction of the display device, and the height of adjacent insulating layers may not be greater than the height of each of the multiple pad units.

[0019] According to one or more embodiments, a display device having a display area and a non-display area includes: a plurality of pad units disposed in the non-display area; an adjacent insulating layer disposed between adjacent pad units among the plurality of pad units; and at least one groove disposed in the adjacent insulating layer to be spaced apart from the plurality of pad units.

[0020] According to some embodiments, the display device may further include: a circuit component arranged to be electrically connected to a plurality of pad units; and a plurality of lead units arranged on the circuit component, electrically connected to the plurality of pad units, and spaced apart from at least one recess.

[0021] According to some embodiments, at least one groove may be arranged to spatially overlap with adjacent lead units among a plurality of lead units.

[0022] According to some embodiments, the display device may also include an intermediate insulating layer disposed between a plurality of pad units and circuit components.

[0023] According to some embodiments, the regions of each of the plurality of lead units and the corresponding pad unit can be arranged to contact each other.

[0024] According to some embodiments, each of the plurality of pad units may include at least one protrusion projecting toward a circuit member, and a region of the at least one protrusion may be arranged to contact a corresponding lead unit.

[0025] According to some embodiments, each of the plurality of pad units may include a raised pattern comprising an organic material to correspond to at least one raised portion.

[0026] According to some embodiments, adjacent insulating layers and multiple pad units may have a height based on the thickness direction of the display device, and the height of adjacent insulating layers may not be greater than the height of each of the multiple pad units.

[0027] According to one or more embodiments, an electronic device includes a display device in which a processor executes at least one application and implements at least one image. According to some embodiments, the display device has a display area and a non-display area, and includes: a plurality of pad units disposed in the non-display area; at least one dummy pattern unit disposed between adjacent pad units among the plurality of pad units; and an adjacent insulating layer disposed at least between the plurality of pad units and the at least one dummy pattern unit, and arranged not to cover at least one area among the areas of the plurality of pad units. Attached Figure Description

[0028] The accompanying drawings, which are attached to this specification, illustrate aspects of some embodiments of this disclosure and, together with the detailed description of the disclosure below, serve to further understand the technical ideas disclosed; therefore, embodiments based on this disclosure should not be construed as limited to what is described in these drawings: Figure 1 This is a schematic plan view of an example of a display device according to some embodiments; Figure 2 It is viewed from one direction. Figure 1 A perspective view of the display device; Figure 3 yes Figure 2 An exploded perspective view; Figure 4 yes Figure 1A schematic block diagram of the structure of the display device shown; Figure 5 yes Figure 1 A schematic diagram of the equivalent circuit of the pixels of the display device shown; Figure 6 It is along Figures 1 to 3 A schematic cross-sectional view of an example of a section cut by line VI-VI'; Figure 7 yes Figure 3 A magnified view of the first connecting region CA1 in the image; Figure 8 It is along Figures 1 to 3 and Figure 7 A schematic diagram of an example of a cross section taken by line VIII-VIII'; Figure 9 It is along Figures 1 to 3 and Figure 7 A schematic diagram of an example of a cross section taken by line IX-IX'; Figure 10 yes Figure 8 A magnified view showing further details of region A1 in the image; Figures 11 to 13 According to some embodiments Figure 8 A magnified view of area A2 and a modified example view; Figure 14 This is an exploded perspective view of a portion of a display device according to some embodiments; Figure 15 yes Figure 14 A magnified view of the first connecting region CA1' in the image; Figure 16 It is along Figure 14 and Figure 15 A schematic diagram of an example of a cross section taken by line XVI-XVI'; Figure 17 and Figure 18 yes Figure 16 A magnified view of area A3 in the image; Figure 19 This is a view of an electronic device used to explain the application of a display device according to some embodiments; and Figure 20 It is used for explanation Figure 19 Views of various examples of electronic devices. Detailed Implementation

[0029] Because the disclosure allows for various modifications and numerous embodiments, some embodiments will be shown in the accompanying drawings and described in detail in the written description. The effects and features of the disclosure, as well as methods for achieving them, will be illustrated by referring to the embodiments described in detail below with reference to the accompanying drawings. However, the disclosure can be implemented in many different forms and should not be construed as limiting itself to the embodiments set forth herein.

[0030] In the following embodiments, the terms "first," "second," etc., are not used in a limiting sense, but are used to distinguish one element from another.

[0031] Unless the context clearly indicates otherwise, the singular form used here is also intended to include the plural form.

[0032] In the embodiments described below, it will be understood that terms such as “comprising” or “having” are intended to indicate the presence of a feature or component disclosed in the disclosure and are not intended to exclude the possibility that one or more other features or elements may be present or added.

[0033] In the following embodiments, it will be understood that when a portion, such as a layer, unit, region, or element, is referred to as being "on" another portion, this can include not only the case where the portion is directly on the other portion, but also the case where there may be intervening layers, intervening units, intervening regions, or intervening elements between them.

[0034] In the following embodiments, unless the context clearly indicates otherwise, terms such as connection or combination do not necessarily refer to a direct and / or fixed connection or combination of two components, and do not exclude the situation where another component is placed between the two components.

[0035] In the examples below, the X-axis, Y-axis, and Z-axis directions are not limited to directions corresponding to the three axes of a Cartesian coordinate system, and can be interpreted in a general sense that includes such axial directions. For example, the X-axis, Y-axis, and Z-axis directions can be orthogonal to each other, but can also represent different directions that are not orthogonal to each other.

[0036] For ease of explanation, the dimensions of the elements in the accompanying drawings may be exaggerated. For example, the disclosure is not limited thereto because the dimensions and / or thicknesses of the elements in the accompanying drawings are arbitrarily shown for ease of explanation.

[0037] In the following description, aspects of some embodiments will be described in more detail with reference to the accompanying drawings. When describing embodiments with reference to the drawings, the same or corresponding elements are indicated by the same reference numerals, and redundant descriptions thereof are omitted.

[0038] Figure 1 This is a schematic plan view of an example of a display device according to some embodiments. Figure 2It is viewed from one direction. Figure 1 A perspective view of the display device. Figure 3 yes Figure 2 An exploded perspective view.

[0039] Reference Figure 1 and Figure 2 The display device 100 can be a device for displaying moving or still images, and can display images on a display panel DP or perform data input and output. The display device 100 can be used as a display screen for various electronic devices such as televisions, laptops, monitors, billboards, and Internet of Things (IoT) devices, as well as portable electronic devices such as mobile phones, smartphones, tablet PCs, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation systems, and ultra-mobile personal computers (UMPCs).

[0040] The display device 100 according to some embodiments can also be applied to electronic devices, such as wearable devices (e.g., smartwatches, watch phones, glasses-type displays, and head-mounted displays (HMDs)). The display device 100 according to some embodiments can also be used as a display for various electronic devices, such as a central information display (CID) on a car's dashboard, a car's central instrument panel or dashboard, an interior mirror display that replaces a car's side mirrors, and a display on the rear surface of the front seats that serves as an entertainment device for rear-seat passengers of a car.

[0041] According to some embodiments, the display device 100 may include a display panel DP, circuit components 101, and a printed circuit board PCB.

[0042] The display panel DP may include a substrate SUB1. On the substrate SUB1, a display area DA that emits visible light and a non-display area NDA located to one side or outside of the display area DA (e.g., located outside the periphery or coverage area of ​​the display area DA) may be arranged.

[0043] In these areas, the display area DA may include at least one pixel PX arranged on the substrate SUB1.

[0044] The non-display area NDA can be an area where no multiple pixels PX are arranged, and can surround the display area DA (e.g., on the periphery of the display area DA or outside the coverage area of ​​the display area DA). According to some embodiments, the non-display area NDA can be located outside one edge of the display area DA (e.g., outside one edge of the display area DA or outside the coverage area) or outside multiple edges of the display area DA.

[0045] The non-display area NDA may include the first connection area CA1.

[0046] Circuit components 101, etc., may be arranged to be connected (e.g., electrically connected) to or in contact with a portion of the non-display area NDA. For example, such as Figure 3 As shown, the second connection region CA2 arranged on the circuit component 101 and the first connection region CA1 arranged in the non-display region NDA on the substrate SUB1 can be arranged along a third direction (e.g., Figures 1 to 3 The Z-axis direction) are connected or in contact with each other. Here, the first direction (e.g., Figures 1 to 3 The X-axis direction can be either the width or length direction of the base SUB1, or a second direction (e.g., Figures 1 to 3 The Y-axis direction can be a direction that intersects (or is orthogonal) the first direction, and the third direction can be a direction that intersects (or is orthogonal) the first and second directions (e.g., it can correspond to the thickness direction of the substrate SUB1). In the embodiment, the first connecting region CA1 and the second connecting region CA2 can be collectively referred to as the connecting region CA.

[0047] At least one circuit element (e.g., a driver chip IC) may be arranged on the circuit member 101. The circuit member 101 may have various forms and may include, for example, a flexible material, and according to some embodiments, may include the form of a flexible printed circuit board (FPCB).

[0048] Circuit component 101 can be electrically connected to display panel DP, and can transmit electrical signals to display panel DP, for example. According to some embodiments, a driver chip IC on circuit component 101 can transmit electrical signals to display panel DP.

[0049] According to some embodiments, circuit component 101 may be electrically connected to a printed circuit board (PCB). In this case, the PCB can transmit electrical signals to circuit component 101. The PCB may include a flexible printed circuit board (FPCB).

[0050] Figure 4 yes Figure 1 The diagram shows a schematic block diagram of the structure of the display device.

[0051] Reference Figure 4 At least one scan line SL and at least one data line DL can be arranged in the display area DA. For example, multiple scan lines SL1, ..., SLn extending along a first direction (X-axis direction), multiple data lines DL1, ..., DLm extending along a direction intersecting the first direction (e.g., a second direction (Y-axis direction)), and multiple pixels PX can be positioned in the display area DA. Here, m and n represent natural numbers greater than 0. Although for ease of explanation, Figure 4A single pixel PX is shown, but as those skilled in the art will understand, the display device 100 may include any suitable number of pixels PX depending on the design and size of the display device 100.

[0052] The wiring along which electrical signals are applied to multiple pixels PX may include multiple scan lines SL1, ..., SLn and multiple data lines DL1, ..., DLm. For example, the multiple scan lines SL1, ..., SLn may be arranged in multiple rows extending in a first direction (X-axis direction) to transmit scan signals to pixels PX. For example, the multiple data lines DL1, ..., DLm may be arranged in multiple columns extending in a second direction (Y-axis direction) to transmit data signals to pixels PX. The multiple pixels PX may be positioned at the intersections of the multiple scan lines SL1, ..., SLn and the multiple data lines DL1, ..., DLm.

[0053] Each pixel PX may include an emitting element to generate at least one type of light, such as red, green, blue, or white light. For example, each pixel PX may include an organic light-emitting diode (OLED) as the emitting element (see [link to OLED documentation]). Figure 5 However, it is not limited to this.

[0054] In the non-display area NDA, a data driver 102 for applying data signals to the display area DA, a scan driver 103 for applying scan signals to the display area DA, a voltage controller 104 for controlling the voltage applied to the display area DA, and a controller 105 for controlling the data driver 102, the scan driver 103, and the voltage controller 104 may be arranged.

[0055] The voltage controller 104 can generate and control the first voltage ELVDD, the second voltage ELVSS, and the initialization voltage VINT applied to the display area DA.

[0056] The first voltage ELVDD, the second voltage ELVSS, and the initialization voltage VINT can be applied to multiple pixels PX. For example, the first voltage ELVDD can be a positive voltage, and the second voltage ELVSS can be a negative voltage or a ground voltage. That is, the second voltage ELVSS can have a lower level than the first voltage ELVDD.

[0057] Controller 105 can receive image signals RGB and control signals CS from another component (e.g., a system board). Controller 105 can generate image data DATA by converting the data format of the image signals RGB into a format suitable for the interface between data driver 102 and controller 105. Controller 105 can then apply the image data DATA with the converted data format to data driver 102.

[0058] The controller 105 can generate and output a first control signal CS1, a second control signal CS2, and a third control signal CS3 in response to the control signal CS. The first control signal CS1 can be defined as a scan control signal, and the second control signal CS2 can be defined as a data control signal. The first control signal CS1 can be applied to the scan driver 103. The second control signal CS2 can be applied to the data driver 102, and the third control signal CS3 can be applied to the voltage controller 104.

[0059] The scan driver 103 can generate multiple scan signals in response to the first control signal CS1. The multiple scan signals can be applied to multiple pixels PX through multiple scan lines SL1, ..., SLn.

[0060] The data driver 102 can generate multiple data voltages corresponding to the image data DATA in response to the second control signal CS2. These multiple data voltages can be applied to multiple pixels PX via multiple data lines DL1, ..., DLm. The data driver 102 can simultaneously apply the data voltages generated in pixel rows to multiple pixels PX via multiple data lines DL1, ..., DLm.

[0061] Multiple pixels (PXs) can receive multiple data voltages in response to multiple scan signals. Multiple pixels (PXs) can display images by emitting light with brightness corresponding to the multiple data voltages. Multiple pixels (PXs) can display images by emitting light sequentially or simultaneously.

[0062] Figure 5 yes Figure 1 A schematic diagram of the equivalent circuit of the pixels of the display device shown. Although Figure 5 Various components in the circuitry of a pixel according to some embodiments are shown, but embodiments of the present disclosure are not limited thereto, and the circuitry may include additional components according to various embodiments without departing from the spirit and scope of embodiments of the present disclosure.

[0063] Reference Figure 5 The pixel circuit PC can be connected to a display element (e.g., an organic light-emitting diode OLED). The pixel circuit PC can be positioned within the display area DA. The pixel circuit PC can include at least a driving thin-film transistor T1, a switching thin-film transistor T2, and a storage capacitor Cst. The organic light-emitting diode OLED can emit at least one type of light, such as red, green, or blue light, or red, green, blue, or white light.

[0064] The switching thin-film transistor T2 can be connected to the scan line SL and the data line DL, and can transmit the data signal or data voltage input from the data line DL to the driving thin-film transistor T1 based on the scan signal or switching voltage input from the scan line SL. The storage capacitor Cst can be connected to the switching thin-film transistor T2 and the driving voltage line PL, and can store the voltage corresponding to the difference between the voltage transmitted from the switching thin-film transistor T2 and the first voltage ELVDD applied to the driving voltage line PL.

[0065] The driving thin-film transistor T1 can be connected to the driving voltage line PL and the storage capacitor Cst, and can control the driving current flowing from the driving voltage line PL into the organic light-emitting diode (OLED) in response to the value of the voltage stored in the storage capacitor Cst. The OLED can emit light with a specific brightness according to the driving current. The counter electrode of the OLED can receive a second voltage ELVSS.

[0066] although Figure 5 The pixel circuit PC shown includes two thin-film transistors and a storage capacitor, but the pixel circuit PC may include at least three, four or five thin-film transistors and may include at least two or three capacitors.

[0067] Figure 6 It is along Figures 1 to 3 A schematic cross-sectional view of an example of a section cut by line VI-VI'.

[0068] Reference Figures 1 to 3 and Figure 6 The display device 100 may include a display panel DP. The display panel DP may include a substrate SUB1, a buffer layer 111, a pixel circuit layer PCL, a display element layer DEL, and a packaging unit TFE.

[0069] The substrate SUB1 may include a glass material, such as a transparent glass material primarily comprising SiO2. However, it is not limited to this, and the substrate SUB1 may include a plastic material. The plastic material may include polyethersulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide, polycarbonate, cellulose triacetate (TAC), cellulose acetate propionate (CAP), etc. According to some embodiments, the substrate SUB1 may have a multilayer structure comprising plastic materials and may also include at least one barrier layer.

[0070] According to some embodiments, the substrate SUB1 may have flexible, rollable and bendable properties.

[0071] According to some embodiments, the buffer layer 111 may be disposed on the substrate SUB1. The buffer layer 111 may include an inorganic insulating material such as silicon nitride, silicon oxynitride, and silicon oxide, and may be a single layer or multiple layers comprising the inorganic insulating material.

[0072] The pixel circuit layer PCL can be disposed on the buffer layer 111. The pixel circuit layer PCL may include an inorganic insulating layer IIL, a first planarization layer 115, and a second planarization layer 116, which are disposed below and / or above the thin-film transistors (TFTs) and TFT components included in the pixel circuit PC. The inorganic insulating layer IIL may include a first gate insulating layer 112, a second gate insulating layer 113, and an interlayer insulating layer 114.

[0073] A thin-film transistor (TFT) may include a semiconductor layer A, and semiconductor layer A may include polycrystalline silicon. According to some embodiments, semiconductor layer A may include amorphous silicon, oxide semiconductor, or organic semiconductor. Semiconductor layer A may include a channel region and drain and source regions respectively disposed on opposite sides of the channel region. A gate electrode G may be stacked with the channel region.

[0074] The gate electrode G may include a conductive material, for example, a low-resistance metallic material. According to some embodiments, the gate electrode G may include a conductive material comprising molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer or a single layer comprising said material.

[0075] The first gate insulating layer 112 between the semiconductor layer A and the gate electrode G may include an insulating material, for example, an inorganic insulating material such as silicon oxide (SiO2) or silicon nitride (SiN). X ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) or zinc oxide (ZnO) X ), and zinc oxide (ZnO) X () can be zinc oxide (ZnO) and / or zinc peroxide (ZnO2).

[0076] The second gate insulating layer 113 may cover the gate electrode G. The second gate insulating layer 113 may include an insulating material; for example, similar to the first gate insulating layer 112, it may include an inorganic insulating material such as silicon oxide (SiO2) or silicon nitride (SiN). X ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) or zinc oxide (ZnO) X ), and zinc oxide (ZnO) X() can be zinc oxide (ZnO) and / or zinc peroxide (ZnO2).

[0077] According to some embodiments, the upper electrode CE2 of the storage capacitor Cst can be disposed on the second gate insulating layer 113. The upper electrode CE2 can be stacked with the gate electrode G positioned below the upper electrode CE2.

[0078] The gate electrode G and the upper electrode CE2, which are stacked on top of each other and with the second gate insulating layer 113 disposed between the gate electrode G and the upper electrode CE2, can also form the storage capacitor Cst of the pixel circuit PC. For example, the gate electrode G can be used as the lower electrode CE1 of the storage capacitor Cst.

[0079] exist Figure 6 In this configuration, the storage capacitor Cst and the thin-film transistor TFT are stacked on top of each other; however, according to some embodiments, the storage capacitor Cst may be formed without being stacked with the thin-film transistor TFT.

[0080] The upper electrode CE2 may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be a single layer or multiple layers of said material.

[0081] Interlayer insulating layer 114 may cover the upper electrode CE2. Interlayer insulating layer 114 may include insulating materials, for example, inorganic insulating materials such as silicon oxide (SiO2) or silicon nitride (SiN). X ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) or zinc oxide (ZnO) X Zinc oxide (ZnO) X The inorganic insulating material can be zinc oxide (ZnO) and / or zinc peroxide (ZnO2). The interlayer insulation layer 114 can be a single layer or multiple layers comprising the inorganic insulating material.

[0082] Both the drain electrode D and the source electrode S can be positioned on the interlayer insulating layer 114. The drain electrode D and the source electrode S can include conductive materials, such as metallic materials. Specific examples include molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and can be formed as a multilayer or a single layer comprising said materials. According to some embodiments, the drain electrode D and the source electrode S can have a Ti / Al / Ti multilayer structure.

[0083] The first planarization layer 115 may be arranged to cover the drain electrode D and the source electrode S. The first planarization layer 115 may include various insulating materials, for example, it may include an organic insulating layer, and according to some embodiments, it may include general polymers (such as polymethyl methacrylate (PMMA) or polystyrene (PS)), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, and blends thereof.

[0084] According to some embodiments, the connection electrode CML can be disposed on the first planarization layer 115. The connection electrode CML can be connected to the drain electrode D or the source electrode S through contact holes in the first planarization layer 115. The connection electrode CML can include a material with good conductivity. The connection electrode CML can include conductive materials comprising molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and can be formed as a multilayer or a single layer comprising said material. According to some embodiments, the connection electrode CML can have a Ti / Al / Ti multilayer structure.

[0085] The second planarization layer 116 may be arranged to cover the connection electrode CML. The second planarization layer 116 may include various insulating materials (e.g., organic insulating layers), and according to some embodiments, may include general polymers (such as polymethyl methacrylate (PMMA) or polystyrene (PS)), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, and blends thereof.

[0086] The display element layer (DEL) can be disposed on the pixel circuit layer (PCL). According to some embodiments, at least one of the display element layers (DEL) can be disposed on the same layer as a layer of the pixel circuit layer (PCL) or disposed below the pixel circuit layer (PCL).

[0087] The display element layer DEL may include a display element DE. The display element DE may be an organic light-emitting diode (OLED). The pixel electrode 121 of the display element DE may be electrically connected to the connection electrode CML through the contact hole of the second planarization layer 116.

[0088] Pixel electrode 121 may include a conductive material, such as a conductive oxide, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). According to some embodiments, pixel electrode 121 may include a reflective film comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or compounds or mixtures thereof. According to some embodiments, pixel electrode 121 may also include a film comprising ITO, IZO, ZnO, or In2O3 and positioned above / below the reflective film.

[0089] A pixel defining layer 118, including an opening 118OP corresponding to at least one region of the pixel electrode 121 (e.g., including the central region), may be disposed on the pixel electrode 121. The pixel defining layer 118 may include an organic insulating material and / or an inorganic insulating material. The opening 118OP may define an emission region EA of light emitted from the display element DE (hereinafter referred to as the emission region of the display element DE). For example, at least a portion of the width of the opening 118OP may correspond to the width of the emission region EA of the display element DE.

[0090] According to some embodiments, the pixel defining layer 118 may include a black-based light-shielding material, which may include resins or pastes (including carbon black, carbon nanotubes, or black dyes), metal particles (e.g., nickel, aluminum, molybdenum, and alloys thereof), metal oxide particles (e.g., chromium oxide), or metal nitride particles (e.g., chromium nitride). When the pixel defining layer 118 includes a light-shielding material, external light reflection caused by the metal structure disposed beneath the pixel defining layer 118 can be relatively reduced.

[0091] According to some embodiments, spacer 119 may be disposed on pixel defining layer 118. Spacer 119 may be arranged to suppress damage to substrate SUB1 during a method of manufacturing a display device. In the case of manufacturing display panel DP, a mask may be used. The mask may enter the opening 118OP of pixel defining layer 118 or may be in close contact with pixel defining layer 118, thereby causing defects such as damage or breakage of a portion of substrate SUB1 when deposited material is deposited on substrate SUB1. Spacer 119 may suppress such damage or breakage of substrate SUB1 caused by mask.

[0092] Spacer 119 may include an insulating material, such as an organic insulating material (e.g., polyimide). According to some embodiments, spacer 119 may include an inorganic insulating material such as silicon nitride or silicon oxide, or may include both organic and inorganic insulating materials.

[0093] According to some embodiments, spacer 119 may comprise a different material than pixel defining layer 118. According to some embodiments, spacer 119 may comprise the same material as pixel defining layer 118. In this case, pixel defining layer 118 and spacer 119 may be formed together during a masking process using a halftone mask or the like.

[0094] Intermediate layer 122 may be disposed on pixel defining layer 118. Intermediate layer 122 may include emitting layer 122b disposed in opening 118OP of pixel defining layer 118. Emitting layer 122b may include a polymeric or low-molecular-weight organic material that emits light of a specific color.

[0095] The first functional layer 122a and the second functional layer 122c can be disposed below and above the emitter layer 122b, respectively. For example, the first functional layer 122a may include a hole transport layer (HTL), or may include a hole transport layer and a hole injection layer (HIL). The second functional layer 122c may be a component disposed on the emitter layer 122b and may include an electron transport layer (ETL) and / or an electron injection layer (EIL). Similar to the counter electrode 123 described later, the first functional layer 122a and / or the second functional layer 122c may be a common layer formed to cover the entire substrate SUB1.

[0096] The counter electrode 123 may comprise a conductive material having a relatively low work function. For example, the counter electrode 123 may comprise a (semi-)transparent layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or alloys thereof. According to some embodiments, the counter electrode 123 may also comprise a layer such as ITO, IZO, ZnO, or In2O3 disposed on a (semi-)transparent layer comprising the aforementioned material.

[0097] In some embodiments, the coating may be further disposed on the counter electrode 123. The coating may include inorganic materials (e.g., LiF) and / or organic materials.

[0098] The encapsulation unit TFE can be disposed on the counter electrode 123. According to some embodiments, the encapsulation unit TFE may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. For example, the encapsulation unit TFE may include a first inorganic encapsulation layer 131, an organic encapsulation layer 132, and a second inorganic encapsulation layer 133 stacked sequentially.

[0099] The first inorganic encapsulation layer 131 and the second inorganic encapsulation layer 133 may comprise at least one inorganic material selected from alumina, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The organic encapsulation layer 132 may comprise a polymeric material. This polymeric material may include acrylic resin, epoxy resin, polyimide, and polyethylene. According to some embodiments, the organic encapsulation layer 132 may comprise an acrylate.

[0100] Figure 7 yes Figure 3 A magnified view of the first connecting region CA1 in the image.

[0101] Reference Figure 7 The first connection area CA1 may include multiple pad (also known as solder pad) units PU1. For example, Figure 7 A plurality of pad units PU1 are shown, including a first pad unit PU1a, a second pad unit PU1b, a third pad unit PU1c, and a fourth pad unit PU1d. For ease of description, the first pad unit PU1a, the second pad unit PU1b, the third pad unit PU1c, and the fourth pad unit PU1d can all be referred to as pad unit PU1. According to some embodiments, the number of the plurality of pad units PU1 can be determined in various ways depending on the conditions of the display panel DP. According to some embodiments, the number of the plurality of pad units PU1 arranged in the first connection area CA1 can be one, two, three, four, five, or more.

[0102] Each of the plurality of pad units PU1 may have a width and a length. For example, each pad unit PU1 may have a length extending in a second direction (Y-axis direction) and a width relative to a first direction (X-axis direction).

[0103] Multiple pad units PU1 may be arranged spaced apart from each other along a first direction (X-axis direction). According to some embodiments, multiple pad units PU1 may be arranged in parallel and spaced apart from each other along the first direction (X-axis direction).

[0104] At least one raised pattern 144 and a conductive layer covering the raised pattern 144 may be disposed on each of the plurality of pad units PU1, and an opening may be disposed in the region of the corresponding pad unit PU1. According to some embodiments, the pad unit PU1 may include at least one raised pattern 144, a second connecting conductive layer 145 covering at least one raised pattern 144, and contact holes CNTs disposed in the region of the pad unit PU1. As will be discussed later... Figure 9 and Figure 10 As described in Figure 7 The raised pattern 144 shown is covered by the second conductive layer 145, but for ease of explanation, it is shown in solid lines. Figure 7 The raised pattern 144.

[0105] At least one dummy pattern unit DU1 can be arranged between two adjacent pad units PU1. For example, as Figure 7 As shown, the dummy pattern unit DU1 may include dummy pattern units DU1a, DU1b, and DU1c. One dummy pattern unit DU1a may be arranged between the first pad unit PU1a and the second pad unit PU1b. For ease of description, the dummy pattern units DU1a, DU1b, and DU1c may be referred to as dummy pattern unit DU1. The dummy pattern unit DU1 may be arranged to be spaced apart from two adjacent pad units PU1 along a first direction (X-axis direction).

[0106] According to some embodiments, the gap between a pad unit PU1 adjacent to a dummy pattern unit DU1 on one side and the dummy pattern unit DU1 can be equal to the gap between a pad unit PU1 adjacent to a dummy pattern unit DU1 on the other side. For example, based on the dummy pattern unit DU1 arranged between the first pad unit PU1a and the second pad unit PU1b, the gap between the dummy pattern unit DU1 and the first pad unit PU1a can be substantially the same as the gap between the dummy pattern unit DU1 and the second pad unit PU1b.

[0107] According to some embodiments, the dummy pattern unit DU1 can be arranged parallel to two adjacent pad units PU1 along a first direction (X-axis direction).

[0108] According to some embodiments, each of the plurality of pad units PU1 and each of the plurality of dummy pattern units DU1 may be alternately arranged to be spaced apart from each other along a first direction (X-axis direction).

[0109] Adjacent insulating layers IL1 can be arranged in the space between adjacent pad units PU1 and dummy pattern units DU1, and in the space between two adjacent pad units PU1. According to some embodiments, adjacent insulating layers IL1 can also be arranged around the pad units PU1 and dummy pattern units DU1, for example, they can be arranged to surround the pad units PU1 and dummy pattern units DU1. According to some embodiments, adjacent insulating layers IL1 can be arranged to contact the pad units PU1 and dummy pattern units DU1 in the first connection region CA1. According to some embodiments, adjacent insulating layers IL1 can be arranged to cover the entire first connection region CA1 except for the pad units PU1 and dummy pattern units DU1.

[0110] The adjacent insulating layer IL1 may include insulating material, for example, an insulating material including organic material.

[0111] Figure 8 It is along Figures 1 to 3 and Figure 7A schematic diagram of an example of a cross section taken by line VIII-VIII'.

[0112] Reference Figure 8 The first connection area CA1 on the substrate SUB1 and the second connection area CA2 on the circuit member 101 can be connected to each other (e.g., in contact with each other) along a third direction (Z-axis direction). Therefore, the display panel DP and the circuit member 101 can be electrically connected.

[0113] The pad unit PU1 and the dummy pattern unit DU1 can be arranged on the substrate SUB1, and the area of ​​the pad unit PU1 can be electrically connected to the circuit member 101, for example, it can be in contact with the circuit member 101. The pad unit PU1 and the circuit member 101 can be electrically connected.

[0114] Lead units LU1, protruding in the direction toward pad unit PU1, can be arranged on circuit member 101. Lead units LU1 can extend along a second direction (Y-axis direction). According to some embodiments, lead units LU1 can be arranged as a plurality of lead units, and the plurality of lead units LU1 can be arranged spaced apart along a first direction (X-axis direction). For example, the plurality of lead units LU1 can be arranged parallel along the first direction (X-axis direction).

[0115] According to some embodiments, Figure 8 A plurality of lead units LU1 are shown, including a first lead unit LU1a, a second lead unit LU1b, and a third lead unit LU1c. For ease of description, the first lead unit LU1a, the second lead unit LU1b, and the third lead unit LU1c may all be referred to as lead unit LU1. According to some embodiments, the number of the plurality of lead units LU1 can be determined in various ways depending on the conditions of the display panel DP. According to some embodiments, the number of the plurality of lead units LU1 arranged on the circuit member 101 may be one, two, three, four, five, or more.

[0116] Lead unit LU1 can be arranged at a position corresponding to pad unit PU1, for example, arranged to overlap with pad unit PU1 along a third direction (Z-axis direction). Multiple pad units PU1 and multiple lead units LU1 can be matched with each other, for example, arranged in a one-to-one matching manner. According to some embodiments, lead unit LU1 can be electrically connected to pad unit PU1, for example, in contact with pad unit PU1.

[0117] Lead unit LU1 may include a conductive material (e.g., a material including copper (Cu) and tin (Sn), and multiple lead units LU1 may include the same material. Multiple lead units LU1 may be formed by the same process.

[0118] The dummy pattern unit DU1 can be arranged at a distance from the lead unit LU1. The dummy pattern unit DU1 can be arranged to overlap with the space between multiple lead units LU1. For example, the dummy pattern unit DU1 can correspond to the space between two adjacent lead units LU1 in the third direction (Z-axis direction) and can be not overlapped with the lead units LU1.

[0119] The dummy pattern unit DU1 can be electrically insulated from the lead unit LU1 and the circuit component 101.

[0120] The intermediate insulating layer NCF1 can be disposed in the space between the substrate SUB1 and the circuit component 101. According to some embodiments, the intermediate insulating layer NCF1 can be disposed in contact with the pad unit PU1, the dummy pattern unit DU1, the lead unit LU1 and the adjacent insulating layer IL1.

[0121] The arrangement of the dummy pattern unit DU1 can reduce the volume of the space where the intermediate insulating layer NCF1 can be arranged. The arrangement of the dummy pattern unit DU1 can cause a relative reduction in the thickness of the intermediate insulating layer NCF1, thereby allowing for precise thickness control of the display device 100.

[0122] According to some embodiments, the intermediate insulating layer NCF1 may include a non-conductive adhesive film or a molded underfill.

[0123] Reference Figure 8 The adjacent insulating layer IL1 can be positioned between the substrate SUB1 and the intermediate insulating layer NCF1. For example, the substrate SUB1 and the intermediate insulating layer NCF1 can be spaced apart from each other by the adjacent insulating layers IL1 or can be non-contacting.

[0124] According to some embodiments, adjacent insulating layers IL1 can be arranged without gaps in the space between pad unit PU1 and dummy pattern unit DU1. Adjacent insulating layers IL1 can be arranged such that their upper surfaces bulge upwards.

[0125] According to some embodiments, adjacent insulating layers IL1 may have an asymmetrical shape relative to a third direction (Z-axis direction). The upper surface of adjacent insulating layers IL1 may be uneven.

[0126] The pad unit PU1, the dummy pattern unit DU1, and the adjacent insulating layer IL1 may have heights based on the thickness direction of the display device 100. The height of the pad unit PU1 may be equal to or greater than the height of the adjacent insulating layer IL1. According to some embodiments, the height of the pad unit PU1 may be greater than the height of the edge of the adjacent insulating layer IL1 adjacent to the pad unit PU1. According to some embodiments, an extension line from the edge of the upper surface of the adjacent insulating layer IL1 in a first direction (X-axis direction) may be lower than the height of the adjacent pad unit PU1.

[0127] For example, adjacent insulating layers IL1 can be arranged using a photolithography process. The photolithography process may include a photosensitive material application step, an exposure step, and a development step. The adjacent insulating layers IL1 may include a photosensitive material, such as a photosensitive organic material or a photosensitive resin.

[0128] According to some embodiments, the adjacent insulating layer IL1 can be applied to a region on the first connection region CA1 during the application step (e.g., including the upper surface of the pad unit PU1, the upper surface of the dummy pattern unit DU1, the space between the pad unit PU1 and the dummy pattern unit DU1, and the region surrounding the pad unit PU1 and the dummy pattern unit DU1). According to some embodiments, the adjacent insulating layer IL1 can be applied to a region including the entire first connection region CA1. In subsequent exposure and development steps, the regions of the adjacent insulating layer IL1 applied to the upper surfaces of the pad unit PU1 and the dummy pattern unit DU1 can be removed.

[0129] In this configuration, during the exposure step, the portion of the upper surface of the adjacent insulating layer IL1 adjacent to the pad unit PU1 and the dummy pattern unit DU1 can be exposed to light. The portion of the upper surface of the adjacent insulating layer IL1 exposed to light can be partially removed. According to some embodiments, the height of the adjacent insulating layer IL1 can be relatively reduced.

[0130] The reduction in height of adjacent insulating layers IL1 can occur unevenly on the upper surface of adjacent insulating layers IL1. For example, the height of adjacent insulating layers IL1 can be further reduced in regions closer to adjacent pad units PU1 and dummy pattern units DU1 on the upper surface of adjacent insulating layers IL1. In some embodiments, more of the region closer to pad units PU1 and dummy pattern units DU1 can be removed from the upper surface of adjacent insulating layers IL1, while less or no removal can be made from regions relatively far from pad units PU1 and dummy pattern units DU1. Therefore, the height of adjacent insulating layers IL1 can decrease as adjacent insulating layers IL1 approach pad units PU1 and dummy pattern units DU1, thus the upper surface of adjacent insulating layers IL1 can have an upwardly convex shape.

[0131] The adjacent insulating layer IL1 can have a width based on a first direction (X-axis direction). As the width of the adjacent insulating layer IL1 decreases, more of the upper region of the adjacent insulating layer IL1 can be removed. According to some embodiments, during the exposure step, as the gap between the mask patterns decreases, more of the upper region of the adjacent insulating layer IL1 can be removed. According to some embodiments, as the width of the adjacent insulating layer IL1 decreases, the ratio of the removed area of ​​the adjacent insulating layer IL1 to the entire adjacent insulating layer IL1 can increase. Under the same conditions, for example, when the applied thickness of the adjacent insulating layers IL1 is equal, the height of the adjacent insulating layer IL1 can decrease more as the width of the adjacent insulating layer IL1 decreases.

[0132] The width of adjacent insulating layers IL1 can correspond to the gap between adjacent pad units PU1 and dummy pattern units DU1. Therefore, by adjusting the gap between adjacent pad units PU1 and dummy pattern units DU1, the width of adjacent insulating layers IL1 can be adjusted, and the height of adjacent insulating layers IL1 can also be adjusted. For example, while maintaining the gap between two adjacent pad units PU1, at least one dummy pattern unit DU1 can be arranged between the pad units PU1, thereby relatively reducing the width of adjacent insulating layers IL1. According to some embodiments, by increasing the width of each of the adjacent pad units PU1 and dummy pattern units DU1, the width of adjacent insulating layers IL1 arranged between pad units PU1 and dummy pattern units DU1 can be reduced.

[0133] Therefore, when the gap between adjacent pad unit PU1 and dummy pattern unit DU1 is reduced, the height of the adjacent insulating layer IL1 arranged between adjacent pad unit PU1 and dummy pattern unit DU1 can be further reduced.

[0134] Depending on the height control of the adjacent insulating layer IL1 (e.g., height reduction), the size of the area where the adjacent insulating layer IL1 connects to (or contacts) the lead unit LU1 can be relatively reduced, or the adjacent insulating layer IL1 may not be connected to the lead unit LU1. According to some embodiments, the interference of the adjacent insulating layer IL1 on the connection between the pad unit PU1 and the lead unit LU1 can be relatively reduced. Therefore, pressure applied in the direction from the lead unit LU1 towards the pad unit PU1, or pressure applied in the opposite direction, can be effectively transmitted to the lead unit LU1 and the pad unit PU1, and the electrical connection or contact characteristics between the lead unit LU1 and the pad unit PU1 can be relatively improved.

[0135] According to some embodiments, the adjacent insulating layer IL1 arranged in the space between adjacent pad units PU1 and dummy pattern units DU1 can be spaced apart from the lead unit LU1. In this case, the pressure applied by the lead unit LU1 in the direction from the lead unit LU1 toward the pad unit PU1 may not be transmitted to the adjacent insulating layer IL1. Therefore, the pressure can be effectively applied to the pad unit PU1, thereby relatively improving the reliability of the electrical connection between the lead unit LU1 and the pad unit PU1.

[0136] Figure 9 It is along Figures 1 to 3 and Figure 7 A schematic diagram of an example of a cross section taken by line IX-IX'.

[0137] Multiple raised patterns 144 can be arranged on the pad unit PU1. According to some embodiments, the multiple raised patterns 144 can be arranged spaced apart from each other along a second direction (Y-axis direction), and according to some embodiments, the multiple raised patterns 144 can be arranged with equal or different gaps for each pad unit PU1. For example, Figure 7 A pad unit PU1 comprising four raised patterns 144 is shown. According to some embodiments, the number of raised patterns 144 can be determined in various ways depending on the conditions of the display panel DP. According to some embodiments, the number of raised patterns 144 arranged on the pad unit PU1 is not limited to the embodiments and can be three, four, five, or more.

[0138] The raised pattern 144 may comprise various materials, such as inorganic or organic materials. According to some embodiments, multiple raised patterns 144 may comprise the same material as at least one of multiple insulating layers disposed in the display area DA under the same process. The dimensions of the formed raised patterns 144 may be the same or different from each other.

[0139] The raised pattern 144 may be arranged to be surrounded by at least one conductive layer. According to some embodiments, a plurality of raised patterns 144 may be arranged on a first conductive layer 143, and a second conductive layer 145 may be arranged on the plurality of raised patterns 144. For example, the plurality of raised patterns 144 may be arranged between the first conductive layer 143 and the second conductive layer 145, and may cover at least one region of the first conductive layer 143. The first conductive layer 143 and the second conductive layer 145 may be electrically connected in regions where the raised patterns 144 are not arranged.

[0140] According to some embodiments, a substrate conductive layer 141, a pad unit insulating layer 142, a first connecting conductive layer 143, and a second connecting conductive layer 145 may be sequentially arranged on a substrate SUB1, and a plurality of raised patterns 144 may be arranged between the first connecting conductive layer 143 and the second connecting conductive layer 145. In this case, the pad unit insulating layer 142 may include an opening, and the opening may be a contact hole (CNT). For example, the substrate conductive layer 141 may be electrically connected to the first connecting conductive layer 143 and the second connecting conductive layer 145 through the contact hole (CNT). The number of conductive layers arranged on the pad unit PU1 is not limited to the disclosed embodiments and may be three, four, five, or more.

[0141] Reference Figure 9 The contact hole CNT can be a portion in which the opening is formed on the pad unit PU1, and can have a shape that is recessed in the third direction (Z-axis direction). The portions of the plurality of raised patterns 144 arranged on the pad unit PU1 can form raised portions CP of the second connecting conductive layer 145 that protrude in the third direction (Z-axis direction).

[0142] For example, the portion with the raised pattern 144 can be superimposed on the raised portion CP. The raised portion CP can contact the lead unit LU1 and can be electrically connected to the lead unit LU1.

[0143] The gaps between the plurality of raised portions CP arranged in a pad unit PU1 can be different, and can be the same if desired. The gaps between the plurality of raised portions CP arranged in two adjacent pad units PU1 can be different for each pad unit PU1. According to some embodiments, the gaps between the plurality of raised portions CP in each of the plurality of pad units PU1 arranged outwardly can be narrower than the gaps between the plurality of raised portions CP in each of the plurality of pad units PU1 arranged inwardly. According to some embodiments, the number of the plurality of raised portions CP in each of the plurality of pad units PU1 arranged outwardly can be greater than the number of the plurality of raised portions CP in each of the plurality of pad units PU1 arranged inwardly. According to some embodiments, the number of the plurality of raised portions CP arranged on each of the plurality of pad units PU1 can be the same.

[0144] Multiple protrusions CP can have different widths in the first direction (X-axis direction) and the second direction (Y-axis direction), or different heights in the third direction (Z-axis direction).

[0145] Figure 10 yes Figure 8 A magnified view of area A1 in the image; Reference Figure 10In one embodiment, the upper and side surfaces of the substrate conductive layer 141 disposed on the substrate SUB1 may be covered by the pad unit insulating layer 142.

[0146] According to some embodiments, the first connecting conductive layer 143 and the second connecting conductive layer 145 disposed on the pad unit insulating layer 142 may have the same width in the first direction (X-axis direction), and according to some embodiments, the first connecting conductive layer 143 and the second connecting conductive layer 145 disposed on the pad unit insulating layer 142 may have different widths in the first direction (X-axis direction).

[0147] The substrate conductive layer 141, the first connecting conductive layer 143, and the second connecting conductive layer 145 may include various conductive materials. For example, the substrate conductive layer 141, the first connecting conductive layer 143, and the second connecting conductive layer 145 may include metal layers, and for example, may include conductive materials containing molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc.

[0148] According to some embodiments, the substrate conductive layer 141, the first connecting conductive layer 143, and the second connecting conductive layer 145 may comprise the same material. According to some embodiments, the substrate conductive layer 141, the first connecting conductive layer 143, and the second connecting conductive layer 145 may comprise the same material as at least one of the electrodes used in the display area DA (e.g., the gate electrode G, drain electrode D, source electrode S, or connecting electrode CML described above) under the same process.

[0149] The adjacent insulating layer IL1 may not overlap with the area of ​​the second connecting conductive layer 145.

[0150] Figures 11 to 13 yes Figure 8 A magnified view of area A2 and a modified example view.

[0151] Reference Figure 11 The dummy pattern unit DU1 may include insulating material and may be arranged to have height in a third direction (Z-axis direction). (See reference...) Figure 11 The dummy pattern unit DU1 may include a first dummy conductive layer 151 disposed on the substrate SUB1 and a dummy insulating layer 153 covering the upper and side surfaces of the first dummy conductive layer 151. For example, the first dummy conductive layer 151 may be electrically insulated from the adjacent insulating layer IL1 or the intermediate insulating layer NCF1 and arranged not to contact the adjacent insulating layer IL1 or the intermediate insulating layer NCF1, while the adjacent insulating layer IL1 or the intermediate insulating layer NCF1 may contact the dummy insulating layer 153.

[0152] According to some embodiments, the conductive layer may be further disposed on the dummy insulating layer 153. For example, see reference to Figure 12The upper conductive layer 154 can be disposed on the dummy insulating layer 153. The first dummy conductive layer 151 and the upper conductive layer 154 can be electrically insulated from each other, and for example, can be arranged so that they do not contact each other through the dummy insulating layer 153.

[0153] According to some embodiments, the dummy conductive layer can be arranged as multiple dummy conductive layers. (Refer to...) Figure 13 The second dummy conductive layer 152 can be disposed on the first dummy conductive layer 151, and the dummy insulating layer 153 can be disposed on the second dummy conductive layer 152. Therefore, the dummy insulating layer 153 can cover the upper surface of the second dummy conductive layer 152 and the side surfaces of the first dummy conductive layer 151 and the second dummy conductive layer 152. The first dummy conductive layer 151 and the second dummy conductive layer 152 can be electrically insulated from the upper conductive layer 154, and, for example, can be arranged such that they pass through the dummy insulating layer 153 without contacting the upper conductive layer 154.

[0154] According to some embodiments, the arranged dummy conductive layers may have the same width in a first direction (X-axis direction). However, this is only an example, and at least three dummy conductive layers may be stacked in a third direction (Z-axis direction).

[0155] Reference Figures 11 to 13 The first dummy conductive layer 151, the second dummy conductive layer 152, and the upper conductive layer 154 may include various conductive materials. For example, the first dummy conductive layer 151, the second dummy conductive layer 152, and the upper conductive layer 154 may include metal layers, and for example, may include conductive materials containing molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc. According to some embodiments, the first dummy conductive layer 151, the second dummy conductive layer 152, and the upper conductive layer 154 may include the same material as at least one of the electrodes used in the display area DA (e.g., gate electrode G, drain electrode D, source electrode S, or connection electrode CML) and the conductive layers used in the pad unit PU1 (e.g., substrate conductive layer 141, first connection conductive layer 143, or second connection conductive layer 145) under the same process.

[0156] The dummy pattern unit DU1 may be electrically insulated from the lead unit LU1 or circuit member 101, and may be arranged spaced apart from the lead unit LU1 or circuit member 101, for example. According to some embodiments, the height of the dummy pattern unit DU1 in the third direction (Z-axis direction) may not be greater than the height of at least one of two adjacent pad units PU1. For example, the height of the dummy pattern unit DU1 may not be greater than the height of at least one of the areas of the pad unit PU1 where the raised pattern 144 is arranged.

[0157] A display device 100 according to some embodiments may include at least one dummy pattern unit DU1 between a plurality of pad units PU1. By means of the dummy pattern unit DU1, the width of adjacent insulating layers IL1 disposed between the dummy pattern unit DU1 and the pad units PU1 can be relatively reduced, and the height of the adjacent insulating layers IL1 can be relatively reduced. For example, the degree of etching during subsequent etching processes can be controlled by increasing the area of ​​the adjacent insulating layers IL1 exposed to light during the photolithography process, and the height of the adjacent insulating layers IL1 can be relatively reduced.

[0158] In this configuration, the interference of the adjacent insulating layer IL1 on the connection between the pad unit PU1 and the lead unit LU1 can be relatively reduced, and the pressure applied from the lead unit LU1 toward the pad unit PU1 or in the opposite direction can be effectively transmitted to the lead unit LU1 and the pad unit PU1. In other words, the reduction in connection reliability between the lead unit LU1 and the pad unit PU1 due to the adjacent insulating layer IL1 is suppressed. As a result, the electrical connection or contact characteristics between the pad unit PU1 and the circuit component 101 can be relatively improved, and the electrical characteristics and durability of the display device 100 can be enhanced.

[0159] Figure 14 This is an exploded perspective view of a portion of a display device according to some embodiments.

[0160] Reference Figure 14 The display device 200 may include a substrate SUB2, a display area DA' and a non-display area NDA' on the substrate SUB2, circuit components 201, and a printed circuit board PCB'. The display area DA' may include an area on the substrate SUB2 that emits visible light, and the non-display area NDA' may surround the display area DA'. According to some embodiments, the non-display area NDA' may be located outside one edge or multiple edges of the display area DA'.

[0161] The non-display area NDA' may include the first connection area CA1'.

[0162] Circuit components 201, etc., may be arranged to be connected (e.g., electrically connected) to or in contact with a portion of the non-display area NDA'. For example, as Figure 14 As shown, the second connection region CA2' arranged on the circuit component 201 and the first connection region CA1' in the non-display region NDA' arranged on the substrate SUB2 can be arranged along a third direction (e.g., Figure 14 The Z-axis direction) are connected or in contact with each other. Here, the first direction (e.g., Figure 14 The X-axis direction can be either the width or length direction of the base SUB2, or a second direction (e.g., Figure 14 The Y-axis direction can be a direction that intersects (or is orthogonal to) the first direction, and a third direction (e.g., Figure 14 The Z-axis direction can be a direction that intersects (or is orthogonal) the first and second directions (e.g., it can correspond to the thickness direction of the substrate SUB2).

[0163] At least one circuit element (e.g., a driver chip IC) may be disposed on circuit member 201. According to some embodiments, at least one circuit element may be disposed on circuit member 201 in a chip-on-film (COF) manner. For example, driver chip IC may be disposed on circuit member 201, and circuit member 201 may include flexible printed circuit board (FPCB).

[0164] Circuit component 201 can be electrically connected to display panel DP', and for example, can transmit electrical signals to display panel DP'. According to some embodiments, driver chip IC' on circuit component 201 can transmit electrical signals to display panel DP'.

[0165] According to some embodiments, circuit component 201 may be electrically connected to a printed circuit board PCB '. In this case, the printed circuit board PCB ' can transmit electrical signals to circuit component 201. The printed circuit board PCB ' may include a flexible printed circuit board (FPCB).

[0166] According to some embodiments, Figures 4 to 6 The structure can be applied in essentially the same way to these embodiments, or with some modifications within a similar scope.

[0167] Figure 15 yes Figure 14 A magnified view of the first connecting region CA1' in the image.

[0168] Reference Figure 15 Multiple pad units PU2 can be arranged in the first connection area CA1'. For example, Figure 15 A plurality of pad units PU2 are shown, including a first pad unit PU2a, a second pad unit PU2b, a third pad unit PU2c, and a fourth pad unit PU2d. For ease of description, the first pad unit PU2a, the second pad unit PU2b, the third pad unit PU2c, and the fourth pad unit PU2d may all be referred to as pad units PU2. According to some embodiments, the number of the plurality of pad units PU2 can be determined in various ways depending on the conditions of the display panel DP'. For example, the number of the plurality of pad units PU2 arranged in the first connection area CA1' can be one, two, three, four, five, or more.

[0169] Each of the multiple pad units PU2 can have a width and a length. For example, each pad unit PU2 can have a length extending in a second direction (Y-axis direction) and a width relative to a first direction (X-axis direction).

[0170] Multiple pad units PU2 can be arranged spaced apart from each other along a first direction (X-axis direction). According to some embodiments, multiple pad units PU2 can be arranged in parallel and spaced apart from each other along the first direction (X-axis direction).

[0171] At least one raised pattern 244 and a conductive layer covering the raised pattern 244 can be disposed on each of the plurality of pad units PU2, and an opening can be disposed in the region of the corresponding pad unit PU2. According to some embodiments, the pad unit PU2 may include at least one raised pattern 244, a second connecting conductive layer 245 covering at least one raised pattern 244, and a contact hole CNT' disposed in the region of the pad unit PU2. Similar to... Figure 7 The structure shown, Figure 15 The raised pattern 244 shown is covered by the second conductive layer 245, but for ease of explanation, it is shown in solid lines. Figure 15 The raised pattern 244.

[0172] Adjacent insulating layers IL2 can be arranged between two adjacent pad units PU2, and adjacent insulating layers IL2 can include grooves GV. Grooves GV can include grooves GVa, GVb, and GVc. For example, at least one groove GV can be arranged to correspond at least to the space between two adjacent pad units PU2. For example, as Figure 15 As shown, a groove GVa can be disposed between the first pad unit PU2a and the second pad unit PU2b. For ease of description, grooves GVa, GVb, and GVc can be referred to as groove GV.

[0173] The groove GV can be arranged to be spaced apart from two adjacent pad units PU2 along a first direction (X-axis direction). According to some embodiments, the gap between the pad unit PU2 adjacent to the groove GV on one side and the groove GV can be equal to the gap between the pad unit PU2 adjacent to the groove GV on the other side and the groove GV.

[0174] According to some embodiments, the grooves GV can be arranged parallel to two adjacent pad units PU2 along a first direction (X-axis direction). According to some embodiments, each of the plurality of pad units PU2 and each of the plurality of grooves GV can be alternately arranged to be spaced apart from each other along the first direction (X-axis direction).

[0175] Adjacent insulating layers IL2 can be arranged in the space between adjacent pad units PU2 and grooves GV. According to some embodiments, adjacent insulating layers IL2 can also be arranged around pad units PU2 and grooves GV, for example, they can be arranged to surround pad units PU2 and grooves GV.

[0176] According to some embodiments, the adjacent insulating layer IL2 may be arranged to contact the pad unit PU2 and the groove GV in the first connection region CA1'. According to some embodiments, the adjacent insulating layer IL2 may be arranged to cover the entire first connection region CA1' except for the pad unit PU2 and the groove GV.

[0177] The adjacent insulating layer IL2 may include insulating materials, such as insulating materials including organic materials.

[0178] Figure 16 It is along Figure 14 and Figure 15 A schematic diagram of an example of a cross section taken by line XVI-XVI'.

[0179] Reference Figure 16 The first connection area CA1' on the substrate SUB2 and the second connection area CA2' on the circuit member 201 can be connected to each other (e.g., in contact with each other) along a third direction (Z-axis direction). Therefore, the display panel DP' and the circuit member 201 can be electrically connected.

[0180] The pad unit PU2 and the adjacent insulating layer IL2 can be disposed on the substrate SUB2, and the adjacent insulating layer IL2 may include a groove GV. The area of ​​the pad unit PU2 can be electrically connected to the circuit member 201, for example, can be in contact with the circuit member 201.

[0181] Lead units LU2, protruding in the direction toward pad unit PU2, can be arranged on circuit member 201. Lead units LU2 can extend along a second direction (Y-axis direction). According to some embodiments, lead units LU2 can be arranged as a plurality of lead units, and the plurality of lead units LU2 can be arranged spaced apart along a first direction (X-axis direction). For example, the plurality of lead units LU2 can be arranged parallel along the first direction (X-axis direction).

[0182] According to some embodiments, Figure 16A plurality of lead units LU2 are shown, including a first lead unit LU2a, a second lead unit LU2b, and a third lead unit LU2c. For ease of description, the first lead unit LU2a, the second lead unit LU2b, and the third lead unit LU2c may all be referred to as lead unit LU2. According to some embodiments, the number of the plurality of lead units LU2 can be determined in various ways depending on the conditions of the display panel DP'. According to some embodiments, the number of the plurality of lead units LU2 arranged on the circuit member 201 may be one, two, three, four, five, or more.

[0183] Lead unit LU2 can be arranged at a position corresponding to pad unit PU2, for example, arranged to overlap pad unit PU2 along a third direction (Z-axis direction). Multiple pad units PU2 and multiple lead units LU2 can be matched with each other, for example, arranged in a one-to-one matching manner. According to some embodiments, lead unit LU2 can be electrically connected to pad unit PU2, for example, can be in contact with pad unit PU2.

[0184] Lead unit LU2 may include a conductive material (e.g., a material including copper (Cu) and tin (Sn)), and multiple lead units LU2 may include the same material.

[0185] The groove GV can be arranged to be spatially superimposed with multiple lead units LU2. For example, the groove GV can correspond to the space between two adjacent lead units LU2 in a third direction (Z-axis direction) and can be not superimposed with the lead units LU2.

[0186] The intermediate insulating layer NCF2 can be disposed in the space between the substrate SUB2 and the circuit component 201. According to some embodiments, the intermediate insulating layer NCF2 can be arranged to contact the pad unit PU2, the groove GV, the lead unit LU2, and the adjacent insulating layer IL2. According to some embodiments, the intermediate insulating layer NCF2 may include a non-conductive adhesive film or a molded underfill.

[0187] The pad unit PU2 and the adjacent insulating layer IL2 may have heights based on the thickness direction of the display device 200. The height of the pad unit PU2 may be equal to or greater than the height of the adjacent insulating layer IL2. According to some embodiments, the height of the pad unit PU2 may be greater than the height of the edge of the adjacent insulating layer IL2 adjacent to the pad unit PU2. According to some embodiments, an extension line from the edge of the upper surface of the adjacent insulating layer IL2 in a first direction (X-axis direction) may be lower than the height of the adjacent pad unit PU2.

[0188] The adjacent insulating layers IL2 can be arranged using various processes, and for example, they can be arranged using a process similar to that used to form the adjacent insulating layers IL1 in the above embodiments (e.g., by photolithography).

[0189] According to some embodiments, in the application step, adjacent insulating layers IL2 can be applied to a region on the first connection region CA1' (e.g., a region covering multiple pad units PU2). According to some embodiments, adjacent insulating layers IL2 can be applied to a region encompassing the entire first connection region CA1'. In subsequent exposure and development steps, the region of adjacent insulating layers IL2 applied to the upper surface of the pad units PU2 can be removed. At least one region of adjacent insulating layers IL2 located between two adjacent pad units PU2 can be removed, and for example, a groove GV can be formed.

[0190] In this configuration, during the exposure step, the portion of the upper surface of the adjacent insulating layer IL2 adjacent to the pad unit PU2 and the groove GV can be exposed to light. The portion of the upper surface of the adjacent insulating layer IL2 exposed to light can be partially removed. According to some embodiments, the height of the adjacent insulating layer IL2 can be relatively reduced.

[0191] The reduction in height of adjacent insulating layers IL2 can occur unevenly on the upper surface of adjacent insulating layers IL2. For example, the height of adjacent insulating layers IL2 can be further reduced in the region closer to the adjacent pad unit PU2 and groove GV on the upper surface of adjacent insulating layers IL2. According to some embodiments, more of the region closer to the pad unit PU2 and groove GV on the upper surface of adjacent insulating layers IL2 can be removed. Therefore, the height of adjacent insulating layers IL2 can decrease as adjacent insulating layers IL2 approach the pad unit PU2 and groove GV, thus the upper surface of adjacent insulating layers IL2 can have an upwardly convex shape.

[0192] The groove GV and the adjacent insulating layer IL2 may have a width based on a first direction (X-axis direction). In the thickness direction of the display device 200, the groove GV may have a depth, and the adjacent insulating layer IL2 may have a height.

[0193] According to some embodiments, during the exposure step, as the width of the adjacent insulating layer IL2 decreases, more of the area above the adjacent insulating layer IL2 can be removed. According to some embodiments, during the exposure step, as the gap between the mask patterns decreases, more of the area above the adjacent insulating layer IL2 can be removed.

[0194] As an example of the process, the width or depth of the groove GV can be proportional to the size of the area of ​​the adjacent insulating layer IL2 that is removed.

[0195] Depending on the height control of the adjacent insulating layer IL2 (e.g., height reduction), the size of the area where the adjacent insulating layer IL2 connects to (or contacts) the lead unit LU2 can be relatively reduced, or the adjacent insulating layer IL2 may not be connected to the lead unit LU2. According to some embodiments, the interference of the adjacent insulating layer IL2 on the connection between the pad unit PU2 and the lead unit LU2 can be relatively reduced. Therefore, pressure applied in the direction from the lead unit LU2 towards the pad unit PU2, or pressure applied in the opposite direction, can be effectively transmitted to the lead unit LU2 and the pad unit PU2, and the electrical connection or contact characteristics between the lead unit LU2 and the pad unit PU2 can be relatively improved.

[0196] According to some embodiments, the adjacent insulating layer IL2 disposed in the space between adjacent pad units PU2 and groove GV can be arranged to be spaced apart from the lead unit LU2. In this case, the pressure applied by the lead unit LU2 in the direction from the lead unit LU2 toward the pad unit PU2 may not be transmitted to the adjacent insulating layer IL2. Therefore, the pressure can be effectively applied to the pad unit PU2, thereby relatively improving the reliability of the electrical connection between the lead unit LU2 and the pad unit PU2.

[0197] According to some embodiments, Figure 9 and Figure 10 The structure can be applied in essentially the same way to these embodiments, or with some modifications within a similar scope.

[0198] Figure 17 and Figure 18 yes Figure 16 A magnified view of area A3 in the image. For example, Figure 18 It shows Figure 17 Example of modification.

[0199] The groove GV1 can be arranged in the region of the adjacent insulating layer IL2 located between two adjacent pad units PU2. For example, the groove GV1 can be formed by recessing the upper surface of the adjacent insulating layer IL2 located between two adjacent pad units PU2 or by removing a portion of the region of the adjacent insulating layer IL2 located between two adjacent pad units PU2 that is adjacent to the circuit member 201.

[0200] Reference Figure 17In some embodiments, the groove GV1 can be formed by recessing the upper surface of the adjacent insulating layer IL2 while forming a gentle curve towards the substrate SUB2, and can be formed, for example, by etching a portion of the adjacent insulating layer IL2. The bottom surface of the groove GV1 can be arranged to be spaced apart from the upper surface of the substrate SUB2. Therefore, the adjacent insulating layers IL2 disposed between two adjacent pad units PU2 can be not interrupted by the groove GV1. According to some embodiments, the groove GV1 can have an asymmetrical shape relative to the Z-axis direction and can be non-flat.

[0201] Reference Figure 18 In some embodiments, the groove GV2 may have a hole shape and, for example, may be formed by etching a region of the adjacent insulating layer IL2 that corresponds to the entire thickness in the thickness direction. According to some embodiments, the bottom of the groove GV2 may also correspond to the upper surface of the substrate SUB2. Therefore, the adjacent insulating layers IL2 disposed between two adjacent pad units PU2 can be disconnected by the groove GV2, and according to some embodiments, the intermediate insulating layer NCF2 can contact the substrate SUB2 through an opening.

[0202] The side surface of the groove GV2 may have an arcuate shape that protrudes toward the adjacent pad unit PU2, or it may have an arcuate shape that protrudes in the opposite direction. According to some embodiments, the groove GV2 may have an asymmetrical shape relative to the Z-axis direction, and it may be non-flat.

[0203] According to some embodiments, the display device 200 may optionally include Figure 17 The groove GV1 or Figure 18 The groove GV2, and according to some embodiments, may include... Figure 17 At least one groove GV1 and Figure 18 At least one groove GV2.

[0204] Reference Figures 16 to 18 The groove GV1 or GV2 can have a width based on a first direction (X-axis direction) and a depth based on a third direction (Z-axis direction). Multiple grooves GV1 or GV2 can have different widths and depths, or they can have the same width or depth as needed.

[0205] According to some embodiments, the display device 200 may include at least one recess GV between a plurality of pad units PU2. For example, adjacent insulating layers IL2 may be arranged between two adjacent pad units PU2 and may include a recess GV. The recess GV can relatively reduce the interference of adjacent insulating layers IL2 on the connection between pad units PU2 and lead units LU2, and pressure applied from lead units LU2 toward pad units PU2 or in the opposite direction can be effectively transmitted to lead units LU2 and pad units PU2. In other words, it relatively reduces or suppresses the decrease in connection reliability between lead units LU2 and pad units PU2 due to adjacent insulating layers IL2. As a result, the electrical connection or contact characteristics between pad units PU2 and circuit components 201 can be relatively improved, and the electrical characteristics and durability of the display device 200 can be enhanced.

[0206] Figure 19 This is a view of an electronic device used to explain the application of a display device according to some embodiments.

[0207] The display devices according to some embodiments included in this specification can be applied to various electronic devices. According to some embodiments, an electronic device may include at least one of the display devices according to the embodiments included in the specification, and optionally, in addition to the display devices, it may also include modules or devices with additional functions.

[0208] Reference Figure 19 According to some embodiments, the electronic device 1000 may include a display module 1100, a processor 1200, a memory 1300, and a power module 1400.

[0209] Processor 1200 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor, an image signal processor (ISP), and a controller. For example, processor 1200 may operate by executing at least one program.

[0210] The memory 1300 can store data necessary for the operation of the processor 1200 or the display module 1100. When the processor 1200 executes the application stored in the memory 1300, image data signals and / or input control signals can be transmitted to the display module 1100, and the display module 1100 can process the received signals and output image information through the display screen.

[0211] The power module 1400 may include a power module such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power module to generate the power required for the operation of the electronic device 1000.

[0212] At least one of the components of electronic device 1000 may be included in the display device according to the foregoing embodiments. Some of the various modules functionally included in electronic device 1000 may be included in the display device, while other modules may be disposed separately from the display device. For example, the display device may include display module 1100, and processor 1200, memory 1300, and power module 1400 may be disposed in other devices within electronic device 1000 besides the display device.

[0213] According to some embodiments, electronic device 1000 may be configured such that the display device according to the embodiments of the above description includes display module 1100.

[0214] Figure 20 It is used for explanation Figure 19 Views of various examples of electronic devices.

[0215] Reference Figure 20 Various electronic devices that utilize the display device according to the embodiments may include image display electronic devices (such as smartphones 1000.1a, tablet PCs 1000.1b, laptops 1000.1c, TVs 1000.1d, and desktop monitors 1000.1e), wearable electronic devices including display devices (such as smart glasses 1000.2a, head-mounted displays 1000.2b, and smartwatches 1000.2c), and vehicle electronic devices 1000.3 including display devices (such as central information displays (CIDs), central instrument panels and dashboards, and interior mirror displays arranged on the dashboard of a car).

[0216] The display device and electronic device according to some embodiments can achieve relatively improved electrical reliability.

[0217] Each of the above embodiments can be implemented independently, but it is evident that the structures of each embodiment can be combined and applied to other embodiments.

[0218] The disclosure has been described with reference to the embodiments shown in the accompanying drawings, but these are merely examples. It will be understood by those skilled in the art that various modifications and changes can be made therein. Therefore, the true scope of protection of the disclosure should be defined by the technical concept of the appended claims.

[0219] The specific implementations described in the embodiments are illustrative only and do not limit the scope of disclosure in any way. Furthermore, unless explicitly indicated by terms such as "essential" or "important," a component may not be necessary for the disclosed application.

[0220] In the description of the embodiments (especially in the claims), the term "described" and similar reference terms may refer to both the singular and the plural.

[0221] In the case of a range described in the embodiments, it includes inventions that apply the individual values ​​within that range (unless otherwise stated herein). This is the same as stating each individual value constituting the range above in the detailed description.

[0222] Finally, unless otherwise expressly stated herein or otherwise obviously contradicts the context, the steps of the method according to some embodiments may be performed in any suitable order. The embodiments are not necessarily limited to the order of the steps described above.

[0223] Any example or illustrative terms used in the disclosed embodiments are merely for the purpose of describing aspects of some embodiments in more detail, and the scope of the embodiments is not limited by the example or illustrative terms unless limited by the claims.

[0224] Furthermore, those skilled in the art will understand that various modifications, combinations, and alterations can be made based on the design conditions and factors within the scope of the appended claims or their equivalents.

Claims

1. A display device having a display area and a non-display area, the display device comprising: Multiple pad units are located in the non-display area; At least one dummy pattern unit is located between adjacent pad units among the plurality of pad units; as well as An adjacent insulating layer is arranged at least between the plurality of pad units and the at least one dummy pattern unit, and is arranged not to cover at least one region of the regions of the plurality of pad units.

2. The display device according to claim 1, further comprising: Circuit components are electrically connected to the plurality of pad units; as well as Multiple lead units are arranged on the circuit member, electrically connected to at least one area of ​​the multiple pad units that is not covered by the adjacent insulating layer, and spaced apart from the at least one dummy pattern unit.

3. The display device according to claim 2, wherein, The at least one dummy pattern unit is spatially overlapped with an adjacent lead unit among the plurality of lead units.

4. The display device according to claim 2, further comprising: An intermediate insulating layer is provided between the plurality of pad units and the circuit components.

5. The display device according to claim 2, wherein, The regions of each of the plurality of lead units and the corresponding pad unit are in contact with each other.

6. The display device according to claim 5, wherein, Each of the plurality of pad units includes at least one protrusion projecting toward the circuit member, and The area of ​​at least one protruding portion is in contact with the corresponding lead unit.

7. The display device according to claim 6, wherein, Each of the plurality of pad units includes: Substrate conductive layer; At least one conductive layer is electrically connected to the substrate conductive layer; and A raised pattern, corresponding to the at least one raised portion, is disposed between the substrate conductive layer and the at least one connecting conductive layer.

8. The display device according to claim 7, wherein, The raised pattern comprises organic materials.

9. The display device according to claim 1, wherein, The at least one dummy pattern unit includes: At least one dummy conductive layer; and A dummy insulating layer is provided to cover the at least one dummy conductive layer.

10. The display device according to claim 1, wherein, The at least one dummy pattern unit and the plurality of pad units have a height based on the thickness direction of the display device, and The height of the at least one dummy pattern unit is not greater than the height of each of the plurality of pad units.

11. The display device according to claim 1, wherein, The adjacent insulating layers and the plurality of pad units have a height based on the thickness direction of the display device, and The height of the adjacent insulating layer is not greater than the height of each of the plurality of pad units.

12. A display device having a display area and a non-display area, the display device comprising: Multiple pad units are located in the non-display area; Adjacent insulating layers, between adjacent pad units among the plurality of pad units; as well as At least one groove is located in the adjacent insulating layer and is spaced apart from the plurality of pad units.

13. The display device according to claim 12, further comprising: Circuit components are electrically connected to the plurality of pad units; as well as Multiple lead units are arranged on the circuit component, electrically connected to the multiple pad units, and spaced apart from the at least one groove.

14. The display device according to claim 13, wherein, The at least one groove is spatially overlapped with the adjacent lead unit among the plurality of lead units.

15. The display device according to claim 13, further comprising: An intermediate insulating layer is provided between the plurality of pad units and the circuit components.

16. The display device according to claim 13, wherein, Each of the plurality of lead units and its corresponding pad unit is arranged in a region that is in contact with each other.

17. The display device according to claim 16, wherein, Each of the plurality of pad units includes at least one protrusion projecting toward the circuit member, and The area of ​​at least one protruding portion is in contact with the corresponding lead unit.

18. The display device according to claim 17, wherein, Each of the plurality of pad units includes a raised pattern containing organic material corresponding to the at least one raised portion.

19. The display device according to claim 12, wherein, The adjacent insulating layers and the plurality of pad units have a height based on the thickness direction of the display device, and The height of the adjacent insulating layer is not greater than the height of each of the plurality of pad units.

20. An electronic device including a display device, wherein a processor is configured to execute at least one application and implement at least one image. in, The display device has a display area and a non-display area. The display device includes: Multiple pad units are located in the non-display area; At least one dummy pattern unit is located between adjacent pad units among the plurality of pad units; and Adjacent insulating layers are arranged at least between the plurality of pad units and the at least one dummy pattern unit, and are arranged to not cover at least one region of the regions of the plurality of pad units.

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