Display device

Abstract

The application provides a display device, and the pixel of the display device comprises at least a first thin film transistor and a second thin film transistor. The second thin film transistor is located above the level of the first thin film transistor. The second thin film transistor comprises a first electrode, a first insulating layer, a second electrode, a second semiconductor layer, a second gate insulating layer and a second gate. The first insulating layer is located on the first electrode and has an opening penetrating through the first insulating layer. The second electrode is located on the first insulating layer around the opening. A first part of the second semiconductor layer is located in the opening and is electrically connected with the first electrode. A second part of the second semiconductor layer is located on the sidewall of the opening. A third part of the second semiconductor layer is located on the second electrode and is electrically connected with the second electrode. The second gate insulating layer covers the second semiconductor layer. The second gate is located on the part of the second gate insulating layer which is located on the sidewall of the opening. The technical scheme of the application is beneficial to improving the pixel density of the display panel.

Description

Technical Field

[0001] This application relates to the field of display technology, and more specifically to a display device. Background Technology

[0002] Organic light-emitting diode (OLED) display panels include light-emitting devices and pixel driving circuits for driving the light-emitting devices. The pixel driving circuits include multiple thin film transistors (TFTs).

[0003] In traditional OLED display panels, the main types of thin-film transistors include low-temperature polycrystalline silicon (LTPS) thin-film transistors and metal-oxide-semiconductor (MODS) thin-film transistors.

[0004] In traditional OLED display panels, the semiconductor layer of thin-film transistors (TFTs) is typically arranged parallel to the display panel, which occupies a significant amount of space. When pixel density (Pixels Per Inch, PPI) needs to be further increased, the space available for TFTs within the pixel area of ​​the OLED display panel becomes limited. Traditional TFT arrangement methods struggle to achieve the required number and functionality of TFTs within a limited pixel area, thus restricting the improvement of pixel density.

[0005] Therefore, it is necessary to propose a new technical solution to solve the above-mentioned technical problems. Summary of the Invention

[0006] The purpose of this application is to provide a display device that addresses the technical problem that traditional display devices struggle to further increase pixel density.

[0007] This application provides a display device, the display device including a display panel, the display panel including a plurality of pixels, each pixel including a light-emitting device and a pixel driving circuit, the pixel driving circuit including at least a first thin-film transistor and a second thin-film transistor; the first thin-film transistor including a first semiconductor layer, a first gate and a first source / drain; the second thin-film transistor disposed above the layer containing the first thin-film transistor, the second thin-film transistor including: a first electrode; a first insulating layer, the first insulating layer being located on the first electrode and having an opening penetrating the first insulating layer; a second electrode, the second electrode being located on the surface of the first insulating layer surrounding the opening; a second semiconductor layer, a first portion of the second semiconductor layer being located within the opening and electrically connected to the first electrode, a second portion of the second semiconductor layer being located on the sidewall of the opening, and a third portion of the second semiconductor layer being located on the surface of the second electrode and electrically connected to the second electrode; a second gate insulating layer, the second gate insulating layer covering the second semiconductor layer; and a second gate, the second gate being located on the portion of the second gate insulating layer disposed on the sidewall of the opening.

[0008] In the above-described display device, the material of the first semiconductor layer includes low-temperature polycrystalline silicon, and the material of the second semiconductor layer includes metal oxide.

[0009] In the above-described display device, the second gate insulating layer and the second gate cover the second semiconductor layer along the surface of the second semiconductor layer.

[0010] In the above-described display device, the first thin-film transistor further includes a first intermediate metal layer, which is located between the layer where the first source and drain electrodes are located and the layer where the first electrode is located, and is electrically connected to the first semiconductor layer.

[0011] In the above-described display device, the display panel further includes a capacitor, the first plate of the capacitor includes the first intermediate metal layer, the second plate of the capacitor includes the first electrode, and from a top view of the display panel, the first intermediate metal layer and the first electrode at least partially overlap.

[0012] In the above-described display device, the second semiconductor layer includes a first sub-semiconductor layer and a second sub-semiconductor layer; the opening includes a first opening and a second opening; the second thin-film transistor includes a first portion of the first electrode, the first sub-semiconductor layer, a second gate insulating layer, a first portion of the second gate, and a first portion of the second electrode; the pixel driving circuit further includes a third thin-film transistor, which includes a second portion of the first electrode, a second sub-semiconductor layer, a second gate insulating layer, a second portion of the second gate, and a second portion of the second electrode; the first portion of the first sub-semiconductor layer is located within the first opening and electrically connected to the first portion of the first electrode; the second portion of the first sub-semiconductor layer is located on the sidewall of the first opening; the third portion of the first sub-semiconductor layer is located on the surface of the first portion of the second electrode and electrically connected to the first portion of the second electrode; the first portion of the second sub-semiconductor layer is located within the second opening and electrically connected to the second portion of the first electrode; the second portion of the second sub-semiconductor layer is located on the sidewall of the second opening; the third portion of the second sub-semiconductor layer is located on the surface of the second portion of the second electrode and electrically connected to the second portion of the second electrode; the first portion of the second gate is located on the portion of the second gate insulating layer disposed on the sidewall of the first opening; the second portion of the second gate is located on the portion of the second gate insulating layer disposed on the sidewall of the second opening.

[0013] In the above-described display device, the display panel further includes a first intermediate metal layer, which is located between the layer containing the first source / drain electrode and the layer containing the first electrode. The first intermediate metal layer is electrically connected to the first semiconductor layer. A first portion of the second gate is electrically connected to the first intermediate metal layer through a through-hole penetrating the first insulating layer and the second gate insulating layer. A first portion of the first electrode is electrically connected to a second portion of the second electrode through a through-hole penetrating the first insulating layer. The second portion of the second electrode is electrically connected to the anode of the light-emitting device.

[0014] In the above-described display device, from a top-view perspective of the display panel, the length direction of the first portion of the first semiconductor layer is parallel to the first direction, the length direction of the second portion of the first semiconductor layer is parallel to the second direction, the first direction is perpendicular to the second direction, the first portion of the first semiconductor layer is connected to the second portion of the first semiconductor layer, and the length of the first portion of the first semiconductor layer is greater than the length of the second portion of the first semiconductor layer.

[0015] In the above-described display device, from a top-view perspective of the display panel, at least a portion of the second opening overlaps with a first portion of the first semiconductor layer, and at least a portion of the second portion of the first electrode overlaps with a first portion of the first semiconductor layer.

[0016] In the above-described display device, in the first direction, the width of the gap between the first portion of the second electrode and the second portion of the second electrode is greater than the size of the first portion of the second electrode in the first direction.

[0017] In the above-described display device, the length direction of the first gate is parallel to the second direction, and from a top-view perspective of the display panel, the first gate overlaps with a first portion of the first semiconductor layer.

[0018] In the above-described display device, the length direction of the second portion of the second gate is parallel to the second direction. From a top-view perspective of the display panel, the second portion of the second gate overlaps with the first gate and the second portion of the second gate overlaps with the first portion of the first semiconductor layer.

[0019] In the above-described display device, in the first direction, the width of the second portion of the second gate is smaller than the width of the first gate, and the width of the first gate is smaller than the width of the second portion of the second electrode.

[0020] In the above-described display device, in a first direction, the size of the second opening in the first direction is smaller than the width of the second portion of the second gate, the second opening does not extend beyond the two edges of the second portion of the second gate in the first direction, and the second portion of the first electrode covers the second opening.

[0021] This application also provides a display device, the display device including a display panel, the display panel including a plurality of pixels, each pixel including a light-emitting device and a pixel driving circuit, the pixel driving circuit including a first thin-film transistor and a second thin-film transistor, the first thin-film transistor and the second thin-film transistor being both vertical thin-film transistors; the display panel including: a first electrode; a first insulating layer, the first insulating layer being located on the first electrode and having a first opening and a second opening penetrating the first insulating layer, the first opening exposing a first portion of the first electrode, the second opening exposing a second portion of the first electrode; a second electrode, the first portion of the second electrode being located on the surface of the first insulating layer surrounding the first opening, the second portion of the second electrode being located on the surface of the first insulating layer surrounding the second opening; a semiconductor layer, the semiconductor layer including a first sub-semiconductor layer and a second sub-semiconductor layer, the first portion of the first sub-semiconductor layer being located within the first opening and electrically connected to the first portion of the first electrode, the second portion of the first sub-semiconductor layer being located on the sidewall of the first opening, the third portion of the first sub-semiconductor layer being... The first portion of the second electrode is located on the surface of the first portion of the second electrode and electrically connected to the first portion of the second electrode; the first portion of the second sub-semiconductor layer is located within the second opening and electrically connected to the second portion of the first electrode; the second portion of the second sub-semiconductor layer is located on the sidewall of the second opening; the third portion of the second sub-semiconductor layer is located on the surface of the second portion of the second electrode and electrically connected to the second portion of the second electrode; a first gate insulating layer covers the semiconductor layer; and a first gate is located on the first gate insulating layer, with a first portion of the first gate located on the portion of the first gate insulating layer disposed on the sidewall of the first opening, and a second portion of the first gate located on the portion of the first gate insulating layer disposed on the sidewall of the second opening; the first thin-film transistor includes the first portion of the first electrode, the first sub-semiconductor layer, the first portion of the second electrode, and the first portion of the first gate; the second thin-film transistor includes the second portion of the first electrode, the second sub-semiconductor layer, the second portion of the second electrode, and the second portion of the first gate.

[0022] In the above-described display device, the material of the semiconductor layer includes metal oxides.

[0023] In the above-described display device, from a top-view perspective of the display panel, the first gate insulating layer and the first gate cover the semiconductor layer along the surface of the semiconductor layer.

[0024] In the above-described display device, the display panel further includes a second insulating layer and a second gate. The second insulating layer is located on the first gate, and the second gate is located on the second insulating layer. From a top-view perspective of the display panel, a first portion of the second gate overlaps with a first portion of the first gate. A second portion of the first gate is electrically connected to a first portion of the second electrode through a through-hole penetrating the first gate insulating layer. A second portion of the second gate is electrically connected to a second portion of the second electrode through a through-hole penetrating both the second insulating layer and the first gate insulating layer.

[0025] In the above-described display device, in the first direction, the width of the gap between the first part of the first electrode and the second part of the first electrode is greater than the size of the first part of the first electrode in the first direction, and the width of the gap between the first part of the first electrode and the second part of the first electrode is smaller than the size of the second part of the first electrode in the first direction.

[0026] In the above-described display device, the area of ​​the first opening is larger than the area of ​​the second opening.

[0027] In the above-described display device, from a top-view perspective of the display panel, a first portion of the first gate at least partially overlaps with a first portion of the first electrode, and a first portion of the first gate at least partially overlaps with a second portion of the first electrode.

[0028] In the above-described display device, in a first direction, the size of the first portion of the first gate in the first direction is greater than the size of the first portion of the first electrode in the first direction, the size of the first portion of the first gate in the first direction is greater than the size of the second portion of the first gate in the first direction, the size of the first portion of the first gate in the first direction is greater than the size of the first portion of the second electrode in the first direction, and the size of the first portion of the first gate in the first direction is greater than the size of the second portion of the second electrode in the first direction.

[0029] In the above-described display device, in a first direction, the size of the second portion of the first electrode in the first direction is greater than the size of the first portion of the first electrode in the first direction, the size of the second portion of the first electrode in the first direction is greater than the size of the second portion of the first gate in the first direction, the size of the second portion of the first electrode in the first direction is greater than the size of the first portion of the second electrode in the first direction, and the size of the second portion of the first electrode in the first direction is greater than the size of the second portion of the second electrode in the first direction.

[0030] In the above-described display device, in a first direction, the width of the first portion of the first electrode is greater than the size of the first opening in the first direction, and the width of the second portion of the first gate is greater than the size of the second opening in the first direction.

[0031] In the above-described display device, the display panel further includes a bottom metal layer, which is located below the layer where the first electrode is located; from a top-view perspective, a first portion of the first gate at least partially overlaps with the bottom metal layer, a second portion of the first electrode at least partially overlaps with the bottom metal layer, and a second portion of the first gate at least partially overlaps with the bottom metal layer.

[0032] The present application provides a display device including a display panel with multiple pixels. Each pixel includes a light-emitting device and a pixel driving circuit. The pixel driving circuit includes at least a first thin-film transistor (TFT) and a second TFT. The first TFT includes a first semiconductor layer, a first gate, and a first source / drain electrode. The second TFT is disposed above the layer containing the first TFT. The second TFT includes a first electrode, a first insulating layer, a second electrode, a second semiconductor layer, a second gate insulating layer, and a second gate. The first insulating layer is located on the first electrode and has an opening penetrating the first insulating layer. The second electrode is located on the surface of the first insulating layer surrounding the opening. A first portion of the second semiconductor layer is located within the opening and electrically connected to the first electrode. A second portion of the second semiconductor layer is located on the sidewall of the opening. A third portion of the second semiconductor layer is located on the surface of the second electrode and electrically connected to the second electrode. The second gate insulating layer covers the second semiconductor layer, and the second gate is located on the portion of the second gate insulating layer disposed on the sidewall of the opening. Because the second thin-film transistor is disposed above the layer containing the first thin-film transistor, the first and second thin-film transistors are stacked in a direction perpendicular to the display panel, rather than arranged side-by-side in a direction parallel to the display panel. This reduces the area occupied by the pixel driving circuit in the direction parallel to the display panel. Simultaneously, since the second portion of the second semiconductor layer is located on the sidewall of the opening, and the second gate is located on the portion of the second gate insulating layer disposed on the sidewall of the opening, the channel of the second thin-film transistor extends along the sidewall of the opening, forming a vertical thin-film transistor. Compared to conventional planar thin-film transistors, this vertical thin-film transistor occupies a smaller area in the direction parallel to the display panel. Therefore, the technical solution of this application can arrange more thin-film transistors within a limited pixel area, thereby improving the pixel density of the display panel.

[0033] The technical solution of this application also provides another display device, the pixel driving circuit of which includes a first thin-film transistor and a second thin-film transistor, both of which are vertical thin-film transistors. The display panel includes a first electrode, a first insulating layer, a second electrode, a semiconductor layer, a first gate insulating layer, and a first gate. The first insulating layer is located on the first electrode and has a first opening and a second opening penetrating the first insulating layer. The first opening exposes a first portion of the first electrode, and the second opening exposes a second portion of the first electrode. The first portion of the second electrode is located on the surface of the first insulating layer surrounding the first opening, and the second portion of the second electrode is located on the surface of the first insulating layer surrounding the second opening. The semiconductor layer includes a first sub-semiconductor layer and a second sub-semiconductor layer. The first portion of the first sub-semiconductor layer is located within the first opening and electrically connected to the first portion of the first electrode. The second portion of the first sub-semiconductor layer is located on the sidewall of the first opening, and a third portion of the first sub-semiconductor layer is located on the surface of the first portion of the second electrode and electrically connected to the first portion of the second electrode. The first portion of the second sub-semiconductor layer is located within the second opening and electrically connected to the second portion of the first electrode. The second portion of the second sub-semiconductor layer is located on the sidewall of the second opening, and the third portion of the second sub-semiconductor layer is located on the surface of the second portion of the second electrode and electrically connected to the second portion of the second electrode. A first gate insulating layer covers the semiconductor layer. A first portion of the first gate is located on the portion of the first gate insulating layer disposed on the sidewall of the first opening, and a second portion of the first gate is located on the portion of the first gate insulating layer disposed on the sidewall of the second opening. The first thin-film transistor includes a first portion of a first electrode, a first sub-semiconductor layer, a first portion of a second electrode, and a first portion of the first gate. The second thin-film transistor includes a second portion of a first electrode, a second sub-semiconductor layer, a second portion of a second electrode, and a second portion of the first gate. Since both the first and second thin-film transistors are vertical thin-film transistors, the channel portions of the semiconductor layer extend along the sidewall of the opening. Compared to conventional planar thin-film transistors, these vertical thin-film transistors occupy a smaller area in the direction parallel to the display panel. Therefore, more thin-film transistors can be arranged within a limited pixel area, thereby improving the pixel density of the display panel. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of a display device provided in an embodiment of this application.

[0035] Figure 2 A circuit diagram of the pixels of a display device provided for an embodiment of this application.

[0036] Figure 3 A schematic cross-sectional view of a first embodiment of the display panel of the display device provided in this application.

[0037] Figure 4 for Figure 3 The diagram shows a planar layout of the display panel.

[0038] Figure 5 A schematic cross-sectional view of a second embodiment of the display panel of the display device provided in this application.

[0039] Figure 6 for Figure 5 The diagram shows a planar layout of the display panel. Detailed Implementation

[0040] The specific embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0041] The terms “first,” “second,” and similar words do not indicate any order, quantity, or importance, but are merely used to distinguish different technical features. The terms “multiple,” and similar words mean two or more, unless otherwise expressly specified.

[0042] The technical solutions of different embodiments of this application can be combined with each other.

[0043] The display devices provided in the embodiments of this application may be, for example, organic light-emitting diode (OLED) display devices, mini light-emitting diode (Mini-LED) display devices, or micro light-emitting diode (Micro-LED) display devices. The embodiments of this application are described using organic light-emitting diode display devices as an example.

[0044] Embodiments of this application provide a display device, such as... Figure 1 As shown, the display device includes a display panel (organic light-emitting diode display panel) DP, a timing controller TCON, and a source driver chip SDIC. The display panel DP includes a gate driver circuit GOA, multiple gate lines GL1 / GL2, multiple light-emitting control signal lines EM, multiple data lines DL, a first power line VDD, a second power line VSS, and multiple pixels PX. The timing controller TCON provides image data signals and control signals to the source driver chip SDIC, which outputs data voltages to the data lines DL based on the received signals. The gate driver circuit GOA sequentially outputs scan signals to the gate lines GL1 / GL2. The gate lines GL1 / GL2 and the data lines DL are electrically connected to the pixels PX. The first power line VDD and the second power line VSS provide driving voltages to the pixels PX respectively. Each pixel PX includes a light-emitting device and a pixel driver circuit, which includes multiple thin-film transistors.

[0045] The multiple thin-film transistors include multiple metal-oxide-semiconductor (MODS) thin-film transistors, or multiple thin-film transistors include multiple low-temperature polycrystalline silicon (LTPS) thin-film transistors and multiple MODS thin-film transistors. In embodiments of this application, at least some MODS thin-film transistors are vertical MODS thin-film transistors. Vertical MODS thin-film transistors achieve a vertical arrangement by forming openings in an insulating layer and placing different portions of the semiconductor layer within the openings, on the sidewalls of the openings, and on the surface of the insulating layer surrounding the openings. By placing different portions of the semiconductor layer of the thin-film transistor within the openings penetrating the insulating layer, on the sidewalls of the openings, and on the surface of the electrodes, the semiconductor layer exhibits a vertical arrangement. In this vertical arrangement, the gate insulating layer and the gate cover the surface of the semiconductor layer, thereby forming a channel portion at the sidewall position of the opening. The plane containing this channel portion forms an angle with the plane containing the display panel DP, thereby reducing the space occupied by the thin-film transistors in the direction parallel to the surface of the display panel DP. Because the planar space occupied by thin-film transistors in the pixel area is reduced, the area occupied by the pixel driving circuit is correspondingly reduced, thus allowing more pixels (PX) to be arranged in a unit area. This enables higher pixel density to be achieved in the same area of ​​the display panel (DP), solving the technical problem that traditional display devices are limited by the planar arrangement space of thin-film transistors in improving pixel density.

[0046] Example 1 The display device provided in Embodiment 1 of this application includes a display panel DP, which includes a plurality of pixels PX. Each pixel PX includes a light-emitting device and a pixel driving circuit. The pixel driving circuit includes at least a first thin-film transistor T1 and a second thin-film transistor T2. The first thin-film transistor T1 includes a first semiconductor layer Poly, a first gate GE1, and a first source-drain electrode SD1. The second thin-film transistor T2 is disposed above the layer on which the first thin-film transistor T1 is located.

[0047] like Figure 3As shown, the display panel DP includes a substrate Glass, a buffer layer disposed on the substrate Glass, a first semiconductor layer Poly disposed on the buffer layer Buffer, a first gate insulating layer GI1 disposed on the first semiconductor layer Poly, a first gate GE1 disposed on the first gate insulating layer GI1, a second gate insulating layer GI2 disposed on the buffer layer Buffer, the first semiconductor layer Poly, the first gate insulating layer GI1 and the first gate GE1, a third gate GE2 disposed on the second gate insulating layer GI2, a first interlayer insulating layer ILD1 disposed on the second gate insulating layer GI2 and the third gate GE2, a first source drain SD1 disposed on the first interlayer insulating layer ILD1, a second interlayer insulating layer ILD2 disposed on the first interlayer insulating layer ILD1 and the first source drain SD1, a first intermediate metal layer BSM disposed on the second interlayer insulating layer ILD2, and a first intermediate metal layer BSM disposed on the second interlayer insulating layer ILD2 and the first source drain SD1. The system comprises: a third interlayer insulating layer ILD3 on the intermediate metal layer BSM; a first electrode SD2 disposed on the third interlayer insulating layer ILD3; a first insulating layer ILD4 disposed on the third interlayer insulating layer ILD3 and the first electrode SD2; a second electrode SD3 disposed on the surface of the first insulating layer ILD4; a second semiconductor layer IGZO disposed on the first insulating layer ILD4, the first electrode SD2, and the second electrode SD3; a second gate insulating layer GI3 disposed on the first insulating layer ILD4, the first electrode SD2, the second electrode SD3, and the second semiconductor layer IGZO; a second gate GE3 disposed on the second gate insulating layer GI3; a first passivation layer PV1 disposed on the second gate insulating layer GI3 and the second gate GE3; a first planarization layer PLN1 disposed on the first passivation layer PV1; an anode layer Anode disposed on the first planarization layer PLN1; and a pixel definition layer PDL disposed on the first planarization layer PLN1 and the anode layer Anode.

[0048] The substrate (Glass) is a glass substrate. The buffer layer is made of materials including silicon oxide, silicon nitride, or silicon oxynitride.

[0049] The first semiconductor layer, Poly, is made of low-temperature polycrystalline silicon. The first semiconductor layer Poly includes the active region, source region, and drain region of a low-temperature polycrystalline silicon thin-film transistor. Viewed from above the display panel DP, the first semiconductor layer Poly appears L-shaped.

[0050] A first gate insulating layer GI1 is located on the first semiconductor layer Poly, and the first gate insulating layer GI1 is used to isolate the first semiconductor layer Poly from the first gate GE1. The material of the first gate insulating layer GI1 includes silicon oxide, silicon nitride, or silicon oxynitride. The first gate GE1 is located on the first gate insulating layer GI1, and the first gate GE1 constitutes the gate of the low-temperature polycrystalline silicon thin-film transistor and the gate lines GL1 / GL2. The material of the first gate GE1 includes molybdenum, aluminum, copper, titanium, or alloys of the above materials.

[0051] The second gate insulating layer GI2 is located above the first gate GE1 and is used to isolate different metal layers. The material of the second gate insulating layer GI2 includes silicon oxide, silicon nitride, or silicon oxynitride. The display panel DP also includes a third gate GE2, the film layer containing the third gate GE2 is located between the film layer containing the first gate GE1 and the film layer containing the first source / drain SD1, and the third gate GE2 is located on the second gate insulating layer GI2. The first thin-film transistor T1 also includes a third gate GE2. The material of the third gate GE2 includes molybdenum, aluminum, copper, titanium, or an alloy of the above materials.

[0052] The first interlayer insulating layer ILD1 is located on the second gate insulating layer GI2 and the third gate GE2, and is used to isolate the gate metal layer from the source / drain metal layer. The material of the first interlayer insulating layer ILD1 includes silicon oxide, silicon nitride, or silicon oxynitride. The first source / drain electrode SD1 is located on the first interlayer insulating layer ILD1, and the layer containing the first source / drain electrode SD1 is located above the layer containing the first gate GE1. The first source / drain electrode SD1 is electrically connected to the first semiconductor layer Poly through a via penetrating the first interlayer insulating layer ILD1 and the second gate insulating layer GI2. The first source / drain electrode SD1 constitutes the source or drain of a low-temperature polycrystalline silicon thin-film transistor. The material of the first source / drain electrode SD1 includes molybdenum, aluminum, copper, titanium, or alloys of the above materials.

[0053] The second interlayer insulating layer ILD2 is located on the first interlayer insulating layer ILD1 and the first source / drain electrode SD1. The material of the second interlayer insulating layer ILD2 includes silicon oxide, silicon nitride, or silicon oxynitride. The first intermediate metal layer BSM is located on the second interlayer insulating layer ILD2. The layer containing the first intermediate metal layer BSM is located between the layer containing the first source / drain electrode SD1 and the layer containing the first electrode SD2. The first intermediate metal layer BSM is electrically connected to the first semiconductor layer Poly through a via penetrating the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1, and the second gate insulating layer GI2. The first intermediate metal layer BSM constitutes the drain or source of a low-temperature polycrystalline silicon thin-film transistor and also constitutes the electrode of a capacitor Cst. The material of the first intermediate metal layer BSM includes molybdenum, aluminum, copper, titanium, or alloys of the above materials.

[0054] The third interlayer insulating layer (ILD3) is located on the second interlayer insulating layer (ILD2) and the first intermediate metal layer (BSM). The material of the third interlayer insulating layer (ILD3) includes silicon oxide, silicon nitride, or silicon oxynitride. The first electrode (SD2) is located on the third interlayer insulating layer (ILD3), and the layer containing the first electrode (SD2) is located above the layer containing the first source / drain electrode (SD1). The first electrode (SD2) includes a first portion (SD2-1) and a second portion (SD2-2). From a top view of the display panel (DP), the first portion (SD2-1) of the first electrode (SD2) at least partially overlaps with the first intermediate metal layer (BSM). The display panel (DP) also includes a capacitor (Cst). The first electrode of the capacitor (Cst) includes the first intermediate metal layer (BSM), and the second electrode of the capacitor (Cst) includes the first portion (SD2-1) of the first electrode (SD2). The first electrode (SD2) constitutes the source or drain of a vertical metal-oxide-semiconductor thin-film transistor. The material of the first electrode (SD2) includes molybdenum, aluminum, copper, titanium, or alloys of the above materials.

[0055] A first insulating layer ILD4 is located on the third interlayer insulating layer ILD3 and the first electrode SD2. The first insulating layer ILD4 has an opening penetrating the first insulating layer ILD4. The opening includes a first opening and a second opening. The first opening exposes a first portion SD2-1 of the first electrode SD2, and the second opening exposes a second portion SD2-2 of the first electrode SD2. The material of the first insulating layer ILD4 includes silicon oxide, silicon nitride, or silicon oxynitride.

[0056] like Figure 3 As shown, the second electrode SD3 is located on the surface of the first insulating layer ILD4 surrounding the opening. The second electrode SD3 includes a first portion SD3-1 and a second portion SD3-2. The first portion SD3-1 of the second electrode SD3 is located on the surface of the first insulating layer ILD4 surrounding the first opening, and does not extend to the sidewall of the first opening. The second portion SD3-2 of the second electrode SD3 is located on the surface of the first insulating layer ILD4 surrounding the second opening, and does not extend to the sidewall of the second opening. The second electrode SD3 constitutes the drain or source of a vertical metal-oxide-semiconductor thin-film transistor. The material of the second electrode SD3 includes molybdenum, aluminum, copper, titanium, or alloys of the above materials.

[0057] The material of the second semiconductor layer IGZO includes metal oxide. A first portion of the second semiconductor layer IGZO is located within the opening and electrically connected to the first electrode SD2. A second portion of the second semiconductor layer IGZO is located on the sidewall of the opening. A third portion of the second semiconductor layer IGZO is located on the surface of the second electrode SD3 and electrically connected to the second electrode SD3. The material of the second semiconductor layer IGZO includes indium gallium zinc oxide.

[0058] The pixel driving circuit also includes a third thin-film transistor T3. The second semiconductor layer IGZO includes a first sub-semiconductor layer IGZO1 and a second sub-semiconductor layer IGZO2. The opening includes a first opening and a second opening. (As shown...) Figure 3 As shown, the first portion of the first sub-semiconductor layer IGZO1 is located within the first opening and electrically connected to the first portion SD2-1 of the first electrode SD2. The second portion of the first sub-semiconductor layer IGZO1 is located on the sidewall of the first opening. The third portion of the first sub-semiconductor layer IGZO1 is located on the surface of the first portion SD3-1 of the second electrode SD3 and electrically connected to the first portion SD3-1 of the second electrode SD3. The cross-section of the first sub-semiconductor layer IGZO1 is U-shaped. The bottom of the first sub-semiconductor layer IGZO1 is located within the first opening, the two sides of the first sub-semiconductor layer IGZO1 are located on the two opposite sidewalls of the first opening, and the top of the first sub-semiconductor layer IGZO1 is located on the surface of the first portion SD3-1 of the second electrode SD3.

[0059] like Figure 3 As shown, the first portion of the second sub-semiconductor layer IGZO2 is located within the second opening and electrically connected to the second portion SD2-2 of the first electrode SD2. The second portion of the second sub-semiconductor layer IGZO2 is located on the sidewall of the second opening. The third portion of the second sub-semiconductor layer IGZO2 is located on the surface of the second portion SD3-2 of the second electrode SD3 and electrically connected to the second portion SD3-2 of the second electrode SD3. The cross-section of the second sub-semiconductor layer IGZO2 is U-shaped. The bottom of the second sub-semiconductor layer IGZO2 is located within the second opening, the two sides of the second sub-semiconductor layer IGZO2 are located on the two opposite sidewalls of the second opening, and the top of the second sub-semiconductor layer IGZO2 is located on the surface of the second portion SD3-2 of the second electrode SD3.

[0060] like Figure 3 As shown, a second gate insulating layer GI3 covers a first insulating layer ILD4, the portion of the first electrode SD2 exposed within the opening, a second electrode SD3, and a second semiconductor layer IGZO. The second gate insulating layer GI3 and the second gate GE3 cover the second semiconductor layer IGZO along its surface. The second gate insulating layer GI3 extends along the surface of the second semiconductor layer IGZO, covering the portion of the first sub-semiconductor layer IGZO1 located on the sidewall of the first opening and the portion of the second sub-semiconductor layer IGZO2 located on the sidewall of the second opening. The second gate insulating layer GI3 is conformally bonded to the second semiconductor layer IGZO. The material of the second gate insulating layer GI3 includes silicon oxide, silicon nitride, or silicon oxynitride.

[0061] like Figure 3As shown, the second gate GE3 is located on the second gate insulating layer GI3, specifically on the portion of the second gate insulating layer GI3 disposed on the sidewall of the opening. The second gate GE3 includes a first portion GE3-1 and a second portion GE3-2. The first portion GE3-1 of the second gate GE3 is located on the portion of the second gate insulating layer GI3 disposed on the sidewall of the first opening, and in a top-viewing perspective of the display panel DP, the first portion GE3-1 overlaps with the first sub-semiconductor layer IGZO1. The second portion GE3-2 of the second gate GE3 is located on the portion of the second gate insulating layer GI3 disposed on the sidewall of the second opening, and in a top-viewing perspective of the display panel DP, the second portion GE3-2 overlaps with the second sub-semiconductor layer IGZO2. The second gate GE3 extends along the surface of the second gate insulating layer GI3 and is conformally fitted to the second gate insulating layer GI3. The material of the second gate GE3 includes molybdenum, aluminum, copper, titanium, or alloys of the above materials.

[0062] like Figure 3 As shown, the second gate insulating layer GI3 and the second gate GE3 cover the groove of the second semiconductor layer IGZO. The first sub-semiconductor layer IGZO1 and the second sub-semiconductor layer IGZO2 form channel portions at the sidewall positions of the first opening and the second opening, respectively. The plane containing the channel portion forms an angle with the plane containing the display panel DP, and this angle is in the range of 5 degrees to 85 degrees. For example, the angle is 5 degrees, 10 degrees, 15 degrees, 20 degrees, 25 degrees, 30 degrees, 35 degrees, 40 degrees, 45 degrees, 50 degrees, 55 degrees, 60 degrees, 65 degrees, 70 degrees, 75 degrees, 80 degrees, and 85 degrees.

[0063] like Figure 3 As shown, the first portion GE3-1 of the second gate GE3 is electrically connected to the first intermediate metal layer BSM through a via penetrating the second gate insulating layer GI3, the third interlayer insulating layer ILD3, and the first insulating layer ILD4. The first portion SD2-1 of the first electrode SD2 is electrically connected to the second portion SD3-2 of the second electrode SD3 through a via penetrating the second gate insulating layer GI3 and the first insulating layer ILD4. The second portion SD3-2 of the second electrode SD3 is electrically connected to the anode of the light-emitting device OLED through a via penetrating the second gate insulating layer GI3, the first passivation layer PV1, and the first planarization layer PLN1.

[0064] A first passivation layer PV1 is located on the second gate insulating layer GI3 and the second gate GE3. The material of the first passivation layer PV1 includes silicon oxide, silicon nitride, or silicon oxynitride. A first planarization layer PLN1 is located on the first passivation layer PV1, and the first planarization layer PLN1 is used to provide a flat surface. The material of the first planarization layer PLN1 includes an organic material, including polyimide or acrylic resin.

[0065] like Figure 3 As shown, the anode layer is located on the first planarization layer PLN1, and is electrically connected to the second portion SD3-2 of the second electrode SD3 through a via penetrating the first planarization layer PLN1 and the first passivation layer PV1. The anode layer comprises the anode of the light-emitting device OLED. The material of the anode layer comprises indium tin oxide.

[0066] The pixel definition layer (PDL) is located on the first planarization layer (PLN1) and the anode layer (Anode). The PDL has an opening that exposes the anode layer (Anode), and it is used to define the light-emitting area. The PDL is made of organic materials, including polyimide or acrylic resin.

[0067] In embodiments of this application, the display panel DP further includes a light-emitting functional layer, a cathode layer, and an encapsulation layer. The light-emitting functional layer is located within the opening of the pixel definition layer (PDL) and contacts the anode layer. The light-emitting functional layer includes a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer. The cathode layer is located on the light-emitting functional layer, and the cathode layer is made of a magnesium-silver alloy or aluminum. The encapsulation layer covers the cathode layer.

[0068] like Figure 2 and Figure 3 As shown, the display panel DP provided in Embodiment 1 of this application includes a first thin-film transistor T1, a second thin-film transistor T2, and a third thin-film transistor T3.

[0069] The first thin-film transistor T1 is a top-gate type low-temperature polycrystalline silicon thin-film transistor. The first thin-film transistor T1 includes a first semiconductor layer Poly, a first gate GE1, a third gate GE2, a first source / drain SD1, and a first intermediate metal layer BSM. The first semiconductor layer Poly constitutes the active layer of the first thin-film transistor T1, the first gate GE1 and the third gate GE2 constitute the gate of the first thin-film transistor T1, the first source / drain SD1 constitutes the source of the first thin-film transistor T1, and the first intermediate metal layer BSM constitutes the drain of the first thin-film transistor T1. In a top-gate type low-temperature polycrystalline silicon thin-film transistor, the gate is located above the active layer.

[0070] like Figure 3As shown, the second thin-film transistor T2 is a vertical metal-oxide-semiconductor thin-film transistor, and it is disposed above the layer containing the first thin-film transistor T1. The second thin-film transistor T2 includes a first portion SD2-1 of a first electrode SD2, a first sub-semiconductor layer IGZO1, a second gate insulating layer GI3, a first portion GE3-1 of a second gate GE3, and a first portion SD3-1 of a second electrode SD3. The first portion SD2-1 of the first electrode SD2 constitutes the drain of the second thin-film transistor T2, the first portion SD3-1 of the second electrode SD3 constitutes the source of the second thin-film transistor T2, the first portion GE3-1 of the second gate GE3 constitutes the gate of the second thin-film transistor T2, the first sub-semiconductor layer IGZO1 constitutes the active layer of the second thin-film transistor T2, and the second gate insulating layer GI3 is located between the first sub-semiconductor layer IGZO1 and the first portion GE3-1 of the second gate GE3. In the vertical metal-oxide-semiconductor thin-film transistor, the channel portion of the active layer extends along a direction that forms an angle with the plane containing the display panel DP.

[0071] like Figure 3 As shown, the third thin-film transistor T3 is a vertical metal-oxide-semiconductor thin-film transistor. The third thin-film transistor T3 includes a second portion SD2-2 of a first electrode SD2, a second sub-semiconductor layer IGZO2, a second gate insulating layer GI3, a second portion GE3-2 of a second gate GE3, and a second portion SD3-2 of the second electrode SD3. The second portion SD2-2 of the first electrode SD2 constitutes the source of the third thin-film transistor T3, the second portion SD3-2 of the second electrode SD3 constitutes the drain of the third thin-film transistor T3, the second portion GE3-2 of the second gate GE3 constitutes the gate of the third thin-film transistor T3, the second sub-semiconductor layer IGZO2 constitutes the active layer of the third thin-film transistor T3, and the second gate insulating layer GI3 is located between the second sub-semiconductor layer IGZO2 and the second portion GE3-2 of the second gate GE3.

[0072] like Figure 2 As shown, the pixel PX of the display panel DP provided in Embodiment 1 of this application includes a light-emitting device OLED and a pixel driving circuit. The pixel driving circuit includes a first thin-film transistor T1, a second thin-film transistor T2, a third thin-film transistor T3, and a capacitor Cst.

[0073] The gate of the first thin-film transistor T1 is electrically connected to the first gate line GL1, the source of the first thin-film transistor T1 is electrically connected to the data line DL, and the drain of the first thin-film transistor T1 is electrically connected to the gate of the second thin-film transistor T2. The first thin-film transistor T1 is used to control the transmission of data signals to the gate of the second thin-film transistor T2.

[0074] The first plate of capacitor Cst is electrically connected to the gate of the second thin-film transistor T2, and the second plate of capacitor Cst is electrically connected to the drain of the second thin-film transistor T2. Capacitor Cst is used to store the gate voltage of the second thin-film transistor T2. The first plate of capacitor Cst includes a first intermediate metal layer BSM, and the second plate of capacitor Cst includes a first portion SD2-1 of the first electrode SD2.

[0075] The source of the second thin-film transistor T2 is electrically connected to the first power supply line VDD, and the drain of the second thin-film transistor T2 is electrically connected to the anode of the light-emitting device OLED. The second thin-film transistor T2 is used to drive the light-emitting device OLED to emit light, and the second thin-film transistor T2 adjusts the driving current flowing through the light-emitting device OLED according to its gate voltage.

[0076] The gate of the third thin-film transistor T3 is electrically connected to the second gate line GL2, the source of the third thin-film transistor T3 is electrically connected to the initialization signal line Vin, and the drain of the third thin-film transistor T3 is electrically connected to the drain of the second thin-film transistor T2. The third thin-film transistor T3 is used to initialize the voltage of the drain of the second thin-film transistor T2 / anode of the OLED light-emitting device to a preset voltage.

[0077] The anode of the OLED is electrically connected to the drain of the second thin-film transistor T2, and the cathode of the OLED is electrically connected to the second power line VSS. The OLED emits light under the action of a driving current.

[0078] like Figure 4 As shown, from a top-view perspective of the display panel DP, the first semiconductor layer Poly comprises a first portion Poly1 and a second portion Poly2. The length direction of the first portion Poly1 is parallel to the first direction D1, and the length direction of the second portion Poly2 is parallel to the second direction D2. The first direction D1 and the second direction D2 are perpendicular. The first portion Poly1 and the second portion Poly2 are connected, and the first semiconductor layer Poly is in the shape of an inverted L. The length of the first portion Poly1 is greater than the length of the second portion Poly2. The first end of the first portion Poly1 is connected to the first end of the second portion Poly2, and the second end of the second portion Poly2 is electrically connected to the first source / drain electrode SD1 through a via. The second end of the first portion Poly1 is located in the gap between the first portion SD3-1 and the second portion SD3-2 of the second electrode SD3.

[0079] like Figure 4 As shown, the first source / drain SD1 is arranged in a trace configuration. The length direction of the first source / drain SD1 is parallel to the length direction of the first portion Poly1 of the first semiconductor layer Poly, and the length direction of the first source / drain SD1 is perpendicular to the length direction of the second portion Poly2 of the first semiconductor layer Poly. The first source / drain SD1 overlaps with the first gate GE1, the first portion GE3-1 of the second gate GE3, the first portion SD2-1 of the first electrode SD2, the second portion GE3-2 of the second gate GE3, and the second portion SD2-2 of the first electrode SD2.

[0080] like Figure 4 As shown, the first gate GE1 is in the form of a trace. The length direction of the first gate GE1 is parallel to the second direction D2 and perpendicular to the first direction D1. From the top view of the display panel DP, the first gate GE1 intersects with and partially overlaps with the first portion Poly1 of the first semiconductor layer Poly.

[0081] like Figure 4 As shown, the second gate GE3 includes a first portion GE3-1 and a second portion GE3-2. The second portion GE3-2 of the second gate GE3 is in the form of a trace. The length direction of the second portion GE3-2 of the second gate GE3 is parallel to the second direction D2. From the top view of the display panel DP, the second portion GE3-2 of the second gate GE3 overlaps with the first gate GE1, and the second portion GE3-2 of the second gate GE3 intersects with and partially overlaps with the first portion Poly1 of the first semiconductor layer Poly. In the first direction D1, the width of the second portion GE3-2 of the second gate GE3 is smaller than the width of the first gate GE1, and the width of the first gate GE1 is smaller than the width of the second portion SD3-2 of the second electrode SD3.

[0082] like Figure 4 As shown, the first electrode SD2 includes a first portion SD2-1 and a second portion SD2-2. The second portion SD2-2 of the first electrode SD2 is rectangular and overlaps with the second portion GE3-2 of the second gate GE3. The dimension of the second portion SD2-2 of the first electrode SD2 in the first direction D1 is larger than the width of the first gate GE1. From a top-view perspective of the display panel DP, the opening includes a first opening and a second opening. At least a portion of the second opening overlaps with the first portion Poly1 of the first semiconductor layer Poly, and at least a portion of the second portion SD2-2 of the first electrode SD2 overlaps with the first portion Poly1 of the first semiconductor layer Poly.

[0083] like Figure 4As shown, the second opening is located within the coverage area of ​​the second portion SD2-2 of the first electrode SD2. The second opening overlaps with the first gate GE1, the second portion SD2-2 of the first electrode SD2, the second portion SD3-2 of the second electrode SD3, and the second portion GE3-2 of the second gate GE3. In the first direction D1, the size of the second opening is smaller than the width of the second portion GE3-2 of the second gate GE3. The second opening does not extend beyond the two edges of the second portion GE3-2 of the second gate GE3 in the first direction D1. The second portion SD2-2 of the first electrode SD2 covers the second opening. The second portion GE3-2 of the second gate GE3 covers the second opening. A portion of the second opening overlaps with a portion of the first portion Poly1 of the first semiconductor layer Poly.

[0084] like Figure 4 As shown, the first portion GE3-1 of the second gate GE3 is in the form of a trace, and the length direction of the first portion GE3-1 of the second gate GE3 is parallel to the second direction D2. The second electrode SD3 includes a first portion SD3-1 and a second portion SD3-2. The first portion SD3-1 of the second electrode SD3 is in the form of a trace, and the length direction of the first portion SD3-1 of the second electrode SD3 is parallel to the second direction D2. The first portion SD3-1 of the second electrode SD3 overlaps with the first portion GE3-1 of the second gate GE3. In the first direction D1, the width of the gap between the first portion SD3-1 and the second portion SD3-2 of the second electrode SD3 is greater than the dimension of the first portion SD3-1 of the second electrode SD3 in the first direction D1, and the width of the first portion SD3-1 of the second electrode SD3 is greater than the width of the first portion GE3-1 of the second gate GE3.

[0085] like Figure 4 As shown, the first portion SD2-1 of the first electrode SD2 is rectangular, and its dimension in the first direction D1 is larger than the width of the first portion GE3-1 of the second gate GE3. A first opening is located within the coverage area of ​​the first portion SD2-1 of the first electrode SD2, and its dimension in the first direction D1 is smaller than the width of the first portion GE3-1 of the second gate GE3. The first opening does not extend beyond the two edges of the first portion GE3-1 of the second gate GE3 in the first direction D1. The first portion SD2-1 of the first electrode SD2 covers the first opening.

[0086] like Figure 4 As shown, the first end of the first part Poly1 of the first semiconductor layer Poly and the second part Poly2 of the first semiconductor layer Poly are located on the side of the second part SD3-2 of the second electrode SD3 away from the first part SD3-1 of the second electrode SD3.

[0087] like Figure 4 As shown, the first sub-semiconductor layer IGZO1 covers the first opening, and the second sub-semiconductor layer IGZO2 covers the second opening.

[0088] In Embodiment 1 of this application, the second thin-film transistor T2 and the third thin-film transistor T3 of the pixel driving circuit are vertical metal-oxide-semiconductor thin-film transistors, and the first thin-film transistor T1 is a top-gate low-temperature polysilicon thin-film transistor. By employing hybrid thin-film transistors, the area occupied by the pixel driving circuit in the direction parallel to the surface of the display panel DP is reduced, the number of pixels PX arranged per unit area is increased, and the pixel density of the display panel is improved.

[0089] Example 2 like Figure 5 As shown, the display device provided in Embodiment 2 of this application includes a display panel DP, which includes a plurality of pixels PX. Each pixel PX includes a light-emitting device and a pixel driving circuit. The pixel driving circuit includes a first thin-film transistor T1 and a second thin-film transistor T2. Both the first thin-film transistor T1 and the second thin-film transistor T2 are vertical metal-oxide-semiconductor thin-film transistors.

[0090] The display panel DP includes a substrate Glass, a bottom metal layer SD1 disposed on the substrate Glass, a first buffer layer Buffer1 disposed on the substrate Glass and the bottom metal layer SD1, a first intermediate metal layer BSM disposed on the first buffer layer Buffer1, a second buffer layer Buffer2 disposed on the first buffer layer Buffer1 and the first intermediate metal layer BSM, a first electrode SD2 disposed on the second buffer layer Buffer2, a first insulating layer Buffer3 disposed on the second buffer layer Buffer2 and the first electrode SD2, a second electrode SD3 disposed on the surface of the first insulating layer Buffer3, a semiconductor layer IGZO disposed on the first insulating layer Buffer3, the first electrode SD2 and the second electrode SD3, a first gate insulating layer GI1 disposed on the first insulating layer Buffer3, the first electrode SD2, the second electrode SD3 and the semiconductor layer IGZO, a first gate GE1 disposed on the first gate insulating layer GI1, and a first gate GE1 disposed on the first gate insulating layer GI1 and the first gate GE1. The second insulating layer ILD, the second gate GE2 disposed on the second insulating layer ILD, the first passivation layer PV1 disposed on the second insulating layer ILD and the second gate GE2, the first planarization layer PLN1 disposed on the first passivation layer PV1, the fourth source / drain metal layer SD4 disposed on the first planarization layer PLN1, the second passivation layer PV2 disposed on the first planarization layer PLN1 and the fourth source / drain metal layer SD4, the second planarization layer PLN2 disposed on the second passivation layer PV2, and the second planarization layer PLN2 disposed on the second planarization layer PLN2. The second intermediate metal layer MSM, the third passivation layer PV3 disposed on the second planarization layer PLN2 and the second intermediate metal layer MSM, the fifth source / drain metal layer SD5 disposed on the third passivation layer PV3, the fourth passivation layer PV4 disposed on the third passivation layer PV3 and the fifth source / drain metal layer SD5, the third planarization layer PLN3 disposed on the fourth passivation layer PV4, the anode layer Anode disposed on the third planarization layer PLN3, and the pixel definition layer PDL disposed on the third planarization layer PLN3 and the anode layer Anode.

[0091] The substrate Glass is a glass substrate. The bottom metal layer SD1 is located on the substrate Glass, and is located below the layer containing the first electrode SD2. The first portion SD2-1 of the first electrode SD2 is electrically connected to the bottom metal layer SD1. The material of the bottom metal layer SD1 includes molybdenum, aluminum, copper, titanium, or alloys of the above materials.

[0092] like Figure 5As shown, the display panel DP also includes a first buffer layer Buffer1 and a second buffer layer Buffer2. The first buffer layer Buffer1 is located on the substrate Glass and the bottom metal layer SD1, and the material of the first buffer layer Buffer1 includes silicon oxide, silicon nitride, or silicon oxynitride. A first intermediate metal layer BSM is located on the first buffer layer Buffer1, and the material of the first intermediate metal layer BSM includes molybdenum, aluminum, copper, titanium, or an alloy of the above materials. The second buffer layer Buffer2 is located on the first buffer layer Buffer1 and the first intermediate metal layer BSM, and the material of the second buffer layer Buffer2 includes silicon oxide, silicon nitride, or silicon oxynitride.

[0093] like Figure 5 As shown, the first electrode SD2 is located on the second buffer layer Buffer2, and the first electrode SD2 includes a first portion SD2-1 and a second portion SD2-2. The first portion SD2-1 of the first electrode SD2 is electrically connected to the underlying metal layer SD1 through a via penetrating the first buffer layer Buffer1 and the second buffer layer Buffer2. The first electrode SD2 constitutes the source or drain of a vertical metal-oxide-semiconductor thin-film transistor. The material of the first electrode SD2 includes molybdenum, aluminum, copper, titanium, or alloys of the above materials.

[0094] like Figure 5 As shown, a first insulating layer Buffer 3 is located on a second buffer layer Buffer 2 and a first electrode SD2. The first insulating layer Buffer 3 has a first opening and a second opening penetrating through it. The first opening exposes a first portion SD2-1 of the first electrode SD2, and the second opening exposes a second portion SD2-2 of the first electrode SD2. The material of the first insulating layer Buffer 3 includes silicon oxide, silicon nitride, or silicon oxynitride.

[0095] like Figure 5 As shown, the second electrode SD3 is located on the surface of the first insulating layer Buffer3. The second electrode SD3 includes a first portion SD3-1 and a second portion SD3-2. The first portion SD3-1 of the second electrode SD3 is located on the surface of the first insulating layer Buffer3 around the first opening, and the second portion SD3-2 of the second electrode SD3 is located on the surface of the first insulating layer Buffer3 around the second opening. The second electrode SD3 constitutes the drain or source of a vertical metal-oxide-semiconductor thin-film transistor. The material of the second electrode SD3 includes molybdenum, aluminum, copper, titanium, or alloys of the above materials.

[0096] like Figure 5As shown, the material of the IGZO semiconductor layer includes metal oxide. The IGZO semiconductor layer includes a first sub-semiconductor layer IGZO1 and a second sub-semiconductor layer IGZO2. A first portion of the first sub-semiconductor layer IGZO1 is located within a first opening and is electrically connected to a first portion SD2-1 of the first electrode SD2. A second portion of the first sub-semiconductor layer IGZO1 is located on the sidewall of the first opening. A third portion of the first sub-semiconductor layer IGZO1 is located on the surface of a first portion SD3-1 of the second electrode SD3 and is electrically connected to a first portion SD3-1 of the second electrode SD3. The cross-section of the first sub-semiconductor layer IGZO1 is U-shaped.

[0097] like Figure 5 As shown, the first portion of the second sub-semiconductor layer IGZO2 is located within the second opening and electrically connected to the second portion SD2-2 of the first electrode SD2. The second portion of the second sub-semiconductor layer IGZO2 is located on the sidewall of the second opening. The third portion of the second sub-semiconductor layer IGZO2 is located on the surface of the second portion SD3-2 of the second electrode SD3 and electrically connected to the second portion SD3-2 of the second electrode SD3. The cross-section of the second sub-semiconductor layer IGZO2 is U-shaped. The material of the IGZO semiconductor layer includes indium gallium zinc oxide.

[0098] like Figure 5 As shown, a first gate insulating layer GI1 covers a first insulating layer Buffer3, the portion of the first electrode SD2 exposed within the opening, a second electrode SD3, and a semiconductor layer IGZO. From a top-view perspective of the display panel DP, the first gate insulating layer GI1 and the first gate GE1 cover the semiconductor layer IGZO along its surface. The first gate insulating layer GI1 extends along the surface of the semiconductor layer IGZO, covering the portion of the first sub-semiconductor layer IGZO1 located on the sidewall of the first opening and the portion of the second sub-semiconductor layer IGZO2 located on the sidewall of the second opening. The first gate insulating layer GI1 is conformally bonded to the semiconductor layer IGZO. The material of the first gate insulating layer GI1 includes silicon oxide, silicon nitride, or silicon oxynitride.

[0099] like Figure 5 As shown, a first gate GE1 is located on a first gate insulating layer GI1. The first gate GE1 includes a first portion GE1-1 and a second portion GE1-2. The first portion GE1-1 of the first gate GE1 is located on the portion of the first gate insulating layer GI1 disposed on the sidewall of the first opening, and the second portion GE1-2 of the first gate GE1 is located on the portion of the first gate insulating layer GI1 disposed on the sidewall of the second opening. The first gate GE1 extends along the surface of the first gate insulating layer GI1 and is conformally fitted to the first gate insulating layer GI1. The material of the first gate GE1 includes molybdenum, aluminum, copper, titanium, or alloys of the above materials.

[0100] like Figure 5 As shown, the first gate insulating layer GI1 and the first gate GE1 cover the groove of the semiconductor layer IGZO. The first sub-semiconductor layer IGZO1 and the second sub-semiconductor layer IGZO2 form channel portions at the sidewall positions of the first opening and the second opening, respectively. The plane where the channel portion is located forms an angle with the plane where the display panel DP is located. The angle is in the range of 5 degrees to 85 degrees. For example, the angle is 5 degrees, 10 degrees, 15 degrees, 20 degrees, 25 degrees, 30 degrees, 35 degrees, 40 degrees, 45 degrees, 50 degrees, 55 degrees, 60 degrees, 65 degrees, 70 degrees, 75 degrees, 80 degrees, and 85 degrees.

[0101] like Figure 5 As shown, the display panel DP also includes a second insulating layer ILD and a second gate GE2. The second insulating layer ILD is located on the first gate insulating layer GI1 and the first gate GE1. The material of the second insulating layer ILD includes silicon oxide, silicon nitride or silicon oxynitride.

[0102] The second gate GE2 is located on the second insulating layer ILD, and includes a first portion GE2-1 and a second portion GE2-2. From a top-view perspective of the display panel DP, the first portion GE2-1 of the second gate GE2 overlaps with the second portion GE1-2 of the first gate GE1. The second portion GE1-2 of the first gate GE1 is electrically connected to the first portion SD3-1 of the second electrode SD3 through a via penetrating the first gate insulating layer GI1. The second portion GE2-2 of the second gate GE2 is electrically connected to the second portion SD3-2 of the second electrode SD3 through a via penetrating both the second insulating layer ILD and the first gate insulating layer GI1. The second portion GE2-2 of the second gate GE2 is located above the second portion GE1-2 of the first gate GE1. The material of the second gate GE2 includes molybdenum, aluminum, copper, titanium, or alloys of the above materials.

[0103] A first passivation layer PV1 is located on the second insulating layer ILD and the second gate GE2. The material of the first passivation layer PV1 includes silicon oxide, silicon nitride, or silicon oxynitride. A first planarization layer PLN1 is located on the first passivation layer PV1. The material of the first planarization layer PLN1 includes an organic material.

[0104] The fourth source / drain metal layer SD4 is located on the first planarization layer PLN1. The fourth source / drain metal layer SD4 is electrically connected to the first portion SD3-1 of the second electrode SD3 through a via penetrating the first planarization layer PLN1, the first passivation layer PV1, the second insulating layer ILD, and the first gate insulating layer GI1. The material of the fourth source / drain metal layer SD4 includes molybdenum, aluminum, copper, titanium, or alloys of the above materials.

[0105] The second passivation layer PV2 is located on the first planarization layer PLN1 and the fourth source / drain metal layer SD4. The material of the second passivation layer PV2 includes silicon oxide, silicon nitride, or silicon oxynitride. The second planarization layer PLN2 is located on the second passivation layer PV2. The material of the second planarization layer PLN2 includes organic materials.

[0106] The second intermediate metal layer MSM is located on the second planarization layer PLN2. The second intermediate metal layer MSM is electrically connected to the second portion GE2-2 of the second gate GE2 through a via penetrating the second planarization layer PLN2, the second passivation layer PV2, the first planarization layer PLN1, and the first passivation layer PV1. The material of the second intermediate metal layer MSM includes molybdenum, aluminum, copper, titanium, or alloys of the above materials.

[0107] The third passivation layer PV3 is located on the second planarization layer PLN2 and the second intermediate metal layer MSM. The material of the third passivation layer PV3 includes silicon oxide, silicon nitride, or silicon oxynitride. The fifth source / drain metal layer SD5 is located on the third passivation layer PV3. The material of the fifth source / drain metal layer SD5 includes molybdenum, aluminum, copper, titanium, or alloys of the above materials.

[0108] The fourth passivation layer PV4 is located on the third passivation layer PV3 and the fifth source / drain metal layer SD5. The material of the fourth passivation layer PV4 includes silicon oxide, silicon nitride, or silicon oxynitride. The third planarization layer PLN3 is located on the fourth passivation layer PV4. The material of the third planarization layer PLN3 includes organic materials.

[0109] The anode layer is located on the third planarization layer PLN3, and is electrically connected to the fifth source / drain metal layer SD5 through a via penetrating the third planarization layer PLN3 and the fourth passivation layer PV4. The material of the anode layer includes indium tin oxide.

[0110] The pixel definition layer (PDL) is located on the third planarization layer (PLN3) and the anode layer (Anode). The PDL includes support pillars (PS). The PDL is made of organic materials.

[0111] like Figure 5 As shown, the display panel DP provided in Embodiment 2 of this application includes a first thin-film transistor T1 and a second thin-film transistor T2.

[0112] The first thin-film transistor T1 is a vertical metal-oxide-semiconductor thin-film transistor. The first thin-film transistor T1 includes a first portion SD2-1 of a first electrode SD2, a first sub-semiconductor layer IGZO1, a first portion SD3-1 of a second electrode SD3, and a first portion GE1-1 of a first gate GE1.

[0113] The second thin-film transistor T2 is a vertical metal-oxide-semiconductor thin-film transistor. The second thin-film transistor T2 includes a second portion SD2-2 of the first electrode SD2, a second sub-semiconductor layer IGZO2, a second portion SD3-2 of the second electrode SD3, and a second portion GE1-2 of the first gate GE1.

[0114] The circuit of the pixel PX of the display panel DP provided in Embodiment 2 of this application is the same as the circuit of the pixel PX in Embodiment 1.

[0115] like Figure 6 As shown, from a top-down view of the display panel DP, the second portion GE1-2 of the first gate GE1 is in the form of a trace, and the first portion GE1-1 of the first gate GE1 is in the form of a rectangular block. The first portion SD2-1 of the first electrode SD2 is in the form of a trace, and the second portion SD2-2 of the first electrode SD2 is in the form of a rectangular block. The first portion SD3-1 of the second electrode SD3 is in the form of a rectangular block, and the second portion SD3-2 of the second electrode SD3 is in the form of a rectangular block. The bottom metal layer SD1 is in the form of a trace.

[0116] like Figure 6 As shown, in the first direction D1, the width of the gap between the first part SD2-1 and the second part SD2-2 of the first electrode SD2 is greater than the size of the first part SD2-1 of the first electrode SD2 in the first direction D1, and the width of the gap between the first part SD2-1 and the second part SD2-2 of the first electrode SD2 is less than the size of the second part SD2-2 of the first electrode SD2 in the first direction D1.

[0117] like Figure 6 As shown, the first sub-semiconductor layer IGZO1 is in the shape of a rectangular block, and the second sub-semiconductor layer IGZO2 is in the shape of a rectangular block. From a top-view perspective of the display panel DP, the first portion GE1-1 of the first gate GE1 at least partially overlaps with the first portion SD2-1 of the first electrode SD2, and the first portion GE1-1 of the first gate GE1 at least partially overlaps with the second portion SD2-2 of the first electrode SD2. The second portion SD2-2 of the first electrode SD2, in addition to partially overlapping with the first portion GE1-1 of the first gate GE1, also partially overlaps with the second portion GE1-2 of the first gate GE1.

[0118] The length direction of the second part GE1-2 of the first gate GE1 is parallel to the second direction D2, the length direction of the first part SD2-1 of the first electrode SD2 is parallel to the second direction D2, the length direction of the bottom metal layer SD1 is parallel to the first direction D1, and the first direction D1 and the second direction D2 are perpendicular to each other.

[0119] like Figure 6As shown, the first sub-semiconductor layer IGZO1 overlaps with the first opening, and the second sub-semiconductor layer IGZO2 overlaps with the second opening. The area of ​​the first opening is larger than the area of ​​the second opening. The first sub-semiconductor layer IGZO1 overlaps with the first portion SD2-1 of the first electrode SD2, and the second sub-semiconductor layer IGZO2 overlaps with the second portion GE1-2 of the first gate GE1.

[0120] like Figure 6 As shown, from the top view of the display panel DP, the first part GE1-1 of the first gate GE1 at least partially overlaps with the bottom metal layer SD1, the second part SD2-2 of the first electrode SD2 at least partially overlaps with the bottom metal layer SD1, the first part SD2-1 of the first electrode SD2 intersects with and partially overlaps with the bottom metal layer SD1, and the second part GE1-2 of the first gate GE1 intersects with and partially overlaps with the bottom metal layer SD1.

[0121] like Figure 6 As shown, in the first direction D1, the size of the first portion GE1-1 of the first gate GE1 in the first direction D1 is greater than the size of the first portion SD2-1 of the first electrode SD2 in the first direction D1, the size of the first portion GE1-1 of the first gate GE1 in the first direction D1 is greater than the size of the second portion GE1-2 of the first gate GE1 in the first direction D1, the size of the first portion GE1-1 of the first gate GE1 in the first direction D1 is greater than the size of the first portion SD3-1 of the second electrode SD3 in the first direction D1, and the size of the first portion GE1-1 of the first gate GE1 in the first direction D1 is greater than the size of the second portion SD3-2 of the second electrode SD3 in the first direction D1.

[0122] like Figure 6 As shown, in the first direction D1, the size of the second part SD2-2 of the first electrode SD2 in the first direction D1 is greater than the size of the first part SD2-1 of the first electrode SD2 in the first direction D1, the size of the second part SD2-2 of the first electrode SD2 in the first direction D1 is greater than the size of the second part GE1-2 of the first gate GE1 in the first direction D1, the size of the second part SD2-2 of the first electrode SD2 in the first direction D1 is greater than the size of the first part SD3-1 of the second electrode SD3 in the first direction D1, and the size of the second part SD2-2 of the first electrode SD2 in the first direction D1 is greater than the size of the second part SD3-2 of the second electrode SD3 in the first direction D1.

[0123] like Figure 6As shown, in the first direction D1, the width of the first portion SD2-1 of the first electrode SD2 is greater than the size of the first opening in the first direction D1, and the width of the second portion GE1-2 of the first gate GE1 is greater than the size of the second opening in the first direction D1.

[0124] like Figure 6 As shown, from a top-down view of the display panel DP, the size of the first portion GE1-1 of the first gate GE1 in the first direction D1 is larger than the size of the first portion GE1-1 of the first gate GE1 in the second direction D2. Similarly, the size of the second portion SD2-2 of the first electrode SD2 in the first direction D1 is larger than the size of the second portion SD2-2 of the first electrode SD2 in the second direction D2. The size of the first portion SD3-1 of the second electrode SD3 in the second direction D2 is larger than the size of the first opening in the second direction D2, and the size of the second portion SD3-2 of the second electrode SD3 in the second direction D2 is larger than the size of the second opening in the second direction D2. Furthermore, the size of the first portion GE1-1 of the first gate GE1 in the second direction D2 is larger than the size of the bottom metal layer SD1 in the second direction D2, and the size of the second portion SD2-2 of the first electrode SD2 in the second direction D2 is larger than the size of the bottom metal layer SD1 in the second direction D2.

[0125] In Embodiment 2 of this application, the first thin-film transistor T1 and the second thin-film transistor T2 of the pixel driving circuit are both vertical metal-oxide-semiconductor (MOS) thin-film transistors. The display panel DP does not include low-temperature polysilicon (LTPS) thin-film transistors; all thin-film transistors are vertical MOS transistors. The vertical MOS transistors occupy less space in the direction parallel to the surface of the display panel DP, allowing for further improvement in pixel density.

[0126] In summary, the display device provided by the embodiments of this application reduces the space occupied by the thin-film transistors in the direction parallel to the surface of the display panel DP by employing vertical metal-oxide-semiconductor thin-film transistors. This reduces the area occupied by the pixel driving circuit in the direction parallel to the surface of the display panel DP, increases the number of pixels PX arranged per unit area, and improves the pixel density of the display panel DP. This solves the technical problem that traditional display devices are limited by the planar arrangement space of thin-film transistors in improving pixel density.

[0127] The embodiments of this application have been described in detail above. The content of this specification should not be construed as limiting the scope of protection of this application.

Claims

1. A display device, characterized in that, The display device includes a display panel, the display panel includes a plurality of pixels, each pixel includes a light-emitting device and a pixel driving circuit, and the pixel driving circuit includes at least a first thin-film transistor and a second thin-film transistor. The first thin-film transistor includes a first semiconductor layer, a first gate, and a first source / drain. The second thin-film transistor is disposed above the layer containing the first thin-film transistor, and the second thin-film transistor includes: First electrode; A first insulating layer is located on the first electrode and has an opening penetrating the first insulating layer; A second electrode is located on the surface of the first insulating layer surrounding the opening; A second semiconductor layer, wherein a first portion of the second semiconductor layer is located within the opening and electrically connected to the first electrode, a second portion of the second semiconductor layer is located on the sidewall of the opening, and a third portion of the second semiconductor layer is located on the surface of the second electrode and electrically connected to the second electrode; A second gate insulating layer, the second gate insulating layer covering the second semiconductor layer; and The second gate is located on the portion of the second gate insulating layer disposed on the sidewall of the opening.

2. The display device according to claim 1, characterized in that, The material of the first semiconductor layer includes low-temperature polycrystalline silicon, and the material of the second semiconductor layer includes metal oxide.

3. The display device according to claim 1, characterized in that, The second gate insulating layer and the second gate cover the second semiconductor layer along the surface of the second semiconductor layer.

4. The display device according to claim 1, characterized in that, The first thin-film transistor further includes a first intermediate metal layer, which is located between the layer containing the first source and drain electrodes and the layer containing the first electrode, and is electrically connected to the first semiconductor layer.

5. The display device according to claim 4, characterized in that, The display panel also includes a capacitor, the first plate of the capacitor includes the first intermediate metal layer, the second plate of the capacitor includes the first electrode, and the first intermediate metal layer and the first electrode at least partially overlap when viewed from above the display panel.

6. The display device according to claim 1, characterized in that, The second semiconductor layer includes a first sub-semiconductor layer and a second sub-semiconductor layer, the opening includes a first opening and a second opening, and the second thin-film transistor includes a first portion of the first electrode, the first sub-semiconductor layer, the second gate insulating layer, a first portion of the second gate, and a first portion of the second electrode. The pixel driving circuit further includes a third thin-film transistor, which includes a second portion of the first electrode, a second sub-semiconductor layer, a second gate insulating layer, a second portion of the second gate, and a second portion of the second electrode. A first portion of the first sub-semiconductor layer is located within the first opening and is electrically connected to a first portion of the first electrode; a second portion of the first sub-semiconductor layer is located on the sidewall of the first opening; and a third portion of the first sub-semiconductor layer is located on the surface of a first portion of the second electrode and is electrically connected to a first portion of the second electrode. The first portion of the second sub-semiconductor layer is located inside the second opening and is electrically connected to the second portion of the first electrode; the second portion of the second sub-semiconductor layer is located on the sidewall of the second opening; and the third portion of the second sub-semiconductor layer is located on the surface of the second portion of the second electrode and is electrically connected to the second portion of the second electrode. The first portion of the second gate is located on the portion of the second gate insulating layer disposed on the sidewall of the first opening, and the second portion of the second gate is located on the portion of the second gate insulating layer disposed on the sidewall of the second opening.

7. The display device according to claim 6, characterized in that, The display panel further includes a first intermediate metal layer, which is located between the layer where the first source and drain are located and the layer where the first electrode is located. The first intermediate metal layer is electrically connected to the first semiconductor layer, and a first portion of the second gate is electrically connected to the first intermediate metal layer through a through-hole that penetrates the first insulating layer and the second gate insulating layer. The first part of the first electrode is electrically connected to the second part of the second electrode through a through hole penetrating the first insulating layer; The second part of the second electrode is electrically connected to the anode of the light-emitting device.

8. The display device according to claim 6, characterized in that, From a top-down view of the display panel, the length direction of the first portion of the first semiconductor layer is parallel to the first direction, the length direction of the second portion of the first semiconductor layer is parallel to the second direction, the first direction is perpendicular to the second direction, the first portion of the first semiconductor layer is connected to the second portion of the first semiconductor layer, and the length of the first portion of the first semiconductor layer is greater than the length of the second portion of the first semiconductor layer.

9. The display device according to claim 8, characterized in that, From a top-down view of the display panel, at least a portion of the second opening overlaps with a first portion of the first semiconductor layer, and at least a portion of the second portion of the first electrode overlaps with a first portion of the first semiconductor layer.

10. The display device according to claim 9, characterized in that, In the first direction, the width of the gap between the first portion of the second electrode and the second portion of the second electrode is greater than the size of the first portion of the second electrode in the first direction.

11. The display device according to claim 9, characterized in that, The length direction of the first gate is parallel to the second direction, and from a top-view perspective of the display panel, the first gate overlaps with a first portion of the first semiconductor layer.

12. The display device according to claim 11, characterized in that, The length direction of the second portion of the second gate is parallel to the second direction. From a top-view perspective of the display panel, the second portion of the second gate overlaps with the first gate and the second portion of the second gate overlaps with the first portion of the first semiconductor layer.

13. The display device according to claim 12, characterized in that, In the first direction, the width of the second portion of the second gate is smaller than the width of the first gate, and the width of the first gate is smaller than the width of the second portion of the second electrode.

14. The display device according to claim 12, characterized in that, In a first direction, the size of the second opening in the first direction is smaller than the width of the second portion of the second gate, the second opening does not extend beyond the two edges of the second portion of the second gate in the first direction, and the second portion of the first electrode covers the second opening.

15. A display device, characterized in that, The display device includes a display panel, the display panel includes a plurality of pixels, each pixel includes a light-emitting device and a pixel driving circuit, the pixel driving circuit includes a first thin-film transistor and a second thin-film transistor, both the first thin-film transistor and the second thin-film transistor being vertical thin-film transistors; The display panel includes: First electrode; A first insulating layer is located on the first electrode and has a first opening and a second opening penetrating the first insulating layer, the first opening exposing a first portion of the first electrode and the second opening exposing a second portion of the first electrode. The second electrode has a first portion located on the surface of the first insulating layer surrounding the first opening, and a second portion located on the surface of the first insulating layer surrounding the second opening. A semiconductor layer, comprising a first sub-semiconductor layer and a second sub-semiconductor layer, wherein a first portion of the first sub-semiconductor layer is located within the first opening and electrically connected to a first portion of the first electrode, a second portion of the first sub-semiconductor layer is located on a sidewall of the first opening, a third portion of the first sub-semiconductor layer is located on a surface of the first portion of the second electrode and electrically connected to the first portion of the second electrode, a first portion of the second sub-semiconductor layer is located within the second opening and electrically connected to a second portion of the first electrode, a second portion of the second sub-semiconductor layer is located on a sidewall of the second opening, and a third portion of the second sub-semiconductor layer is located on a surface of the second portion of the second electrode and electrically connected to the second portion of the second electrode; A first gate insulating layer, the first gate insulating layer covering the semiconductor layer; and A first gate, the first gate being located on a first gate insulating layer, a first portion of the first gate being located on a portion of the first gate insulating layer disposed on a sidewall of the first opening, and a second portion of the first gate being located on a portion of the first gate insulating layer disposed on a sidewall of the second opening; The first thin-film transistor includes a first portion of the first electrode, a first sub-semiconductor layer, a first portion of the second electrode, and a first portion of the first gate. The second thin-film transistor includes a second portion of the first electrode, a second sub-semiconductor layer, a second portion of the second electrode, and a second portion of the first gate.

16. The display device according to claim 15, characterized in that, The semiconductor layer is made of metal oxide.

17. The display device according to claim 15, characterized in that, From a top-down view of the display panel, the first gate insulating layer and the first gate cover the semiconductor layer along the surface of the semiconductor layer.

18. The display device according to claim 15, characterized in that, The display panel further includes a second insulating layer and a second gate, the second insulating layer being located on the first gate and the second gate being located on the second insulating layer, and from a top view of the display panel, a first portion of the second gate overlaps with a first portion of the first gate; The second portion of the first gate is electrically connected to the first portion of the second electrode through a through-hole penetrating the first gate insulating layer; The second portion of the second gate is electrically connected to the second portion of the second electrode through a through-hole penetrating the second insulating layer and the first gate insulating layer.

19. The display device according to claim 15, characterized in that, In a first direction, the width of the gap between the first portion of the first electrode and the second portion of the first electrode is greater than the size of the first portion of the first electrode in the first direction, and the width of the gap between the first portion of the first electrode and the second portion of the first electrode is less than the size of the second portion of the first electrode in the first direction.

20. The display device according to claim 15, characterized in that, The area of ​​the first opening is larger than the area of ​​the second opening.

21. The display device according to claim 15, characterized in that, From a top-down view of the display panel, a first portion of the first gate at least partially overlaps with a first portion of the first electrode, and a first portion of the first gate at least partially overlaps with a second portion of the first electrode.

22. The display device according to claim 15, characterized in that, In a first direction, the size of the first portion of the first gate in the first direction is greater than the size of the first portion of the first electrode in the first direction, the size of the first portion of the first gate in the first direction is greater than the size of the second portion of the first gate in the first direction, the size of the first portion of the first gate in the first direction is greater than the size of the first portion of the second electrode in the first direction, and the size of the first portion of the first gate in the first direction is greater than the size of the second portion of the second electrode in the first direction.

23. The display device according to claim 15, characterized in that, In a first direction, the size of the second portion of the first electrode in the first direction is greater than the size of the first portion of the first electrode in the first direction, the size of the second portion of the first electrode in the first direction is greater than the size of the second portion of the first gate in the first direction, the size of the second portion of the first electrode in the first direction is greater than the size of the first portion of the second electrode in the first direction, and the size of the second portion of the first electrode in the first direction is greater than the size of the second portion of the second electrode in the first direction.

24. The display device according to claim 15, characterized in that, In a first direction, the width of the first portion of the first electrode is greater than the size of the first opening in the first direction, and the width of the second portion of the first gate is greater than the size of the second opening in the first direction.

25. The display device according to claim 15, characterized in that, The display panel further includes a bottom metal layer, which is located below the layer where the first electrode is located; from a top view of the display panel, a first portion of the first gate at least partially overlaps with the bottom metal layer, a second portion of the first electrode at least partially overlaps with the bottom metal layer, and a second portion of the first gate at least partially overlaps with the bottom metal layer.

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