Display device and display module thereof

Abstract

The present disclosure relates to the technical field of display, and in particular to a display device and a display module thereof. The display module comprises a display panel, a flexible circuit board, a buffer structure and an electrical connection structure. The peripheral area of the display panel has a first binding area which is exposed on the backlight side. The flexible circuit board is arranged on the backlight side of the display panel and has a second binding area. The first binding area and the second binding area have a first step surface therebetween. One end of the buffer structure continuously extends to the second binding area through the first step surface and forms a second step surface. On the side close to the display panel, the acute angle between the tangent of the second step surface and the display panel is not greater than 45°. The electrical connection structure is arranged on the second step surface. The two sides of the electrical connection structure are electrically connected with the first binding area and the second binding area respectively. The display module can realize continuous preparation of the electrical connection structure and ensure the electrical connection conduction between the first binding area and the second binding area.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically, to a display device and its display module. Background Technology

[0002] In related technologies, display modules using back-side bonding technology utilize electrical connection structures to connect the first bonding area of ​​the display panel to the second bonding area of ​​the flexible circuit board. However, due to the step difference between the first and second bonding areas, wire breaks are easily generated during the fabrication of the electrical connection structure, affecting the electrical connection conduction between the first and second bonding areas.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this disclosure is to overcome the shortcomings of the prior art and provide a display device and display module thereof, which can realize the continuous fabrication of electrical connection structure and ensure the electrical connection between the first bonding area and the second bonding area.

[0005] According to one aspect of this disclosure, a display module is provided, comprising: A display panel, wherein the peripheral area of ​​the display panel has a first bonding area, and at least a portion of the first bonding area is exposed on the backlight side of the display panel; A flexible circuit board is disposed on the backlight side of the display panel and does not overlap with the first bonding area; the flexible circuit board has a second bonding area, and a first step surface is provided between the second bonding area and the first bonding area; A buffer structure is disposed on the display panel and located on the side of the first bonding area closer to the second bonding area; one end of the buffer structure extends continuously to the second bonding area through the first step surface; a second step surface is formed on the side of the buffer structure away from the first step surface; along the side closer to the first bonding area, the distance between the second step surface and the display panel decreases, and on the side closer to the display panel, the acute angle between the tangent of the second step surface and the display panel is not greater than 45°; An electrical connection structure is disposed on the second segment surface; the two sides of the electrical connection structure extend to the first binding area and the second binding area respectively, and are electrically connected to the first binding area and the second binding area.

[0006] In one embodiment of this disclosure, on the side closer to the display panel, the acute angle between the tangent of the second segment surface and the display panel is 13° to 26°.

[0007] In one embodiment of this disclosure, the display module further includes a back film layer; The back film layer is located between the display panel and the flexible circuit board; the side of the back film layer near the first bonding area and the side of the flexible circuit board near the first bonding area form the first segment surface.

[0008] In one embodiment of this disclosure, the material of the buffer structure is adhesive; The first segmental surface includes at least one first surface and at least two second surfaces, with each first surface and each second surface arranged and connected alternately; The first surface is parallel to the display panel, and the second surface intersects with the display panel.

[0009] In one embodiment of this disclosure, at least a portion of the second surface is perpendicular to the display panel; And / or, at least part of the second surface includes a connected first sub-surface and a second sub-surface, the first sub-surface being disposed close to the display panel and perpendicular to the display panel, and the second sub-surface being disposed at an angle and extending toward the second bonding area.

[0010] In one embodiment of this disclosure, the material of the buffer structure is glue; the first step surface is an inclined surface, and the thickness of the first step surface gradually decreases along the direction close to the first bonding area.

[0011] In one embodiment of this disclosure, at least one shaping structure is provided on the flexible circuit board in the second bonding area, at least a portion of the shaping structure has the buffer structure on one side, and the buffer structure is located on the side close to the first bonding area.

[0012] In one embodiment of this disclosure, the flexible circuit board has a first surface on the side away from the display panel, and the second bonding area is located on the first surface; the first surface has a first edge on the side near the first bonding area, and the distance between the shaping structure on the side away from the first bonding area and the first edge is no greater than 100 micrometers.

[0013] In one embodiment of this disclosure, the shape control structure is either a boss or a groove.

[0014] In one embodiment of this disclosure, in the second bonding area, the flexible circuit board is provided with multiple sets of shape control structures; Each control structure group includes multiple control structures arranged sequentially along a first direction; each control structure group is arranged sequentially along a second direction, and two adjacent control structure groups are staggered.

[0015] In one embodiment of this disclosure, the first edge is serrated; The maximum distance between the side of the shape control structure away from the first binding area and the first edge is no more than 100 micrometers.

[0016] According to another aspect of this disclosure, a display device is provided having the above-described display module.

[0017] The beneficial effects of this disclosure include: In this disclosure, the angle at the junction of the second segment surface and the display panel is limited to no more than 45°, so that the second segment surface and the display panel have a smooth and continuous transition. In this way, the continuity of the electrical connection structure can be guaranteed during the preparation of the electrical connection structure, and no broken wires will occur, thus ensuring the stability of the electrical connection between the first bonding area and the second bonding area.

[0018] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0019] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0020] Figure 1 This is a schematic diagram of the structure of the display panel in one embodiment of the present disclosure.

[0021] Figure 2 This is a schematic diagram of the structure of the display panel in one embodiment of the present disclosure.

[0022] Figure 3 This is a schematic diagram of a partial structure of the display module in one embodiment of the present disclosure.

[0023] Figure 4 for Figure 3 A schematic diagram of the local structure at point A.

[0024] Figure 5 This is a schematic diagram of a partial structure of the display module in one embodiment of the present disclosure.

[0025] Figure 6 for Figure 5 A schematic diagram of the local structure at point B.

[0026] Figure 7 This is a schematic diagram of a partial structure of the display module in one embodiment of the present disclosure.

[0027] Figure 8 This is a schematic diagram of a partial structure of the display module in one embodiment of the present disclosure.

[0028] Figure 9 This is a partial top view of the flexible circuit board in one embodiment of the present disclosure.

[0029] Figure 10 This is a partial top view of the flexible circuit board in one embodiment of the present disclosure.

[0030] Figure 11 This is a partial top view of the flexible circuit board in one embodiment of the present disclosure.

[0031] Figure 12 This is a partial top view of the flexible circuit board in one embodiment of the present disclosure.

[0032] Figure 13 This is a schematic diagram of the cross-sectional structure of a flexible circuit board in one embodiment of the present disclosure.

[0033] Figure 14 This is a schematic diagram of the cross-sectional structure of a flexible circuit board in one embodiment of the present disclosure.

[0034] Figure 15 This is a physical diagram of the electrical connection structure, the first binding area, and the second binding area in one embodiment of this disclosure.

[0035] Figure 16 This is a physical diagram of the electrical connection structure, the first binding area, and the second binding area in one embodiment of this disclosure. Detailed Implementation

[0036] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0037] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0038] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0039] In this embodiment, a thin-film transistor (TFT) includes an active layer, a gate insulating layer, and a gate, stacked together. The active layer is located within the semiconductor layer and includes a channel region and source and drain electrodes located on opposite sides of the channel region. The channel region retains semiconductor characteristics, while both the source and drain electrodes are conductive. In this embodiment, when using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged; that is, the "drain" and "source" can be interchanged. In this embodiment, for any given transistor, one of the "source" and "drain" electrodes is referred to as the first electrode of the transistor, and the other is referred to as the second electrode of the transistor.

[0040] This disclosure provides a display module and a display device using the display module, wherein the display module includes a display panel PNL, a back film layer BF, and a flexible circuit board FPC.

[0041] Figure 1 This is a schematic diagram of the planar structure of the display panel PNL according to one embodiment of this disclosure. See also Figure 1 The display panel PNL includes a display area AA and a peripheral area BB located on at least one side of the display area AA. Within the display area AA, the display panel PNL has an array of display units DU, each DU including sub-pixels PX and pixel driving circuits PDC that drive the sub-pixels PX. The display panel PNL does not have display units DU in the peripheral area BB, or the provided display units DU are not used for displaying images.

[0042] exist Figure 1 In the example, the display panel PNL has multiple scan lines GL extending along the row direction DH in the display area AA, with each scan line GL corresponding to a row of display units. The pixel driving circuit PDC of each display unit DU in a row of display units is electrically connected to the corresponding scan line GL. The display panel PNL also has multiple data lines DL extending along the column direction DV in the display area AA, with each data line DL corresponding to a column of display units. The pixel driving circuit PDC of each display unit DU in a column of display units is electrically connected to the corresponding data line DL. Thus, the pixel driving circuit PDC of each display unit DU is connected to one scan line GL and one data line DL. When a scan signal is applied to the scan line GL, the driving voltage applied to the data line DL can be written into the pixel driving circuit PDC, allowing the pixel driving circuit PDC to control the brightness of the sub-pixel PX according to the written driving voltage. It is understood that in other embodiments of this disclosure, the arrangement of the display units DU and the connection method with the data lines DL, scan lines GL, etc., can also be different from... Figure 1 The examples are different.

[0043] Figure 2 This is a partial cross-sectional schematic diagram of the display panel PNL in one embodiment of this disclosure. Figure 2 In the example, the display panel PNL may include a substrate SBT, a driving layer DRL, a pixel layer PXL, an encapsulation layer TFE, and a touch function layer TSL, which are stacked sequentially. The pixel layer PXL contains sub-pixels PX, the driving layer DRL contains a pixel driving circuit PDC for driving the sub-pixels PX, and each sub-pixel PX can emit light under the drive of the pixel driving circuit PDC to display an image. The encapsulation layer TFE is used to encapsulate and protect the sub-pixels PX, and the touch function layer TSL is used to implement the touch function of the display panel PNL.

[0044] Optionally, the substrate SBT can be an inorganic material substrate or an organic material substrate; of course, it can also be a composite substrate formed by stacking inorganic and organic material substrates. For example, in some embodiments of this disclosure, the material of the substrate SBT can be glass materials such as soda-lime glass, quartz glass, and sapphire glass. In other embodiments of this disclosure, the material of the substrate SBT can be polymethyl methacrylate, polyvinyl alcohol, polyvinylphenol, polyethersulfone, polyimide, polyamide, polyacetal, polycarbonate, polyethylene terephthalate, polyethylene naphthalate, or combinations thereof. In other embodiments of this disclosure, the substrate SBT can also be a flexible substrate, for example, the material of the substrate SBT can be polyimide.

[0045] Optionally, in the driving layer DRL, any pixel driving circuit PDC may include a transistor (e.g., a thin-film transistor) and a storage capacitor. Further, the transistor may be selected from top-gate thin-film transistors, bottom-gate thin-film transistors, or dual-gate thin-film transistors; the material of the active layer of the thin-film transistor may be amorphous silicon semiconductor material, low-temperature polycrystalline silicon semiconductor material, metal oxide semiconductor material, organic semiconductor material, carbon nanotube semiconductor material, or other types of semiconductor material; the thin-film transistor may be an N-type thin-film transistor or a P-type thin-film transistor.

[0046] It is understood that any two transistors in a pixel driving circuit can be of the same or different types. For example, in some embodiments, some transistors in a pixel driving circuit can be N-type transistors and some transistors can be P-type transistors. Further exemplarily, in other embodiments, in a pixel driving circuit, the active layer material of some transistors can be low-temperature polycrystalline silicon semiconductor material, and the active layer material of some transistors can be metal-oxide-semiconductor semiconductor material. In some embodiments of this disclosure, the thin-film transistor is a low-temperature polycrystalline silicon transistor.

[0047] Optionally, the driving layer DRL may include a semiconductor layer SCL, a gate insulating layer GI, a gate metal layer GT, an interlayer dielectric layer ILD, a source / drain metal layer SD, a planarization layer PLN, etc., stacked between the substrate SBT and the pixel layer PXL. Each thin-film transistor and storage capacitor can be formed from the semiconductor layer SCL, gate insulating layer GI, gate metal layer GT, interlayer dielectric layer ILD, source / drain metal layer SD, etc. The positional relationship of each film layer can be determined according to the film layer structure of the thin-film transistor. Of course, in other embodiments of this disclosure, the driving layer DRL may also include other film layers as needed, such as a metal light-shielding layer (not shown in the figure) located between the semiconductor layer SCL and the substrate SBT. Depending on the requirements, any one of the aforementioned semiconductor layer SCL, gate metal layer GT, and source / drain metal layer SD can be multiple layers. For example, the driving layer DRL may include two different semiconductor layers SCL, or two or three source / drain metal layers SD, or two or three gate metal layers GT. Correspondingly, the insulating layers in the driving layer DRL (such as gate insulating layer GI, interlayer dielectric layer ILD, planarization layer PLN, etc.) can be added or removed as needed, or new insulating layers can be added as required. Optionally, the driving layer DRL may also include a passivation layer, which can be disposed on the surface of the source / drain metal layer SD away from the substrate SBT, in order to protect the source / drain metal layer SD.

[0048] In one embodiment of this disclosure, see Figure 2 The film layer between the substrate SBT and the first source / drain metal layer SD1 can be considered as a whole and referred to as the transistor layer TFTL. This transistor layer TFTL has a semiconductor layer SCL, a gate insulating layer GI, and a gate metal layer GT (the semiconductor layer SCL and the gate metal layer GT can be referred to as transistor functional layers) required for forming a thin-film transistor. For example, in... Figure 2 In the example, the transistor layer TFTL includes an inorganic buffer layer BUF, a polysilicon semiconductor layer PSCL, a first gate insulating layer GI1, a first gate metal layer GT1, a second gate insulating layer GI2, a metal oxide semiconductor layer OSCL, a third gate insulating layer GI3, a second gate metal layer GT2, and an interlayer dielectric layer ILD, which are sequentially stacked on one side of the substrate SBT. Figure 2 In the example, the driving layer DRL includes two semiconductor layers SCL (polysilicon semiconductor layer PSCL and metal oxide semiconductor layer OSCL), three gate insulating layers GI (first gate insulating layer GI1, second gate insulating layer GI2, and third gate insulating layer GI3), and two gate metal layers GT (first gate metal layer GT1 and second gate metal layer GT2). The polysilicon semiconductor layer PSCL, the first gate insulating layer GI1, and the first gate metal layer GT1 can form a low-temperature polysilicon thin-film transistor, while the first gate metal layer GT1, the second gate insulating layer GI2, the metal oxide semiconductor layer OSCL, the third gate insulating layer GI3, and the second gate metal layer GT2 can form a metal oxide thin-film transistor. Thus, this display panel PNL is a display panel PNL employing LTPO technology.

[0049] In one embodiment of this disclosure, the structure between the transistor layer TFTL and the pixel layer PXL can be referred to as the wiring layer MRL. One important function of the wiring layer MRL is to realize electrical connections between different devices, such as thin-film transistors, storage capacitors, and sub-pixels PX. Optionally, the wiring layer MRL may include one or more wiring unit layers MF, each wiring unit layer MF may include a source / drain metal layer SD and a planarization layer PLN located on the side of the source / drain metal layer SD away from the substrate SBT. It is understood that in some examples, the wiring unit layer MF may also include a passivation layer, which may be disposed between the source / drain metal layer SD and the planarization layer PLN to protect the source / drain metal layer SD.

[0050] For example, in Figure 2In the example, the wiring layer MRL includes a first source / drain metal layer SD1, a first planarization layer PLN1, a second source / drain metal layer SD2, and a second planarization layer PLN2, which are sequentially stacked on the side of the transistor layer TFTL away from the substrate SBT. Thus, the wiring layer MRL includes two wiring unit layers MF1 (including the first source / drain metal layer SD1 and the first planarization layer PLN1) and a second wiring unit layer MF2 (including the second source / drain metal layer SD2 and the second planarization layer PLN2). When the display panel PNL requires more source / drain metal layers SD, the number of wiring unit layers MF can be adaptively increased (i.e., the source / drain metal layers SD and the planarization layer PLN are added simultaneously). For example, when the display panel PNL is provided with three source / drain metal layers SD, the wiring layer MRL includes a first source / drain metal layer SD1, a first planarization layer PLN1, a second source / drain metal layer SD2, a second planarization layer PLN2, a third source / drain metal layer, and a third planarization layer (the third source / drain metal layer and the third planarization layer serve as the third wiring unit layer) stacked in sequence.

[0051] In one embodiment of this disclosure, see Figure 1 and Figure 2 In pixel layer PXL, sub-pixels PX are thin-film light-emitting elements, which may include two stacked electrodes and a light-emitting functional unit sandwiched between the two electrodes. Figure 2In the example, the pixel layer PXL may include a pixel electrode layer PEL, a pixel definition layer PDL, a light-emitting functional layer EFL, and a common electrode layer COML stacked sequentially. The pixel electrode layer PEL has multiple pixel electrodes in the display area AA of the display panel PXL. The pixel definition layer PDL has multiple through-holes corresponding to the multiple pixel electrodes, with each pixel hole exposing at least a portion of the corresponding pixel electrode. For example, the pixel definition layer PDL covers the edge of the pixel electrode and exposes at least a portion of the internal area of ​​the pixel electrode, so that the pixel definition layer PDL can effectively define the actual effective area of ​​the pixel electrode (the area directly connected to the light-emitting functional layer EFL), thereby defining the light-emitting area and light-emitting region of the sub-pixel PX. The light-emitting functional layer EFL at least covers the pixel electrodes exposed by the pixel definition layer PDL. The common electrode layer COML may cover the light-emitting functional layer EFL in the display area AA. The pixel electrodes and the common electrode layer COML provide electrons, holes, and other charge carriers to the light-emitting functional layer EFL, causing the light-emitting functional layer EFL to emit light. The light-emitting functional layer (EFL) is located between the pixel electrode and the common electrode layer (COML) and can serve as a light-emitting functional unit. The pixel electrode, the common electrode layer (COML), and the light-emitting functional unit form a sub-pixel (PX). One of the pixel electrode and the common electrode layer (COML) serves as the anode of the sub-pixel PX, and the other serves as the cathode of the sub-pixel PX. In one example, the pixel electrode serves as the anode of the sub-pixel PX, and the common electrode layer (COML) serves as the cathode of the sub-pixel PX.

[0052] exist Figure 1 In the example, the sub-pixel PX is an organic light-emitting diode (OLED). It is understood that in other embodiments of this disclosure, the sub-pixel may also be other types of light-emitting elements, such as current-driven light-emitting elements such as QLED, PLED, MicroLED, and MiniLED.

[0053] Figure 2 The driving layer DRL of the illustrated display panel PNL uses LTPO technology to drive the OLED as sub-pixels PX. It is understood that the display panel PNL of the present disclosure is not limited to this, and the driving layer DRL may also use other driving technologies, and the pixel layer PXL may also use other light-emitting elements.

[0054] exist Figure 2In the example, the encapsulation layer TFE can be disposed on the surface of the pixel layer PXL away from the substrate SBT, and it can include alternately stacked inorganic encapsulation layers and organic encapsulation layers. The inorganic encapsulation layer can effectively block external moisture and oxygen, preventing water and oxygen from invading the pixel layer PXL and causing material aging in the pixel layer PXL. Optionally, the edge of the inorganic encapsulation layer can be located in the peripheral region. The organic encapsulation layer is located between two adjacent inorganic encapsulation layers to achieve planarization and reduce stress between the inorganic encapsulation layers. The edge of the organic encapsulation layer can be located between the edge of the display area AA and the edge of the inorganic encapsulation layer. Exemplarily, the encapsulation layer TFE includes a first inorganic encapsulation layer CVD1, an organic encapsulation layer IJP, and a second inorganic encapsulation layer CVD2, which are sequentially stacked on the side of the pixel layer PXL away from the substrate SBT. Of course, in other embodiments of this disclosure, the encapsulation layer TFE can also adopt other structures, such as multiple stacked inorganic encapsulation layers.

[0055] exist Figure 2 In the example, the touch functionality layer TSL can be positioned on the side of the encapsulation layer TFE away from the pixel layer PXL, so that the display panel PNL has touch functionality. Figure 2 In the example, the touch function layer TSL includes a first touch metal layer TMA, a touch insulating layer TLD, and a second touch metal layer TMB, which are sequentially stacked on the surface of the encapsulation layer TFE.

[0056] exist Figure 2 In the example, the touch functionality layer (TSL) comprises two metal layers. It will be understood that in other embodiments of this disclosure, the touch functionality layer (TSL) may also comprise more metal layers or employ fewer metal layers.

[0057] In one embodiment of this disclosure, see Figure 2 The display panel PNL may also include a color filter layer CFL located on the side of the touch function layer TSL away from the substrate SBT. This color filter layer CFL has color filter units CFU corresponding to sub-pixels PX. For example, a red color filter unit is disposed above a red sub-pixel, a green color filter unit is disposed above a green sub-pixel, and a blue color filter unit is disposed above a blue sub-pixel. This improves the purity of the emitted color of the display panel PNL, thereby increasing its color gamut and reducing interference from ambient light on normal display. See one example. Figure 2 The color filter layer CFL also has a black matrix layer BM, which can be located between sub-pixels PX to reduce light crosstalk and further reduce reflection of ambient light.

[0058] In one embodiment of this disclosure, see Figure 2The display panel PNL may also include a protective layer OC, which may be disposed on the surface of the display panel PNL away from the substrate SBT to protect the display panel PNL. Figure 2 In the example, the protective layer OC is disposed on the surface of the color filter layer CFL away from the substrate SBT.

[0059] In one embodiment of this disclosure, see [link to relevant documentation]. Figure 1 In the peripheral area BB, along the column direction DV, the display panel PNL has a first bonding area PD1. Each data line DL extends to the edge of the display area AA and is electrically connected to the first bonding area PD1 through fan-out traces. In this way, driving voltage can be applied to the pixel driving circuit PDC through the data lines DL.

[0060] In one embodiment of this disclosure, see [link to relevant documentation]. Figure 3 and Figure 4 The back film layer (BF) is placed on the backlight side of the display panel PNL to protect the display panel PNL.

[0061] In one embodiment of this disclosure, see [link to relevant documentation]. Figure 3 , Figure 4 and Figure 9 The flexible printed circuit board (FPC) is disposed on the side of the back film layer (BF) away from the display panel (PNL). The side of the FPC away from the PNL is defined as the first surface F1. On the first surface F1, the FPC has a second bonding area (PD2) and a driver chip (IC), which do not overlap with the second bonding area (PD2). The orthographic projection of the FPC onto the PNL is within the orthographic projection of the back film layer (BF) onto the PNL. It can be understood that the orthographic projection of the FPC onto the PNL is smaller than the orthographic projection of the back film layer (BF) onto the PNL. Alternatively, the orthographic projection of the FPC onto the PNL is equal to the orthographic projection of the back film layer (BF) onto the PNL.

[0062] In one embodiment of this disclosure, the orthographic projection of the back film layer BF onto the flexible printed circuit board (FPC) at least partially overlaps with the orthographic projection of the display area AA of the display panel PNL onto the FPC. In one example, the orthographic projection of the back film layer BF onto the FPC covers the orthographic projection of the display area AA of the display panel PNL onto the FPC. This achieves comprehensive protection for the display area AA, and the placement of the back film layer BF between the display panel PNL and the FPC accelerates heat dissipation, preventing the heat generated by the FPC from affecting the performance of the display panel PNL.

[0063] In one embodiment of this disclosure, see [link to relevant documentation]. Figure 5 and Figure 6The first bonding area PD1 of the display panel PNL is electrically connected to the second bonding area PD2 of the flexible circuit board FPC using back bonding technology. Specifically, neither the back film layer BF nor the flexible circuit board FPC overlaps with the first bonding area PD1. In the area where the first bonding area PD1 is located, a slot is provided on the backlight side of the display panel PNL, which exposes at least a portion of the first bonding area PD1, so that the electrical connection between the first bonding area PD1 and the second bonding area PD2 can be achieved on the backlight side of the display panel PNL, reducing the bezel area. The back bonding technology can significantly reduce the module bezel, reducing the distance from the display area to the edge of the cover plate layer to 0.4mm.

[0064] Due to the thickness limitations of the back film layer BF and the flexible circuit board FPC, there is a first segmentation surface DC1 between the first bonding area PD1 and the second bonding area PD2 (wherein, the first segmentation surface DC1 includes the side of the back film layer BF near the first bonding area PD1 and the side of the flexible circuit board FPC near the first bonding area PD1).

[0065] To smooth out the first slope DC1, a buffer structure ZCA is set at the first slope DC1. The buffer structure ZCA forms a gentle slope. On the gentle slope, an electrical connection structure DLJ is then prepared to make an electrical connection between the first binding area PD1 and the second binding area PD2.

[0066] In one embodiment of this disclosure, the electrical connection structure DLJ can be formed by printing nano-silver paste using electrohydrodynamic inkjet printing (EHD) technology or by sputtering and depositing nano-silver paste.

[0067] In one embodiment of this disclosure, the material of the buffer structure ZCA is adhesive.

[0068] In related technologies, if too little adhesive is used, it cannot completely cover the first segment surface, forming gaps, which will lead to broken wires in the prepared electrical connection structure; if too much adhesive is used, it will accumulate on the first surface of the flexible circuit board, forming a siphon effect, making it difficult to control the shape of the adhesive and affecting the formation of the electrical connection structure.

[0069] To address the above issues, this disclosure provides the following optimization solutions: In one embodiment of this disclosure, see [link to relevant documentation]. Figure 4 , Figure 7 and Figure 8A buffer structure ZCA is disposed on the display panel PNL and located on the side of the first bonding area PD1 near the second bonding area PD2. One end of the buffer structure ZCA extends continuously to the second bonding area PD2 through the first step surface DC1. The side of the buffer structure ZCA away from the first step surface DC1 forms the second step surface DC2. Along the side near the first bonding area PD1, the distance between the second step surface DC2 and the display panel PNL decreases. Thus, the buffer structure ZCA forms a gentle slope between the first bonding area PD1 and the second bonding area PD2. On the side near the display panel PNL, the acute angle Q between the tangent of the second step surface DC2 and the display panel PNL is no greater than 45°, forming a continuous buffer structure ZCA from the first bonding area PD1 to the second bonding area PD2. An electrical connection structure DLJ is fabricated on the second step surface DC2, and both ends of the electrical connection structure DLJ extend to the first bonding area PD1 and the second bonding area PD2, respectively, and are electrically connected to the first bonding area PD1 and the second bonding area PD2. In this disclosure, the angle at the junction of the second segment DC2 and the display panel PNL is limited to no more than 45°, so that the second segment DC2 and the display panel PNL have a smooth and continuous transition. In this way, the continuity of the electrical connection structure DLJ can be guaranteed during the fabrication of the electrical connection structure DLJ, and no broken wires will occur, thus ensuring the stability of the electrical connection between the first bonding area PD1 and the second bonding area PD2.

[0070] In one embodiment of this disclosure, see [link to relevant documentation]. Figure 4 On the side closest to the display panel PNL, the acute angle Q between the tangent of the second step surface DC2 and the display panel PNL is 13° to 26°. For example, the acute angle Q between the tangent of the second step surface DC2 and the display panel PNL is 13°, 15°, 17°, 19°, 21°, 23°, 26°, etc. Of course, in other embodiments, the acute angle Q between the tangent of the second step surface DC2 and the display panel PNL can also be other angles not shown.

[0071] In one embodiment of this disclosure, the acute angle Q between the tangent at any point on the second segment surface DC2 and the display panel PNL is no greater than 45°. Furthermore, the acute angle Q between the tangent at any point on the second segment surface DC2 and the display panel PNL is always between 13° and 26°. This ensures that the smoothness of the entire second segment surface DC2 is essentially consistent, which is more conducive to forming a continuous electrical connection structure DLJ and guarantees the stability of the electrical connection between the first bonding area PD1 and the second bonding area PD2.

[0072] In one embodiment of this disclosure, the material of the buffer structure ZCA can be glue, which facilitates the preparation of the buffer structure ZCA and is low in cost.

[0073] In one embodiment of this disclosure, in addition to optimizing the second differential surface DC2, the first differential surface DC1 is also structurally optimized to reduce the slope of the first differential surface DC1, which is beneficial to ensure the continuity of the electrical connection structure DLJ while controlling the dose of the buffer structure ZCA.

[0074] In this embodiment, the first step surface DC1 has a first edge L1 close to the display panel PNL and a second edge far from the display panel PNL. The distance between the second edge and the first bonding area PD1 is greater than the distance between the first edge L1 and the first bonding area PD1. It is understood that the entire first step surface DC1 is not perpendicular to the display panel PNL, but rather exhibits an inclined state. This reduces the steepness of the first step surface DC1, making it more gentle. When setting the buffer structure ZCA, the shape of the buffer structure ZCA is smoother, which is more conducive to fabricating a continuous electrical connection structure DLJ, ensuring the conduction stability between the first bonding area PD1 and the second bonding area PD2.

[0075] See the first example in this disclosure. Figure 3 and Figure 4 The first segment surface DC1 is an inclined surface, and the thickness of the first segment surface DC1 gradually decreases along the direction close to the first binding area PD1.

[0076] See the second example in this disclosure. Figure 5 , Figure 6 , Figure 7 and Figure 8 The first segment, DC1, is a stepped surface.

[0077] Optional, see Figure 7 The first step surface DC1 can be a single-layer stepped surface. The first step surface DC1 includes a first surface DC11 and two second surfaces DC12. The two second surfaces DC12 are respectively located on both sides of the first surface DC11 and connected to the first surface DC11. The first surface DC11 is parallel to the display panel PNL, and the second surface DC12 is perpendicular to the display panel PNL (that is, the second surface DC12 intersects the display panel PNL).

[0078] Optionally, the first step surface DC1 can be a single-layer stepped surface. The first step surface DC1 includes a first surface DC11 and two second surfaces DC12. The two second surfaces DC12 are respectively disposed on both sides of the first surface DC11 and connected to the first surface DC11. The first surface DC11 is parallel to the display panel PNL. The second surface DC12 includes a first sub-surface DC121 and a second sub-surface DC122 connected to the first surface DC11. The first sub-surface DC121 is perpendicular to the display panel PNL. The second sub-surface DC122 is inclined and the included angle between the first sub-surface DC121 and the second sub-surface DC122 is greater than 90 degrees.

[0079] Optional, see Figure 5 , Figure 6 and Figure 8 The first segment surface DC1 can be a multi-layered stepped surface, comprising N first surfaces DC11 and (N+1) second surfaces DC12. The first surfaces DC11 and the second surfaces DC12 are staggered, and each first surface DC11 and each second surface DC12 is connected sequentially. The first surface DC11 is parallel to the display panel PNL, and the second surface DC12 is perpendicular to the display panel PNL.

[0080] Optionally, the first stepped surface DC1 can be a multi-layered stepped surface, comprising N first surfaces DC11 and (N+1) second surfaces DC12. The first surfaces DC11 and second surfaces DC12 are staggered, and each first surface DC11 is sequentially connected to each second surface DC12. The first surface DC11 is parallel to the display panel PNL, see [reference needed]. Figure 8At least a portion of the second surface DC12 includes a connected first sub-surface DC121 and a second sub-surface DC122. The first sub-surface DC121 is connected to the first surface DC11. The first sub-surface DC121 is perpendicular to the display panel PNL. The second sub-surface DC122 is tilted, and the angle between the first sub-surface DC121 and the second sub-surface DC122 is greater than 90 degrees (understandably, the second sub-surface DC122 is tilted and extends towards the second bonding area PD2). In this example, the structure of all second surfaces DC12 can be the same or different. For example, all second surfaces DC12 include a connected first sub-surface DC121 and a second sub-surface DC122. The first sub-surface DC121 is connected to the first surface DC11. The first sub-surface DC121 is perpendicular to the display panel PNL. The second sub-surface DC122 is tilted, and the angle between the first sub-surface DC121 and the second sub-surface DC122 is greater than 90 degrees. For another example, a portion of the second surface DC12 includes a connected first sub-surface DC121 and a second sub-surface DC122. The first sub-surface DC121 is connected to the first surface DC11 and is perpendicular to the display panel PNL. The second sub-surface DC122 is tilted, and the angle between the first sub-surface DC121 and the second sub-surface DC122 is greater than 90 degrees. A portion of the second surface DC12 is perpendicular to the display panel PNL.

[0081] In this disclosure, by changing the shape of the first segment DC1 and reducing its slope to make it more gentle, the shape of the buffer structure ZCA becomes smoother when filling the buffer structure ZCA, thereby realizing the fabrication of the continuous electrical connection structure DLJ and ensuring the conduction stability between the first binding region PD1 and the second binding region PD2.

[0082] In this disclosure, the first segment DC1 can be formed by laser etching.

[0083] In one embodiment of this disclosure, in order to control the shape of the buffer structure ZCA on the first surface F1 of the flexible circuit board FPC, a shape control structure XX is provided on the first surface F1. The shape control structure XX can block or guide the buffer structure ZCA, so that its shape on the first surface F1 is controllable. This is more conducive to the fabrication of the electrical connection structure DLJ.

[0084] In this embodiment, see Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 and Figure 14The first surface F1 has a first edge L1 near the first bonding area PD1; in the second bonding area PD2, the flexible circuit board FPC has a plurality of bonding channels PD21 arranged in sequence, each bonding channel PD21 is arranged in parallel and each bonding channel PD21 extends to the first edge L1.

[0085] In one example, the first edge L1 is a straight line. In another example, the first edge L1 is serrated, which increases the contact angle of the buffer structure ZCA, making it less likely for the buffer structure to wet the first surface of the first binding region PD1 during the fabrication of the buffer structure ZCA.

[0086] In this embodiment, at least one shaping structure XX is provided on the flexible circuit board (FPC) in the second bonding area PD2. At least a portion of the shaping structure XX has a buffer structure ZCA on one side, and the buffer structure ZCA is located on the side closer to the first bonding area PD1. The shaping structure XX can be disposed on the bonding channel PD21, or in an area between adjacent bonding channels PD21, etc., and this disclosure does not limit the scope.

[0087] In this embodiment, the distance S between the shape control structure XX and the first edge L1 is no greater than 100 micrometers. This allows for a smaller area covered by the buffer structure over the binding channel PD21, reducing the invalid area of ​​the binding channel PD21 (the area of ​​the binding channel PD21 covered by the buffer structure is the invalid area of ​​the binding channel PD21) and increasing the effective area of ​​the binding channel PD21. For example, the distance S between the shape control structure XX and the first edge L1 can be 20, 30, 40, 60, 80, or 100 micrometers.

[0088] In this embodiment, see Figure 13 and Figure 14 The shaping structure XX can be either a boss or a groove. For example, each shaping structure XX can be a boss. As another example, each shaping structure XX can be a groove. As yet another example, some shaping structures XX can be bosses, and some can be grooves. It is understandable that on the first surface, boss-shaped shaping structures XX and groove-shaped shaping structures XX can coexist.

[0089] In one embodiment of this disclosure, see [link to relevant documentation]. Figure 9In the second bonding area PD2, multiple sets of shape control structures are set on the flexible circuit board (FPC). Each set of shape control structures includes multiple shape control structures XX arranged sequentially along the first direction D1. Each set of shape control structures is arranged sequentially along the second direction D2, and adjacent sets of shape control structures are staggered. In this way, multiple shape control structures XX can be set along the first direction D1, so as to achieve comprehensive shape control of the buffer structure (making the buffer structure controlled on the side of the shape control structure XX closer to the first bonding area PD1), ensuring the continuity of the electrical connection structure DLJ, and facilitating the control of the height of the buffer structure, so as to smoothly realize the electro-hydraulic inkjet printing or sputtering deposition of the electrical connection structure.

[0090] In this embodiment, the distance S between each shape control structure and the first edge L1 is no greater than 100 micrometers. When the first edge L1 is serrated, the maximum distance between the side of the shape control structure XX away from the first binding area PD1 and the first edge L1 is no greater than 100 micrometers.

[0091] In one embodiment of this disclosure, the size of the shape control structure XX can be set according to requirements. For example, along the first direction, the size of the shape control structure XX is 10 micrometers.

[0092] Figure 15 and Figure 16 The electrical connection structure prepared using the scheme in this disclosure, as shown in the figure, has no broken wires and has a good morphology, meeting the requirements.

[0093] In one embodiment of this disclosure, the display module further includes a polarizer POL and a cover plate CG located on the light-emitting side of the display panel PNL. The polarizer POL is disposed close to the display panel PNL, and the polarizer POL and the cover plate CG are bonded and fixed together by an adhesive layer OCA.

[0094] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A display module, characterized in that, include: A display panel, wherein the peripheral area of ​​the display panel has a first bonding area, and at least a portion of the first bonding area is exposed on the backlight side of the display panel; A flexible circuit board is disposed on the backlight side of the display panel and does not overlap with the first bonding area; the flexible circuit board has a second bonding area, and a first step surface is provided between the second bonding area and the first bonding area; A buffer structure is disposed on the display panel and located on the side of the first bonding area closer to the second bonding area; one end of the buffer structure extends continuously to the second bonding area through the first step surface; a second step surface is formed on the side of the buffer structure away from the first step surface; along the side closer to the first bonding area, the distance between the second step surface and the display panel decreases, and on the side closer to the display panel, the acute angle between the tangent of the second step surface and the display panel is not greater than 45°; An electrical connection structure is disposed on the second segment surface; the two sides of the electrical connection structure extend to the first binding area and the second binding area respectively, and are electrically connected to the first binding area and the second binding area.

2. The display module according to claim 1, characterized in that, On the side closest to the display panel, the acute angle between the tangent of the second segment surface and the display panel is 13°~26°.

3. The display module according to claim 2, characterized in that, The display module also includes a back film layer; The back film layer is located between the display panel and the flexible circuit board; the side of the back film layer near the first bonding area and the side of the flexible circuit board near the first bonding area form the first segment surface.

4. The display module according to claim 3, characterized in that, The material of the buffer structure is glue; The first segmental surface includes at least one first surface and at least two second surfaces, with each first surface and each second surface arranged and connected alternately; The first surface is parallel to the display panel, and the second surface intersects with the display panel.

5. The display module according to claim 4, characterized in that, At least a portion of the second surface is perpendicular to the display panel; And / or, at least part of the second surface includes a connected first sub-surface and a second sub-surface, the first sub-surface being disposed close to the display panel and perpendicular to the display panel, and the second sub-surface being disposed at an angle and extending toward the second bonding area.

6. The display module according to claim 3, characterized in that, The material of the buffer structure is glue; the first step surface is an inclined surface, and the thickness of the first step surface gradually decreases along the direction close to the first bonding area.

7. The display module according to any one of claims 3-6, characterized in that, In the second bonding area, at least one shaping structure is provided on the flexible circuit board, at least a portion of the shaping structure has the buffer structure on one side, and the buffer structure is located on the side closer to the first bonding area.

8. The display module according to claim 7, characterized in that, The flexible circuit board has a first surface on the side away from the display panel, and the second bonding area is located on the first surface; the first surface has a first edge on the side near the first bonding area, and the distance between the side of the shaping structure away from the first bonding area and the first edge is no more than 100 micrometers.

9. The display module according to claim 7, characterized in that, The shape control structure is either a boss or a groove.

10. The display module according to claim 7, characterized in that, In the second bonding area, the flexible circuit board is provided with multiple sets of shape control structures; Each control structure group includes multiple control structures arranged sequentially along a first direction; each control structure group is arranged sequentially along a second direction, and two adjacent control structure groups are staggered.

11. The display module according to claim 8, characterized in that, The first edge is serrated; The maximum distance between the side of the shape control structure away from the first binding area and the first edge is no more than 100 micrometers.

12. A display device, characterized in that, It has a display module as described in any one of claims 1-11.

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