Display device and electronic device

Abstract

Disclosed are a display device and an electronic device. The display device includes: a substrate including a light emitting area and a non-light emitting area; a first gate conductive layer and a second gate conductive layer, the first gate conductive layer and the second gate conductive layer being on the substrate and being sequentially stacked; a third gate conductive layer being on the second gate conductive layer and being in contact with at least one of the first gate conductive layer and the second gate conductive layer through a gate contact hole; an interlayer insulating layer being on the third gate conductive layer; a source-drain conductive layer being on the interlayer insulating layer; a gate planar layer being between the interlayer insulating layer and the source-drain conductive layer and being located in the gate contact hole; and a passivation layer being on the source-drain conductive layer, wherein the gate planar layer has an organic pattern shape, and wherein, in a portion overlapping the gate contact hole, the source-drain conductive layer overlaps the gate planar layer.

Description

Cross-references to related applications

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2025-0045072, filed on April 8, 2025, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to display devices and electronic devices using display devices. Background Technology

[0003] With the development of the information society, the demand for display devices for displaying images is increasing in various forms. Display devices can be flat panel display devices such as liquid crystal displays (LCDs), field emission displays (FEDs), and light-emitting displays. Light-emitting displays can include organic light-emitting display devices that include organic light-emitting elements, inorganic light-emitting display devices that include inorganic light-emitting elements such as inorganic semiconductors, and micro-light-emitting display devices or nano-light-emitting display devices that include micro-light-emitting elements or nano-light-emitting elements.

[0004] Recently, due to the application of display devices in various devices, there is a need for display devices suitable for high-resolution electronic devices. Therefore, multiple conductive layers included in the thin-film transistor layer of the display device can be stacked and arranged in a narrow area.

[0005] Furthermore, since display devices are used in various devices, they require high heat resistance and reliability. Therefore, structures that reduce or minimize organic films are being applied to the thin-film transistor layers of display devices. Summary of the Invention

[0006] The aspects and features of embodiments of this disclosure provide a display device suitable for high-resolution electronic devices and having high heat resistance and reliability.

[0007] However, the aspects and features of the embodiments of this disclosure are not limited to those set forth herein. The above and other aspects and features of the embodiments of this disclosure will become more apparent to those skilled in the art from the following detailed description of the disclosure.

[0008] Details of other embodiments are included in the detailed description and accompanying drawings.

[0009] According to one or more embodiments of the present disclosure, a display device includes: a substrate including a light-emitting region and a non-light-emitting region; a first gate conductive layer and a second gate conductive layer, the first gate conductive layer and the second gate conductive layer being stacked sequentially on the substrate; a third gate conductive layer being on the second gate conductive layer and contacting at least one of the first gate conductive layer and the second gate conductive layer through a gate contact hole; an interlayer insulating layer being on the third gate conductive layer; a source-drain conductive layer being on the interlayer insulating layer; a gate planarization layer being between the interlayer insulating layer and the source-drain conductive layer and located in the gate contact hole; and a passivation layer being on the source-drain conductive layer, wherein the gate planarization layer has an organic pattern shape, and wherein the source-drain conductive layer overlaps with the gate planarization layer in the portion overlapping with the gate contact hole.

[0010] In one or more embodiments, the display device further includes: a via layer on the passivation layer and defining a via opening; a light-emitting element on the via layer, the light-emitting element including an anode electrode, a light-emitting layer, and a cathode electrode; and a pixel defining layer on the via layer and the anode electrode and defining a light-emitting opening, the light-emitting opening defining a light-emitting region and a non-light-emitting region, wherein, in the portion overlapping with the light-emitting opening, the anode electrode is in contact with the light-emitting layer, and wherein, in the portion overlapping with the via opening, the passivation layer is exposed.

[0011] In one or more embodiments, the light-emitting opening and the via opening are spaced apart from each other, wherein the pixel defining layer does not overlap with the via opening, and wherein the pixel defining layer has an organic pattern shape.

[0012] In one or more embodiments, the gate planarization layer and the third gate conductive layer that overlap with the gate contact via overlap with the via opening.

[0013] In one or more embodiments, the source-drain conductive layer includes a first source-drain conductive layer and a second source-drain conductive layer stacked sequentially, wherein, in a plan view, the first source-drain conductive layer and the second source-drain conductive layer overlap with a gate contact via.

[0014] In one or more embodiments, the gate planarization layer is in contact with the first source-drain conductive layer, and wherein the gate planarization layer is completely surrounded by the interlayer insulating layer and the first source-drain conductive layer.

[0015] In one or more embodiments, the first source-drain conductive layer includes at least one of a data connection electrode, a power line, and a connection electrode.

[0016] In one or more embodiments, the passivation layer includes: a first passivation layer located between a gate planarization layer and a second source-drain conductive layer; and a second passivation layer covering the second source-drain conductive layer, wherein the gate planarization layer is in contact with an interlayer insulating layer and the first passivation layer, and wherein the gate planarization layer is completely surrounded by the interlayer insulating layer and the first passivation layer.

[0017] In one or more embodiments, the second source-drain conductive layer includes at least one of a data line and a power line.

[0018] In one or more embodiments, the first passivation layer and the second passivation layer comprise inorganic insulating materials.

[0019] In one or more embodiments, the display device further includes: a first semiconductor layer located between a substrate and a first gate conductive layer and including a source region, a channel region, and a drain region; and a second semiconductor layer located between a second gate conductive layer and a third gate conductive layer, wherein the source-drain conductive layer is connected to at least one of the first semiconductor layer and the second semiconductor layer.

[0020] In one or more embodiments, the first semiconductor layer comprises polycrystalline silicon, and wherein the second semiconductor layer comprises an oxide semiconductor.

[0021] In one or more embodiments, in the portion overlapping with the gate contact hole, the interlayer insulating layer includes a step difference, and the thickness of the gate planarization layer is greater than or equal to the height of the step difference in the interlayer insulating layer.

[0022] In one or more embodiments, the gate planarization layer is spaced apart from the third gate conductive layer, and wherein the gate planarization layer contacts and covers a portion of the upper surface of the interlayer insulating layer facing the source-drain conductive layer.

[0023] In one or more embodiments, an electronic device includes: at least one display device including a substrate, the substrate including a light-emitting region and a non-light-emitting region; and at least one of a display module, a processor, a memory, and a power module, the display module, processor, memory, and power module being connected to the display device, wherein the display device further includes: a first gate conductive layer and a second gate conductive layer, the first gate conductive layer and the second gate conductive layer being on the substrate and sequentially stacked; a third gate conductive layer, on the second gate conductive layer and in contact with at least one of the first gate conductive layer and the second gate conductive layer through a gate contact hole; an interlayer insulating layer, on the third gate conductive layer; a source-drain conductive layer, on the interlayer insulating layer; a gate planarization layer, between the interlayer insulating layer and the source-drain conductive layer and located in the gate contact hole; and a passivation layer, on the source-drain conductive layer, wherein the gate planarization layer has an organic pattern shape, and wherein the source-drain conductive layer overlaps with the gate planarization layer in the portion overlapping with the gate contact hole.

[0024] In one or more embodiments, the display device further includes: a via layer on the passivation layer and defining a via opening; a light-emitting element on the via layer, the light-emitting element including an anode electrode, a light-emitting layer, and a cathode electrode; and a pixel defining layer on the via layer and the anode electrode and defining a light-emitting opening, the light-emitting opening defining a light-emitting region and a non-light-emitting region, wherein, in the portion overlapping with the light-emitting opening, the anode electrode is in contact with the light-emitting layer, and wherein, in the portion overlapping with the via opening, the passivation layer is exposed.

[0025] In one or more embodiments, the gate planarization layer and the third gate conductive layer that overlap with the gate contact via overlap with the via opening.

[0026] In one or more embodiments, the source-drain conductive layer includes a first source-drain conductive layer and a second source-drain conductive layer stacked sequentially, wherein, in a plan view, the first source-drain conductive layer and the second source-drain conductive layer overlap with a gate contact via.

[0027] In one or more embodiments, the gate planarization layer is in contact with a first source-drain conductive layer, wherein the gate planarization layer is completely surrounded by an interlayer insulating layer and the first source-drain conductive layer, and wherein the first source-drain conductive layer includes at least one of a data connection electrode, a power line, and a connection electrode.

[0028] In one or more embodiments, the passivation layer includes: a first passivation layer located between a gate planarization layer and a second source-drain conductive layer; and a second passivation layer covering the second source-drain conductive layer, wherein the gate planarization layer is in contact with an interlayer insulating layer and the first passivation layer, wherein the gate planarization layer is completely surrounded by the interlayer insulating layer and the first passivation layer, wherein the second source-drain conductive layer includes at least one of a data line and a power line, and wherein the first passivation layer and the second passivation layer include an inorganic insulating material.

[0029] A display device and an electronic device using the display device according to one or more embodiments may include an organic via layer formed to define a via opening and a gate planarization layer located in a gate contact hole in a portion overlapping with the via opening. Furthermore, a display device and an electronic device using the display device according to one or more embodiments may include a source-drain conductive layer overlapping with the gate planarization layer located in the gate contact hole. Therefore, a display device suitable for high-resolution electronic devices and possessing high thermal reliability can be provided.

[0030] However, the effects, aspects, and features of the embodiments are not limited to those set forth herein. The above and other effects, aspects, and features of the embodiments will become more apparent to those skilled in the art upon which the embodiments pertain by referring to the claims. Attached Figure Description

[0031] The above and other aspects and features of the embodiments of this disclosure will become more apparent from the detailed description of the embodiments with reference to the accompanying drawings, in which: Figure 1 This is a perspective view showing a display device according to one or more embodiments; Figure 2 This is a block diagram illustrating a display device according to one or more embodiments; Figure 3 This is an equivalent circuit diagram showing a sub-pixel according to one or more embodiments; Figure 4 It is a layout diagram of sub-pixels overlapping the display area according to one or more embodiments; Figure 5 It is shown in detail Figure 3 An example layout diagram of the equivalent circuit diagram; Figure 6 It is along Figure 5 A cross-sectional view taken by line X1-X1' in the diagram; Figure 7 It is shown in detail Figure 5 A layout diagram of an example of the first semiconductor layer and the first gate conductive layer; Figure 8 It is shown in detail Figure 5A layout diagram of an example of the second gate conductive layer, the second semiconductor layer, and the third gate conductive layer; Figure 9 It is shown in detail Figure 5 A layout diagram of an example of the first source-drain conductive layer and the second source-drain conductive layer; Figure 10 It is along Figure 5 A cross-sectional view taken from line X3-X3' in the diagram; Figure 11 yes Figure 10 An enlarged cross-sectional view of region "A" in the image; Figure 12 According to one or more other embodiments Figure 10 An enlarged cross-sectional view of region "A"; Figure 13 It is along Figure 5 A cross-sectional view taken from line X5-X5' in the diagram; Figure 14 It is a block diagram of an electronic device according to one or more embodiments; and Figure 15 A schematic diagram of an electronic device according to various embodiments is shown. Detailed Implementation

[0032] This disclosure will now be described more fully herein with reference to the accompanying drawings, in which some embodiments of the disclosure are illustrated. However, this disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art.

[0033] It should also be understood that when a layer is referred to as being "on" another layer or substrate, the layer may be directly on the other layer or substrate, or one or more intervening layers may be present. Throughout the specification, the same reference numerals denote the same components.

[0034] It should be understood that although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, without departing from the teachings of this disclosure, the first element discussed below may be referred to as the second element. Similarly, the second element may also be referred to as the first element.

[0035] Furthermore, the phrase "in a plan view" means when viewing a portion of an object from above, and the phrase "in a schematic cross-sectional view" means when viewing a schematic cross-section obtained by vertically cutting a portion of an object from the side. The terms "overlapping with" or "overlapping" mean that the first object may be above or below the second object, or to one side of the second object, and vice versa. Furthermore, the term "overlapping with" can include layering, stacking, facing or confronting, extending over (overlapping), covering or partially covering, or any other suitable term as will be understood and appreciated by one of ordinary skill in the art. The expression "not overlapping with" can include meanings such as "separated from," "displaced from," or "offset from," and any other suitable equivalent meaning as will be understood and appreciated by one of ordinary skill in the art. The terms "facing" and "confronting" can mean that the first object may be directly or indirectly opposite the second object. In the case where a third object is located between the first and second objects, the first and second objects can be understood as indirectly opposite each other, but still facing each other.

[0036] For ease of description, spatial relative terms such as “below,” “under,” “down,” “above,” and / or “above” may be used herein to describe the relationship between one element or component and another, as shown in the accompanying drawings. It will be understood that spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the drawings. For example, in the case where the device shown in the drawings is flipped, a device positioned “below” or “under” another device may be placed “above” another device. Therefore, the descriptive term “below” can include both a lower and an upper position. The device may also be oriented in other directions, and therefore spatial relative terms may be interpreted differently depending on the orientation.

[0037] When an element is referred to as being “connected” or “coupled” to another element, the element may be “directly connected” or “directly coupled” to the other element, or “electrically connected” or “electrically coupled” to the other element, with one or more intermediary elements between the element and the other element. It will be further understood that when the terms “comprises,” “comprising,” “has,” “have,” and / or “includes,” they may indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not preclude the presence or addition of other features, integrals, steps, operations, elements, components, and / or any combinations thereof.

[0038] Given the measurements discussed and the errors associated with the measurement of a particular quantity (e.g., limitations of the measurement system), the terms “about” or “approximately” as used herein include the stated value and mean within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art. For example, “about” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0039] In the specification and claims, the term "and / or" is intended, for the purposes of its meaning and interpretation, to include any combination of the terms "and" and "or". For example, "A and / or B" can be understood to mean "A, B, or A and B". The terms "and" and "or" can be used in the sense of conjunction or disjunction and can be understood to be equivalent to "and / or". In the specification and claims, the phrase "at least one of..." is intended, for the purposes of its meaning and interpretation, to include the meaning of "at least one of the group consisting of...". For example, "at least one of A and B" can be understood to mean "A, B, or A and B".

[0040] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that, unless a term is interpreted in an idealized or overly formal sense, a term as defined in a general dictionary should be interpreted as having a meaning consistent with its meaning in the context of the relevant field and is explicitly defined herein.

[0041] It will be appreciated by those skilled in the art that, in view of the entirety of this disclosure, unless otherwise stated or implied, each suitable feature of the various embodiments of this disclosure may be combined in part or in whole, or combined with one another, and may be technically interlocked and operated in a variety of suitable manners, and each embodiment may be implemented independently of one another or in any suitable combination with one another.

[0042] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0043] Figure 1 This is a perspective view showing a display device according to one or more embodiments.

[0044] Reference Figure 1The display device 10 is a device for displaying moving images and / or still images, and can be used as a display screen for each of a variety of products such as televisions, laptops, monitors, billboards and / or Internet of Things (IoT) devices, as well as portable electronic devices such as mobile phones, smartphones, tablet PCs, smartwatches, watch phones, mobile communication terminals, e-notebooks, e-books, portable multimedia players (PMPs), navigation devices and / or ultra-mobile PCs (UMPCs).

[0045] Display device 10 may be a light-emitting display device, such as an organic light-emitting display device using organic light-emitting diodes (OLEDs), a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including inorganic semiconductors, and a micro-light-emitting display device or nano-light-emitting display device using micro-light-emitting diodes or nano-light-emitting diodes (micro-LEDs or nano-LEDs). In the following description, display device 10 is primarily described as an organic light-emitting display device, but this disclosure is not limited thereto.

[0046] The display device 10 may include a display panel 100, a plurality of source drive circuits 200, a plurality of flexible circuit boards 300, a timing control circuit (e.g., a timing controller) 400, a power supply circuit (e.g., a power supply unit) 500, and a circuit board 600.

[0047] The display panel 100 can be formed as a rectangular plane having a long side in a first direction DR1 and a short side in a second direction DR2 intersecting the first direction DR1. The corners where the long side in the first direction DR1 and the short side in the second direction DR2 intersect can be rounded to have curvature, or can be formed at right angles. The planar shape of the display panel 100 is not limited to a rectangular shape, and can be formed as another polygonal shape, circular shape, or elliptical shape. The display panel 100 can be formed as flat, but is not limited to this. For example, the display panel 100 may include curved surface portions formed at its left and right distal ends and having constant or variable curvature. Furthermore, the display panel 100 can be flexibly configured as bendable, flexible, foldable, and / or rollable.

[0048] The display panel 100 may include a display area DA for displaying images and a non-display area NDA disposed around the display area DA along the edge or periphery of the display area DA.

[0049] The display area DA can occupy most of the display panel 100. The display area DA can be set at the center of the display panel 100. Multiple pixels can be set in the display area DA to display images. Pixels will be described later.

[0050] The non-display area NDA can be an area where no image is displayed. The non-display area NDA can be an edge area of ​​the display panel 100. The non-display area NDA can be an area outside the display area DA. The non-display area NDA can be set to surround the display area DA.

[0051] Display pads can be located in the non-display area NDA to connect to multiple flexible circuit boards 300. Display pads can also be located at the edge of one side of the display panel 100.

[0052] Each of the source drive circuits 200 may be formed as an integrated circuit (IC) and attached to a corresponding flexible circuit board 300, but this disclosure is not limited thereto. Each of the source drive circuits 200 may be attached to the display panel 100 by a glass-on-chip (COG) method, a plastic-on-chip (COP) method, or an ultrasonic bonding method.

[0053] Each of the plurality of flexible circuit boards 300 may be disposed on a display pad located at the edge on one side of the display panel 100. Each of the plurality of flexible circuit boards 300 may be attached to the display pad using a conductive adhesive component such as an anisotropic conductive film. Therefore, the plurality of flexible circuit boards 300 may be electrically connected to the signal lines of the display panel 100. The plurality of flexible circuit boards 300 may be flexible films such as flexible printed circuit boards (FPCBs) or chip-on-film (COF).

[0054] The timing control circuit 400 can generate timing control signals for controlling the timing of the scan drive circuit, the light-emitting drive circuit, and the source control circuit. The power supply circuit 500 can generate multiple power voltages for driving the display panel 100 based on input power from an external source. Each of the timing control circuit 400 and the power supply circuit 500 can be formed as an integrated circuit (IC) and attached to the circuit board 600.

[0055] Circuit board 600 can be connected to one side of each of the plurality of flexible circuit boards 300. Circuit board 600 can be a rigid printed circuit board.

[0056] Figure 2 This is a block diagram illustrating a display device according to one or more embodiments.

[0057] Reference Figure 2 According to one or more embodiments, the display device 10 may include a plurality of sub-pixels SPX, a plurality of scan lines SL, a plurality of emission control lines EML, and a plurality of data lines DL in the portion overlapping with the display area DA. The plurality of scan lines SL may include a plurality of scan write lines GWL, a plurality of scan control lines GCL, a plurality of scan initialization lines GIL, and a plurality of bias scan lines GBL.

[0058] Multiple sub-pixels SPX can be arranged in a matrix along the first direction DR1 and the second direction DR2.

[0059] Each of the multiple sub-pixels SPX can be connected to one of the multiple scan write lines GWL, one of the multiple scan control lines GCL, one of the multiple scan initialization lines GIL, one of the multiple bias scan lines GBL, one of the multiple transmit control lines EML, and one of the multiple data lines DL.

[0060] Each of the multiple sub-pixels SPX can receive a data voltage from the data line DL according to the scan write signal from the scan write line GWL, and can emit light from the light-emitting element according to the data voltage.

[0061] Multiple scan lines SL and multiple transmit control lines EML can extend along the first direction DR1 and can be arranged along the second direction DR2. Multiple data lines DL can extend along the second direction DR2 and can be arranged along the first direction DR1.

[0062] The display device 10 according to one or more embodiments may include a first scan driving circuit GDC1, a second scan driving circuit GDC2, a first light-emitting driving circuit EDC1, and a second light-emitting driving circuit EDC2 in the portion overlapping with the non-display area NDA.

[0063] Each of the first scan drive circuit GDC1 and the second scan drive circuit GDC2 may include a scan write drive circuit GWC, a scan control drive circuit GCC, a scan initialization drive circuit GIC, and a bias scan drive circuit GBC. Figure 2 The scan write drive circuit GWC, scan control drive circuit GCC, scan initialization drive circuit GIC, and bias scan drive circuit GBC are shown arranged in sequence from the display area DA to the edge of the display panel 100, but this disclosure is not limited thereto.

[0064] The scan write driver circuit GWC can receive the write timing signal GWTS from the timing control circuit 400. The scan write driver circuit GWC can generate scan write signals according to the write timing signal GWTS and output the scan write signals sequentially to the scan write line GWL.

[0065] The scan control drive circuit GCC can receive the control timing signal GCTS from the timing control circuit 400. The scan control drive circuit GCC can generate scan control signals according to the control timing signal GCTS and output the scan control signals sequentially to the scan control line GCL.

[0066] The scan initialization driver circuit GIC can receive the initialization timing signal GITS from the timing control circuit 400. The scan initialization driver circuit GIC can generate scan initialization signals according to the initialization timing signal GITS and output the scan initialization signals sequentially to the scan initialization line GIL.

[0067] The bias scan drive circuit GBC can receive the bias timing signal GBTS from the timing control circuit 400. The bias scan drive circuit GBC can generate a bias scan signal according to the bias timing signal GBTS and output the bias scan signal sequentially to the bias scan line GBL.

[0068] Each of the first light-emitting driving circuit EDC1 and the second light-emitting driving circuit EDC2 can receive a light-emitting timing signal EMTS from the timing control circuit 400. Each of the first light-emitting driving circuit EDC1 and the second light-emitting driving circuit EDC2 can generate a transmission control signal based on the light-emitting timing signal EMTS and sequentially output the transmission control signal to the transmission control line EML.

[0069] The data driving circuit 200G includes multiple source driving circuits 200. Each of the multiple source driving circuits 200 can receive digital video data DATA and a data timing signal DCS from the timing control circuit 400. Each of the multiple source driving circuits 200 converts the digital video data DATA into an analog data voltage according to the data timing signal DCS and outputs the analog data voltage to the data line DL. In this case, a sub-pixel SPX can be selected by scanning the write signal, and the analog data voltage can be supplied to the selected sub-pixel SPX.

[0070] The timing control circuit 400 can receive digital video data DATA and timing signals TS from an external source. Based on the timing signals TS, the timing control circuit 400 generates a write timing signal GWTS, a control timing signal GCTS, an initialization timing signal GITS, a bias timing signal GBTS, and an emission timing signal EMTS. The timing control circuit 400 can output the write timing signal GWTS to the scan write driver circuit GWC and the control timing signal GCTS to the scan control driver circuit GCC. Furthermore, the timing control circuit 400 can output the initialization timing signal GITS to the scan initialization driver circuit GIC and the bias timing signal GBTS to the bias scan driver circuit GBC. The timing control circuit 400 can output the emission timing signal EMTS to the first emission driver circuit EDC1 and the second emission driver circuit EDC2. Additionally, the timing control circuit 400 can output the digital video data DATA and the data timing signal DCS to the source driver circuit 200.

[0071] The power supply circuit 500 can generate multiple panel driving voltages based on the power voltage from an external source. For example, the power supply circuit 500 can generate a first power voltage VSS, a second power voltage VDD, a third power voltage VINT, a fourth power voltage VAINT, and a fifth power voltage VOB, and supply the generated power voltages to the display panel 100.

[0072] The first electrical voltage VSS can be a low-potential voltage, and the second electrical voltage VDD can be a high-potential voltage. The third electrical voltage VINT can be the first initialization voltage, the fourth electrical voltage VAINT can be the second initialization voltage, and the fifth electrical voltage VOB can be the third initialization voltage. The third electrical voltage VINT, the fourth electrical voltage VAINT, and the fifth electrical voltage VOB can be voltages higher than the first electrical voltage VSS and lower than the second electrical voltage VDD.

[0073] Figure 3 This is an equivalent circuit diagram showing a sub-pixel according to one or more embodiments.

[0074] Reference Figure 3 as well as Figure 1 and Figure 2 According to one or more embodiments, the sub-pixel SPX can be connected to the scan write line GWL, scan initialization line GIL, scan control line GCL, bias scan line GBL, emission control line EML, and data line DL.

[0075] According to one or more embodiments, a sub-pixel SPX may include a first transistor T1 (e.g., a driving transistor), a switching element, a capacitor Cst, and a light-emitting element LE. The switching element includes a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8.

[0076] The first transistor T1 controls the source-drain current (hereinafter referred to as the "drive current") according to the voltage applied to the gate electrode of the first transistor T1. The gate electrode of the first transistor T1 can be connected to the second power line VDL to which the second power voltage VDD is applied.

[0077] The light-emitting element LE can be an organic light-emitting diode (OLED). The light-emitting element LE emits light according to the driving current. The brightness of the light-emitting element LE can be proportional to the driving current. The first electrode of the light-emitting element LE can be connected to the first electrode of the seventh transistor T7 and the second electrode of the sixth transistor T6. The second electrode of the light-emitting element LE can be connected to the first electric field line VSL to which the first electric voltage VSS is applied. The first electrode of the light-emitting element LE can be an anode electrode or a pixel electrode, and the second electrode of the light-emitting element LE can be a cathode electrode.

[0078] The second transistor T2 is turned on by a scan write signal that applies a gate on-state voltage to the scan write line GWL, and connects the data line DL to the first electrode of the first transistor T1. As a result, during the period when the second transistor T2 is on, a data voltage can be applied to the first electrode of the first transistor T1. The gate electrode of the second transistor T2 can be connected to the scan write line GWL, the first electrode of the second transistor T2 can be connected to the data line DL, and the second electrode of the second transistor T2 can be connected to the first electrode of the first transistor T1.

[0079] The third transistor T3 is turned on by a scan control signal that applies a gate on-state voltage to the scan control line GCL, and connects the gate electrode and the second electrode of the first transistor T1 to each other. As a result, during the period when the third transistor T3 is on, the first transistor T1 can operate like a diode (e.g., the first transistor T1 can be connected in a diode configuration). The gate electrode of the third transistor T3 can be connected to the scan control line GCL, the first electrode of the third transistor T3 can be connected to the second electrode of the first transistor T1, and the second electrode of the third transistor T3 can be connected to the gate electrode of the first transistor T1.

[0080] The fourth transistor T4 is turned on by a scan initialization signal, which applies a gate-on voltage to the scan initialization line GIL, and connects the gate electrode of the first transistor T1 to the third power line VIL. During the period when the fourth transistor T4 is turned on, the gate electrode of the first transistor T1 can be initialized to the third power voltage VINT from the third power line VIL. The gate electrode of the fourth transistor T4 can be connected to the scan initialization line GIL, the first electrode of the fourth transistor T4 can be connected to the gate electrode of the first transistor T1, and the second electrode of the fourth transistor T4 can be connected to the third power line VIL.

[0081] The fifth transistor T5 is turned on by an emitter control signal that applies a gate turn-on voltage to the emitter control line EML and connects the second power line VDL to the first electrode of the first transistor T1. During the period when the fifth transistor T5 is turned on, the second power voltage of the second power line VDL ( Figure 2 The second power voltage (VDD) can be applied to the first electrode of the first transistor T1. The gate electrode of the fifth transistor T5 can be connected to the emitter control line EML, the first electrode of the fifth transistor T5 can be connected to the second power line VDL, and the second electrode of the fifth transistor T5 can be connected to the first electrode of the first transistor T1.

[0082] The sixth transistor T6 is turned on by an emission control signal with a gate turn-on voltage applied to the emission control line EML, and connects the second electrode of the first transistor T1 to the first electrode of the light-emitting element LE. During the period when the sixth transistor T6 is turned on, the drive current of the first transistor T1 can be supplied to the light-emitting element LE. The gate electrode of the sixth transistor T6 can be connected to the emission control line EML, the first electrode of the sixth transistor T6 can be connected to the second electrode of the first transistor T1, and the second electrode of the sixth transistor T6 can be connected to the first electrode of the light-emitting element LE.

[0083] The seventh transistor T7 is turned on by a bias scan signal applied to the gate turn-on voltage of the bias scan line GBL, and connects the first electrode of the light-emitting element LE to the fourth power line VAIL. During the period when the seventh transistor T7 is turned on, the first electrode of the light-emitting element LE can be initialized to the fourth power voltage from the fourth power line VAIL. Figure 2 The fourth power line voltage (VAINT) is used. The gate electrode of the seventh transistor T7 can be connected to the bias scan line GBL, the first electrode of the seventh transistor T7 can be connected to the first electrode of the light-emitting element LE, and the second electrode of the seventh transistor T7 can be connected to the fourth power line VAIL.

[0084] The eighth transistor T8 is turned on by a bias scan signal applied to the gate turn-on voltage of the bias scan line GBL, and connects the first electrode of the first transistor T1 to the fifth power line VOBL. During the period when the eighth transistor T8 is turned on, the first electrode of the first transistor T1 can be initialized to the fifth power voltage from the fifth power line VOBL. Figure 2 The fifth power voltage VOB). The gate electrode of the eighth transistor T8 can be connected to the bias scan line GBL, the first electrode of the eighth transistor T8 can be connected to the first electrode of the first transistor T1, and the second electrode of the eighth transistor T8 can be connected to the fifth power line VOBL.

[0085] A capacitor Cst is formed between the gate electrode of the first transistor T1 and the second electric field line VDL. One electrode of the capacitor Cst can be connected to the gate electrode of the first transistor T1, and the other electrode of the capacitor Cst can be connected to the second electric field line VDL.

[0086] The first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can be formed as a P-type metal-oxide-semiconductor field-effect transistor (MOSFET).

[0087] As an example, the active layer of each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may comprise polysilicon. Furthermore, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may be turned on by a signal with a low gate voltage.

[0088] Furthermore, the third transistor T3 and the fourth transistor T4 can be formed as N-type metal-oxide-semiconductor field-effect transistors (MOSFETs). In this case, the active layer of each of the third transistor T3 and the fourth transistor T4 can include oxide semiconductor. Additionally, the third transistor T3 and the fourth transistor T4 can be turned on by a signal with a high gate voltage.

[0089] Figure 4 It is a layout diagram of sub-pixels that overlap with the display area according to one or more embodiments.

[0090] Reference Figure 4 According to one or more embodiments, a pixel PX may include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3 located in a portion overlapping with the display area DA. The first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may be spaced apart from each other (e.g., spaced apart).

[0091] Pixel PX may include a light-emitting region EA. The light-emitting region EA may be the portion from which light is emitted. As an example, the first sub-pixel SPX1 may include a first light-emitting region EA1, the second sub-pixel SPX2 may include a second light-emitting region EA2, and the third sub-pixel SPX3 may include a third light-emitting region EA3.

[0092] In one or more embodiments, the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 can emit light of different colors. For example, the first light-emitting region EA1 can emit red light, the second light-emitting region EA2 can emit green light, and the third light-emitting region EA3 can emit blue light. However, the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 are not limited thereto, and according to embodiments, the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 can also emit the same color.

[0093] The display device 10 according to one or more embodiments may include a non-emitting region NLA in the portion overlapping with the display area DA. The non-emitting region NLA may be positioned around each of the first emitting region EA1, the second emitting region EA2, and the third emitting region EA3 (e.g., around each of the first emitting region EA1, the second emitting region EA2, and the third emitting region EA3), and may help prevent color mixing of light emitted from each of the first emitting region EA1, the second emitting region EA2, and the third emitting region EA3.

[0094] In one or more embodiments, the light-emitting region EA and the non-light-emitting region NLA may be defined by a light-emitting opening OP2. The light-emitting opening OP2 may be defined by a pixel-defined layer as described later. Figure 6 The "pixel-limited layer 153" in the text is limited.

[0095] Figure 5 It is shown in detail Figure 3 The layout diagram of the equivalent circuit diagram is shown in the example, and Figure 6 It is along Figure 5 The cross-sectional view taken by line X1-X1' in the diagram.

[0096] Reference Figure 5 and Figure 6 as well as Figures 1 to 4 The display device 10 may include a substrate SUB, a thin-film transistor layer (TFTL), and a display element layer (DIL) stacked on a third-direction DR3. The aforementioned plurality of first transistors T1 to eighth transistors T8 and a plurality of conductive lines may be positioned in the thin-film transistor layer (TFTL).

[0097] like Figure 5 As shown, in one or more embodiments, the gate electrode G1 of the first transistor T1 can be connected to the third drain region D3 of the third transistor T3 and the fourth source region S4 of the fourth transistor T4 via the second connection electrode BE2 passing through the first contact hole CNH1.

[0098] The first source region S1 of the first transistor T1 can be connected to the second drain region D2 of the second transistor T2, and the first drain region D1 of the first transistor T1 can be connected to the sixth source region S6 of the sixth transistor T6. Furthermore, the first drain region D1 of the first transistor T1 can be connected to the third source region S3 of the third transistor T3 via the third connection electrode BE3.

[0099] The gate electrode G2 of the second transistor T2 can be connected to the scan write line GWL extending in the first direction DR1, and the second source region S2 can be connected through the first contact hole CNH1 (see, for example, see...). Figure 6The data connection electrode DCE is connected to the data connection electrode DCE. Furthermore, the data connection electrode DCE can be connected to the data line DL extending in the second direction DR2 via the source-drain contact hole CNH4. The second drain region D2 of the second transistor T2 can be connected to the first source region S1 of the first transistor T1.

[0100] The gate electrode G3 of the third transistor T3 can be connected to the scan control line GCL extending in the first direction DR1. The third source region S3 can be connected to the first drain region D1 of the first transistor T1 through the third connection electrode BE3, and the third drain region D3 can be connected to the gate electrode G1 of the first transistor T1 through the second connection electrode BE2.

[0101] The gate electrode G4 of the fourth transistor T4 can be connected to the scan initialization line GIL extending in the first direction DR1, and the fourth source region S4 can be connected to the gate electrode G1 of the first transistor T1 via the second connection electrode BE2. Furthermore, the fourth source region S4 can be connected to the third drain region D3. The fourth drain region D4 can be connected to the third electric field line VIL extending in the first direction DR1 and can be connected to the fourth drain region D4 of an adjacent sub-pixel via the first connection electrode BE1.

[0102] One electrode of capacitor Cst can be connected to the gate electrode G1 of the first transistor T1, and the other electrode of capacitor Cst can be connected to the second vertical electric field line V_VDL.

[0103] The gate electrode G5 of the fifth transistor T5 can be connected to the emitter control line EML through the gate contact hole CNH3, and the fifth source region S5 can be connected to the second horizontal electric field line HVDL through the first contact hole CNH1. Furthermore, the fifth source region S5 can be connected to the second vertical electric field line V_VDL through the source-drain contact hole CNH4. The fifth drain region D5 can be connected to the first source region S1 of the first transistor T1.

[0104] The gate electrode G6 of the sixth transistor T6 can be connected to the emitter control line EML, the sixth source region S6 can be connected to the first drain region D1 of the first transistor T1, and the sixth drain region D6 can be connected to the anode electrode AE ​​of the light-emitting element LE, which will be described later, through the first contact hole CNH1.

[0105] The gate electrode G7 of the seventh transistor T7 can be connected to the bias scan line GBL extending in the first direction DR1, and the seventh source region S7 can be connected to the anode electrode AE ​​of the light-emitting element LE through the first contact hole CNH1. Furthermore, the seventh source region S7 can be connected to the sixth drain region D6. The seventh drain region D7 can be connected to the fourth electric field line VAIL extending in the first direction DR1 through the first contact hole CNH1.

[0106] The gate electrode G8 of the eighth transistor T8 can be connected to the bias scan line GBL, the eighth source region S8 can be connected to the first source region S1 of the first transistor T1, and the eighth drain region D8 can be connected to the fifth electric field line VOBL extending in the first direction DR1 through the first contact hole CNH1.

[0107] In one or more embodiments, in a plan view, the anode electrode AE ​​of the light-emitting element LE may be located in a portion overlapping with the sixth drain region D6 of the sixth transistor T6, the seventh source region S7 of the seventh transistor T7, and the gate electrode G1 and the first drain region D1 of the first transistor T1.

[0108] like Figure 6 As shown, the substrate SUB can be a rigid substrate or a flexible substrate that can be bent, folded, and / or rolled. The substrate SUB may include insulating materials such as glass, quartz, and / or polymer resins. Examples of polymer resins may include polyethersulfone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), cellulose acetate propionate (CAP), and / or combinations thereof. Alternatively, the substrate SUB may also include metallic materials.

[0109] A thin-film transistor layer (TFTL) can be positioned on a substrate (SUB). A TFTL may include multiple insulating layers, multiple semiconductor layers, and multiple conductive layers.

[0110] As an example, the plurality of insulating layers included in the thin-film transistor layer (TFTL) may include a buffer layer 131, a first gate insulating layer 133, a second gate insulating layer 135, a first interlayer insulating layer 137, a third gate insulating layer 139, a second interlayer insulating layer 141, a first passivation layer 143, and a second passivation layer 145.

[0111] The multiple insulating layers included in the thin-film transistor layer (TFTL) may comprise inorganic insulating materials. As an example, the inorganic insulating material may include silicon nitride (SiN). x ), silicon oxynitride (SiON), silicon oxide (SiO) x Titanium oxide (TiO) x ) and / or aluminum oxide (AlO) x ).

[0112] Furthermore, a thin-film transistor layer (TFTL) according to one or more embodiments may include a first semiconductor layer SCL1, a first gate conductive layer CDL1, a second gate conductive layer CDL2, a second semiconductor layer SCL2, a third gate conductive layer CDL3, a first source-drain conductive layer SD1, and a second source-drain conductive layer SD2, which are sequentially stacked. In an embodiment, the source-drain conductive layer may include the first source-drain conductive layer SD1 and the second source-drain conductive layer SD2, which are sequentially stacked. In an embodiment, the source-drain conductive layer may be connected to at least one of the first semiconductor layer SCL1 and the second semiconductor layer SCL2.

[0113] A buffer layer 131 according to one or more embodiments may be disposed on a substrate SUB. The buffer layer 131 may protect the conductive layer included in the thin-film transistor layer (TFTL) from moisture that permeates through the moisture-permeable substrate SUB.

[0114] Figure 7 It is shown in detail Figure 5 A layout diagram of an example of the first semiconductor layer and the first gate conductive layer.

[0115] Reference Figures 5 to 7 The first semiconductor layer SCL1 may be located on the buffer layer 131. The first semiconductor layer SCL1 may include polycrystalline silicon (e.g., low-temperature polycrystalline silicon), monocrystalline silicon, or amorphous silicon.

[0116] In one or more embodiments, the first semiconductor layer SCL1 may include the first active layer ACT1 of the first transistor T1, the second active layer ACT2 of the second transistor T2, the fifth active layer ACT5 of the fifth transistor T5, the sixth active layer ACT6 of the sixth transistor T6, the seventh active layer ACT7 of the seventh transistor T7, and the eighth active layer ACT8 of the eighth transistor T8.

[0117] The first active layer ACT1 may include a first channel region CHA1, a first source region S1, and a first drain region D1, and the first channel region CHA1 may overlap with the gate electrode G1 included in the first gate conductive layer CDL1 on a third direction DR3, which is the thickness direction of the substrate SUB. In this specification, the third direction DR3 may be defined as the thickness direction of the substrate SUB or the display device 10 (see [reference]). Figure 1 (in the thickness direction)

[0118] The first source region S1 can be disposed on one side of the first channel region CHA1, and the first drain region D1 can be disposed on the other side of the first channel region CHA1. The first source region S1 and the first drain region D1 can be regions on the third-direction DR3 that do not overlap with the gate electrode G1. The first source region S1 and the first drain region D1 can be regions that are conductive by doping the semiconductor material with ions.

[0119] The second active layer ACT2 may include a second channel region CHA2, a second source region S2, and a second drain region D2. The second channel region CHA2 may be a region on a third direction DR3, which is the thickness direction of the substrate SUB, that overlaps with the gate electrode G2 included in the first gate conductive layer CDL1.

[0120] The second source region S2 can be disposed on one side of the second channel region CHA2, and the second drain region D2 can be disposed on the other side of the second channel region CHA2. The second source region S2 and the second drain region D2 can be regions on the third-direction DR3 that do not overlap with the gate electrode G2. The second source region S2 and the second drain region D2 can be regions that are conductive by doping the semiconductor material with ions.

[0121] The sixth active layer ACT6 may include a sixth channel region CHA6, a sixth source region S6, and a sixth drain region D6. The sixth channel region CHA6 may be a region on the third direction DR3, which is the thickness direction of the substrate SUB, that overlaps with the gate electrode G6 included in the first gate conductive layer CDL1.

[0122] The sixth source region S6 can be disposed on one side of the sixth channel region CHA6, and the sixth drain region D6 can be disposed on the other side of the sixth channel region CHA6. The sixth source region S6 and the sixth drain region D6 can be regions on the third-direction DR3 that do not overlap with the gate electrode G6. The sixth source region S6 and the sixth drain region D6 can be regions that become conductive by doping the semiconductor material with ions.

[0123] The fifth transistor T5, the seventh transistor T7, and the eighth transistor T8 can have essentially the same structure as the first transistor T1, the second transistor T2, and the sixth transistor T6. Redundant details will be omitted.

[0124] The first gate insulating layer 133 may be located on the first semiconductor layer SCL1 and on the buffer layer 131. The first gate insulating layer 133 may completely cover the first semiconductor layer SCL1 and the buffer layer 131.

[0125] The first gate conductive layer CDL1 can be positioned on the first gate insulating layer 133. The first gate conductive layer CDL1 can be formed as a single layer or multiple layers made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) and / or alloys thereof.

[0126] In one or more embodiments, the first gate conductive layer CDL1 may include a gate electrode contained in each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8.

[0127] In one or more embodiments, the gate electrode G1 of the first transistor T1 may overlap with the first channel region CHA1 of the first transistor T1, the gate electrode G2 of the second transistor T2 may overlap with the second channel region CHA2 of the second transistor T2, and the gate electrode G6 of the sixth transistor T6 may overlap with the sixth channel region CHA6 of the sixth transistor T6. Redundant details will be omitted.

[0128] Furthermore, the first gate conductive layer CDL1 may include a third power line VIL, a scan write line GWL, and a bias scan line GBL. The third power line VIL, the scan write line GWL, and the bias scan line GBL may extend in the first direction DR1.

[0129] In one or more embodiments, the gate electrode G2 of the second transistor T2 may be connected to the scan write line GWL, and the gate electrodes G7 of the seventh transistor T7 and G8 of the eighth transistor T8 may be connected to the bias scan line GBL.

[0130] The second gate insulating layer 135 can be positioned on the first gate conductive layer CDL1 and on the first gate insulating layer 133. The second gate insulating layer 135 can completely cover the first gate conductive layer CDL1 and the first gate insulating layer 133.

[0131] Reference Figures 5 to 7 The display device 10 according to one or more embodiments may include a valley region located around a plurality of first transistors T1 to eighth transistors T8. The valley region may be a portion of the first semiconductor layer SCL1 and the first gate conductive layer CDL1 that does not overlap. The accompanying drawings show the valley region facing each other on one side and the other side in the second direction DR2, but this disclosure is not limited thereto. According to embodiments, the arrangement of the valley region can be varied.

[0132] Figure 8 It is shown in detail Figure 5A layout diagram of an example of the second gate conductive layer, the second semiconductor layer, and the third gate conductive layer. Figure 8 It shows in Figure 7 The layout diagram shows the additional formation of a second gate conductive layer CDL2, a second semiconductor layer SCL2, and a third gate conductive layer CDL3 on the layout.

[0133] Reference Figures 5 to 8 The second gate conductive layer CDL2 can be positioned on the second gate insulating layer 135. The second gate conductive layer CDL2 can be formed as a single layer or multiple layers made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) and / or alloys thereof.

[0134] In one or more embodiments, the second gate conductive layer CDL2 may include a capacitor electrode CAE, a first lower electrode BG1, a second lower electrode BG2, and a fifth electric field line VOBL.

[0135] The capacitor electrode CAE can overlap with the gate electrode G1 of the first transistor T1. Because the second gate insulating layer 135 has a dielectric constant, a capacitor Cst can be formed between the gate electrode G1 and the capacitor electrode CAE (see [link to relevant documentation]). Figure 3 ).

[0136] The first lower electrode BG1 can be located in the portion overlapping with the third channel region CHA3 of the third transistor T3 and the gate electrode G3 of the third transistor T3. The first lower electrode BG1 can be used as a back gate electrode to adjust the characteristics of the third transistor T3.

[0137] The second lower electrode BG2 can be located in the portion overlapping with the fourth channel region CHA4 and the gate electrode G4 of the fourth transistor T4. The second lower electrode BG2 can be used as a back gate electrode to modulate the characteristics of the fourth transistor T4.

[0138] The first interlayer insulating layer 137 can be positioned on the second gate conductive layer CDL2 and on the second gate insulating layer 135. The first interlayer insulating layer 137 can completely cover the second gate conductive layer CDL2 and the second gate insulating layer 135.

[0139] The second semiconductor layer SCL2 may be located on the first interlayer insulating layer 137. The second semiconductor layer SCL2 may include an oxide semiconductor. For example, the second semiconductor layer SCL2 may include indium gallium zinc oxide (IGZO) (indium (In), gallium (Ga), zinc (Zn) and oxygen (O)), indium gallium zinc tin oxide (IGZTO) (indium (In), gallium (Ga), zinc (Zn), tin (Sn) and oxygen (O)) and / or indium gallium tin oxide (IGTO) (indium (In), gallium (Ga), tin (Sn) and oxygen (O)).

[0140] In one or more embodiments, the second semiconductor layer SCL2 may include the third active layer ACT3 of the third transistor T3 and the fourth active layer ACT4 of the fourth transistor T4.

[0141] The third active layer ACT3 may include a third channel region CHA3, a third source region S3, and a third drain region D3, and the third channel region CHA3 may be a region that overlaps with the gate electrode G3 and the first lower electrode BG1 included in the third gate conductive layer CDL3.

[0142] The third source region S3 can be disposed on one side of the third channel region CHA3, and the third drain region D3 can be disposed on the other side of the third channel region CHA3. The third source region S3 and the third drain region D3 can be regions on the third-direction DR3 that do not overlap with the gate electrode G3. The third source region S3 and the third drain region D3 can be regions that become conductive by doping the semiconductor material with ions.

[0143] The fourth active layer ACT4 may include a fourth channel region CHA4, a fourth source region S4, and a fourth drain region D4, and the fourth channel region CHA4 may be the same as the gate electrode G4 and the second lower electrode BG2 included in the third gate conductive layer CDL3 (see, for example, see...). Figure 8 (overlapping areas)

[0144] The fourth source region S4 can be disposed on one side of the fourth channel region CHA4, and the fourth drain region D4 can be disposed on the other side of the fourth channel region CHA4. The fourth source region S4 and the fourth drain region D4 can be regions on the third-direction DR3 that do not overlap with the gate electrode G4. The fourth source region S4 and the fourth drain region D4 can be regions that become conductive by doping the semiconductor material with ions.

[0145] The third gate insulating layer 139 can be positioned on the second semiconductor layer SCL2 and on the first interlayer insulating layer 137. The third gate insulating layer 139 can completely cover the second semiconductor layer SCL2 and the first interlayer insulating layer 137.

[0146] The third gate conductive layer CDL3 can be positioned on the third gate insulating layer 139. The third gate conductive layer CDL3 can be formed as a single layer or multiple layers made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) and / or alloys thereof.

[0147] According to one or more embodiments, the third gate conductive layer CDL3 may include a gate electrode G3 of a third transistor T3 and a gate electrode G4 of a fourth transistor T4. The gate electrode G3 may overlap with the third active layer ACT3 on the third-direction DR3, and the gate electrode G4 may overlap with the fourth active layer ACT4 on the third-direction DR3.

[0148] Furthermore, the third gate conductive layer CDL3 according to one or more embodiments may include a scan initialization line GIL extending on the first direction DR1, a scan control line GCL extending on the first direction DR1, and an emitt control line EML extending on the first direction DR1. Redundant descriptions will be omitted.

[0149] The second interlayer insulating layer 141 may be located on the third gate conductive layer CDL3 and positioned on the third gate insulating layer 139. The second interlayer insulating layer 141 may completely cover the third gate conductive layer CDL3 and the third gate insulating layer 139.

[0150] In one or more embodiments, the second semiconductor layer SCL2 and the second gate conductive layer CDL2 may not overlap with the valley region.

[0151] Figure 9 It is shown in detail Figure 5 An example layout diagram of the first source-drain conductive layer and the second source-drain conductive layer. Figure 9 It shows in Figure 8 The layout diagram shows the additional formation of a first source-drain conductive layer SD1 and a second source-drain conductive layer SD2 on the existing structure.

[0152] Reference Figures 5 to 9 The first source-drain conductive layer SD1 may be located on the second interlayer insulating layer 141. The first source-drain conductive layer SD1 may be formed as a single layer or multiple layers made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) and / or alloys thereof.

[0153] In one or more embodiments, the first source-drain conductive layer SD1 may include a data connection electrode DCE, a fourth power line VAIL, a second horizontal power line HVDL, and a connection electrode BE.

[0154] The connecting electrode BE may include a first connecting electrode BE1, a second connecting electrode BE2, a third connecting electrode BE3, a fourth connecting electrode BE4, and a fifth connecting electrode BE5. The first connecting electrode BE1 can connect a fourth drain region D4 included in each of a plurality of adjacent sub-pixels. Each fourth drain region D4 can be connected to the first connecting electrode BE1 through a second contact hole CNH2.

[0155] The second connection electrode BE2 can connect the third drain region D3 of the third transistor T3 and the gate electrode G1 of the first transistor T1. The third drain region D3 can be connected to the second connection electrode BE2 through the second contact hole CNH2, and the gate electrode G1 can be connected to the second connection electrode BE2 through the first contact hole CNH1.

[0156] The third connecting electrode BE3 can connect the third source region S3 of the third transistor T3 to the first drain region D1 of the first transistor T1. The third source region S3 can be connected to the third connecting electrode BE3 through the second contact hole CNH2, and the first drain region D1 can be connected to the third connecting electrode BE3 through the first contact hole CNH1.

[0157] The fourth connecting electrode BE4 can connect the sixth drain region D6 of the sixth transistor T6 and the seventh source region S7 of the seventh transistor T7 to the anode electrode AE ​​through the first contact hole CNH1. In other words, the fourth connecting electrode BE4 can be the first anode connecting electrode ANCE1.

[0158] The fifth connection electrode BE5 can connect the eighth drain region D8 of the eighth transistor T8 and the fifth electric field line VOBL. Each of the eighth drain region D8 and the fifth electric field line VOBL can be connected to the fifth connection electrode BE5 through the first contact hole CNH1.

[0159] The data connection electrode DCE can be electrically connected to the second source region S2 of the second transistor T2 through the first contact hole CNH1. Furthermore, the data connection electrode DCE can be connected to the data line DL through the source-drain contact hole CNH4.

[0160] The first anode connection electrode ANCE1 can be electrically connected to the sixth drain region D6 of the sixth transistor T6 through the first contact hole CNH1. Furthermore, the first anode connection electrode ANCE1 can be connected to the second anode connection electrode ANCE2 through the source-drain contact hole CNH4.

[0161] The fourth power line VAIL can be connected to the seventh drain region D7 of the seventh transistor T7 through the first contact hole CNH1. The fourth power line VAIL can overlap with the emitter control line EML and the bias scan line GBL on the third-direction DR3. The fourth power line VAIL can be configured to pass through the portion that overlaps with the gate contact hole CNH3.

[0162] The second horizontal power line HVDL can be connected to the fifth source region S5 of the fifth transistor T5 through the first contact hole CNH1. The second horizontal power line HVDL can overlap with the scan initialization line GIL, scan control line GCL, and scan write line GWL on the third-direction DR3. The second horizontal power line HVDL can be configured to pass through the portion overlapping with the gate contact hole CNH3.

[0163] The first passivation layer 143 may be located on the first source-drain conductive layer SD1 and on the second interlayer insulating layer 141. The first passivation layer 143 may completely cover the first source-drain conductive layer SD1 and the second interlayer insulating layer 141.

[0164] In one or more embodiments, the first passivation layer 143 may include an inorganic insulating material. Details will be described later.

[0165] The second source-drain conductive layer SD2 can be located on the first passivation layer 143. The second source-drain conductive layer SD2 can be formed as a single layer or multiple layers made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) and / or alloys thereof.

[0166] In one or more embodiments, the second source-drain conductive layer SD2 may include a data line DL, a second vertical power line V_VDL, and a second anode connection electrode. Figure 6 The second anode is connected to electrode ANCE2.

[0167] The data line DL can extend along the second direction DR2. The data line DL can be electrically connected to the data connection electrode DCE through the source-drain contact hole CNH4 passing through the first passivation layer 143. As a result, the data line DL can be electrically connected to the second source region S2 of the second transistor T2.

[0168] In one or more embodiments, the data line DL may overlap on the third-direction DR3 with the third power line VIL, scan write line GWL and bias scan line GBL included in the first gate conductive layer CDL1, the fifth power line VOBL included in the second gate conductive layer CDL2, the scan initialization line GIL, scan control line GCL and emit control line EML included in the third gate conductive layer CDL3, and the second horizontal power line HVDL and the fourth power line VAIL included in the first source-drain conductive layer SD1.

[0169] Furthermore, the data line DL may overlap with at least one of the first transistor T1 to the eighth transistor T8 on the third-direction DR3.

[0170] The second vertical electric field line V_VDL can extend along the second direction DR2. The second vertical electric field line V_VDL can be connected to the second horizontal electric field line HVDL through the source-drain contact hole CNH4.

[0171] In one or more embodiments, the second vertical power line V_VDL may overlap on the third-direction DR3 with the third power line VIL, scan write line GWL and bias scan line GBL included in the first gate conductive layer CDL1, the fifth power line VOBL included in the second gate conductive layer CDL2, the scan initialization line GIL, scan control line GCL and emit control line EML included in the third gate conductive layer CDL3, and the second horizontal power line HVDL and the fourth power line VAIL included in the first source-drain conductive layer SD1.

[0172] Furthermore, the second vertical electric field line V_VDL can overlap with at least one of the first transistor T1 to the eighth transistor T8 on the third direction DR3.

[0173] In one or more embodiments, the second vertical power line V_VDL may be configured to pass through the portion overlapping with the gate contact hole CNH3.

[0174] The second anode connection electrode ANCE2 can be electrically connected to the first anode connection electrode ANCE1 through the source-drain contact hole CNH4 passing through the first passivation layer 143.

[0175] In one or more embodiments, the first source-drain conductive layer SD1 and the second source-drain conductive layer SD2 may be located in the portion overlapping with the Valley region.

[0176] The second passivation layer 145 can be located on the second source-drain conductive layer SD2 and on the first passivation layer 143. The second passivation layer 145 can completely cover the second source-drain conductive layer SD2 and the first passivation layer 143.

[0177] The second passivation layer 145 may include an inorganic insulating material. Details will be described later.

[0178] like Figure 6 As shown, the display element layer DIL can be located on the thin film transistor layer TFTL. The display element layer DIL may include a via layer 151, a pixel defining layer 153, and a light-emitting element LE.

[0179] The via layer 151 can be located on the thin-film transistor layer TFTL. The via layer 151 can contact the second passivation layer 145. The via layer 151 can planarize the step difference of the underlying structure.

[0180] The via layer 151 may include organic materials. As an example, the via layer 151 may include acrylic resin, silicone resin, silicone acrylic resin, epoxy resin, polyimide, polyamide, benzocyclobutene, phenolic resin, etc.

[0181] In one or more embodiments, the via layer 151 may include a via opening OP1. The via layer 151 may be around (e.g., surrounding) the via opening OP1. The via opening OP1 may refer to the portion of the via layer 151 that does not overlap with the light-emitting element LE. In other words, the via layer 151 may have an organic patterned shape.

[0182] According to one or more embodiments, the second passivation layer 145 may be exposed at the portion overlapping with the via opening OP1.

[0183] Display device 10 according to one or more embodiments (see also) Figure 1 ) for use in various electronic devices 1 (such as Figure 14 As shown in the illustration, and therefore may require heat resistance reliability in high-temperature environments. For example, the display device 10 according to one or more embodiments may be placed in a vehicle in which a large amount of external light is incident. In this case, the display device 10 may be exposed to high temperatures for extended periods of time, and therefore may require heat resistance reliability.

[0184] Typically, a thin-film transistor layer (TFTL) may include multiple organic material layers that planarize the step differences between multiple conductive layers. For example, when a display device includes multiple stacked organic material layers, degassing of the organic materials may occur in high-temperature exposure environments. Degassing of the organic materials may lead to damage to the multiple conductive layers included in the TFTL.

[0185] Therefore, the display device 10 according to one or more embodiments aims to reduce or minimize the organic material layer included in the thin-film transistor layer (TFTL). As a result, in the display device 10 according to one or more embodiments, the first passivation layer 143 and the second passivation layer 145 included in the TFTL can be formed to include an inorganic insulating material, and the via layer 151 including an organic material can be patterned to include a via opening OP1.

[0186] In this way, the display device 10 according to one or more embodiments can reduce the amount of organic material layer overlapping with multiple conductive layers included in the thin film transistor layer (TFTL), and can prevent the conductive layers from being damaged due to degassing of organic materials in a high-temperature exposure environment.

[0187] The light-emitting element LE can be located on the via layer 151. The light-emitting element LE may include an anode electrode AE, a light-emitting layer EL, and a cathode electrode CE. The light-emitting element LE is a device that emits light by recombination of holes from the anode electrode AE ​​and electrons from the cathode electrode CE in the light-emitting layer EL. Each of the plurality of light-emitting elements LE may be an organic light-emitting diode (OLED) in which the light-emitting layer EL is formed as an organic light-emitting layer, but this disclosure is not limited thereto.

[0188] The anode electrode AE ​​can be located on the via layer 151. The anode electrode AE ​​can have a flat shape due to its location on the via layer 151. The anode electrode AE ​​can not overlap with the via opening OP1.

[0189] The anode electrode AE ​​can be electrically connected to the second anode connection electrode ANCE2 through the anode contact hole ACNH. The anode electrode AE ​​can be connected to the sixth drain region D6 of the sixth transistor T6 through the second anode connection electrode ANCE2 and the first anode connection electrode ANCE1.

[0190] The anode electrode AE ​​can have a stacked structure in which layers of materials having high work functions, including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and / or indium oxide (In2O3), are stacked together with reflective material layers including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), and / or mixtures thereof. As an example, the anode electrode AE ​​can have multilayer structures such as ITO / Mg, ITO / MgF2, ITO / Ag, and ITO / Ag / ITO, but is not limited thereto.

[0191] A pixel defining layer 153 can be disposed on the anode electrode AE ​​and the via layer 151 in the portion overlapping with the non-light-emitting region NLA. The pixel defining layer 153 can cover the edge of the anode electrode AE ​​and can define the light-emitting opening OP2. The light-emitting region EA and the non-light-emitting region NLA can be defined by the light-emitting opening OP2.

[0192] The pixel-defining layer 153 can help to separate the anode electrode AE ​​and the cathode electrode CE from each other (e.g., to insulate them).

[0193] The pixel defining layer 153 may include organic materials. As an example, the pixel defining layer 153 may include acrylic resin, silicone resin, silicone acrylic resin, epoxy resin, polyimide, polyamide, benzocyclobutene, phenolic resin, etc.

[0194] In one or more embodiments, the via opening OP1 may be spaced apart from the light-emitting opening OP2 (e.g., spaced apart). In other words, the via opening OP1 may not overlap with the light-emitting opening OP2.

[0195] According to one or more embodiments, the pixel defining layer 153 may have an organic pattern shape so as not to overlap with the via opening OP1 and the light-emitting opening OP2. In other words, the pixel defining layer 153 may be positioned between the via opening OP1 and the light-emitting opening OP2.

[0196] For example, when the pixel defining layer 153 is fully formed on the thin-film transistor layer (TFTL), the organic material included in the pixel defining layer 153 may degas in a high-temperature exposure environment, and the degassing of the organic material may cause damage to multiple conductive layers included in the TFTL. Redundant descriptions will be omitted.

[0197] Therefore, the display device 10 according to one or more embodiments can pattern the pixel defining layer 153 including organic material, thereby reducing the organic material layer overlapping with multiple conductive layers included in the thin film transistor layer TFTL and preventing the conductive layer from being damaged due to degassing of the organic material in a high-temperature exposure environment.

[0198] The light-emitting layer EL can be located on the anode electrode AE ​​and the pixel defining layer 153. The light-emitting layer EL can contact the anode electrode AE ​​at the portion that overlaps with the light-emitting opening OP2.

[0199] Each of the light-emitting layers (ELs) may include an organic material and emit light. For example, the EL of the first light-emitting region EA1 may emit a first light, the EL of the second light-emitting region EA2 may emit a second light, and the EL of the third light-emitting region EA3 may emit a third light (see, for example, [link to relevant documentation]). Figure 4 and Figure 6Each of the light-emitting layers (ELs) can include a hole transport layer, an organic material layer, and an electron transport layer.

[0200] The cathode electrode CE can be disposed on the light-emitting layer EL and the pixel defining layer 153. The cathode electrode CE can contact the light-emitting layer EL and the pixel defining layer 153 and completely cover the light-emitting layer EL and the pixel defining layer 153.

[0201] Furthermore, according to one or more embodiments, the cathode electrode CE may contact and cover the second passivation layer 145 at the portion overlapping with the via opening OP1.

[0202] In the top-emitting structure, the cathode electrode CE may include a transparent conductive material (TCO) capable of transmitting light (such as ITO and / or IZO) or a semi-transmissive conductive material (such as magnesium (Mg), silver (Ag), and / or an alloy of magnesium (Mg) and silver (Ag)). When the cathode electrode CE includes a semi-transmissive conductive material, the luminous efficiency of each of the light-emitting elements LE can be improved by the microcavity.

[0203] In one or more embodiments, an encapsulation layer comprising at least one inorganic insulating material and preventing the penetration of oxygen and / or moisture, a polarizing film for preventing visibility degradation due to external light, or sensor electrodes for sensing touch may also be disposed on the display element layer (DIL).

[0204] Figure 10 It is along Figure 5 The cross-sectional view taken by line X3-X3' in the diagram. Figure 10 It shows along Figure 5 An example of a substrate SUB and a thin-film transistor layer (TFTL) with X3-X3' cut lines.

[0205] Reference Figure 10 as well as Figures 1 to 9 The display device 10 according to one or more embodiments may include a via opening OP1 and a valley region located in a portion overlapping with the non-light-emitting region NLA.

[0206] The third electric field line VIL included in the first gate conductive layer CDL1 can be located on the first gate insulating layer 133 in the portion overlapping with the non-light-emitting region NLA. The third electric field line VIL included in the first gate conductive layer CDL1 can be located in the portion overlapping with the via opening OP1.

[0207] The second lower electrode BG2, included in the second gate conductive layer CDL2, can be located on the second gate insulating layer 135 in the portion overlapping with the non-light-emitting region NLA. The second lower electrode BG2, included in the second gate conductive layer CDL2, can also be located in the portion overlapping with the via opening OP1.

[0208] The second lower electrode BG2 can overlap with the fourth channel region CHA4 included in the second semiconductor layer SCL2 on the third-direction DR3.

[0209] The scan initialization line GIL included in the third gate conductive layer CDL3 can be located on the third gate insulating layer 139 in the portion overlapping with the non-light-emitting region NLA. The scan initialization line GIL included in the third gate conductive layer CDL3 can be located in the portion overlapping with the via opening OP1.

[0210] In one or more embodiments, the second lower electrode BG2, included in the second gate conductive layer CDL2, can be connected to the scan initialization line GIL, included in the third gate conductive layer CDL3, via the gate contact hole CNH3. The second lower electrode BG2 can then be used as the back gate electrode of the fourth transistor T4 due to its connection to the scan initialization line GIL.

[0211] The gate contact hole CNH3 can pass through the first interlayer insulating layer 137 and the third gate insulating layer 139. The gate contact hole CNH3 can facilitate the connection of the third gate conductive layer CDL3 to at least one of the first gate conductive layer CDL1 and the second gate conductive layer CDL2.

[0212] The second interlayer insulating layer 141 can completely cover the third gate conductive layer CDL3. The second interlayer insulating layer 141 can contact and cover the scan initialization line GIL included in the third gate conductive layer CDL3 in the portion that overlaps with the gate contact hole CNH3.

[0213] The gate planarization layer GFL can be positioned on the second interlayer insulating layer 141. The gate planarization layer GFL can be positioned within the gate contact via CNH3 (e.g., inside the gate contact via CNH3). The gate planarization layer GFL can be an organic pattern in the form of islands. In an embodiment, the first passivation layer 143 can be located between the gate planarization layer GFL and the second source-drain conductive layer SD2.

[0214] The gate planarization layer (GFL) may include organic materials. As an example, the GFL may include acrylic resin, silicone resin, silicone acrylic resin, epoxy resin, polyimide, polyamide, benzocyclobutene, phenolic resin, etc.

[0215] Figure 11 yes Figure 10 An enlarged cross-sectional view of region "A" in the image.

[0216] Reference Figure 10 and Figure 11 as well as Figures 1 to 9In one or more embodiments, the scan initialization line (GIL) included in the third gate conductive layer (CDL3) can be formed with a uniform thickness along the contour of the lower structure in the portion overlapping with the gate contact hole (CNH3). The uniform thickness mentioned above can include a process tolerance range of 5% or less.

[0217] Therefore, the scan initialization line GIL included in the third gate conductive layer CDL3 can include a step difference st1 in the portion overlapping with the gate contact hole CNH3.

[0218] The scan initialization line GIL included in the third gate conductive layer CDL3 can contact and cover the side surfaces of the first interlayer insulating layer 137 facing the gate contact hole CNH3 and the third gate insulating layer 139 facing the gate contact hole CNH3 in the portion overlapping with the gate contact hole CNH3.

[0219] In one or more embodiments, the scan initialization line GIL included in the third gate conductive layer CDL3 may include an upper surface a2 and a lower surface a1. The upper surface a2 of the scan initialization line GIL may contact the second interlayer insulating layer 141, and the lower surface a1 of the scan initialization line GIL may contact the second gate conductive layer CDL2.

[0220] In one or more embodiments, the second interlayer insulating layer 141 may be formed with a uniform thickness along the contour of the lower structure. Therefore, the second interlayer insulating layer 141 may include a step difference st2 in the portion overlapping with the gate contact hole CNH3.

[0221] The second interlayer insulating layer 141 may cover the side surface in a manner that is spaced apart (e.g., spaced apart) from the side surface of the first interlayer insulating layer 137 facing the gate contact hole CNH3 and the side surface of the third gate insulating layer 139 facing the gate contact hole CNH3.

[0222] The second interlayer insulating layer 141 may include an upper surface g1. The upper surface g1 of the second interlayer insulating layer 141 may contact the gate planarization layer GFL. In an embodiment, the gate planarization layer GFL may contact and cover a portion of the upper surface g1 of the interlayer insulating layer (e.g., the second interlayer insulating layer 141) facing the source-drain conductive layer (e.g., the first source-drain conductive layer SD1).

[0223] The gate planarization layer GFL may be spaced apart from the third gate conductive layer CDL3 (e.g., spaced apart), and the second interlayer insulating layer 141 is located between the gate planarization layer GFL and the third gate conductive layer CDL3. In an embodiment, the gate planarization layer GFL and the third gate conductive layer CDL3, which overlap with the gate contact via CNH3, may overlap with the via opening OP1.

[0224] The gate planarization layer (GFL) can planarize the step difference st2 included in the second interlayer insulating layer 141 in the portion overlapping with the gate contact hole (CNH3). Therefore, the gate planarization layer (GFL) can help the first source-drain conductive layer SD1 to have a flat surface in the portion overlapping with the gate contact hole (CNH3). Details will be described later.

[0225] The gate planarization layer GFL can cover the side surface of the first interlayer insulating layer 137 facing the gate contact hole CNH3, the side surface of the third gate insulating layer 139 facing the gate contact hole CNH3, and the upper surface a2 of the third gate conductive layer CDL3 facing the gate contact hole CNH3.

[0226] In one or more embodiments, the thickness T of the gate planarization layer GFL f1 It can have a value of height Hst2 that is greater than or equal to the step difference st2 of the second interlayer insulation layer 141.

[0227] In one or more embodiments, the second horizontal electric field line HVDL included in the first source-drain conductive layer SD1 may be located on the second interlayer insulating layer 141 and the gate planarization layer GFL in the portion overlapping with the non-light-emitting region NLA. The second horizontal electric field line HVDL included in the first source-drain conductive layer SD1 may be located in the portion overlapping with the via opening OP1.

[0228] In one or more embodiments, the second horizontal electric field line HVDL included in the first source-drain conductive layer SD1 may be located in the portion overlapping with the gate contact hole CNH3 and may have a flat surface.

[0229] The display device 10 according to one or more embodiments is used in various electronic devices 1 (such as...). Figure 14 As shown in the diagram, and therefore may require high-resolution characteristics. This can mean that multiple conductive layers are arranged in a high density in a narrow region (e.g., within) in a direction parallel to one surface of the substrate SUB and in a direction perpendicular to one surface of the substrate SUB. As a result, the contact holes (e.g., gate contact holes CNH3) of the display device 10 applied to the high-resolution electronic device 1 can have a narrow and deep width.

[0230] For example, when conductive lines included in the source-drain conductive layer are formed to overlap each other in the portion overlapping with the contact hole, the conductive lines included in the source-drain conductive layer may include narrow and deep step differences, which may lead to short-circuit defects in the conductive lines. Furthermore, when the conductive lines included in the source-drain conductive layer include narrow and deep step differences, defects may occur where the conductive lines are not insulated from the underlying conductive layer and are in contact with the underlying conductive layer.

[0231] Therefore, it may be necessary to include a design in which conductive lines in the source-drain conductive layer of a display device used in high-resolution electronic devices are formed by bypassing or avoiding multiple contact holes. This could increase the manufacturing complexity of the display device and reduce area efficiency.

[0232] Therefore, since the display device 10 according to one or more embodiments includes a gate planarization layer GFL in the portion overlapping with the gate contact hole CNH3, the conductive lines included in the first source-drain conductive layer SD1 can be formed to include a flat surface, and furthermore, this can help to insulate the first source-drain conductive layer SD1 from the third gate conductive layer CDL3 below the first source-drain conductive layer SD1.

[0233] In other words, even if the display device 10 according to one or more embodiments is applied to the high-resolution electronic device 1, the conductive lines included in the first source-drain conductive layer SD1 can be formed to overlap with the gate contact hole CNH3 without avoiding the gate contact hole CNH3.

[0234] Furthermore, even if the display device 10 according to one or more embodiments is applied to the high-resolution electronic device 1, the conductive lines included in the first source-drain conductive layer SD1 can be insulated from the multiple lower conductive layers.

[0235] As a result, the display device 10 according to one or more embodiments can be easily manufactured, improve area efficiency, and solve reliability problems.

[0236] According to one or more embodiments, the gate planarization layer GFL can be in contact with the second interlayer insulating layer 141 and the first source-drain conductive layer SD1.

[0237] In one or more embodiments, the gate planarization layer GFL may be completely surrounded by the second interlayer insulating layer 141 and the first source-drain conductive layer SD1.

[0238] like Figure 10As shown, the second vertical electric field line V_VDL included in the second source-drain conductive layer SD2 can be located on the first passivation layer 143 in the portion overlapping with the non-light-emitting region NLA. The second vertical electric field line V_VDL included in the second source-drain conductive layer SD2 can also be located in the portion overlapping with the via opening OP1. Furthermore, the second vertical electric field line V_VDL included in the second source-drain conductive layer SD2 can also be located in the portion overlapping with the valley region.

[0239] The display device 10 according to one or more embodiments may include a valley flattening layer VFL in the portion overlapping with the valley region. The valley flattening layer VFL may completely fill the valley aperture VH formed in the portion overlapping with the valley region. The valley flattening layer VFL may be in contact with and covered by the first passivation layer 143.

[0240] According to one or more embodiments, the valley via VH can be formed through the buffer layer 131, the first gate insulating layer 133, the second gate insulating layer 135, the first interlayer insulating layer 137, the third gate insulating layer 139, and the second interlayer insulating layer 141 (see, for example, see...). Figure 10 However, it is not limited thereto. According to one or more embodiments, the valley via VH may pass through the third gate insulating layer 139, and in addition, may be formed to pass through at least one of the buffer layer 131, the first gate insulating layer 133, the second gate insulating layer 135 and the first interlayer insulating layer 137.

[0241] The valley planarization layer (VFL) can be made of the same material as the gate planarization layer (GFL). In the manufacturing process of the display device 10, the valley planarization layer (VFL) can be formed in the same process as the gate planarization layer (GFL). Therefore, the display device 10 can be easily manufactured.

[0242] Valley flattening layers (VFLs) can protect multiple conductive layers included in thin-film transistor layers (TFTLs) from physical impacts.

[0243] In one or more embodiments, the valley flattening layer VFL may overlap with the gate flattening layer GFL in a direction parallel to the substrate SUB.

[0244] The second vertical electric field line V_VDL, included in the second source-drain conductive layer SD2, can overlap with the valley flattening layer VFL on the third direction DR3 in the portion that overlaps with the valley region.

[0245] Figure 12 According to one or more other embodiments Figure 10 An enlarged cross-sectional view of region "A".

[0246] Reference Figure 12 as well as Figures 1 to 11 The upper surface f1 of the gate planarization layer GFL in the display device 10a may be on the same line (e.g., collinear) as the upper surface g1 of the second interlayer insulating layer 141.

[0247] The gate planarization layer GFL included in the display device 10a can planarize the step difference st2 included in the second interlayer insulating layer 141 in the portion overlapping with the gate contact hole CNH3. The thickness T of the gate planarization layer GFL included in the display device 10a... f2 The height Hst2 of the step difference st2 of the second interlayer insulation layer 141 can have the same value. The meaning of the same value as described above can include a range of 5% or less of process tolerance.

[0248] The gate planarization layer (GFL) included in the display device 10a can be formed by additionally performing a planarization process after the process of forming the gate planarization layer (GFL) in the manufacturing process.

[0249] The gate planarization layer (GFL) can help the second horizontal electric field line (HVDL) included in the first source-drain conductive layer (SD1) to have a relatively lower step difference than the step difference (st2) included in the second interlayer insulating layer (141) in the portion overlapping with the gate contact hole (CNH3). Redundant descriptions will be omitted.

[0250] Figure 13 It is along Figure 5 The cross-sectional view taken from line X5-X5' in the diagram.

[0251] Reference Figure 13 as well as Figures 1 to 12 In one or more embodiments, the fifth active layer ACT5 included in the first semiconductor layer SCL1 may be located on the buffer layer 131. The fifth channel region CHA5 included in the fifth active layer ACT5 may overlap with the gate electrode G5 included in the first gate conductive layer CDL1.

[0252] The fifth source region S5, included in the fifth active layer ACT5, can be connected to the second horizontal electric field line HVDL, included in the first source-drain conductive layer SD1, through the first contact hole CNH1, and the second horizontal electric field line HVDL can be connected to the second vertical electric field line V_VDL, included in the second source-drain conductive layer SD2, through the source-drain contact hole CNH4.

[0253] The emitter control line EML, which is included in the third gate conductive layer CDL3, can be positioned on the third gate insulating layer 139.

[0254] The emitter control line EML included in the third gate conductive layer CDL3 can be connected to the gate electrode G5 included in the first gate conductive layer CDL1 in the portion overlapping with the gate contact hole CNH3. Therefore, the emitter control line EML can include a step difference in the portion overlapping with the gate contact hole CNH3. Redundant descriptions will be omitted.

[0255] The second interlayer insulating layer 141 may completely cover the emitter control line EML included in the third gate conductive layer CDL3. The second interlayer insulating layer 141 may include a step difference st2 in the portion overlapping with the gate contact hole CNH3. Redundant descriptions will be omitted.

[0256] The second interlayer insulating layer 141 may be separated from the first gate conductive layer CDL1 in the portion overlapping with the gate contact hole CNH3 (e.g., spaced apart), and the third gate conductive layer CDL3 is located between the second interlayer insulating layer 141 and the first gate conductive layer CDL1.

[0257] The gate planarization layer (GFL) can be on the second interlayer insulating layer 141. The gate planarization layer (GFL) can be an organic pattern in the form of islands. The gate planarization layer (GFL) can planarize the step difference st2 included in the second interlayer insulating layer 141 in the portion overlapping with the gate contact hole CNH3. Redundant descriptions will be omitted.

[0258] In one or more embodiments, the gate planarization layer GFL may contact the second interlayer insulating layer 141 and the first passivation layer 143, and may be completely surrounded by the second interlayer insulating layer 141 and the first passivation layer 143.

[0259] The second vertical electric field line V_VDL, included in the second source-drain conductive layer SD2, can be on the first passivation layer 143. The second vertical electric field line V_VDL, included in the second source-drain conductive layer SD2, can be in the portion overlapping with the gate contact hole CNH3 and can also overlap with the gate planarization layer GFL.

[0260] The second vertical electric field line V_VDL included in the second source-drain conductive layer SD2 may include a flat surface in the portion overlapping with the gate contact hole CNH3.

[0261] Since the display device 10 according to one or more embodiments includes a gate planarization layer GFL in the portion overlapping with the gate contact hole CNH3, the conductive lines included in the second source-drain conductive layer SD2 can be formed to include a flat surface, and can help to insulate the second source-drain conductive layer SD2 from the third gate conductive layer CDL3 below the second source-drain conductive layer SD2.

[0262] In other words, even if the display device 10 according to one or more embodiments is applied to a high-resolution electronic device 1 (such as...) Figure 14 As shown in the diagram, the conductive lines included in the second source-drain conductive layer SD2 can also be formed to overlap with the gate contact hole CNH3 without avoiding the gate contact hole CNH3.

[0263] Furthermore, even if the display device 10 according to one or more embodiments is applied to a high-resolution electronic device 1, the conductive lines included in the second source-drain conductive layer SD2 can be insulated from multiple lower conductive layers. As a result, the display device 10 according to one or more embodiments can be easily manufactured, has improved area efficiency, and solves reliability problems.

[0264] Figure 14 It is a block diagram of an electronic device according to one or more embodiments.

[0265] Reference Figure 14 as well as Figures 1 to 13 The display device 10 according to one or more embodiments can be applied to various electronic devices 1. The electronic device 1 according to one or more embodiments may include the above-described display device 10, and may also include modules or devices with additional functions in addition to the display device 10.

[0266] Electronic device 1 according to one or more embodiments may include a display module 11, a processor 12, a memory 13, and a power module 14.

[0267] The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0268] The data required for the operation of the processor 12 or the display module 11 can be stored in the memory 13. When the processor 12 executes the application stored in the memory 13, image data signals and / or input control signals can be transmitted to the display module 11, and the display module 11 can process the provided signals and output image information through the display screen.

[0269] The power module 14 may include a power supply module such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power supply module to generate the power required for the operation of the electronic device 1.

[0270] At least one of the components of the electronic device 1 described above may be included in the display device according to the above embodiments. Furthermore, some modules that are functionally included in a single module (e.g., within) may be included in the display device (e.g., within), while other modules may be provided separately from the display device. For example, the display device includes a display module 11, and the processor 12, memory 13, and power module 14 may be provided as other devices in the electronic device 1 (e.g., within) besides the display device.

[0271] Figure 15 A schematic diagram of an electronic device according to various embodiments is shown.

[0272] Reference Figure 15 The display device 10 according to one or more embodiments (see Figure 1 The various electronic devices 1 to which this technology is applied can include not only image display electronic devices such as smartphones 1_1a, tablet PCs 1_1b, laptop computers 1_1c, televisions (TVs) 1_1d and desktop monitors 1_1e, but also wearable electronic devices such as smart glasses 1_2a, head-mounted displays 1_2b and / or smartwatches 1_2c that include display modules, and vehicle electronic devices 1_3 such as vehicle instrument panels, central instrument panels and / or central information displays (CIDs) mounted on the dashboard, and rearview mirror displays that include display modules.

[0273] In summarizing the detailed description, those skilled in the art will appreciate that many variations and modifications can be made to the embodiments without substantially departing from the principles and scope of this disclosure. Therefore, the embodiments of this disclosure are used in a general and descriptive sense only and not for limiting purposes. The scope of this disclosure is indicated by the scope of the appended claims, not by the detailed description. All changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of this disclosure.

[0274] Although embodiments of the present disclosure have been described with reference to the accompanying drawings, it will be apparent to those skilled in the art that the present disclosure may be implemented in other specific forms without departing from the spirit and essential characteristics of the technology. Therefore, the above embodiments should be considered illustrative rather than restrictive in all respects.

[0275] Embodiments of this disclosure have been described above with reference to the accompanying drawings. However, those skilled in the art will understand that various modifications and changes can be made without departing from the technical spirit or essential characteristics of this disclosure. Therefore, it should be understood that the above embodiments are illustrative in all respects and not restrictive.

[0276] The features of the various embodiments of this disclosure can be combined in whole or in part. As will be clearly appreciated by those skilled in the art, various technical interactions and operations can be implemented. Furthermore, the various embodiments can be practiced individually or in combination.

[0277] In summarizing the detailed description, those skilled in the art will appreciate that many variations and modifications can be made to the described embodiments without substantially departing from the principles and scope of this disclosure. Therefore, the embodiments of this disclosure are used in a general and descriptive sense and not for limiting purposes.

Claims

1. A display device, wherein, The display device includes: The substrate includes luminescent and non-luminescent regions; A first gate conductive layer and a second gate conductive layer are stacked sequentially on the substrate. A third gate conductive layer is on the second gate conductive layer and is in contact with at least one of the first gate conductive layer and the second gate conductive layer through a gate contact hole; An interlayer insulating layer is provided on the third gate conductive layer; A source-drain conductive layer is located on the interlayer insulating layer; A gate planarization layer, situated between the interlayer insulating layer and the source-drain conductive layer and within the gate contact via; and A passivation layer is applied to the source-drain conductive layer. The gate planarization layer has an organic pattern shape, and In the portion that overlaps with the gate contact hole, the source-drain conductive layer overlaps with the gate planarization layer.

2. The display device according to claim 1, wherein, The display device further includes: A via layer is provided on the passivation layer and defines via openings; A light-emitting element, on the via layer, comprising an anode electrode, a light-emitting layer, and a cathode electrode; and A pixel defining layer is provided on the via layer and the anode electrode, defining a light-emitting opening that defines the light-emitting area and the non-light-emitting area. In the portion overlapping with the light-emitting opening, the anode electrode is in contact with the light-emitting layer, and In the portion that overlaps with the via opening, the passivation layer is exposed.

3. The display device according to claim 2, wherein, The light-emitting opening and the via opening are spaced apart from each other. Wherein, the pixel defining layer does not overlap with the via opening, and The pixel-defining layer has an organic pattern shape.

4. The display device according to claim 3, wherein, The gate planarization layer and the third gate conductive layer, which overlap with the gate contact hole, overlap with the via opening.

5. The display device according to claim 2, wherein, The source-drain conductive layer comprises a first source-drain conductive layer and a second source-drain conductive layer stacked sequentially, and In the planar view, the first source-drain conductive layer and the second source-drain conductive layer overlap with the gate contact hole.

6. The display device according to claim 5, wherein, The gate planarization layer is in contact with the first source-drain conductive layer, and The gate planarization layer is completely surrounded by the interlayer insulating layer and the first source-drain conductive layer.

7. The display device according to claim 6, wherein, The first source-drain conductive layer includes at least one of a data connection electrode, a power line, and a connection electrode.

8. The display device according to claim 5, wherein, The passivation layer includes: A first passivation layer is located between the gate planarization layer and the second source-drain conductive layer; and The second passivation layer covers the second source-drain conductive layer. The gate planarization layer is in contact with the interlayer insulating layer and the first passivation layer, and The gate planarization layer is completely surrounded by the interlayer insulating layer and the first passivation layer.

9. The display device according to claim 8, wherein, The second source-drain conductive layer includes at least one of a data line and a power line.

10. The display device according to claim 8, wherein, The first passivation layer and the second passivation layer comprise inorganic insulating materials.

11. The display device according to any one of claims 2 to 10, wherein, The display device further includes: A first semiconductor layer, located between the substrate and the first gate conductive layer, includes a source region, a channel region, and a drain region; and The second semiconductor layer is located between the second gate conductive layer and the third gate conductive layer. The source-drain conductive layer is connected to at least one of the first semiconductor layer and the second semiconductor layer.

12. The display device according to claim 11, wherein, The first semiconductor layer comprises polycrystalline silicon, and The second semiconductor layer includes an oxide semiconductor.

13. The display device according to any one of claims 2 to 10, wherein, In the portion overlapping with the gate contact hole, the interlayer insulating layer includes a step difference, and the thickness of the gate planarization layer is greater than or equal to the height of the step difference in the interlayer insulating layer.

14. The display device according to claim 13, wherein, The gate planarization layer is separated from the third gate conductive layer, and The gate planarization layer contacts and covers a portion of the upper surface of the interlayer insulating layer facing the source-drain conductive layer.

15. An electronic device, wherein, The electronic device includes: At least one display device includes a substrate, the substrate comprising a light-emitting region and a non-light-emitting region; and At least one of a display module, a processor, a memory, and a power module, wherein the at least one of the display module, the processor, the memory, and the power module is connected to the display device. The display device further includes: A first gate conductive layer and a second gate conductive layer are stacked sequentially on the substrate. A third gate conductive layer is on the second gate conductive layer and is in contact with at least one of the first gate conductive layer and the second gate conductive layer through a gate contact hole; An interlayer insulating layer is provided on the third gate conductive layer; A source-drain conductive layer is located on the interlayer insulating layer; A gate planarization layer, situated between the interlayer insulating layer and the source-drain conductive layer and within the gate contact via; and A passivation layer is applied to the source-drain conductive layer. The gate planarization layer has an organic pattern shape, and In the portion that overlaps with the gate contact hole, the source-drain conductive layer overlaps with the gate planarization layer.

16. The electronic device according to claim 15, wherein, The display device further includes: A via layer is provided on the passivation layer and defines via openings; A light-emitting element, on the via layer, comprising an anode electrode, a light-emitting layer, and a cathode electrode; and A pixel defining layer is provided on the via layer and the anode electrode, defining a light-emitting opening that defines the light-emitting area and the non-light-emitting area. In the portion overlapping with the light-emitting opening, the anode electrode is in contact with the light-emitting layer, and In the portion that overlaps with the via opening, the passivation layer is exposed.

17. The electronic device according to claim 16, wherein, The gate planarization layer and the third gate conductive layer, which overlap with the gate contact hole, overlap with the via opening.

18. The electronic device according to claim 16, wherein, The source-drain conductive layer comprises a first source-drain conductive layer and a second source-drain conductive layer stacked sequentially, and In the planar view, the first source-drain conductive layer and the second source-drain conductive layer overlap with the gate contact hole.

19. The electronic device according to claim 18, wherein, The gate planarization layer is in contact with the first source-drain conductive layer. Wherein, the gate planarization layer is completely surrounded by the interlayer insulating layer and the first source-drain conductive layer, and The first source-drain conductive layer includes at least one of a data connection electrode, a power line, and a connection electrode.

20. The electronic device according to claim 18, wherein, The passivation layer includes: A first passivation layer is located between the gate planarization layer and the second source-drain conductive layer; and The second passivation layer covers the second source-drain conductive layer. The gate planarization layer is in contact with the interlayer insulating layer and the first passivation layer. The gate planarization layer is completely surrounded by the interlayer insulating layer and the first passivation layer. The second source-drain conductive layer includes at least one of a data line and a power line, and The first passivation layer and the second passivation layer comprise inorganic insulating materials.

Images