Semiconductor structure and method of forming the same

Abstract

The application relates to a semiconductor structure and a forming method thereof. In the forming method, before a to-be-cut substrate is cut to obtain core particles, a curved groove with a curved top side wall is formed around a first area along a second area from the back side of the to-be-cut substrate, the to-be-cut substrate is then cut, the curved surface is located at the edge of each core particle obtained by cutting, the back surface and the side surface of the core particle form a smooth transition, and a medium material is covered on the back surface of the core particle, so that stress concentration points can be avoided at the edge of the core particle due to the sharp corners of the back surface edge of the core particle, the risk of cracks in the filling covering layer can be reduced, the quality of the filling covering layer can be ensured, the core particle can be prevented from being damaged due to stress aggravation, the internal stress of the formed semiconductor structure can be balanced, and the quality of the semiconductor structure can be ensured.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming a semiconductor structure. Background Technology

[0002] In the existing technology, W2W (substrate-to-substrate bonding) and C2W (chip-to-substrate bonding) technologies are used to integrate multiple components of a semiconductor module. This allows for the integration of different types of chips, achieving heterogeneous integration, and offers advantages such as high performance, small size, and low power consumption.

[0003] Before performing the C2W process, chip cells fabricated on a substrate using wafer-scale processes are divided into dies. During C2W, one or more dies are bonded to a bottom substrate, connecting the dies to the circuitry in the bottom substrate. Then, a filler layer is formed to cover the dies and fill the gaps around them. Further planarization processes (such as CMP (chemical mechanical polishing)) can be performed to make the surface of the filler layer flat.

[0004] However, research has found that after the core and the bottom substrate are bonded and the filler capping layer is deposited, cracks can easily appear that extend from the top edge of the core into the filler capping layer, resulting in a deterioration in the quality of the filler capping layer. After further planarization of the filler capping layer, the above cracks may also cause core breakage. Summary of the Invention

[0005] Research has found that the sharp angle between the side and top surfaces formed during the cutting of the core particles bonded to the bottom substrate is close to 90°. This causes the sharp angle to become a stress concentration point when the C2W process is completed and the filler capping layer is deposited. The stress accumulation makes it easy for cracks to extend from the top edge of the core particle into the filler capping layer after the dielectric layer is covered. This not only affects the quality of the filler capping layer, but also increases the stress risk after the subsequent planarization process, leading to core particle breakage.

[0006] To avoid cracks extending from the top edge of the core to the filler layer covering the core, to ensure the quality of the filler layer, and to prevent damage to the core due to increased stress, the present invention provides a semiconductor structure and a method for forming a semiconductor structure.

[0007] On one hand, the present invention provides a method for forming a semiconductor structure, the method comprising:

[0008] A substrate to be cut is provided, the substrate to be cut includes a plurality of first regions and a second region located around the first regions, and the surface of the substrate to be cut has a front side and a back side facing away from each other;

[0009] A curved groove is formed from the back side of the substrate to be cut along the second region around the first region, and the top of the sidewall of the curved groove is curved.

[0010] Multiple core particles are obtained by cutting the substrate to be cut. The orthographic projection of the cutting position on the surface plane of the substrate to be cut is located within the orthographic projection of the curved groove on the surface plane of the substrate to be cut. The connection between the back side and the side side of each core particle includes the curved surface.

[0011] Optionally, the substrate to be cut includes a semiconductor substrate and a top metal layer and a metal pad formed on one side of the semiconductor substrate, and the back side of the substrate to be cut is the surface of the semiconductor substrate facing away from the metal pad.

[0012] Optionally, before forming the curved groove, the forming method includes:

[0013] The front side of the substrate to be cut is bonded to a carrier plate; and the substrate to be cut is thinned from the back side.

[0014] Optionally, a primary groove is formed in the second region of the substrate to be cut, and the curved groove is formed by removing part of the sidewall of the primary groove and the part of the substrate to be cut located in the second region on both sides of the primary groove.

[0015] Optionally, forming the primary trench includes:

[0016] A first mask layer is formed on the back side of the substrate to be cut. The first mask layer has a first opening located above the second region, and the width of the first opening is smaller than the width of the second region.

[0017] A portion of the substrate to be cut is removed, and a primary trench is formed corresponding to the first opening, extending from the back side into the substrate to be cut.

[0018] Optionally, forming the curved groove includes:

[0019] A planarization layer is filled within the primary trench, and the planarization layer also covers the back surface outside the primary trench;

[0020] A second mask layer is formed on the surface of the planarization layer. The second mask layer has a second opening located above the second region. The orthographic projection of the second opening on the back side of the substrate to be cut covers the primary trench and the orthographic projection of the second region on both sides of the primary trench on the back side of the substrate to be cut.

[0021] A portion of the planarization layer and a portion of the substrate to be cut are removed, and a curved groove is formed on the back side of the substrate to be cut corresponding to the second opening.

[0022] Optionally, the bottom wall width of the curved groove is less than the width of the second region, and the maximum width of the side wall of the curved groove is equal to the width of the second region; from the bottom to the top of the curved groove, the distance between the two side walls of the curved groove gradually increases.

[0023] Optionally, the longitudinal section of the sidewall of the curved groove is a circular arc.

[0024] Optionally, the substrate to be cut is cut from the front side or the back side using a plasma etching process.

[0025] Optionally, the orthographic projection of the cutting position on the surface plane of the substrate to be cut coincides with the orthographic projection of the bottom wall of the curved groove or the bottom wall and the part of the side wall connected to the bottom wall on the surface plane of the substrate to be cut.

[0026] Optionally, the forming method further includes:

[0027] At least one of the core particles is stacked and connected to a bottom substrate, wherein the edge of the core particle having the curved surface faces away from the bottom substrate;

[0028] A filling capping layer is formed, which covers the core and fills the voids around the core; and

[0029] A planarization process is performed to remove at least part of the filler coating that covers the back side of the core.

[0030] On the other hand, the present invention provides a semiconductor structure, the semiconductor structure comprising:

[0031] Bottom substrate;

[0032] At least one core particle is stacked and connected to the surface of the bottom substrate, the front side of the core particle faces the bottom substrate and the back side faces away from the bottom substrate, and the connection between the back side and the side of the core particle is curved.

[0033] And a filling cover layer that at least covers the sidewalls of the core and fills the voids around the core.

[0034] Optionally, the core is obtained by cutting the substrate to be cut from the substrate having curved grooves, and the orthographic projection of the cutting position on the surface plane of the substrate to be cut is located within the orthographic projection of the curved groove on the surface plane of the substrate to be cut, and the top of the sidewall of the curved groove includes the curved surface.

[0035] Optionally, the substrate to be cut includes a plurality of first regions and a second region located around the first regions. The second region of the substrate to be cut has a primary trench formed. The curved trench is formed by removing part of the sidewalls of the primary trench and the portion of the substrate to be cut located in the second region on both sides of the primary trench.

[0036] In the semiconductor structure formation method provided by the present invention, before cutting the substrate to be cut to obtain a core, a curved groove with a curved top sidewall is formed around the first region along the second region from one side of the back side of the substrate to be cut. After cutting the substrate to be cut to obtain multiple cores, the connection between the back side and the side side of each core edge includes the curved surface, so that the back side and the side side of the core form a smooth transition. When covering the back side of the core with a dielectric material, such as bonding the front side of the core to the bottom substrate and covering the core with a filler layer, it can avoid stress concentration points at the edge of the core due to the sharp corners of the back side edge of the core, reduce the risk of cracks in the filler layer, help ensure the quality of the filler layer and avoid damage to the core due to stress intensification, help to balance the internal stress of the formed semiconductor structure, and ensure the quality of the semiconductor structure.

[0037] In the semiconductor structure provided by the present invention, the connection between the back side and the side of the core stacked on the surface of the bottom substrate is a curved surface. The exposed surface of the core does not have sharp corners, so that stress concentration points will not be generated at the edge of the core due to sharp corners. This can reduce the risk of cracks in the filling capping layer, help ensure the quality of the filling capping layer and avoid damage to the core due to stress aggravation, facilitate the stress balance inside the formed semiconductor structure, and ensure the quality of the semiconductor structure. Attached Figure Description

[0038] Figure 1 This is a schematic flowchart of a method for forming a semiconductor structure according to an embodiment of the present invention.

[0039] Figures 2A to 2M This is a cross-sectional schematic diagram of a method for forming a semiconductor structure according to an embodiment of the present invention. Detailed Implementation

[0040] The semiconductor structure and its formation method of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. The advantages and features of the present invention will become clearer from the following description. It should be understood that the accompanying drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention. The terms "first" and "second," etc., in the specification are used to distinguish between similar elements and are not necessarily used to describe a specific order or chronological sequence. It should be understood that these terms, as used so, can be replaced where appropriate.

[0041] Reference Figure 1 This invention relates to a method for forming a semiconductor structure. Figure 2 shows a cross-sectional structure of a substrate to be cut in one embodiment. (Refer to...) Figure 1 and Figure 2A According to the semiconductor structure formation method of the present invention, step S1 is performed to provide a substrate 100 to be cut. The substrate 100 to be cut includes a plurality of first regions A1 and a second region A2 located around the first regions A1. The surface of the substrate 100 to be cut has a front side 100a and a back side 100b that are opposite to each other.

[0042] The substrate 100 to be diced can be a silicon wafer or other substrate on which integrated circuits are formed. A first region A1 and a second region A2 are laterally arranged in the substrate 100 and extend along the thickness direction of the substrate 100. The first region A1 may have semiconductor devices and metal interconnect structures connected to the semiconductor devices. Each first region A1 is separated from the substrate 100 after a subsequent dicing process to form a corresponding die. The second region A2 is the area other than the first region A1, and the dicing position is located in the second region A2 during the subsequent dicing process. The second region A2 may surround the first region A1. Depending on the needs, the second region A2 may have at least one of a test key, alignment mark, measurement mark, and feature pattern. The substrate 100 to be diced can be a single-layer substrate or a stacked substrate formed by vertically bonding at least two single-layer substrates. In this context, the first region A1 can be a chip region, and the second region A2 can be a cutting region; or, the first region A1 can be a chip region and a portion of the cutting region located around the chip region and close to the chip region, and the second region A2 can be the remaining cutting region located around the chip region and far from the chip region; or, the first region A1 can be a portion of the chip region located far from the cutting region, and the second region A2 can be the remaining chip region located close to the cutting region and the cutting region located around the chip region.

[0043] Reference Figure 2A The substrate 100 to be cut is, for example, a single-layer substrate, which includes a semiconductor substrate 101. The semiconductor substrate 101 can be a silicon substrate, a germanium-silicon substrate, a silicon carbide substrate, or a silicon-on-insulator substrate.

[0044] (SOI) substrates, germanium-on-insulator substrates, germanium-silicon-on-insulator substrates, or group III-V compound substrates (e.g., gallium nitride or gallium arsenide substrates), or other substrates used to support semiconductor devices. The semiconductor devices may be formed on the semiconductor substrate 101, and may include at least one of, for example, MOS devices, sensor devices, memory devices, and passive devices. In the following description, the semiconductor substrate 101 is, for example, a silicon substrate. The front side 100a and / or the back side 100b of the substrate 100 to be diced are, for example, the side surfaces on which the semiconductor devices are formed, with the back side 100b opposite to the front side 100a.

[0045] For example, the substrate 100 to be cut includes a top metal layer and a metal pad formed on one side of the semiconductor substrate 101, and the back surface 100b of the substrate 100 to be cut is the surface of the semiconductor substrate 101 facing away from the metal pad.

[0046] like Figure 2A As shown, in one embodiment, the substrate 100 to be cut may include a metal interconnect layer 102 and a metal pad PAD0 formed on one side of a semiconductor substrate 101. The metal interconnect layer 102 is, for example, the top metal layer of the substrate 100 before it is cut. A first dielectric layer 103 is formed around the metal interconnect layer 102 and the metal pad PAD0. The first dielectric layer 103 may include one or a combination of dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, and NDC (Nitrogen-doped Silicon Carbide). It should be noted that a metal layer and conductive vias may also be formed between the metal interconnect layer 102 and the semiconductor substrate 101 for interconnecting doped regions, semiconductor devices, and the metal interconnect layer 102 in the substrate 100 to be cut. The metal pad PAD0 is used to connect the substrate 100 to the outside. A first passivation layer 104 is formed on the first dielectric layer 103 and the metal pad PAD0, and the metal pad PAD0 is exposed through an opening in the first passivation layer 104.

[0047] Figure 2B The cross-sectional structure is shown after a redistribution layer 105 and a metal bonding pad PAD1 are formed on the front side 100a of the substrate 100 to be cut. (Refer to...) Figure 2B In one embodiment, a redistribution layer 105 and metal pads PAD1 may be further formed on the front side 100a of the substrate 100 to be cut, as needed. The redistribution layer 105 connects metal pads PAD0 and metal pads PAD1 respectively. In this embodiment, the redistribution layer 105 is the top metal layer of the substrate 100 to be cut before it is cut. The redistribution layer 105 can be used to interconnect multiple metal pads PAD0 or adjust the relative positions between metal pads PAD0 and metal pads PAD1 as needed. As an example, each metal pad PAD0 is connected to one or more metal pads PAD1, and the number of metal pads PAD1 corresponding to the same first region A1 is, for example, greater than the number of metal pads PAD0.

[0048] Forming the redistribution layer 105 and the metal pad PAD1 includes, by way of example, the following process: First, a redistribution layer 105 is formed on one side of the front surface 100a of the substrate 100 to be cut, and the redistribution layer 105 is connected to the metal pad PAD0; then, the metal pad PAD1 is formed on the redistribution layer 105 and is connected to the redistribution layer 105. To isolate the redistribution layer 105, metal pad PAD1, and metal pad PAD0, multiple dielectric material depositions can be performed during the formation of the redistribution layer 105 and metal pad PAD1 to form a second dielectric layer 106 (e.g., silicon oxide), a third dielectric layer 107 (e.g., silicon nitride), and a fourth dielectric layer 108 (e.g., silicon oxide) on the first passivation layer 104. The redistribution layer 105 is located on the surface of the second dielectric layer 106 and is connected to the metal pad PAD0 through metal vias in the second dielectric layer 106. The third dielectric layer 107 and the fourth dielectric layer 108 are located on the second dielectric layer 106 and the redistribution layer 105. The metal pad PAD1 is embedded in the surface of the fourth dielectric layer 108 and is connected to the redistribution layer 105 through metal vias located in the third dielectric layer 107 and the fourth dielectric layer 108.

[0049] Reference Figure 1 In step S2, a curved groove is formed from the back side 100b of the substrate to be cut along the second region A2 around the first region A1, and the top of the sidewall of the curved groove is curved.

[0050] Figure 2C The diagram shows a cross-section of the substrate 100 after the carrier plate 200 has been bonded to the front side 100a of the substrate 100 to be cut. Figure 2D A cross-section of the substrate 100 to be cut is shown after thinning from the back side 100b. (Refer to...) Figure 2C Before forming the curved grooves, the front side 100a of the substrate 100 to be cut is bonded to a carrier plate 200 (e.g., using bonding adhesive). Then, referring to... Figure 2D The substrate 100 to be cut is thinned from the back side 100b. In this embodiment, the substrate 100 to be cut is thinned by thinning the semiconductor substrate 101. After thinning, the thickness of the substrate 100 to be cut is, for example, about 50 μm to 400 μm.

[0051] Next, the curved groove is fabricated. As an example, the curved groove can be formed on the back side of the thinned substrate 100 to be cut using the following process.

[0052] First, such as Figure 2EAs shown, a first mask layer 10 (which may be photoresist or other suitable material) is formed on the back surface 100b of the substrate 100 to be cut. The first mask layer 10 has a first opening 11 located above the second region A2, and the width of the first opening 11 is smaller than the width of the second region A2 below. The first opening 11 extends laterally along the second region A2 (i.e., extends in a direction perpendicular to the normal of the substrate 100 to be cut) and is distributed around the first region A1. The first opening 11, viewed from a top view, is, for example, a grid shape. In this embodiment, the lateral distance between the first opening 11 and each of the first regions A1 is greater than 0. The orthographic projection of the first opening 11 onto the back surface 100b of the substrate 100 to be cut is, for example, located in the middle region of the second region A2. The width of the first opening 11 is, for example, 1 / 4 to 1 / 2 of the width of the second region A2.

[0053] Next, as Figure 2F As shown, a portion of the substrate 100 to be cut is removed, for example, using a dry etching process or a wet etching process, to etch the substrate 100 to be cut, forming a primary trench T1 corresponding to the first opening 11, extending from the back surface 100b of the substrate 100 to be cut (i.e., the back surface of the semiconductor substrate 101) into the substrate 100 to be cut. Then, the first mask layer 10 is removed. The depth of the primary trench T1 in the semiconductor substrate 101 is, for example, 10 μm to 20 μm. The primary trench T1 is formed corresponding to the first opening 11, and its bottom wall width is equal to the width of the first opening 11. In some embodiments, a laser process can also be used to remove a portion of the substrate 100 to be cut to form the primary trench T1. The sidewalls of the primary trench T1 can be planar, curved, or other irregular shapes, and the maximum width of the primary trench T1 is less than the width of the second region A2.

[0054] After that, as Figure 2G As shown, a planarization layer 20 is filled within the primary trench T1. The planarization layer 20 at least fills the primary trench T1, and can completely fill the primary trench T1 and further cover the back surface 100b of the substrate 100 to be cut outside the primary trench T1. The planarization layer 20 may include at least one of a bottom anti-reflective material (BARC), amorphous carbon, and other suitable materials. Figure 2G As shown, the thickness of the planarization layer 30 portion located within the primary trench T1 is greater than the thickness of the planarization layer 20 portion located outside the primary trench T1.

[0055] Next, refer to Figure 2GTaking the planarization layer 20 filling the primary trench T1 and covering the back surface 100b of the substrate 100 to be cut as an example, a second mask layer 30 is then formed on the surface of the planarization layer 20. The second mask layer 30 has a second opening 31 located above the second region A2. The orthographic projection of the second opening 31 onto the back surface 100b of the substrate 100 to be cut covers the primary trench T1 and the orthographic projection of the second regions A2 on both sides of the primary trench T1 onto the back surface 100b of the substrate 100 to be cut, and is adjacent to each of the first regions A1. Here, the width of the second opening 31 is, for example, equal to the width of the second region A2.

[0056] After that, as Figure 2H As shown, a portion of the planarization layer 20 and a portion of the substrate 100 to be cut are removed. Corresponding to the second opening 31, a curved groove T2 is formed on the back surface 100b of the substrate 100 to be cut. The top of the sidewall of the curved groove T2 is curved. The connection between the top of the sidewall and the bottom wall can be either a plane or a curved surface. The curved surface can be convex or concave. When the curved surface is convex, the surface of the top of the sidewall of the curved groove T2 protrudes away from the substrate 100 to be cut. When the curved surface is concave, the surface of the top of the sidewall of the curved groove T2 protrudes towards the substrate 100 to be cut. The sidewall of the curved groove T2 can be formed in the second region A2 on both sides of the primary groove T1. Then, the second mask layer 30 is removed.

[0057] After etching begins, the planarization layer 20 is etched first. Since the portion of the planarization layer 20 located within the primary trench T1 is thicker, even after the planarization layer 20 outside the primary trench T1 is completely etched, a planarization layer 20 still exists within the primary trench T1. When etching continues at this point, in addition to the planarization layer 20 within the primary trench T1 being etched, the exposed semiconductor substrate 101 is also etched, causing the sidewalls of the primary trench T1 and the surfaces of the second regions A2 on both sides of the primary trench T1 to no longer be perpendicular to each other, but instead form curved surfaces. After the planarization layer 20 within the primary trench T1 is etched away, the sidewalls of the primary trench T1 and the second regions A2 on both sides of the primary trench T1 form the sidewalls of the curved trench T2. To ensure that the planarization layer 20 at the bottom of the primary trench T1 is completely removed, the etching time can be controlled to etch the bottom of the primary trench T1 as well, for example, by continuing to etch downwards for 5μm to 10μm and then stopping the etching. Figure 2H As shown, after removing the second mask layer 30, the curved groove T2 corresponding to the second region A2 is exposed.

[0058] like Figure 2HAs shown, as an example, the bottom wall width of the curved groove T2 is less than the width of the second region A2, and the maximum width of the side wall of the curved groove T2 is less than, greater than, or equal to the width of the second region A2; from the bottom to the top of the curved groove T2, the distance between the two side walls of the curved groove T2 gradually increases. The longitudinal section of the side wall of the curved groove T2 is a circular arc.

[0059] Reference Figure 1 In step S3, the substrate 100 to be cut is cut to obtain multiple core particles. The orthographic projection of the cutting position on the surface plane of the substrate 100 to be cut lies within the orthographic projection of the curved groove T2 on the surface plane of the substrate 100 to be cut. The connection between the back side and the side side of each core particle includes the curved surface. The connection between the back side and the side side of each core particle includes the area where the corner is located and the area where the edge is located.

[0060] The substrate 100 to be cut can be cut from either the back side or the front side. In this embodiment, when cutting the substrate 100 from the back side, the substrate 100 is cut from the curved groove T2; when cutting the substrate 100 from the front side, the substrate 100 is cut from the position where the curved groove T2 is projected onto the front side 100a of the substrate 100. The projected image of the cutting position onto the surface plane of the substrate 100 can be located within the projected image of the bottom wall or side wall of the curved groove T2, or the connection between the bottom wall and the side wall; or, the projected image of the cutting position onto the surface plane of the substrate 100 coincides with the projected image of the bottom wall or the bottom wall and the part of the side wall connected to the bottom wall of the curved groove T2 onto the surface plane of the substrate 100. Figure 2I As shown, a lamination process is performed by bonding the back side 100b of the substrate 100 to be cut to a carrier tape, such as the UV film 300, and then debonding to remove the carrier 200. Afterwards, as... Figure 2J As shown, plasma etching or other cutting processes can be used to cut the substrate 100 from the position of the orthographic projection of the curved trench T2 onto the front surface 100a of the substrate 100 to be cut. For example, this may include: forming a mask layer on the front surface 100a of the substrate 100 to be cut and patterning an opening in the mask layer to expose a portion of the front surface 100a of the substrate 100 to be cut located in the second region A2; the orthographic projection of the bottom wall of the curved trench T2 and at least a portion of the curved sidewalls connected to the bottom wall onto the surface plane of the substrate 100 to be cut lies within the orthographic projection of the mask layer opening onto the surface plane of the substrate 100 to be cut; then, a plasma etching process is performed to remove the second region A2 exposed by the mask layer opening, forming a channel through the substrate 100 to be cut corresponding to the second region A2; and each first region A1 is separated from the substrate 100 to form a core (e.g., Figure 2J The core particles CP1 and CP2 shown are formed on the surface of the substrate 100 to be cut, that is, the front side 100a of the substrate 100 to be cut is the front side of the core particle, and the back side 100b of the substrate 100 to be cut is the back side of the core particle.

[0061] The orthographic projection of the cutting position on the surface plane of the substrate 100 to be cut in the above-described cutting process can coincide with the orthographic projection of the bottom wall of the curved groove T2 on the surface plane of the substrate 100 to be cut. Alternatively, the orthographic projection of the cutting position on the surface plane of the substrate 100 to be cut can coincide with the orthographic projection of the bottom wall of the curved groove T2 and the portion of the sidewall connected to the bottom wall on the surface plane of the substrate 100 to be cut. By cutting the substrate 100 to be cut, the removed portion may be located only on the bottom wall of the curved groove T2, or the removed portion may include the bottom wall of the curved groove T2 and a portion of the sidewall. The curved surface at the top of the sidewall of the curved groove T2 is retained at the edge of the corresponding core particle CP, so that the edge of the core particle CP is curved, resulting in a smooth transition between the back and side surfaces of the core particle CP and avoiding the generation of sharp corners.

[0062] Reference Figure 1 and Figure 2K Optionally, step S4 may be further performed to stack at least one of the core particles with the bottom substrate 400, wherein the edge of the core particle having the curved surface faces away from the bottom substrate 400.

[0063] Depending on the requirements, the bottom substrate 400 may have a metal interconnect structure and may also have semiconductor devices formed thereon. As an example, the bottom substrate 400 is bonded to cores CP1 and CP2. The bottom substrate 400 may be a single-layer substrate or a three-dimensional stacked substrate. Figure 2K As shown, a metal pad PAD2 is formed on the surface of the bottom substrate 400. The specific structure of the bottom substrate 400 can be configured according to specific needs. For example, in one embodiment, the bottom substrate 400 may include a semiconductor substrate and metal interconnect structures, metal pads, redistribution layers, dielectric materials, and metal vias formed on the semiconductor substrate.

[0064] UV irradiation can reduce the adhesion between the core and the UV film 300, thereby facilitating the removal of the core. In this embodiment, a metal pad PAD1 is formed on the front side of the core, and a corresponding metal pad PAD2 is formed on the surface of the bottom substrate 400. At least one of the cores can be bonded to the bottom substrate 400 through hybrid bonding. In other embodiments, other processes can be used to stack and connect the core and the bottom substrate 400, for example, through bump bonding.

[0065] Reference Figure 1 and Figure 2LFurther, step S5 can be performed to form a filling cover layer 110, which covers the core and fills the voids around the core.

[0066] The filler capping layer 110 may include one or a combination of dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, and NDC (nitrogen-doped silicon carbide). In one embodiment, the filler capping layer 110 includes a nitride layer and an oxide layer, wherein the nitride layer conformally covers the bottom substrate 400 and the core chip bonded to the bottom substrate 400, and the oxide layer covers the nitride layer.

[0067] like Figure 2M As shown, in one embodiment, after forming the filler capping layer 110, the forming method may further include: performing a planarization process (e.g., chemical mechanical polishing) to remove at least a portion of the filler capping layer 110 covering the back side of the core.

[0068] In the semiconductor structure formation method provided by the present invention, before cutting the substrate 100 to be cut to obtain the core, a curved groove T2 with a curved top sidewall is formed along the second region A2 around the first region A1 from the back side 100b of the substrate 100 to be cut. Then, the substrate 100 to be cut is cut from the position where the curved groove T2 is projected onto the surface plane of the substrate 100 to be cut, so that the curved surface of the sidewall of the curved groove T2 is retained at the edge of the corresponding core. After the core is stacked and connected to the bottom substrate 400, the edge with the curved surface faces away from the bottom substrate 400, that is, the exposed surface of the core does not have sharp corners. In this way, after the filling capping layer 110 is formed, stress concentration points will not be generated at the edge of the core due to sharp corners, thereby reducing the risk of cracking of the filling capping layer 110, ensuring the quality of the filling capping layer 110 and avoiding damage to the core due to stress intensification. This facilitates the stress balance inside the formed semiconductor structure and ensures the quality of the semiconductor structure.

[0069] This invention also relates to a semiconductor structure, which can be formed using the semiconductor structure formation method described in the above embodiments.

[0070] Reference Figure 2M In this embodiment of the invention, the semiconductor structure includes a bottom substrate 400, at least one core (such as core CP1 and core CP2) stacked on the surface of the bottom substrate 400, and a filling cover layer 110. The front side 100a of the core faces the bottom substrate 400 and the back side 100b faces away from the bottom substrate 400. Furthermore, the connection between the back side 100b and the side of the core edge is curved. The filling cover layer 110 at least covers the sidewalls of the core and fills the gaps around the core.

[0071] Reference Figures 2A to 2J In some embodiments, the core is obtained by cutting the substrate 100 to be cut, which has a curved groove T2 formed thereon. The orthographic projection of the cutting position on the surface plane of the substrate 100 to be cut lies within the orthographic projection of the curved groove T2 on the surface plane of the substrate 100 to be cut. The top of the sidewall of the curved groove T2 includes the curved surface. As an example, the substrate 100 to be cut includes a plurality of first regions A1 and a second region A2 located around the first regions A1. The second region A2 of the substrate 100 to be cut has a primary groove T1 formed. The curved groove T2 is formed by partially removing the sidewall of the primary groove T1 and the substrate 100 to be cut located on both sides of the primary groove T1 in the second region A2.

[0072] In some embodiments, the semiconductor structure may further include other substrates stacked on one side of the back face 100b of the die. Furthermore, in some embodiments, by performing TSV and redistribution processes from the back face 100b of the die, the semiconductor structure may further include a TSV via penetrating the semiconductor substrate 101 in the die and a redistribution layer located on one side of the back face 100b of the die, the TSV via being connected to a metal layer in the die, and the redistribution layer being connected to the TSV via.

[0073] In the semiconductor structure of this invention, the connection between the back surface 100b and the side surface of the chip edge stacked on the bottom substrate 400 is curved. The exposed surface of the chip does not have sharp corners, so stress concentration points will not be generated at the chip edge due to sharp corners. This can avoid the stress concentration points from causing cracks in the filling cover layer 110, which helps to ensure the quality of the filling cover layer 110 and avoid damage to the chip due to stress aggravation. It also facilitates the stress balance inside the formed semiconductor structure and ensures the quality of the semiconductor structure.

[0074] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. As for the semiconductor structure in the embodiments, since it corresponds to the semiconductor structure fabrication method disclosed in the embodiments, the description is relatively simple. For relevant details, please refer to the description of the semiconductor structure fabrication method.

[0075] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate to be cut is provided, the substrate to be cut includes a plurality of first regions and a second region located around the first regions, and the surface of the substrate to be cut has a front side and a back side facing away from each other; A curved groove is formed from the back side of the substrate to be cut along the second region around the first region, and the top of the sidewall of the curved groove is curved. Multiple core particles are obtained by cutting the substrate to be cut. The orthographic projection of the cutting position on the surface plane of the substrate to be cut is located within the orthographic projection of the curved groove on the surface plane of the substrate to be cut. The connection between the back side and the side side of each core particle includes the curved surface.

2. The forming method as described in claim 1, characterized in that, The substrate to be cut includes a semiconductor substrate and a top metal layer and a metal pad formed on one side of the semiconductor substrate, and the back side of the substrate to be cut is the surface of the semiconductor substrate facing away from the metal pad.

3. The forming method as described in claim 1, characterized in that, Before forming the curved groove, the method further includes: Bond the front side of the substrate to be cut to a carrier plate; and The substrate to be cut is thinned from the back side.

4. The forming method as described in claim 1, characterized in that, The second region of the substrate to be cut has a primary groove, and the curved groove is formed by removing part of the sidewall of the primary groove and the part of the substrate to be cut located in the second region on both sides of the primary groove.

5. The forming method as described in claim 4, characterized in that, Forming the primary trench includes: A first mask layer is formed on the back side of the substrate to be cut. The first mask layer has a first opening located above the second region, and the width of the first opening is smaller than the width of the second region. A portion of the substrate to be cut is removed, and a primary trench is formed corresponding to the first opening, extending from the back side into the substrate to be cut.

6. The forming method as described in claim 4, characterized in that, Forming the curved groove includes: A planarization layer is filled within the primary trench, and the planarization layer also covers the back surface outside the primary trench; A second mask layer is formed on the surface of the planarization layer. The second mask layer has a second opening located above the second region. The orthographic projection of the second opening on the back side of the substrate to be cut covers the primary trench and the orthographic projection of the second region on both sides of the primary trench on the back side of the substrate to be cut. A portion of the planarization layer and a portion of the substrate to be cut are removed, and a curved groove is formed on the back side of the substrate to be cut corresponding to the second opening.

7. The forming method as described in claim 1, characterized in that, The bottom wall width of the curved groove is less than the width of the second area, and the maximum width of the side wall of the curved groove is equal to the width of the second area; from the bottom to the top of the curved groove, the distance between the two side walls of the curved groove gradually increases.

8. The forming method as described in claim 1, characterized in that, The longitudinal section of the sidewall of the curved groove is an arc.

9. The forming method as described in claim 1, characterized in that, The substrate to be cut is cut from either the front side or the back side using a plasma etching process.

10. The forming method according to claim 1, characterized in that, The orthographic projection of the cutting position on the surface plane of the substrate to be cut coincides with the orthographic projection of the bottom wall of the curved groove or the bottom wall and the part of the side wall connected to the bottom wall on the surface plane of the substrate to be cut.

11. The forming method according to any one of claims 1 to 10, characterized in that, The forming method further includes: At least one of the core particles is stacked and connected to a bottom substrate, wherein the edge of the core particle having the curved surface faces away from the bottom substrate; A filling cover layer is formed, which covers the core and fills the voids around the core; A planarization process is performed to remove at least part of the filler coating that covers the back side of the core.

12. A semiconductor structure, characterized in that, include: Bottom substrate; At least one core particle is stacked and connected to the surface of the bottom substrate, the front side of the core particle faces the bottom substrate and the back side faces away from the bottom substrate, and the connection between the back side and the side of the core particle is curved. And a filling cover layer that at least covers the sidewalls of the core and fills the voids around the core.

13. The semiconductor structure as described in claim 12, characterized in that, The core is obtained by cutting the substrate to be cut from a substrate with a curved groove. The orthographic projection of the cutting position on the surface plane of the substrate to be cut is located within the orthographic projection of the curved groove on the surface plane of the substrate to be cut. The top of the sidewall of the curved groove includes the curved surface.

14. The semiconductor structure as described in claim 13, characterized in that, The substrate to be cut includes a plurality of first regions and a second region located around the first regions. The second region of the substrate to be cut has a primary trench formed. The curved trench is formed by removing part of the sidewalls of the primary trench and the portion of the substrate to be cut located in the second region on both sides of the primary trench.

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