Semiconductor element and method for manufacturing the same

Abstract

A semiconductor device and a method of fabricating the same are disclosed. The method includes providing a first interposer including a plurality of first passive components, providing a second interposer including a plurality of first active components, bonding the first interposer to the second interposer to form a first stack structure, and bonding a plurality of dies having different functions to the second interposer. The plurality of dies and the second interposer include a plurality of micro-bumps therebetween. The first interposer and the second interposer include a plurality of hybrid bonds therebetween. The plurality of first passive components include deep trench capacitors.

Description

Technical Field

[0001] This invention relates to a method for manufacturing semiconductor devices, and more particularly to a method for stacking passive component interposers and active component interposers to form a stacked structure. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to the continuous increase in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). To a large extent, this increase in integration density stems from the continuous reduction in the minimum feature size, allowing more smaller components to be integrated into a given area. These smaller electronic components also require smaller packages utilizing smaller areas compared to previous packages. Some smaller types of semiconductor component packages include quad flat packages (QFP), pin grid array (PGA) packages, ball grid array (BGA) packages, flip chips (FC), three-dimensional integrated chips (3DIC), wafer-level packages (WLP), and package-on-package (PoP) devices, among others.

[0003] 3D integrated chips offer increased integration density and other advantages, such as faster speeds and higher bandwidth, due to the reduced length of interconnects between stacked chips. However, many challenges remain to be addressed for 3D integrated chip technology. Summary of the Invention

[0004] One embodiment of the present invention discloses a method for fabricating a semiconductor device. The method primarily involves providing a first interposer layer containing a plurality of first passive (non-active) devices, and a second interposer layer containing a plurality of first active (active) devices. The first interposer layer is bonded to the second interposer layer to form a first stacked structure. Then, a plurality of dies (bare dies) with different functions are bonded to the second interposer layer. The plurality of dies and the second interposer layer contain a plurality of microbumps, the first interposer layer and the second interposer layer contain a plurality of hybrid bonds, and the plurality of first passive devices include deep trench capacitors.

[0005] Another embodiment of the present invention discloses a semiconductor device comprising a first stacked structure, wherein the first stacked structure further comprises a first interposer, a second interposer bonded to the first interposer, and a hybrid bonding connecting the first interposer and the second interposer. The first interposer comprises a plurality of passive elements, and the second interposer comprises a plurality of active elements. Attached Figure Description

[0006] Figure 1 This is a schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention;

[0007] Figure 2 This is a schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention.

[0008] Symbol explanation:

[0009] 12: First Intermediary Layer

[0010] 14: Base

[0011] 16: Deep trench capacitors

[0012] 18: Metal interconnects

[0013] 20: Silicon Through-Hole

[0014] 22: Second Intermediary Layer

[0015] 24: Stacked Structure

[0016] 26: Direct-bonded internal connections

[0017] 28: Grains

[0018] 30: Grain

[0019] 32: Microbulbs

[0020] 34: Stacked structure

[0021] 36: Supporting substrate

[0022] 38: Through-mold guide hole

[0023] 40: Sealing layer

[0024] 42: Third Intermediary Layer

[0025] 44: Protrusion

[0026] 46: Grains

[0027] 48: Grains

[0028] 50: Grain

[0029] 52: Fourth Intermediary Layer Detailed Implementation

[0030] Although this document discusses specific configurations and arrangements, it should be understood that this is for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of this disclosure. It will be apparent to those skilled in the art that this disclosure can also be used in a variety of other applications.

[0031] It should be noted that references to "an embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc., in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but each embodiment may not necessarily include those specific features, structures, or characteristics. Furthermore, such terms do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments is within the knowledge of those skilled in the art.

[0032] Generally, terms can be understood, at least in part, based on their usage in context. For example, the term “one or more” (at least in part, depending on context), as used herein, can be used to describe any feature, structure, or characteristic in a single sense, or to describe multiple combinations of features, structures, or characteristics. Similarly, terms such as “a,” “an,” or “the” can again be understood to express a single usage or to convey multiple usages, at least in part, depending on context. Furthermore, the term “based on” can be understood to not necessarily convey an exclusive set of factors, and can conversely allow for additional factors that are not necessarily explicitly described, at least in part, depending on context.

[0033] It should be readily understood that the meanings of “on top of,” “above,” and “above” in the disclosed content of this case should be interpreted in the broadest possible sense, such that “on top of” not only means “directly” on something, but also includes the meaning of being on something and having intermediate features or layers between them, and that “above” or “above” not only means being on or above something, but also includes the meaning of not having intermediate features or layers (i.e., being directly on something).

[0034] Furthermore, for ease of description, as illustrated in the accompanying drawings, spatial relative terms such as "below," "under," "lower," "above," and "higher" may be used to describe the relationship of one or more elements or features to another. In addition to the orientations depicted in the accompanying drawings, the spatial relative terms are intended to encompass different orientations of elements in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptions used herein may be interpreted accordingly.

[0035] As used herein, the term "substrate" refers to the material on which layers of material are subsequently added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials, such as glass, plastic, or sapphire wafers.

[0036] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of an underlying or upper layer structure, or may have a extent smaller than that of the underlying or upper layer structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes between the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a single layer, which may include one or more layers, and / or may have one or more layers on and / or below it. A single layer may contain multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where contacts, interconnects, and / or vias are formed) and one or more dielectric layers.

[0037] Please refer to Figure 1 , Figure 1 This is a schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention. Figure 1 As shown, a first interposer 12 made of semiconductor material is first provided. The first interposer 12 includes a wafer or substrate 14 made of semiconductor material. The substrate 14 can be a semiconductor substrate, such as a silicon substrate, an epitaxial silicon substrate, a silicon carbide substrate, or even a silicon-on-insulator (SOI) substrate; all these material choices are within the scope of this invention. In this embodiment, the first interposer 12 preferably includes multiple passive components, such as multiple deep trench capacitors (DTCs) 16, and these passive components are preferably fabricated according to process nodes such as 65 nm or 130 nm.

[0038] According to one embodiment of the present invention, the first interposer 12 may include an interlayer dielectric layer or an intermetallic dielectric layer disposed on the substrate 14, and a metal interconnect 18 disposed within the intermetallic dielectric layer. The uppermost metal interconnect 18 may also serve as a contact point for a hybrid bond or a direct bond interconnect (DBI) 26, which can be mated with a direct bond interconnect 26 of another interposer or wafer in subsequent fabrication processes. Furthermore, the substrate 14 of the first interposer 12 preferably contains through-silicon vias (TSVs) 20 to connect passive components on the substrate 14, which can be used to connect bumps in subsequent fabrication processes. In this embodiment, the interlayer dielectric layer and the intermetal dielectric layer may contain oxides such as, but not limited to, tetraethyl orthosilicate (TES). The metal interconnect 18, the direct bonding interconnect 26, and the silicon through-hole 20 may contain aluminum, chromium, copper, tantalum, molybdenum, tungsten, or combinations thereof, but are not limited thereto.

[0039] Then, a second interposer 22 made of semiconductor material is provided. Like the first interposer 12, the second interposer 22 preferably comprises a wafer or substrate 14 made of semiconductor material, and the substrate 14 may be a semiconductor substrate such as a silicon substrate, an epitaxial silicon substrate, a silicon carbide substrate, or even a substrate made of silicon-on-insulator (SOI), all of which fall within the scope of this invention. In this embodiment, the second interposer 22 preferably comprises multiple active components (not shown) such as static random-access memory (SRAM), medium-voltage components, high-voltage components, pixel circuits, low-voltage components of low-voltage drive circuits, and / or graphics processing units (GPUs), etc., and the active components are preferably fabricated according to process nodes such as 28 nm, 22 nm, 14 nm, or 12 nm.

[0040] Then, a front-end of line (FEOL) fabrication process and a back-end of line (BEOL) fabrication process are performed on the second interposer 22. In this embodiment, the front-end of line fabrication process may include fabricating, for example, metal oxide semiconductor (MOS) transistors, oxide field-effect semiconductor (OS FETs), fin field-effect transistors (FinFETs), or other active devices on the second interposer 22, depending on the fabrication process or product selection. The back-end of line fabrication process may form metal interconnect structures, such as inter-metal dielectric layers and metal interconnects 18, on these active devices. Taking the fabrication of a metal-oxide-semiconductor transistor as an example, the front-end fabrication process may include forming a base with a gate structure on a substrate 14, spacers (not shown) on the sidewalls of the gate structure, and source / drain regions on both sides of the spacers. The gate structure may contain polysilicon or metal material, the spacers may contain dielectric materials such as silicon oxide or silicon nitride, and the source / drain regions may contain different dopants depending on the conductivity type of the transistor being fabricated, such as P-type dopants or N-type dopants.

[0041] Next, an interlayer dielectric layer can be formed on the substrate 14 and cover the metal oxide semiconductor transistor or other active components. Then, contact plugs and subsequent metal interconnect fabrication processes are performed to form multiple contact plugs connecting the source / drain regions and the gate structure within the interlayer dielectric layer. The interlayer dielectric layer is disposed on the interlayer dielectric layer, and the metal interconnect 18 is disposed within the interlayer dielectric layer and connects to the contact plugs. The metal interconnect 18 on the topmost front side of the second interlayer 22 can also serve as a contact point for the direct bond interconnect (DBI) 26, which can be docked with the direct bond interconnect 26 of another interlayer or wafer in subsequent fabrication processes. In this embodiment, the interlayer dielectric layer and the intermetal dielectric layer may contain oxides, such as, but not limited to, tetraethylorthosilicate (TES). The contact plugs, metal interconnects 18, or direct bonding interconnects 26 may contain aluminum, chromium, copper, tantalum, molybdenum, tungsten, or combinations thereof, but are not limited thereto. Furthermore, a through-silicon via (TSV) 20 is preferably provided within the substrate 14 of the second interposer 22 to connect the active elements on the substrate 14.

[0042] It should be noted that, according to one embodiment of the present invention, the first intermediary layer 12 includes passive elements as described above, while the second intermediary layer 22 includes active elements. Preferably, the first intermediary layer 12 does not include any other elements such as active elements besides passive elements, and the second intermediary layer 22 also preferably does not include any other elements such as passive elements besides active elements.

[0043] Next, a hybrid bonding process is performed to connect the first interposer 12 and the second interposer 22 to form a stacked structure 24. During the bonding process, the second interposer 22 can be flipped so that the front side of the second interposer 22 or the side exposing the metal interconnects 18 faces the front side of the first interposer 12 or the side exposing the metal interconnects 18. Then, by means of heating, the metal interconnects 18 of the second interposer 22 are brought into direct contact with the metal interconnects 18 of the first interposer 12, thereby directly bonding the metal interconnects 18 of the two interposers to form a direct bond interconnect 26 or a hybrid bond.

[0044] Multiple bumps 44 or solder balls can then be formed and connected to silicon vias 20 via metal interconnects 18 at the bottom of the first interposer 12. Multiple dies 28 and 30, fabricated using wafer dicing processes and possessing different functions, are then bonded to the second interposer 20. The dies 28 and 30 can be connected to the interposer using, for example, microbumps 32 or direct bonding interconnects 26, depending on the product or specification. For example, in this embodiment, the die 28 on the left is bonded to the second interposer 22 using microbumps 32, while the die 30 on the right is bonded to the second interposer 22 using direct bonding interconnects 26. In this embodiment, the dies 28 and 30 may include high bandwidth memory (HBM) dies, radio frequency integrated circuit (RFIC) dies, power amplifier (PA) dies, or high electron mobility transistor (HEMT) dies based on III-V semiconductors such as gallium nitride (GaN).

[0045] It should be noted that although this embodiment stacks two intermediary layers with the passive element at the bottom and the active element at the top, it is not limited to this order. According to other embodiments of the present invention, the active element intermediary layer can be placed at the bottom of the stacked structure and the passive element intermediary layer at the top of the stacked structure. This variation is also within the scope of the present invention.

[0046] Please continue to refer to Figure 2 , Figure 2This is a schematic diagram of a semiconductor device according to an embodiment of the present invention. To correspond with the foregoing embodiments, the same elements in this embodiment are preferably referred to by the same reference numerals as those in the foregoing embodiments. For example... Figure 2 As shown, a carrier or carrier substrate 36 is first provided. Like the aforementioned interposer, the carrier substrate 36 also includes a silicon wafer or substrate 14 made of semiconductor material. The substrate 14 can be a semiconductor substrate, such as a silicon substrate, an epitaxial silicon substrate, a silicon carbide substrate, or even a substrate made of silicon-on-insulator (SOI). However, it is not limited to this; according to other embodiments of the present invention, the carrier substrate 36 may also include materials such as silicon, silicon carbide, or glass. Unlike the first interposer 12 or the second interposer 22, which have active and / or passive components fabricated by front-end or back-end processes, the carrier substrate 36 is preferably a blank wafer without any active and / or passive components fabricated by front-end or back-end processes.

[0047] Then, a patterned dielectric material (not shown) or sealing material can be formed on the carrier substrate 36, and then a plurality of through molding vias (TMVs) 38 can be formed in the dielectric material or sealing material. The through molding vias 38 may contain aluminum, chromium, copper, tantalum, molybdenum, tungsten or combinations thereof, but are not limited thereto.

[0048] Two sets of stacked structures 24 and 34 can then be provided, wherein each stacked structure 24 and 34 is preferably formed by stacking a passive component intermediary layer and an active component intermediary layer in the aforementioned embodiments. In detail, the stacked structure 24 includes the first intermediary layer 12 and the second intermediary layer 22 in the aforementioned embodiments, and the stacked structure 34 includes the third intermediary layer 42 and the fourth intermediary layer 52, wherein the first intermediary layer 12 is a passive component intermediary layer as described above and contains a plurality of passive components and metal interconnects 18 connecting the passive components, and the second intermediary layer 22 is an active component intermediary layer and contains a plurality of active components and metal interconnects 18 connecting the active components.

[0049] Unlike stacked structure 24, where passive components are located at the bottom and active components at the top, the stacking positions of passive and active components in stacked structure 34 are preferably reversed. For example, the third interposer layer 42 is preferably an active component interposer layer containing multiple active components and metal interconnects 18 connecting the active components, while the fourth interposer layer 52 is a passive component interposer layer containing multiple passive components such as deep trench capacitors 16 and metal interconnects 18 connecting the passive components. The first interposer layer 12 and the fourth interposer layer 52 can be fabricated using the same process and have the same component composition, while the second interposer layer 22 and the third interposer layer 42 can be fabricated using the same process and have the same component composition. In other words, the passive components located in the lower layer of stacked structure 24 are located on the same layer as the active components located in the lower layer of stacked structure 34, and the active components located in the upper layer of stacked structure 24 are located on the same layer as the passive components located in the upper layer of stacked structure 34.

[0050] The two stacked structures 24 and 34 are then bonded to the carrier substrate 36, and a molding layer 40 is formed surrounding the two stacked structures 24 and 34 and the through-hole 38. According to one embodiment of the present invention, the molding layer 40 may comprise an organic or inorganic thin film material such as oxide or fluorinated silicate glass (FSG). Furthermore, the molding layer 40 may comprise a polymer material such as a thermosetting polymer, a thermoplastic polymer, or a mixture thereof. More specifically, the polymer material may comprise plastic materials, epoxy resins, polyimide, polyethylene terephthalate (PET), polyvinyl chloride (PVC), polymethyl methacrylate (PMMA), polymer components doped with specific fillers, or combinations thereof.

[0051] Then, multiple bumps 44 or solder balls can be formed to connect the through-hole 38 and the two stacked structures 24 and 34. Multiple dies 46, 48, and 50, which have undergone wafer dicing and have different functions, are then bonded to the carrier substrate 36 via microbumps 32. It should be noted that although the dies 46, 48, and 50 in this embodiment are connected to the carrier substrate 36 using microbumps 32, this is not a limitation. According to other embodiments of the present invention, dies 46, 48, and 50 can be bonded to the carrier substrate 36 using hybrid bonding or direct bonding interconnects, depending on the die specifications. This variation is also within the scope of the present invention. In this embodiment, the chips 46, 48, and 50 may include high bandwidth memory (HBM) chips, radio frequency integrated circuit (RFIC) chips, power amplifier (PA) chips, or high electron mobility transistor (HEMT) chips based on III-V semiconductors such as gallium nitride (GaN).

[0052] In summary, this invention primarily discloses a method for vertically stacking and bonding two intermediate layers using hybrid bonding or direct bonding interconnects (DBI), wherein each intermediate layer contains passive or active elements, such as those described above. Figure 1 The first interposer layer 12 is preferably a passive element interposer layer containing only passive elements, while the second interposer layer 22 is an active element interposer layer containing only active elements. According to a preferred embodiment of the present invention, by using this vertical stacking method to stack interposers having passive and active elements respectively, the stacked structure prepared by the present invention can significantly reduce power consumption, increase the number of inputs / outputs and bandwidth, and enable products to achieve smaller linewidths, die types and thicknesses.

[0053] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, Include: The first intermediary layer includes multiple first passive elements; The second intermediary layer includes multiple first active elements; and The first interposer layer is bonded to the second interposer layer to form a first stacked structure.

2. The method of claim 1 further comprises bonding a plurality of grains with different functions onto the second interposer layer.

3. The method of claim 2 further comprises forming a plurality of microbumps between the plurality of grains and the second interposer layer.

4. The method of claim 1 further comprises forming a plurality of direct bond interconnects between the first interposer layer and the second interposer layer.

5. The method of claim 1, wherein the plurality of first passive elements comprises deep trench capacitors.

6. The method of claim 1, further comprising: The third intermediary layer includes multiple second active elements; The fourth intermediary layer includes multiple second passive elements; and The third intermediate layer is bonded to the fourth intermediate layer to form a second stacked structure.

7. The method of claim 6, further comprising: Provide a substrate; Multiple through-holes are formed within the substrate; The first stacked structure and the second stacked structure are bonded to the carrier substrate; and A sealing layer is formed around the first stacked structure and the second stacked structure.

8. The method of claim 1, wherein the first interposer comprises a silicon wafer.

9. A semiconductor element, characterized in that, Include: The first stacked structure includes: The first intermediary layer contains multiple passive components; and A second interposer layer is attached to the first interposer layer, wherein the second interposer layer contains a plurality of active elements.

10. The semiconductor device of claim 9 further comprises a plurality of grains with different functions disposed on the second interposer layer.

11. The semiconductor device of claim 10, further comprising a plurality of microbumps disposed between the plurality of grains and the second interposer layer.

12. The semiconductor device of claim 9 further includes a plurality of direct-bonded interconnects disposed between the first interposer and the second interposer.

13. The semiconductor element of claim 9, wherein the plurality of first passive elements comprises deep trench capacitors.

14. The semiconductor element of claim 9, further comprising: The second stack structure includes: The third intermediary layer contains multiple second active elements; A fourth interposer layer is attached to the third interposer layer, wherein the fourth interposer layer includes a plurality of second passive elements; and Multiple direct-bond interconnects connect the third and fourth intermediary layers.

15. The semiconductor element of claim 14, further comprising: substrate; Multiple through-holes are provided within the supporting substrate; The first stacked structure and the second stacked structure are disposed on the carrier substrate; and A sealing layer surrounds the first stacked structure and the second stacked structure.

16. The semiconductor device of claim 9, wherein the first interposer comprises a silicon wafer.

17. The semiconductor device of claim 9, wherein the second interposer comprises a silicon wafer.

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