Semiconductor device and method of manufacturing stackable rigid-flex optical modules with flexible cables forming channels

Abstract

Semiconductor devices and methods of manufacturing stackable rigid-flex optical modules with flexible cables forming channels are disclosed. A semiconductor device has a first co-packaged optical (CPO) module and a second CPO module stacked on the first CPO module. The first CPO module has a first flexible cable. A substrate is attached to the first flexible cable. A first semiconductor die and a first photonic semiconductor die are disposed on the first flexible cable opposite the substrate. The first flexible cable is deformed to attach the first flexible cable to a side surface of the first photonic semiconductor die. The second CPO module has a second flexible cable. A second semiconductor die and a second photonic semiconductor die are disposed on a first portion of the second flexible cable. A second portion of the second flexible cable is folded over the second semiconductor die and the second photonic semiconductor die.

Description

Technical Field

[0001] This invention relates generally to semiconductor devices, and more specifically, to semiconductor devices and methods for manufacturing stackable rigid-flex co-package optical (CPO) modules in which flexible cables form channels. Background Technology

[0002] Semiconductor devices are commonly found in modern electronic products. They perform a wide range of functions, such as signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electronic devices, converting sunlight into electrical energy, and creating visual images for television displays. Semiconductor devices are used in communications, power conversion, networking, computers, entertainment, and consumer products. They are also found in military applications, aerospace, automotive, industrial controllers, and office equipment.

[0003] Photonic semiconductor devices capable of transmitting or receiving signals via light are becoming increasingly common. Compared to electrical signals, device-to-device transmission via light offers numerous advantages, particularly avoiding losses due to wire resistance and reducing the effects of electromagnetic interference (EMI). However, to date, the options for packaging photonic semiconductor devices have been limited and unsatisfactory in many respects. Therefore, there is a need for improved co-packaged optical (CPO) modules and their manufacturing methods. Attached Figure Description

[0004] Figures 1a-1c A semiconductor wafer with multiple semiconductor dies separated by saw tracks is shown; Figures 2a-2i The process of forming a rigid-flexible co-packaged optical module with a semiconductor die is shown; Figures 3a-3e Stackable co-packaged optical modules are shown; Figures 4a-4c This illustrates stacking two co-packaged optical modules to form a stacked optical package; Figure 5 An example of flipping is shown; and Figure 6a and 6b An electronic device with stacked optical packages is shown. Detailed Implementation

[0005] In the following description with reference to the figures, the invention is described in one or more embodiments, wherein the same numerals denote the same or similar elements. Although the invention has been described in the best mode for carrying out its objectives, those skilled in the art will appreciate that the invention is intended to cover alternatives, modifications, and equivalents that may be included within the spirit and scope of the invention as defined by the appended claims and their equivalents, supported by the following disclosure and the figures. Features shown in the figures are not necessarily drawn to scale. Elements assigned the same reference numerals in the figures have similar functions to each other. As used herein, the term "semiconductor die" refers to both the singular and plural forms of the word, and therefore can refer to both a single semiconductor device and multiple semiconductor devices.

[0006] Semiconductor devices are typically manufactured using two complex processes: front-end fabrication and back-end fabrication. Front-end fabrication involves forming multiple dies on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional circuit. Active electrical components, such as transistors and diodes, have the ability to control the flow of current. Passive electrical components, such as capacitors, inductors, and resistors, create the voltage and current relationships necessary to perform the circuit's function.

[0007] Back-end manufacturing refers to the process of dicing or dicing finished wafers into individual semiconductor dies and packaging these dies for structural support, electrical interconnection, and environmental isolation. To dice a semiconductor die, it is scribed and broken along non-functional areas (referred to as serrations or saw marks). Dicing is performed using laser cutting tools or saw blades. After dicing, the individual semiconductor dies are placed on a package substrate that includes pins or contact pads for interconnection with other system components. Contact pads formed on the semiconductor die are then connected to contact pads within the package. These electrical connections can be made using conductive layers, bumps, column bumps, conductive paste, or wire bonding. A sealant or other molding material is deposited on the package to provide physical support and electrical isolation. The completed package is then inserted into an electrical system, making the semiconductor device functional and available to other system components.

[0008] Figure 1aA semiconductor wafer 100 with a base substrate material 102 is shown, such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, silicon nitride, lithium niobate (LiNbO3), or other bulk materials used for structural support. Multiple semiconductor dies or electrical components 104 are formed on the wafer 100, separated by non-active inter-die wafer regions or saw tracks 106. The saw tracks 106 provide dicing areas to cut the semiconductor wafer 100 into individual semiconductor dies 104. In one embodiment, the semiconductor wafer 100 has a width or diameter of 100-450 millimeters (mm).

[0009] Figure 1b A cross-sectional view of a portion of a semiconductor wafer 100 is shown. Each semiconductor die 104 has a back-side or non-active surface 108 and an active surface 110, the active surface 110 containing analog or digital circuitry implemented as active devices, passive devices, conductive layers, and dielectric layers formed within or on the die, and electrically interconnected according to the die's electrical design and function. For example, the circuitry may include one or more transistors, diodes, and other circuit elements formed within the active surface 110 to implement analog or digital circuitry, such as digital signal processors (DSPs), application-specific integrated circuits (ASICs), memories, power devices, or other signal processing circuitry. The semiconductor die 104 may also include IPDs for RF signal processing, such as inductors, capacitors, and resistors.

[0010] A conductive layer 112 is formed on the active surface 110 using physical vapor deposition (PVD), chemical vapor deposition (CVD), electroplating, electroless plating, or other suitable metal deposition processes. The conductive layer 112 may be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable conductive materials. The conductive layer 112 functions as contact pads of a circuit on the active surface 110.

[0011] Conductive bump material is deposited on conductive layer 112 using evaporation, electrolytic plating, electroless plating, droplet plating, or screen printing processes. The bump material can be Al, Sn, Ni, Au, Ag, lead (Pb), bismuth (Bi), Cu, solder, combinations thereof, and optionally flux solutions. For example, the bump material can be eutectic Sn / Pb, high-lead solder, or lead-free solder. The bump material is bonded to conductive layer 112 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating it above its melting point to form balls or bumps 114. In one embodiment, bumps 114 are formed on an under-bump metallization (UBM) layer having a wetting layer, a barrier layer, and an adhesion layer. Bumps 114 can also be compression bonded or thermo-pressed bonded to conductive layer 112. Bumps 114 represent a type of interconnect structure that can be formed on conductive layer 112. The interconnect structure can also use bonding wires, conductive paste, column bumps, microbumps, or other electrical interconnects.

[0012] exist Figure 1c In this process, a saw blade or laser cutting tool 118 is used to cut the semiconductor wafer 100 into individual semiconductor dies 104 through the saw groove 106. The individual semiconductor dies 104 can be inspected and electrically tested for use in identifying known good dies (KGD) or known good cells (KGU) after cutting.

[0013] Figures 2a-2i The formation of a rigid-flexible co-packaged optical module with a semiconductor die 104 is shown. Figure 2a A substrate 120 is shown. The substrate 120 is a multilayer interconnect substrate including a conductive layer 122 and an insulating layer 124. The conductive layer 122 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. The conductive layer 122 can be formed using PVD, CVD, electrolytic plating, chemical plating, or other suitable metal deposition processes. The conductive layer 122 provides horizontal electrical interconnects across the substrate 120 and vertical electrical interconnects between the top and bottom surfaces. Depending on the design and function of the formed package or module, portions of the conductive layer 122 can be electrically common or electrically isolated.

[0014] The insulating layer 124 comprises one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, PI, BCB, PBO, and other materials with similar insulating and structural properties. The insulating layer 124 can be formed using PVD, CVD, printing, lamination, spin coating, spraying, sintering, thermal oxidation, or other suitable processes. The insulating layer 124 provides isolation between the conductive layers 122. Any number of conductive layers 122 and insulating layers 124 can be interleaved to form the substrate 120.

[0015] In other embodiments, any other suitable type of packaging substrate or lead frame is used for substrate 120. For example, substrate 120 may be a laminated interposer, PCB, wafer form, strip interposer, lead frame, or another suitable substrate. Substrate 120 may comprise one or more laminates of pre-impregnated polytetrafluoroethylene (prepreg), FR-4, FR-1, CEM-1, or CEM-3 combined with phenolic paper, epoxy resin, resin, woven glass, frosted glass, polyester, and other reinforcing fibers or fabrics.

[0016] Substrate 120 is formed on or attached to flexible cable 130. Flexible cable 130 is a flexible cable having multiple conductive traces extending parallel within an insulating film. Flexible cable 130 can be any type of ribbon cable, flexible flat cable (FFC), or flexible printed circuit (FPC). The insulating film can be polyimide, polyester, or another suitable insulating material, such as the material mentioned above for insulating layer 124. The inner conductor can be copper, steel, aluminum, gold, or another suitable conductive material.

[0017] The flexible cable 130 is flexible, allowing it to bend and electrically connect to a connector that is not fully aligned with the substrate 120. The end 130a of the flexible cable 130 has exposed contacts that the connector electrically connects to when the end of the flexible cable is inserted into the connector. In other embodiments, board-to-board or other types of connectors are mounted on the end 130a for subsequent electrical interconnection. Conductive traces in the flexible cable 130 extend from left to right in the figure to connect the substrate 120 to the end 130a.

[0018] The conductor of the flexible cable 130 can be screen-printed onto the insulating film or patterned using photolithography. The patterned conductor can be laminated between two insulating films, having a thermosetting adhesive coating activated by the lamination process. The flexible cable 130 can be formed as a flexible cable with an internal conductor using any suitable process. The flexible cable 130 can be attached to the substrate 120 using a conductive adhesive. In other embodiments, the substrate 120 is formed directly on the flexible cable 130 by directly constructing the insulating layer 124 and the conductive layer 122 onto the flexible cable using thin-film deposition technology. Even in embodiments where the substrate is formed directly on the flexible cable, the substrate 120 is considered attached to the flexible cable 130. The resulting CPO module is referred to as a rigid-flexible module because the flexible cable 130 remains rigid in the area where it is attached to the substrate 120 and flexible elsewhere.

[0019] exist Figure 2b In the process, a conventional electronic semiconductor die 104a and a photonic semiconductor die 140a are disposed on and mounted onto the flexible cable 130. The semiconductor die 104a is derived from... Figure 1c The semiconductor die 104, or another semiconductor die similarly formed and functioning. The photonic semiconductor die 140a is similar to... Figures 1a-1c The semiconductor die 104 is formed in such a way that, except that an optically sensitive or photonic region 142 is formed on the back surface 108. The photonic region 142 is formed of a material that can be or otherwise configured to convert external optical or light signals received at the photonic region into electrical signals within the photonic semiconductor die 140a, which can then be processed by circuitry on the active surface 110 or the back surface 108.

[0020] In some embodiments, the photonic semiconductor die 140a is a photonic integrated circuit (PIC) containing photonic components that form functional circuitry capable of detecting, generating, transmitting, or processing light. The semiconductor die 140a may be formed of indium phosphide (InP), which allows for the integration of various active and passive optical functions on the same chip. The photonic region 142 is configured to receive optical signals directly from the air or via an attached fiber optic cable into the photonic circuitry of the semiconductor die 140a.

[0021] In some embodiments, the photonic region 142 has a physical structure suitable for receiving optical fiber cables or signals, such as a grating coupler, and optionally has a separate connector mounted to the surface of the photonic semiconductor die 140a. In other embodiments, the semiconductor die 140a is configured to emit light from the photonic region 142. The semiconductor die 140a may have multiple photonic regions 142, for example, one or more for receiving optical signals and one or more for transmitting optical signals.

[0022] Both semiconductor dies 140a and 104a are picked up and placed on the flexible cable 130, with solder bumps 114 oriented toward the flexible cable. Solder bumps 114 are aligned with the exposed contact pads of the flexible cable 130. Solder bumps 114 are reflowed to physically and electrically connect semiconductor dies 140a and 104a to conductive traces embedded in the flexible cable 130. Optionally, underfill material is used under semiconductor dies 104a and 140a to physically support the solder connection. A portion of adhesive 146 is applied to the flexible cable 130 adjacent to the photonic semiconductor die 140a by, for example, inkjet printing. The size and shape of adhesive 146 are configured to correspond to the side surface of the photonic semiconductor die 140a when the flexible cable 130 is folded in a later manufacturing stage.

[0023] exist Figure 2cIn this design, a heat sink 150 is disposed above and placed downwards on the back surfaces 108 of semiconductor dies 104a and 140a. The heat sink 150 is a solid material, such as steel, aluminum, copper, their alloys, or another thermally conductive material. The heat sink 150 can be cut from a single piece of material. A thermal interface material (TIM) 152 is disposed on the surface of the heat sink 150 oriented towards the semiconductor dies 104a and 140a. The TIM 152 can be any suitable type of thermal material, such as thermal paste, thermal adhesive, or thermally conductive pads. During subsequent manufacturing steps, the heat sink 150 can be adhered to the semiconductor dies 104a and 140a using thermal adhesive. The heat sink 150 absorbs heat generated by the semiconductor dies 104a and 140a and presents a smooth surface on the exterior of the package being formed. If desired, a heat sink can be attached to the outer surface of the heat sink 150 to more effectively dissipate heat into the surrounding air. TIM 152 improves heat transfer between the semiconductor die and the heat sink 150.

[0024] exist Figure 2d In this embodiment, heat sink 150 is mounted on the back surface 108 of semiconductor dies 104a and 140a. Photonic region 142 remains exposed to heat sink 150. In some embodiments, heat sink 150 is rectangular and positioned outside the coverage area of ​​photonic region 142. In other embodiments, heat sink 150 may have a recess in a plan view, in which photonic region 142 is located, such that the heat sink extends to the left edge of photonic semiconductor die 140a in other cross-sections. In one embodiment, heat sink 150 has an internal opening to accommodate photonic region 142.

[0025] The flexible cable 130 is folded upwards as indicated by arrow 153, or otherwise deformed, so that the adhesive 146 contacts. Figure 2e The side surface of the photonic semiconductor die 140a is shown. Folding the flexible cable 130 creates a circular or radial bend 155. The radius of the bend 155 can be large enough to allow the flexible cable 130 to be folded without damage. In some embodiments, the internal conductor of the flexible cable 130 does not extend beyond the coverage area of ​​the semiconductor die 140a to the bend 155, allowing the flexible cable to be folded without bending the conductor. In this case, only the laminated insulating film needs to be bent, allowing for a smaller radius of the bend 155. Adhesive 146 holds the flexible cable 130 at a right angle across the bend 155.

[0026] The length of the flexible cable 130 on the left side of the photonic semiconductor die 140a is chosen such that, after folding at corner 155, the end 130b of the flexible cable approximately reaches the height of the top surface of the heat sink 150. In other embodiments, the end 130b of the flexible cable 130 may be cut after folding to be flush with the top surface of the heat sink 150. The area between the end 130b of the flexible cable 130 and the heat sink 150 creates a channel or groove 154 above the photonic region 142. The folded portion of the flexible cable 130 operates as a sidewall of the groove 154. The groove 154 may extend across the entire width of the photonic semiconductor die 140a, entering and exiting... Figure 2e The page. In other embodiments, the heat sink 150 extends in other cross-sections to the vertical portion of the flexible cable 130, defining a groove 154 on three sides, while a fourth side is defined by the flexible cable. In embodiments where the heat sink extends in other cross-sections to the left edge of the photonic semiconductor die 140a, the adhesive 146 may optionally extend upwards further to couple the flexible cable 130 to the heat sink 150.

[0027] exist Figure 2f In this process, a temporary protective layer 156 is formed over the photonic region 142. The protective layer 156 fills the groove 154. The protective layer 156 can be constructed as a liquid deposition, as a pre-formed plug insertion, using thin-film deposition techniques, or using any other suitable process, as shown. The protective layer 156 can be formed from photoresist materials, epoxy resin, or any of the methods and materials mentioned above or below for insulation or sealants. The material of the protective layer is deposited to this height or by back-side grinding, such that the top surface of the protective layer 156 is coplanar with the end 130b of the flexible cable 130 and the top surface of the heat sink 150.

[0028] exist Figure 2g In this process, a sealant or molding compound 170 is deposited on the flexible cable 130, the substrate 120, and the semiconductor dies 104a and 140a. The sealant 170 is deposited using paste printing, compression molding, transfer molding, liquid sealant molding, vacuum lamination, spin coating, or other suitable applicators. The sealant 170 can be a liquid or particulate polymer composite, such as epoxy resin, epoxy acrylate, or another suitable polymer, with or without fillers. The sealant 170 is non-conductive, provides structural support, and environmentally protects the embedded electrical components from external factors and contaminants.

[0029] Sealant 170 is deposited in a mold, wherein the end 130a of the flexible cable 130 extends outside the mold, such that the sealant does not completely cover the flexible cable. Sealant 170 fills the space between the flexible cable 130, the semiconductor die 104a, and the photonic semiconductor die 140a. Figure 2hIn the process, the sealant 170 is back-polished using a grinder 176 to complete the CPO module 172. Figure 2i The CPO module 172 after back-grinding is shown. The CPO module 172 has a common electronic semiconductor die 104a co-packaged with an optical or photonic semiconductor die 140a. The end 130a of a flexible cable 130 extends from the sealant 170 for subsequent electrical interconnection with an external system. The CPO module 172 can be considered a chiplet.

[0030] Figures 3a-3e The process for forming a stackable flexible CPO module 200 for stacking on a rigid-flexible CPO module 172 is shown. The CPO module 200 is formed on a flexible cable 210, as... Figure 3a As shown. Flexible cable 210 is structured and operated similarly to flexible cable 130. In some embodiments, flexible cable 210 is disposed on a rigid carrier for manufacturing CPO module 200. CPO module 200 is formed by disposing semiconductor dies 104b, 104c, and 140b on flexible cable 210, as described above with respect to semiconductor dies 104a and 140a on flexible cable 130. The semiconductor dies are disposed on a first portion 210a of flexible cable 210, while another portion 210b remains loose for later use.

[0031] In addition to semiconductor dies 140b, 104b, and 104c, PCB units or e-bars 220 are disposed on flexible cables 210 for vertical interconnection. PCB units 220 are formed of a substrate insulating material and have conductive vias or posts 222 formed through the insulating material. As described above with respect to solder bumps 114, solder bumps 224 are formed on each side of each conductive via 222. In some embodiments, a UBM is formed between each conductive via 222 and each solder ball 224.

[0032] The substrate insulating material of PCB unit 220 is typically composed of a dielectric material, such as FR-4 (glass-reinforced epoxy laminate), polyimide, or ceramic, selected based on the thermal, mechanical, and electrical requirements of the application. Conductive vias 222 are typically made of copper, but in other embodiments, any of the materials described above for conductive layers can be used. Conductive vias 222 are formed by drilling through the substrate insulating material and then typically filling it with conductive material using any of the methods described above for conductive layers. Additional layers, such as solder mask, screen printing, or conductive layers for signal redistribution or shielding, may be applied to the top and bottom surfaces.

[0033] Similar to semiconductor dies 104 and 140, PCB units 220 are picked up and placed on flexible cable 210. As shown, individual PCB units 220 are disposed between each die. Each PCB unit 220 may extend into the page, its length approximately matching the parallel dimensions of the semiconductor die. In other embodiments, any configuration of the PCB units 220 may be used, such as additional PCB units on the outer edge of the die, or PCB units surrounding each die. In some embodiments, there are no PCB units between some adjacent die pairs.

[0034] As shown in the figure, the photonic semiconductor die 140b may have a photonic region 142' formed at the edge of the photonic semiconductor die. In this case, the CPO module 200 will be suitable for use with an edge fiber coupler. In other embodiments, the photonic semiconductor die 140b uses the same photonic region 142 formed at the edge of the photonic semiconductor die as the photonic semiconductor die 140a above, making a vertical fiber coupler more suitable.

[0035] exist Figure 3b In this configuration, spacers or adhesives 230 are disposed on the photonic semiconductor die 140b. The spacers 230 fill gaps above the photonic semiconductor die 140b that will be present when a portion 210b of the flexible cable 210 is folded onto the photonic semiconductor die. In one embodiment, the top of the spacers 230 is approximately flush with the top of the solder bumps 224. Heat sinks 232 are mounted to semiconductor dies 104b and 104c using thermal paste 234, as described above for heat sinks 150 and TIM 152. Heat sinks 232 facilitate thermal management of semiconductor dies 104b and 104c. TIM 234 is a thermal paste, adhesive, or sheet used to attach heat sinks 232 and effectively transfer heat from the die to the heat sink.

[0036] exist Figure 3c In this process, a protective layer 240 is formed over the photonic region 142' of the photonic semiconductor die 140b. The protective layer 240 is a conformal temporary protective layer, such as a sacrificial mask, photoresist layer, or epoxy resin, which is localized to cover only the photonic region 142'. The protective layer 240 can be formed from any material and is typically formed using any of the methods described above for insulating layers. Alternatively, the protective layer 240 can be printed onto the photonic region 142' or be a pre-formed portion of an adhesive tape disposed over the photonic region. The protective layer 240 protects the photonic region 142' during subsequent processing.

[0037] exist Figure 3dIn this configuration, a portion 210b of the flexible cable 210 is folded over semiconductor dies 104b, 104c, and 140b. The end of the flexible cable in portion 210b, opposite portion 210a, does not reach the photonic region 142', ensuring that the flexible cable 210 does not interfere with the operation of the photonic region. Portion 210b rests against spacer 230, and the flexible cable 210 is optionally bonded to the top of the photonic semiconductor die 140b using an adhesive. Spacer 230 maintains the flexible cable 210 at an appropriate height offset so that solder bumps 224 flow back onto the flexible cable. Bumps 224 are flowed back to physically and electrically couple the top bumps 224 of each PCB unit 220 to portion 210b of the flexible cable 210.

[0038] exist Figure 3e In this design, the CPO module 200 is completed by adding solder bumps 242 to portion 210b of the flexible cable 210. Bumps 242 allow electrical interconnection with semiconductor dies 104b, 104c, and 140b via the flexible cable 210 and PCB unit 220. The PCB unit 220 directly connects to portions 210a and 210b of the flexible cable 210 without requiring a path through the folded side of the flexible cable, thus creating a shorter electrical path to the semiconductor dies compared to if all signals were transmitted solely through the flexible cable 210. Furthermore, more external electrical signals could be provided than could be provided otherwise, instead of each having to be transmitted via separate parallel traces through the flexible cable 210. The CPO module 200 can be considered a chiplet.

[0039] Figures 4a-4c A stacked package with CPO modules 172 and 200 is shown. Figure 4a In this process, the formation of the stack begins on a carrier 244 or other suitable substrate. A releasable adhesive layer 246 is disposed on the carrier 244. A CPO module 172 is disposed on the carrier 244, with a heat sink 150 on the carrier and a substrate 120 oriented upward away from the carrier. A CPO module 200 is picked up and placed on the CPO module 172, with bumps 242 oriented downward toward the substrate 120. The CPO module 200 is disposed on the substrate 120, and bumps 242 are reflowed onto the contact pads of the conductive layer 122 to physically and electrically couple CPO modules 172 and 200 to each other. Semiconductor dies 140a and 104a are electrically coupled to the CPO module 200 via a flexible cable 130, the substrate 120, and bumps 242.

[0040] Figure 4bThe stacked CPO module 250 is shown. The carrier 244 is removed by a suitable mechanism, such as thermal release, UV release, or back-side grinding. The protective layer 156 is removed by chemical etching, mechanical etching, physical stretching, laser ablation, or another suitable means to clear the groove 154 and expose the photonic region 142 of the photonic semiconductor die 140a.

[0041] exist Figure 4c In this embodiment, bump 252 is formed on the flexible cable 210 of the bottom CPO module 200, as described above with respect to bumps 114 and 242. In other embodiments, bump 252 is formed at the same stage as bump 242. Bump 252 serves to mount and electrically connect the stacked CPO modules 250 to the PCB or substrate of a larger electrical device or system to combine the functionality of the stack.

[0042] Exemplary fiber optic cable 254 in Figure 4c As shown in the diagram. Fiber optic cable 254 is typically added after stack 250 is installed into a larger system, but for reference, it is shown where the stack is isolated. Fiber optic cable 254 can be attached to photonic region 142 using adhesive, a coupler pre-installed or formed on the photonic region, or any other suitable means. Fiber optic cable 254 extends from photonic region 142 to another device or coupler remote from stack CPO module 250, to which the stack CPO module can communicate via the fiber optic cable. In some embodiments, fiber optic cable 254 includes a fiber optic array unit (FAU). Fiber optic cable 254a is connected to photonic semiconductor die 140a via a vertical coupler. Fiber optic cable 254b is attached to photonic semiconductor die 140b via an edge coupler.

[0043] Figure 5 An alternative embodiment of the stacked CPO module 260 is shown, wherein the bottom CPO module 200 is relative to... Figures 4a-4c The stacked CPO module 250 is vertically flipped. Solder bump 252 replaces bump 242 for attaching the bottom CPO module 200 to CPO module 172. Bump 242 can still be used to subsequently attach the stack 260 to the substrate of a larger electrical system. In the stack 260, the photonic region 142' of the photonic semiconductor die 140b is oriented downward toward the substrate of the larger system, which may be more convenient for vertical fiber couplers. The longer portion 210a of the flexible cable 210 allows for more I / O due to its larger coverage area size, which may be more desirable for external or internal interconnects depending on the specific application.

[0044] The stacked CPO modules 250 and 260 are formed from two independent CPO modules 172 and 200. CPO module 172 is mounted as a rigid-flexible module on a rigid-flexible substrate. The flexible extension 130a of the rigid-flexible substrate deforms into a sidewall to protect the vertical coupler or only the photonic region 142 during handling. The flexible substrate provided by the flexible cable 210 of CPO module 200 presents as a dual insert with longer and shorter ends, providing flexibility for signal routing. CPO module 200 can be formed with edge or vertical fiber optic connector options. A heat sink is applied to the non-photonic semiconductor die 104 to aid in heat dissipation and improve reliability and lifespan.

[0045] Figure 6a and 6b The above-described semiconductor package (e.g., a stacked CPO module 250) is shown being integrated into a larger electronic device 300. Figure 6a A partial cross-section of a stacked CPO module 250 mounted on a printed circuit board (PCB) or other substrate 302 as part of an electronic device 300 is shown. Bumps 252 are routed back to contact pads on a conductive layer 304 to electrically and mechanically couple the stacked CPO module 250 to the substrate 302. A flexible cable 130 is routed such that its end 130a extends into a connector 306. The connector 306 is soldered to the conductive layer 304 of the PCB 302 and has internal electrical contacts that apply pressure to the exposed contacts of the flexible cable 130 for electrical connection. In some embodiments, the connector 306 is disposed on a separate PCB or another semiconductor package, rather than directly on the same PCB 302 on which the stack 250 is mounted and connected to the bumps 252.

[0046] Semiconductor dies 104a, 104b, 104c, 140a, and 104b are electrically coupled to conductive layer 304 via substrate 120, flexible cable 130, and connector 306 parallel to flexible cable 210 and bump 252. Optical fibers 254a and 254b are attached to photonic region 142 to provide optical functionality to device 300. Electronic device 300 uses photonic semiconductor dies 140a and 140b to transmit or receive optical signals via optical fibers, or to perform any other suitable optical function.

[0047] Figure 6b An electronic device 300 with a chip carrier substrate or PCB 302 is shown, with multiple semiconductor packages disposed on the surface of the PCB 302, including stacked CPO modules 250. Depending on the application, the electronic device 300 may have one type of semiconductor package or multiple types of semiconductor packages.

[0048] Electronic device 300 can be a standalone system that uses a semiconductor package to perform one or more electrical functions. Alternatively, electronic device 300 can be a sub-component of a larger system. For example, electronic device 300 can be a part of a tablet computer, cellular phone, digital camera, communication system, or other electronic device. Alternatively, electronic device 300 can be a graphics card, network interface card, or other signal processing card that can be plugged into a computer. Semiconductor packages can include microprocessors, memory, ASICs, logic circuits, analog circuits, RF circuits, discrete devices, or other semiconductor dies or electrical components. Miniaturization and weight reduction are essential for product market acceptance. The distance between semiconductor devices can be reduced to achieve higher density. PCB 302 can have more irregular shapes to easily fit into more ergonomic and smaller device housings.

[0049] exist Figure 6b In this design, PCB 302 provides a universal substrate for the structural support and electrical interconnection of semiconductor packages mounted on the PCB. Conductive signal traces 304 are formed on or within the surface of PCB 302 using evaporation, electrolytic plating, electroless plating, screen printing, or other suitable metal deposition processes. Signal traces 304 provide electrical communication between each of the semiconductor package, mounted components, and other external system components. Trace 304 also provides power and ground connections for each of the semiconductor packages.

[0050] In some embodiments, the semiconductor device has two packaging levels. The first-level package is a technique for mechanically and electrically attaching a semiconductor die to an intermediate substrate. The second-level package involves mechanically and electrically attaching the intermediate substrate to a PCB. In other embodiments, the semiconductor device may have only a first-level package, where the die is mechanically and electrically disposed directly on the PCB.

[0051] For illustrative purposes, several types of first-level packages are shown on PCB 302, including bonded leaded packages 346 and flip chips 348. Furthermore, several types of second-level packages, including ball grid array (BGA) 350, bump chip carrier (BCC) 352, planar grid array (LGA) 356, multi-chip module (MCM) or SIP module 358, square flat leadless package (QFN) 360, square flat package 362, and embedded wafer-level ball grid array (eWLB) 364, are shown disposed on PCB 302. In one embodiment, eWLB 364 is a fan-out wafer-level package (Fo-WLP) or a fan-in wafer-level package (Fi-WLP).

[0052] Depending on system requirements, any combination of semiconductor packages configured with any combination of first-level and second-level packaging styles, along with other electrical components, can be connected to PCB 302. In some embodiments, electronic device 300 includes a single attached semiconductor package, while other embodiments require multiple interconnected packages. By combining one or more semiconductor packages on a single substrate, manufacturers can incorporate prefabricated components into electronic devices and systems. Because semiconductor packages include complex functionality, electronic devices can be manufactured using less expensive components and streamlined manufacturing processes. The resulting devices are less likely to fail and are less expensive to manufacture, resulting in lower costs for consumers.

[0053] Reference numerals 104, 104a, 104b, and 104c refer to semiconductor dies with purely electronic functions. Reference numerals 140, 140a, and 140b refer to semiconductor dies with photonic functions or capabilities. Although three ordinary semiconductor dies 104 and two photonic semiconductor dies 140 are shown in the illustrated embodiment, any number of dies and combinations thereof can be used, including more than one photonic semiconductor die in a single package or module. Any other desired electrical components, such as additional dies, sub-packages, chiplets, or discrete active or passive devices, may be mounted with the semiconductor dies on flexible cables 130 or 210 as needed. The term semiconductor die can refer to an optical semiconductor die or a general semiconductor die with only electrical functions.

[0054] Although one or more embodiments of the invention have been described in detail, those skilled in the art will appreciate that modifications and adaptations may be made to those embodiments without departing from the scope of the invention as set forth in the appended claims.

Claims

1. A method for manufacturing a semiconductor device, comprising: The first co-packaged optical (CPO) module is formed through the following steps. Provide the first flexible cable, The substrate is attached to the first flexible cable. The first semiconductor die and the first photonic semiconductor die are disposed on the first flexible cable, opposite to the substrate, and The first flexible cable is deformed to attach the first flexible cable to the side surface of the first photonic semiconductor die; The second CPO module is formed through the following steps. Provide a second flexible cable, The second semiconductor die and the second photonic semiconductor die are disposed on the first part of the second flexible cable, and The second portion of the second flexible cable is folded over the second semiconductor die and the second photonic semiconductor die to place the second semiconductor die and the second photonic semiconductor die between the first portion and the second portion of the second flexible cable. and Stack the second CPO module on top of the first CPO module.

2. The method according to claim 1 further includes providing solder bumps between the first CPO module and the second CPO module.

3. The method according to claim 1 further includes disposing a PCB unit between the second semiconductor die and the second photonic semiconductor die.

4. The method according to claim 1, further comprising connecting a first optical fiber cable to the first photonic semiconductor die and connecting a second optical fiber cable to the second photonic semiconductor die.

5. The method according to claim 1 further comprises depositing a sealant on the first flexible cable, the substrate, the first semiconductor die, and the first photonic semiconductor die.

6. The method according to claim 1 further includes providing a heat sink on the first semiconductor die or the second semiconductor die.

7. A method for manufacturing a semiconductor device, comprising: The first co-packaged optical (CPO) module is formed through the following steps. Provide the first flexible cable, The substrate is attached to the first flexible cable. The first photonic semiconductor die is placed on the first flexible cable, opposite to the substrate, and The first flexible cable is deformed to attach the first flexible cable to the side surface of the first photonic semiconductor die; The second CPO module is formed through the following steps. Provide a second flexible cable, The second photonic semiconductor die is placed on the first part of the second flexible cable, and Fold the second part of the second flexible cable over the second photonic semiconductor die; and Stack the second CPO module on top of the first CPO module.

8. The method of claim 7, further comprising providing a solder bump between the first CPO module and the second CPO module on a first side of the second CPO module.

9. The method of claim 8 further includes providing a second solder bump on the second side of the second CPO module opposite to the first side.

10. A semiconductor device, comprising: The first co-packaged optical (CPO) module includes, First flexible cable, The substrate attached to the first flexible cable, and The first photonic semiconductor die is disposed on the first flexible cable and opposite to the substrate. The first flexible cable is deformed so that it attaches to the side surface of the first photonic semiconductor die. and A second CPO module stacked on top of the first CPO module, wherein the second CPO module includes, The second flexible cable, and The second photonic semiconductor die is disposed on the first part of the second flexible cable. The second part of the second flexible cable is folded over the second photonic semiconductor die.

11. The semiconductor device of claim 10, further comprising a solder bump disposed on a first side of the second CPO module between the first CPO module and the second CPO module.

12. The semiconductor device of claim 11, further comprising a second solder bump disposed on a second side of the second CPO module opposite to the first side.

13. The semiconductor device according to claim 10, further comprising a PCB unit disposed on the second flexible cable.

14. The semiconductor device of claim 10, further comprising: A first optical fiber cable coupled to a first photonic semiconductor die; and A second optical fiber cable coupled to a second photonic semiconductor die.

15. The semiconductor device of claim 10, further comprising a sealant deposited on the first flexible cable, the substrate, and the first photonic semiconductor die.

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