Method and apparatus for quasi-cyclic low density parity check coding in mobile communications

Abstract

Various solutions for quasi-cyclic low-density parity-check (QC-LDPC) coding for mobile communication devices are described. A device can determine a parity-check matrix for a QC-LDPC code. The parity-check matrix can be generated by multiple lifts, and the number of lifts can be equal to or greater than three. The device can use the QC-LDPC code to transmit or receive multiple signals based on the parity-check matrix.

Description

[0001] Cross-references

[0002] This invention is part of a non-provisional application claiming priority to U.S. Patent Application No. 63 / 711,724, filed October 25, 2024, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure generally relates to mobile communications, and more specifically, to quasi-cyclic low-density parity-check (QC-LDPC) coding for devices in mobile communications. Background Technology

[0004] Unless otherwise stated herein, the methods described in this section are not prior art to the claims, nor are they admitted as prior art by virtue of their inclusion in this section.

[0005] In New Radio (NR) mobile communication systems, Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) codes have been introduced. Specifically, QC-LDPC coding provides a structured low-density parity-check technique designed to balance error correction performance with implementation efficiency, supporting the demands for higher throughput and parallel processing in evolving communication technologies.

[0006] However, the QC-LDPC design used in NR is typically geared towards a throughput level of around 20 Gbps. This capability may be sufficient for existing deployments, but it is still insufficient for future communication systems, such as those including 6G networks, whose use cases and service demands are expected to require throughput far exceeding 100 Gbps.

[0007] Therefore, how to provide a QC-LDPC coding scheme that can support significantly higher data throughput has become an important issue in next-generation wireless communication networks. Thus, there is an urgent need to provide a QC-LDPC coding scheme that can support significantly higher data throughput. Summary of the Invention

[0008] The following summary is for illustrative purposes only and is not intended to be limiting. That is, the following summary aims to introduce the concepts, key points, benefits, and advantages of the novel and non-obvious techniques described herein. Some embodiments will be further described in the detailed description below. Therefore, the following summary is not intended to identify the essential features of the claimed subject matter, nor to determine the scope of the claimed subject matter.

[0009] One objective of this disclosure is to provide a solution or scheme for the aforementioned problems related to quasi-cyclic low-density parity-check (QC-LDPC) coding in mobile communication devices.

[0010] In one aspect, a method may include having a device determine a parity matrix of a quasi-cyclic low-density parity-check (QC-LDPC) code. The parity matrix may be generated through multiple boosts, with the number of boosts being equal to or greater than three. The method may also include having the device transmit and receive multiple signals using the QC-LDPC code based on the parity matrix.

[0011] In one aspect, an apparatus may include a transceiver that wirelessly communicates with a wireless network during operation. The apparatus may also include a processor communicatively connected to the transceiver. During operation, the processor may perform operations including determining a parity check matrix of a QC-LDPC code. The parity check matrix is ​​generated through multiple boosts, with the number of boosts being equal to or greater than three. The processor may further perform operations including transmitting and receiving multiple signals using the QC-LDPC code via the transceiver based on the parity check matrix.

[0012] It is worth noting that although the content described herein may be set against the backdrop of certain wireless access technologies, networks, and network topologies, such as Long-Term Evolution (LTE), LTE-Advanced, LTE-Advanced Pro, and 5G (5G) networks, th Generation III (5G), New Radio (NR), Internet of Things (IoT), Narrow Band Internet of Things (NB-IoT), Industrial Internet of Things (IIoT), and 6G (6G) th The concepts, schemes, and any variations / derivatives of Generation 6G (or 6G for short) can be implemented, used, or implemented by other types of wireless access technologies, networks, and network topologies. Therefore, the scope of this disclosure is not limited to the examples described herein. Attached Figure Description

[0013] The accompanying drawings are included in this specification to further understand this disclosure and form part of this disclosure. The drawings illustrate embodiments of this disclosure and, in conjunction with the description, explain the principles of this disclosure. It will be understood that the drawings are not necessarily drawn to scale, as some components may be shown out of proportion to their actual dimensions for clarity of the concepts presented in this disclosure.

[0014] Figure 1 This is a schematic diagram illustrating an example scenario of the scheme according to an implementation of the present disclosure.

[0015] Figure 2This is a schematic diagram illustrating an example scenario of the scheme according to an implementation of the present disclosure.

[0016] Figure 3 This is a block diagram of an example communication system according to an implementation of the present disclosure.

[0017] Figure 4 This is a flowchart illustrating an example process based on an implementation of this disclosure. Detailed Implementation

[0018] Detailed embodiments and implementations of the claims of this application are disclosed herein. However, it should be understood that the disclosed embodiments and implementations are for illustrative purposes only, and the claims may be implemented in various forms. This disclosure may take many different forms and should not be construed as limited to the exemplary embodiments and implementations listed herein. Rather, these exemplary embodiments and implementations are provided to make the description of this disclosure exhaustive and complete, and to fully convey the scope of this disclosure to those skilled in the art. In the following description, well-known features and technical details may be omitted to avoid unnecessarily obscuring the proposed embodiments and implementations.

[0019] Overview

[0020] Implementations of this disclosure relate to various techniques, methods, schemes, and / or solutions for quasi-cyclic low-density parity-check (QC-LDPC) coding associated with mobile communication devices. According to this disclosure, several possible solutions can be implemented individually or in combination. That is, although these possible solutions are described separately below, two or more of them can be implemented in different combinations.

[0021] Regarding this disclosure, a device (e.g., a network node or user equipment (UE)) can use QC-LDPC codes to transmit and / or receive signals. Specifically, the device can determine a parity check matrix for the QC-LDPC codes. To support higher data throughput, the parity check matrix can be generated through multiple boosting operations, with the number of boosting operations equal to or greater than three. The device can use QC-LDPC codes to transmit and receive signals based on the parity check matrix.

[0022] Therefore, by employing QC-LDPC codes based on parity check matrices with multiple lifting structures, higher data throughput can be supported in communication systems while maintaining high performance and implementation efficiency.

[0023] Figure 1Example scenario 100 illustrates an implementation of this disclosure. Scenario 100 involves a first device and a second device, both of which can be part of a wireless communication network (e.g., an LTE network, a 5G / NR network, an Internet of Things (IoT) network, or a 6G network). Scenario 100 illustrates a current network framework. The first device can communicate with the second device.

[0024] It should be noted that, for ease of explanation and clarification, in Figure 1 In this embodiment, the first device may include a UE, and the second device may include a network node. However, this description is merely illustrative and is not intended to limit the scope of this disclosure. Those skilled in the art will recognize that in other embodiments, the first device may be implemented by a network node, and / or the second device may be implemented by a UE.

[0025] In some embodiments, the first device may use QC-LDPC codes to transmit and / or receive signals. Specifically, the first device may determine the parity check matrix of the QC-LDPC code. To support higher data throughput, the parity check matrix may be constructed to enhance parallel processing (i.e., encoding / decoding) capabilities. Therefore, the parity check matrix may be generated through multiple boosting operations, with the number of boosting operations equal to or greater than three.

[0026] In some implementations, after determining the parity check matrix, the first device can apply QC-LDPC codes to the information bits to generate codewords based on the parity check matrix. The first device can then map the codewords to modulation symbols, forming multiple signals, and transmit these signals to the second device.

[0027] In some implementations, after determining the parity check matrix, the first device can receive other signals from the second device and decode these signals into codewords using QC-LDPC codes based on the parity check matrix. The first device can then obtain information bits from the codewords.

[0028] In some implementations, the parity check matrix can be predefined. Specifically, the parity check matrix can be predefined by the network system. More specifically, the boost order can be... The parity check matrix can be predefined as follows: matrix H... i-1 According to the enhancement factor Z i Perform boosting to generate matrix H i Where i is chosen from 1 to m, matrix H0 is the basic matrix, and matrix H m This is a parity check matrix. In some cases, all matrices can be binary matrices. Matrix H i-1 Each element with a value of 1 can be replaced with a Z. i ×Z iThe permutation matrix (i.e., a square binary matrix, characterized by exactly one '1' element in each row and exactly one '0' element in each column). Matrix H i-1 Each element with a value of 0 can be replaced with a Z. i ×Z i The zero matrix (i.e., a matrix in which all elements are '0').

[0029] In some implementations, the parity matrix can be determined by the first device. Specifically, when the first device needs to use the parity matrix, it can determine the parity matrix. More specifically, the lifting order can be... The first device can transfer matrix H i-1 According to the enhancement factor Z i Perform boosting to generate matrix H i Where i is chosen from 1 to m, matrix H0 is the basic matrix, and matrix H m This is a parity check matrix. In some cases, all matrices can be binary matrices. Matrix H i-1 Each element with a value of 1 can be replaced with a Z. i ×Z i The permutation matrix. Matrix H i-1 Each element with a value of 0 can be replaced with a Z. i ×Z i The zero matrix.

[0030] In some implementations, the lift factor associated with the parity check matrix can be equal to or greater than 385. Specifically, the parity check matrix lift factor of this disclosure can be greater than 384, while 384 is the maximum lift size used in traditional network systems (such as 5G networks).

[0031] In some cases, the boost factor can be determined based on at least one of the following parameters: (1) code rate, (2) code block size, (3) modulation order, (4) modulation and coding scheme (MCS), (5) number of multiple-input multiple-output (MIMO) layers, and (6) bandwidth. The above parameters can be configured according to different network scenarios.

[0032] In some cases, the enhancement factor can be determined based on the UE's capabilities. For example, when the first device / second device is a UE, the enhancement factor is determined according to the UE's capabilities. As the UE's capabilities improve, the value of the enhancement factor can be configured to increase accordingly.

[0033] Therefore, by repeatedly lifting the parity matrix, more orthogonal rows can be included. This allows the first / second device to process more rows of the parity matrix in parallel, supporting higher data throughput while maintaining performance and efficiency. Furthermore, the flexibility of designing more orthogonal rows and different shift coefficients in the parity matrix during the lifting process reduces the correlation between parity constraints, resulting in higher decoding parallelism and better error correction performance.

[0034] Figure 2 An example scenario 200 is illustrated under the scheme according to an embodiment of this disclosure. For example, the number of boosts is... The parity check matrix is ​​determined as follows: (1) the base matrix H0 is promoted by a first promotion factor Z1 to generate a first matrix H1 (i.e., elements with a value of 1 in H0 are replaced with a Z1 × Z1 permutation matrix, and elements with a value of 0 in H0 are replaced with a Z1 × Z1 zero matrix); (2) matrix H1 is promoted by a second promotion factor Z2 to generate a second matrix H2 (i.e., elements with a value of 1 in H1 are replaced with a Z2 × Z2 permutation matrix, and elements with a value of 0 in H1 are replaced with a Z2 × Z2 zero matrix); and (3) the second matrix H2 is promoted by a third promotion factor Z3 to generate a parity check matrix H3 (i.e., elements with a value of 1 in H2 are replaced with a Z3 × Z3 permutation matrix, and elements with a value of 0 in H2 are replaced with a Z3 × Z3 zero matrix). In this example, the base matrix H0 is a 2 × 3 binary matrix. The first promotion factor Z1 is 2. The second boosting factor Z2 is 2, and the third boosting factor Z3 is equal to or greater than 385.

[0035] Exemplary embodiments

[0036] Figure 3 An example communication system 300 according to an embodiment of this disclosure is illustrated, the system including an example first device 310 and an example second device 320. Each of the first device 310 and the second device 320 may perform multiple functions to implement the schemes, techniques, processes and methods described herein with respect to quasi-cyclic low-density parity-check (QC-LDPC) coding, covering the scenarios / schemes described above and the process 400 described below.

[0037] The first device 310 / second device 320 may be part of an electronic device, which may be a user equipment (UE), such as a portable or mobile device, wearable device, wireless communication device, or computing device. For example, the first device 310 / second device 320 may be implemented in a smartphone, smartwatch, personal digital assistant, digital camera, or computing device such as a tablet, laptop, or netbook. The first device 310 / second device 320 may also be part of a machine-type device, which may be an Internet of Things (IoT), Narrowband Internet of Things (NB-IoT), or Industrial Internet of Things (IIoT) device, such as a non-mobile or fixed device, home appliance, wired communication device, or computing device. For example, the first device 310 / second device 320 may be implemented in a smart thermostat, smart refrigerator, smart door lock, wireless speaker, or home control center.

[0038] The first device 310 / second device 320 can be part of a network device, which can be a network node, such as a satellite, base station, cell, router, or gateway. For example, the first device 310 / second device 320 can be implemented in an eNodeB in an LTE network, a gNB in ​​a 5G / New Radio (NR), Internet of Things (IoT), Narrowband Internet of Things (NB-IoT) or Industrial Internet of Things (IIoT) network, or in a satellite or base station in a 6G network.

[0039] Alternatively, the first device 310 / second device 320 may be implemented as one or more integrated circuit (IC) chips, such as, but not limited to, one or more single-core processors, one or more multi-core processors, one or more reduced-instruction-set computing (RISC) processors, or one or more complex-instruction-set computing (CISC) processors. The first device 310 / second device 320 may include... Figure 3 At least some components are shown, such as processors 312 / 322. The first device 310 / second device 320 may also include one or more other components unrelated to the present disclosure (e.g., internal power supply, display device, and / or user interface device), therefore, such components of the first device 310 / second device 320 are not included in... Figure 3 As shown in the text and not described below, this is for the purpose of simplification and conciseness.

[0040] In one aspect, each of processors 312 and 322 may be implemented as one or more single-core processors, one or more multi-core processors, or one or more Complex Instruction Set Computing (CISC) processors. That is, although the singular term “processor” is used herein to refer to processors 312 and 322, each of processors 312 and 322 may include multiple processors, or in other embodiments, a single processor, according to certain embodiments of this disclosure. In another aspect, each of processors 312 and 322 may be implemented in hardware (and optionally firmware) comprising, for example, but not limited to, one or more transistors, one or more diodes, one or more capacitors, one or more resistors, one or more inductors, one or more memristors, and / or one or more varactor diodes, these electronic components being configured and arranged to achieve a particular purpose of this disclosure. In other words, in at least some embodiments, each of processors 312 and 322 is a dedicated machine specifically designed, arranged, and configured to perform specific tasks in devices (e.g., represented by first device 310 / second device 320) and networks (e.g., represented by first device 310 / second device 320), including QC-LDPC encoding.

[0041] In some embodiments, the first device 310 / second device 320 may further include a transceiver 316 / 326 coupled to the processor 312 / 322, capable of wireless data transmission and reception. In other words, the processor 312 / 322 can transmit and receive data, such as configurations, messages, signals, information, indications, etc., through the transceiver 316 / 326. In some embodiments, the first device 310 / second device 320 may further include a memory 314 / 324 coupled to the processor 312 / 322 and accessible and able to store data by the processor 312 / 322. Therefore, the first device 310 and the second device 320 can wirelessly communicate through the transceiver 316 and transceiver 326, respectively. For ease of understanding, the following description of the operation, function, and capabilities of the first device 310 and the second device 320 is provided in the context of a mobile communication environment, wherein the first device 310 / second device 320 is implemented as a communication device or a user equipment (UE), and the first device 310 / second device 320 is implemented as a network node of a communication network.

[0042] In some embodiments, each of memories 314 and 324 may include a random-access memory (RAM), such as dynamic RAM (DRAM), static RAM (SRAM), thyristor RAM (T-RAM), and / or zero-capacitor RAM (Z-RAM). Alternatively, each of memories 314 and 324 may include a read-only memory (ROM), such as a mask ROM, programmable ROM (PROM), erasable programmable ROM (EPROM), and / or electrically erasable programmable ROM (EEPROM). Alternatively, each of memories 314 and 324 may include a non-volatile RAM (NVRAM), such as flash memory, solid-state memory, ferroelectric RAM (FeRAM), magnetoresistive RAM (MRAM), and / or phase-change memory.

[0043] Exemplary process

[0044] Figure 4 An example flow 400 from an embodiment of this disclosure is illustrated. Flow 400 may be an example implementation of the scenario / scheme described above, whether partially or entirely, and is related to the quasi-cyclic low-density parity-check (QC-LDPC) coding of this disclosure. Flow 400 may represent one aspect of the feature implementation of device 310 / 320. Flow 400 may include one or more operations, actions, or functions, as shown in blocks 410 and 420. Although shown in discrete block form, the individual blocks of flow 400 may be divided into more blocks, merged into fewer blocks, or omitted depending on the desired implementation. Furthermore, each block of flow 400 may be arranged according to... Figure 4 The process can be executed in the order shown, or in a different order. Process 400 can be implemented by device 310 / 320 or any applicable user equipment (UE), network node, or machine type device. For illustrative purposes only and without limitation, process 400 is described below in the context of device 310 / 320. Process 400 may begin at box 410.

[0045] In block 410, process 400 may involve processor 312 / 322 of device 310 / 320 determining the parity check matrix of the QC-LDPC code. The parity check matrix can be generated through multiple lifts, with the number of lifts being equal to or greater than three. Process 400 may continue from block 410 to block 420.

[0046] In block 420, process 400 may involve the processors 312 / 322 of devices 310 / 320 transmitting and receiving multiple signals via transceivers, based on a parity check matrix and using QC-LDPC codes.

[0047] In some embodiments, the number of boosts can be The parity check matrix can be predefined as follows: matrix H... i-1 According to the enhancement factor Z i Perform boosting to generate matrix H i Where i is chosen from 1 to m, matrix H0 is the basic matrix, and matrix H m This is the parity check matrix.

[0048] In some embodiments, matrix H i-1 According to the enhancement factor Z i Perform boosting to generate matrix H i Further steps include: replacing each element with a value of 1 in matrix Hi-1 with a Zi × Zi permutation matrix; and replacing matrix H... i-1 Replace each element with a value of 0 with a Z. i ×Z i The zero matrix.

[0049] In some embodiments, the number of boosts can be Process 400 may further involve the processor 312 / 322 of device 310 / 320 to process matrix H. i-1 According to the enhancement factor Z i Perform boosting to generate matrix H i Where i is chosen from 1 to m, matrix H0 is the basic matrix, and matrix H m This is the parity check matrix.

[0050] In some embodiments, process 400 may further involve the processor 312 / 322 of device 310 / 320 converting matrix H i-1 Replace each element with a value of 1 with a Z. i ×Z i The permutation matrix; and the matrix H i-1 Replace each element with a value of 0 with a Z. i ×Z i The zero matrix.

[0051] In some embodiments, process 400 may further involve the processor 312 / 322 of device 310 / 320 boosting the base matrix by a first boosting factor to generate a first matrix; boosting the first matrix by a second boosting factor to generate a second matrix; and boosting the second matrix by a third boosting factor to generate a parity check matrix.

[0052] In some embodiments, the first boosting factor can be 2, the second boosting factor can be 2, and the third boosting factor can be equal to or greater than 385.

[0053] In some embodiments, the lifting factor associated with the parity check matrix may be equal to or greater than 385.

[0054] In some embodiments, the boost factor may be determined based on at least one of the following: code rate, code block size, modulation order, modulation and coding scheme (MCS), number of multiple-input multiple-output (MIMO) layers, and bandwidth.

[0055] In some embodiments, the enhancement factor can be determined based on UE capabilities.

[0056] Additional notes

[0057] The topics described in this document sometimes show different components contained within or connected to other different components. It should be understood that such architectures are merely examples, and many other architectures can actually be implemented to achieve the same functionality. Conceptually, any arrangement of components to achieve the same functionality is effectively “associated” to achieve the desired function. Therefore, any two components combined in this document to achieve a specific function can be considered “associated with each other” to achieve the desired function, regardless of the architecture or intermediate components. Similarly, any two components so associated can also be considered “operationally connected” or “operationally coupled” to achieve the desired function, and any two components that can be so associated can also be considered “operationally coupled” to achieve the desired function. Specific examples of operational coupling include, but are not limited to, physically matable and / or physically interactive components and / or wirelessly interactive components and / or logically interactive and / or logically interactive components.

[0058] Furthermore, regarding the use of almost all plural and / or singular terms in this document, those skilled in the art can appropriately convert plural to singular and / or singular to plural depending on the context and / or application. For clarity, various singular / plural permutations and combinations may be explicitly listed herein.

[0059] Furthermore, those skilled in the art will understand that terms commonly used in this specification, particularly in claims, such as the body of a claim, are generally considered "open-ended" terms. For example, the word "comprising" should be interpreted as "including but not limited to," the word "having" should be interpreted as "having at least," and the word "including" should be interpreted as "including but not limited to," etc. Those skilled in the art will also further understand that if a specific quantity is introduced in a claim intentionally, that intention will be explicitly stated in the claim; if no such statement is made, then that intention does not exist. For example, for ease of understanding, a claim may include introductory phrases such as "at least one" and "one or more" to introduce the content of the claim. However, the use of such phrases should not be construed as limiting a claim containing that content to containing only one instance of that content by introducing the content of the claim with the indefinite article "a" or "one," even if the same claim contains both "one or more" or "at least one" and the indefinite article "a" or "one," for example, "a" and / or "one" should be interpreted as "at least one" or "one or more"; the same applies to cases where the content of the claim is introduced with a definite article. Furthermore, even if a specific number of introduced elements is explicitly stated in the claims, those skilled in the art will recognize that such a statement should be interpreted as at least the number stated. For example, stating only "two elements" without any other modifiers indicates at least two elements, or two or more elements. Additionally, when using conventions such as "at least one A, B, and C," such structures should generally be interpreted in the way that those skilled in the art understand the convention. For example, "a system having at least one A, B, and C" includes, but is not limited to, systems with only A, only B, only C, A and B, A and C, B and C, and systems where A, B, and C are present simultaneously. Similarly, when using conventions such as "at least one A, B, or C," such structures should generally be interpreted in the way that those skilled in the art understand the convention. For example, "a system having at least one A, B, or C" includes, but is not limited to, systems with only A, only B, only C, A and B, A and C, B and C, and systems where A, B, and C are present simultaneously. Those skilled in the art will further understand that almost all disjunctive terms and / or phrases appearing in the specification, claims, or drawings, when presenting two or more alternative terms, should be understood to include the possibility of including one term, any term, or both terms. For example, the phrase “A or B” should be understood as including the possibility of “A” or “B” or “A and B”.

[0060] As can be seen from the foregoing, various embodiments of this disclosure have been described for illustrative purposes, and various modifications can be made without departing from the scope and spirit of this disclosure. Therefore, the various embodiments disclosed in this specification are not intended to be limiting, and the true scope and spirit are determined by the claims.

Claims

1. A method comprising: The parity check matrix of the quasi-cyclic low-density parity check code is determined by the device's processor, wherein the parity check matrix is ​​generated by multiple boosts, and the number of boosts is equal to or greater than three. as well as The processor uses the quasi-cyclic low-density parity check code to transmit and receive multiple signals based on the parity check matrix.

2. The method of claim 1, wherein the number of times the multiple increases are... And this parity check matrix is ​​predefined in the following way: matrix H i-1 By increasing factor Z i Perform boosting to generate matrix H i Where i is chosen from 1 to m, matrix H0 is the basic matrix, and matrix H m This is the parity check matrix.

3. The method of claim 2, wherein matrix H i-1 By increasing factor Z i Perform boosting to generate matrix H i Further includes: matrix H i-1 Replace each element with a value of 1 with a Z. i ×Z i The permutation matrix; as well as matrix H i-1 Replace each element with a value of 0 with a Z. i ×Z i The zero matrix.

4. The method of claim 1, wherein the number of times the multiple increases are... Furthermore, determining the parity check matrix further includes: The processor will process matrix H i-1 By increasing factor Z i Perform boosting to generate matrix H i Where i is chosen from 1 to m, matrix H0 is the basic matrix, and matrix H m This is the parity check matrix.

5. The method of claim 4, wherein matrix H i-1 Through this enhancement factor Z i Perform boosting to generate matrix H i Further includes: The processor will process matrix H i-1 Replace each element with a value of 1 with a Z. i ×Z i The permutation matrix; as well as The processor will process matrix H i-1 Replace each element with a value of 0 with a Z. i ×Z i The zero matrix.

6. The method of claim 1, wherein determining the parity check matrix further comprises: The base matrix is ​​raised by the first raising factor to generate the first matrix; The first matrix is ​​then improved using a second improvement factor to generate a second matrix; as well as The second matrix is ​​then boosted by a third boosting factor to generate the parity check matrix.

7. The method of claim 6, wherein the first boosting factor is 2, the second boosting factor is 2, and the third boosting factor is equal to or greater than 385.

8. The method of claim 1, wherein the lifting factor associated with the parity check matrix is ​​equal to or greater than 385.

9. The method of claim 8, wherein the boost factor is determined based on at least one of the following: code rate, code block size, modulation order, modulation and coding scheme, number of multiple-input multiple-output layers, and bandwidth.

10. The method of claim 8, wherein the enhancement factor is determined based on the user equipment capabilities.

11. An apparatus comprising: A transceiver that communicates wirelessly with a wireless network during operation; as well as A processor, communicatively coupled to the transceiver, enables the processor to perform the following operations during operation: Determine the parity check matrix of a quasi-cyclic low-density parity check code, wherein the parity check matrix is ​​generated by multiple boosting operations, and the number of boosting operations is equal to or greater than three; and Based on this parity check matrix, the transceiver uses a quasi-cyclic low-density parity check code to send and receive multiple signals.

12. The device of claim 11, wherein the number of times the multiple lifts are... And this parity check matrix is ​​predefined in the following way: matrix H i-1 By increasing factor Z i Perform boosting to generate matrix H i Where i is chosen from 1 to m, matrix H0 is the basic matrix, and matrix H m This is the parity check matrix.

13. The device of claim 12, wherein matrix H i-1 By increasing factor Z i Perform boosting to generate matrix H i Further includes: matrix H i-1 Replace each element with a value of 1 with a Z. i ×Z i The permutation matrix; as well as matrix H i-1 Replace each element with a value of 0 with a Z. i ×Z i The zero matrix.

14. The device of claim 11, wherein the number of times the multiple lifts are... Furthermore, during operation, the processor performs the following operations: matrix H i-1 By increasing factor Z i Perform boosting to generate matrix H i Where i is chosen from 1 to m, matrix H0 is the basic matrix, and matrix H m This is the parity check matrix.

15. The device of claim 14, wherein during operation, the processor further performs the following operations: matrix H i-1 Replace each element with a value of 1 with a Z. i ×Z i The permutation matrix; and matrix H i-1 Replace each element with a value of 0 with a Z. i ×Z i The zero matrix.

16. The device of claim 11, wherein during operation, the processor further performs the following operations: The base matrix is ​​raised by the first raising factor to generate the first matrix; The first matrix is ​​then improved using a second improvement factor to generate a second matrix; as well as The second matrix is ​​then boosted by a third boosting factor to generate the parity check matrix.

17. The device of claim 16, wherein the first boost factor is 2, the second boost factor is 2, and the third boost factor is equal to or greater than 385.

18. The device of claim 11, wherein the lifting factor associated with the parity check matrix is ​​equal to or greater than 385.

19. The device of claim 18, wherein the boost factor is determined based on at least one of the following: code rate, block size, modulation order, modulation and coding scheme, number of multiple-input multiple-output layers, and bandwidth.

20. The device of claim 18, wherein the enhancement factor is determined based on the user equipment capabilities.

Images