Gate trench power semiconductor device with trench shield region and method of forming the same

Abstract

A semiconductor device includes a semiconductor layer structure including a drift region having a first conductivity type and a trench shield region having a second conductivity type, and a gate trench extending in a longitudinal direction in the semiconductor layer structure. The trench shield region extends in the longitudinal direction under the gate trench, and at least a portion of the trench shield region includes a sidewall that angles inward as a distance from the gate trench increases.

Description

[0001] Cross-references to (one or more) related applications

[0002] This application claims priority to U.S. Patent Application Serial No. 18 / 610,394, filed March 20, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This invention relates to power semiconductor devices, and more particularly, to power semiconductor devices having gate trenches and methods of manufacturing such devices. Background Technology

[0004] A metal-oxide-semiconductor field-effect transistor (“MOSFET”) is a well-known semiconductor transistor that can be used as a switch. A MOSFET is a three-terminal device having a gate, drain, and source terminal, as well as a semiconductor body. The semiconductor body is referred to herein as a “semiconductor layer structure” and may comprise one or more semiconductor layers / regions. The source and drain regions are formed within the semiconductor layer structure and are separated by a channel region. The gate electrode (which may serve as a gate terminal or be electrically connected to a gate terminal) is deployed adjacent to the channel region and separated from the channel region by a thin oxide layer. The MOSFET can be turned on or off by setting a bias voltage applied to the gate electrode above or below a threshold value. When the MOSFET is on (i.e., in its “on state”), current flows through the channel region between the source and drain regions. When the bias voltage drops below the threshold level, current stops flowing through the channel region.

[0005] An n-type MOSFET has source and drain regions with n-type (electron) conductivity and a channel region with p-type (hole) conductivity (i.e., an "npn" design). An n-type MOSFET turns on when a gate bias voltage applied to the gate electrode is sufficient to create a conductive n-type inversion layer in the p-type channel region, thereby electrically connecting the n-type source and drain regions and allowing majority carrier conduction between them. A p-type MOSFET has a "pnp" design (i.e., p-type source and drain regions and an n-type channel region). A p-type MOSFET turns on when a gate bias voltage applied to the gate electrode is sufficient to create a conductive p-type inversion layer in the n-type channel region to electrically connect the p-type source and drain regions. In this document, the terms "first conductivity type" and "second conductivity type" are used to indicate n-type or p-type, where the first conductivity type and the second conductivity type are distinct from each other. Therefore, if the first region of the device has a first conductivity type and the second region of the device has a second conductivity type, this means that either the first region has n-type conductivity and the second region has p-type conductivity, or alternatively the first region has p-type conductivity and the second region has n-type conductivity.

[0006] As described above, the gate electrode of a MOSFET is separated from the channel region by a thin oxide layer called the gate oxide layer. In some applications, other non-oxide gate dielectric layers can be used instead of the gate oxide layer. It should be understood that the techniques described herein according to embodiments of the invention are equally applicable to devices having a gate dielectric layer formed of a material other than oxide.

[0007] Because the gate electrode of a MOSFET is insulated from the channel region through a gate oxide layer, the gate current required to maintain the MOSFET in its on-state or to switch it between its off-state and on-state is extremely small. The gate current remains small during switching because the gate forms a capacitor with the channel region. Therefore, only a small charge and discharge current is required during switching, allowing for less complex gate drive circuitry and faster switching speeds. A MOSFET can be a standalone device or combined with other circuitry. For example, an insulated-gate bipolar transistor (“IGBT”) is a semiconductor device that combines a MOSFET and a bipolar junction transistor (“BJT”), integrating the high-impedance gate electrode of the MOSFET with the small on-state conduction losses that can be provided by the BJT. An IGBT can be implemented, for example, as a Darlington pair, comprising a high-voltage n-channel MOSFET at the input and a BJT at the output. The base current of the BJT is supplied through the channel of the MOSFET, allowing for simplified external drive circuitry (since the drive circuitry only charges and discharges the gate electrode of the MOSFET).

[0008] In some applications, MOSFETs may need to carry large currents and / or be able to block high voltages. These types of MOSFETs are often referred to as “power” MOSFETs. Power MOSFETs are typically fabricated from wide-bandgap semiconductor materials (in this document, the term “wide-bandgap semiconductor” encompasses any semiconductor with a bandgap of at least 1.4 eV). Power semiconductor devices are typically formed in silicon carbide (“SiC”), which possesses many advantageous properties, including, for example, high electric field breakdown strength, high thermal conductivity, high electron mobility, high melting point, and high saturated electron drift velocity.

[0009] Power semiconductor devices, such as power MOSFETs, can have either a lateral or vertical structure. In a device with a lateral structure, the terminals of the device (e.g., for a power MOSFET, the drain, gate, and source terminals) are located on the same main surface (i.e., the top or bottom surface) of the semiconductor layer structure. In contrast, in a device with a vertical structure, at least one terminal is disposed on each main surface of the semiconductor layer structure (e.g., in a vertical MOSFET, the source and gate may be located on the upper surface of the semiconductor layer structure, while the drain may be located on the lower surface). The semiconductor layer structure may or may not include a lower substrate, such as a growth substrate.

[0010] The semiconductor layer structure of a power semiconductor device typically includes an "active region" in which one or more functional semiconductor devices are formed. The active region acts as a main junction, blocking voltage during reverse-biased (off-state) operation and providing current flow during forward-biased (on-state) operation. Power semiconductor devices may also have edge termination structures, such as guard rings or junction termination extensions, in the terminal regions adjacent to (and typically surrounding) the active region of the semiconductor layer structure. These edge termination structures, among other functions, can reduce electric field congestion effects that may occur at the outer edges of the power semiconductor device. Typically, multiple power semiconductor devices are formed on / on a common wafer, and each power semiconductor device will have its own edge termination structure. After the wafer is fully processed, the resulting structure can be diced to separate the individual edge-terminated power semiconductor devices. Each power semiconductor device may have a unit cell structure, where the active region of each power semiconductor device includes multiple individually "unit cell" devices connected in parallel, which together function as a single power semiconductor device.

[0011] Vertical power semiconductor devices, including MOSFETs, can have a planar gate electrode design, where the gate electrode of the transistor is formed on top of the semiconductor layer structure, or alternatively, can have a gate electrode in a gate trench within the semiconductor layer structure; this is commonly referred to as a gate trench MOSFET. In the case of a planar gate electrode design, the channel region of each unit transistor is horizontally deployed below the gate electrode. In contrast, in a gate trench MOSFET design, the channel is typically vertically deployed adjacent to the sidewalls of the gate electrode. Gate trench MOSFETs can provide enhanced performance but generally require more complex manufacturing processes.

[0012] One failure mechanism of power MOSFETs is so-called gate oxide layer "breakdown." During normal device operation, the gate oxide layer is subjected to a high electric field. The stress caused by these electric fields on the gate oxide layer creates defects in the oxide material, and these defects accumulate over time. When the defect concentration reaches a critical value, so-called "percolation paths" may form in the gate oxide layer, electrically connecting the gate electrode to the source or drain region, resulting in a short circuit that can damage the device. The "lifetime" of the gate oxide layer (i.e., the time the device can operate before breakdown occurs) depends, among other factors, on the magnitude of the electric field subjected to the gate oxide layer and the length of time the electric field is applied. Figure 1 This is a schematic graph illustrating the relationship between the operating time until breakdown occurs (“gate oxide lifetime”) and the level of electric field applied to the gate oxide layer. This graph assumes that the same electric field is applied continuously (which may not be the case in reality). Figure 1 As shown, in some cases, when gate oxide lifetimes are plotted on a logarithmic scale, the relationship may be approximately linear. From Figure 1 The key takeaway is that the gate oxide lifetime decreases exponentially with increasing electric field level. While gate oxide lifetime can be increased by increasing its thickness, various MOSFET performance parameters are often dependent on gate oxide thickness; therefore, increasing gate oxide thickness is generally not an acceptable way to increase gate oxide lifetime. Summary of the Invention

[0013] According to some embodiments of the present invention, a semiconductor device is provided, the semiconductor device comprising: a semiconductor layer structure including a drift region having a first conductivity type and a trench shielding region having a second conductivity type; and a gate trench extending in a longitudinal direction in the semiconductor layer structure. The trench shielding region extends in a longitudinal direction below the gate trench, and at least a portion of the trench shielding region includes sidewalls that angle inward with increasing distance from the gate trench.

[0014] In some embodiments, the portion of the trench shielding region includes at least the lower half of the trench shielding region.

[0015] In some embodiments, the sidewalls of the portion of the trench shielding region angle inward as the distance from the gate trench increases in a direction perpendicular to the lower surface of the semiconductor layer structure.

[0016] In some embodiments, the maximum width of the portion of the trench shielding region is less than or equal to the maximum width of the gate trench.

[0017] In some embodiments, the semiconductor layer structure further includes a first support shield and a second support shield, the first support shield and the second support shield having a second conductivity type and extending in the longitudinal direction on a first side and a second side of the gate trench, respectively.

[0018] In some embodiments, a portion of the drift region is located between the first support shield and the trench shield, and has a width that is substantially constant or increases with increasing depth in the semiconductor layer structure.

[0019] In some embodiments, the width of the drift region increases with increasing depth in the semiconductor layer structure.

[0020] In some embodiments, the first support shield and the second support shield have corresponding widths that are substantially constant or decrease with increasing depth in the semiconductor layer structure.

[0021] In some embodiments, the first support shield and the second support shield have corresponding widths, which increase with increasing depth in the semiconductor layer structure.

[0022] In some embodiments, the upper portion of the trench shielding region is located between the gate trench and the lower portion of the trench shielding region, and has a higher second conductivity type doping concentration than the lower portion of the trench shielding region.

[0023] In some embodiments, the semiconductor device further includes a gate oxide layer and a gate electrode located in a gate trench. The semiconductor layer structure also includes a well region having a second conductivity type located on a drift region and a source region having a first conductivity type located on the well region.

[0024] In some embodiments, the drift region comprises silicon carbide.

[0025] According to a further embodiment of the present invention, a semiconductor device is provided, comprising: a semiconductor layer structure including a drift region having a first conductivity type and a trench shielding region having a second conductivity type; and a gate trench extending in a longitudinal direction within the semiconductor layer structure. The trench shielding regions extend in a longitudinal direction below the gate trench, and the trench shielding regions include end walls that are opposite to each other along the longitudinal direction and inclined relative to the lower surface of the semiconductor layer structure.

[0026] In some embodiments, the end walls of the trench shielding region extend substantially parallel to each other.

[0027] In some embodiments, the endwall of the trench shielding region is adjacent to the non-active region of the semiconductor device.

[0028] In some embodiments, one of the endwalls of the trench shielding region extends longitudinally beyond the endwall of the gate trench.

[0029] In some embodiments, one of the endwalls of the trench shielding region includes a lower portion that does not vertically overlap with the gate trench.

[0030] According to an additional embodiment of the present invention, a semiconductor device is provided, the semiconductor device comprising: a semiconductor layer structure including a drift region having a first conductivity type and a trench shielding region having a second conductivity type; and a gate trench extending in a longitudinal direction in the semiconductor layer structure. The trench shielding region extends in a longitudinal direction below the gate trench, the trench shielding region including an endwall extending in the longitudinal direction beyond the endwall of the gate trench.

[0031] In some embodiments, the end wall of the trench shielding region is one of a pair of end walls of the trench shielding region, which are opposite each other along the longitudinal direction and inclined relative to the lower surface of the semiconductor layer structure.

[0032] In some embodiments, the endwall of the trench shielding region includes a lower portion that does not vertically overlap with the gate trench.

[0033] In some embodiments, the endwall of the trench shielding region is adjacent to the non-active region of the semiconductor device.

[0034] In some embodiments, the endwalls of the trench shielding region are inclined relative to the lower surface of the semiconductor layer structure.

[0035] According to a further embodiment of the present invention, a semiconductor device is provided, the semiconductor device comprising: a semiconductor layer structure including a drift region having a first conductivity type and a trench shielding region having a second conductivity type; and a gate trench extending in a longitudinal direction in the semiconductor layer structure. The trench shielding region extends in a longitudinal direction below the gate trench, and the average width of the upper half of the trench shielding region is greater than the average width of the lower half of the trench shielding region.

[0036] In some embodiments, the upper portion of the trench shielding region is located between the gate trench and the lower portion of the trench shielding region, and has a higher second conductivity type doping concentration than the lower portion of the trench shielding region.

[0037] In some embodiments, the semiconductor layer structure further includes a first support shield and a second support shield, the first support shield and the second support shield having a second conductivity type and extending in the longitudinal direction on a first side and a second side of the gate trench, respectively.

[0038] In some embodiments, at least a portion of the trench shielding region includes sidewalls that angle inwards with increasing distance from the gate trench.

[0039] According to yet another embodiment of the present invention, a semiconductor device is provided, comprising: a semiconductor layer structure including a drift region having a first conductivity type and a trench shielding region having a second conductivity type; and a gate trench extending in a longitudinal direction within the semiconductor layer structure. The trench shielding region extends in a longitudinal direction below the gate trench and includes an endwall extending along the crystal axis of the semiconductor layer structure.

[0040] In some embodiments, the crystal axis is one of the following crystal axes: <11-23>, <-1-123>, <1-213>, <-12-13>, <2-1-13>, or <-2113>.

[0041] In some embodiments, the crystal axis is <0001> Crystal axis.

[0042] In some embodiments, the trench shielding region extends into the drift region, and the drift region comprises silicon carbide.

[0043] According to another embodiment of the present invention, a semiconductor device is provided, comprising: a semiconductor layer structure including a drift region having a first conductivity type and a trench shielding region having a second conductivity type; and a gate trench extending longitudinally in the semiconductor layer structure over the trench shielding region. The trench shielding region extends below the gate trench into the drift region to provide a superjunction structure in the drift region.

[0044] In some embodiments, at least a portion of the trench shielding region includes sidewalls that angle inwards with increasing distance from the gate trench.

[0045] In some embodiments, at least a portion of the trench shielding region includes sidewalls that extend substantially perpendicular to the lower surface of the semiconductor layer structure as the distance from the gate trench increases.

[0046] In some embodiments, the upper portion of the trench shielding region is located between the gate trench and the lower portion of the trench shielding region, and has a higher second conductivity type doping concentration than the lower portion of the trench shielding region.

[0047] In some embodiments, the trench shielding region extends from the bottom surface of the gate trench to a depth of at least 4 micrometers in the drift region.

[0048] According to yet another embodiment of the present invention, a semiconductor device is provided, the semiconductor device comprising: a semiconductor layer structure including a drift region having a first conductivity type and a trench shielding region having a second conductivity type; and a gate trench extending in a longitudinal direction in the semiconductor layer structure. The trench shielding region extends in a longitudinal direction below the gate trench, and at least a portion of the trench shielding region includes sidewalls extending substantially perpendicular to the lower surface of the semiconductor layer structure as the distance from the gate trench increases.

[0049] In some embodiments, the trench shielding region further includes end walls that are opposite each other in the longitudinal direction and inclined relative to the lower surface of the semiconductor layer structure.

[0050] In some embodiments, the upper portion of the trench shielding region is located between the gate trench and the lower portion of the trench shielding region, and has a higher second conductivity type doping concentration than the lower portion of the trench shielding region.

[0051] According to other embodiments of the present invention, methods for manufacturing semiconductor devices are provided. These methods include: providing a semiconductor layer structure including a drift region having a first conductivity type; forming a gate trench extending in a longitudinal direction in the semiconductor layer structure; and forming a trench shielding region by implanting a dopant of a second conductivity type into the semiconductor layer structure using a channel ion implantation process. The trench shielding region extends in the longitudinal direction below the gate trench.

[0052] In some embodiments, the channel ion implantation process is performed along the crystal axis of the semiconductor layer structure.

[0053] In some embodiments, the drift region comprises silicon carbide, and the crystal axis is <0001> One of the crystal axes: <11-23>, <-1-123>, <1-213>, <-12-13>, <2-1-13>, <-2113>, or <11-20>.

[0054] In some embodiments, the trench shielding region is formed after the gate trench.

[0055] In some embodiments, the trench shielding region is formed by implanting a second conductivity type dopant into the gate trench.

[0056] In some embodiments, the trench shielding region is formed before the gate trench.

[0057] In some embodiments, the method further includes forming a well region on the drift region by implanting a second conductivity type dopant into the semiconductor layer structure using a channel ion implantation process.

[0058] In some embodiments, the well region and the trench shielding region are formed simultaneously using the same channel ion implantation process.

[0059] In some embodiments, the method further includes implanting a second conductivity type dopant into the upper part of the trench shielding region using a random ion implantation process.

[0060] In some embodiments, the upper part of the trench shielding region has a higher second conductivity type doping concentration than the lower part of the trench shielding region.

[0061] In some embodiments, the method further includes: forming a first support shield and a second support shield by implanting a second conductivity type dopant into a semiconductor layer structure using a channel ion implantation process, wherein the first support shield and the second support shield extend in the longitudinal direction on a first side and a second side of the gate trench, respectively.

[0062] In some embodiments, the method further includes: forming a first support shield and a second support shield by implanting a second conductivity type dopant into the semiconductor layer structure using a random ion implantation process, wherein the first support shield and the second support shield extend in the longitudinal direction on a first side and a second side of the gate trench, respectively.

[0063] According to a further embodiment of the present invention, a method for manufacturing a semiconductor device is provided. These methods include: providing a semiconductor layer structure including a drift region having a first conductivity type; forming a gate trench extending in a longitudinal direction in the semiconductor layer structure; and simultaneously forming a well region and a trench shielding region by implanting a dopant of a second conductivity type into the semiconductor layer structure using a channel ion implantation process. The well region is located on the drift region, and the trench shielding region extends in a longitudinal direction below the gate trench.

[0064] According to a further embodiment of the present invention, a method for manufacturing a semiconductor device is provided. These methods include: providing a semiconductor layer structure including a drift region having a first conductivity type; forming a gate trench extending in a longitudinal direction in the semiconductor layer structure; and forming a trench shielding region by implanting a dopant of a second conductivity type into the semiconductor layer structure using both a channel ion implantation process and a random ion implantation process. The trench shielding region extends in the longitudinal direction below the gate trench.

[0065] In some embodiments, after forming the trench shielding region using both channel ion implantation and random ion implantation processes, the upper part of the trench shielding region has a higher second conductivity type doping concentration than the lower part of the trench shielding region.

[0066] According to further embodiments of the present invention, a method of manufacturing a semiconductor device is provided. These methods include: providing a semiconductor layer structure including a drift region having a first conductivity type; forming a gate trench extending in a longitudinal direction in the semiconductor layer structure; and forming a trench shielding region by implanting a dopant of a second conductivity type into the gate trench, such that the trench shielding region is aligned with the gate trench in the longitudinal direction. The trench shielding region extends below the gate trench into the drift region to provide a superjunction structure in the drift region.

[0067] In some embodiments, forming the trench shielding region includes performing a trench ion implantation process.

[0068] In some embodiments, forming a trench shielding region includes performing both a channel ion implantation process and a random ion implantation process. Attached Figure Description

[0069] Figure 1 This is a semi-logarithmic graph illustrating the relationship between the lifetime of the gate oxide layer and the applied electric field strength.

[0070] Figure 2 This is a schematic cross-sectional view of a unit cell of a gate trench silicon carbide power MOSFET with a trench shielding region.

[0071] Figure 3A This is a schematic top view of a gate trench silicon carbide power MOSFET according to some embodiments of the present invention.

[0072] Figure 3B yes Figure 3A A schematic top view of a gate trench silicon carbide power MOSFET after removing various upper metal and dielectric layers.

[0073] Figure 3C It is along Figure 3A The line AA is intercepted Figures 3A-3B A schematic cross-sectional view of a gate trench silicon carbide power MOSFET.

[0074] Figure 3D It is along Figure 3A Midline BB cut Figures 3A-3C A schematic cross-sectional view of a gate trench silicon carbide power MOSFET.

[0075] Figures 4-6 , Figures 7A-7B , Figures 8A-8B , Figures 9A-9B , Figures 10A-10B , Figures 11A-11B and Figures 12A-12B This is according to some embodiments of the present invention. Figures 3A-3DA schematic cross-sectional view of a modified version of the gate trench silicon carbide power MOSFET.

[0076] Figures 13A-13F This is a schematic cross-sectional view illustrating a method for manufacturing a gate trench silicon carbide power MOSFET according to some embodiments of the present invention.

[0077] Figures 14A-14C This is a schematic cross-sectional view illustrating a method for manufacturing a gate trench silicon carbide power MOSFET according to some embodiments of the present invention.

[0078] Figures 15A-15B This is a schematic cross-sectional view illustrating a method for manufacturing a gate trench silicon carbide power MOSFET according to some embodiments of the present invention.

[0079] Figures 16A-16E This is a schematic cross-sectional view illustrating a method for manufacturing a gate trench silicon carbide power MOSFET according to some embodiments of the present invention. Detailed Implementation

[0080] Vertical silicon carbide-based power semiconductor devices with gate trenches (such as vertical power MOSFETs and IGBTs) are attractive for many applications due to their inherently lower specific on-resistance, a characteristic that leads to more efficient power switching operation. In gate trench vertical power devices, the channel is formed on the sidewalls of the gate trench, hence the vertical channel. The carrier mobility in these vertically oriented sidewall channels can be approximately 2–4 times higher than the corresponding carrier mobility in the horizontal channels of planar gate (i.e., non-gate trench) vertical power devices. This results in increased current density during on-state operation, allowing for higher switching speeds. The gate trench design also reduces the overall pitch of the device, which improves device integration. Lower conduction losses (due to reduced on-resistance) and improved switching speeds make gate trench power devices particularly suitable for high-frequency power applications with low to medium voltage blocking requirements (e.g., 600–1200 volts). These devices can reduce the requirements for associated passive components and require relatively simple cooling solutions. Since MOSFETs are the most widely used silicon carbide-based gate trench power semiconductor devices, the following discussion focuses on MOSFET embodiments. However, it should be understood that each of the described embodiments can alternatively be implemented using a non-oxide gate dielectric layer (e.g., nitride, high dielectric constant material, etc.), and the same techniques can be used to form other gate trench power semiconductor devices, such as IGBTs, gate-controlled thyristors, etc.

[0081] As discussed above, gate trench power MOSFETs are susceptible to oxide reliability issues due to the high electric fields present in the gate oxide layer at the bottom and sidewalls of the gate trench. These high electric fields degrade the gate oxide layer over time and can eventually lead to device failure. When a gate trench MOSFET operates in reverse blocking mode (i.e., when the MOSFET is in its off state), the source terminal is typically grounded, the gate terminal is typically grounded or negatively biased, and the drain terminal is typically at a high positive voltage. During this type of reverse blocking operation, the high electric field extends upwards from the drain terminal (located on the lower surface of the semiconductor layer structure) toward the upper surface of the semiconductor layer structure. Therefore, the bottom of the gate dielectric layer experiences the highest electric field level during reverse blocking operation. Due to electric field congestion, the electric field level in the lower "corner" of the gate oxide layer at the bottom edge of the gate trench (i.e., the portion of the gate oxide layer covering the sidewalls of the gate trench that converges into the bottom of the gate trench) can be particularly high. Furthermore, due to the difference in dielectric constant between silicon carbide and silicon oxide, the electric field in the silicon oxide gate oxide layer can be approximately 2.6 times higher than the electric field in the adjacent silicon carbide semiconductor layer structure. When the electric field reaches a critical level, silicon oxide breaks down. To avoid this breakdown, power MOSFETs can operate with a lower drain voltage during reverse blocking operation to ensure that the electric field does not reach a level that would cause breakdown. In other words, the rated voltage of a power MOSFET can be set to ensure that premature gate oxide layer breakdown does not occur.

[0082] Recently, gate trench power MOSFETs including so-called "trench shielding regions" (also known as "trench shielding portions" or "bottom shielding portions") have been proposed. The trench shielding regions are disposed below the gate trench of the gate trench power MOSFET to reduce the electric field level in the gate oxide layer during reverse blocking operation. These trench shielding regions can be formed by doping portions of the semiconductor layer structure below the gate trench with dopants having the same conductivity type as the dopants contained in the channel region of the device. For example, the trench shielding regions can be formed via one or more ion implantation processes, wherein p-type dopant ions (for n-type MOSFETs) are implanted into the semiconductor layer structure below the gate trench. The trench shielding regions can extend down from the bottom of the gate trench by 0.5 to 1.0 micrometers or more into the semiconductor layer structure of the device, and are moderately to heavily doped regions. The trench shielding regions can be electrically connected to the source terminals of the MOSFET via p-type trench shielding connection patterns. These trench shielding connection patterns can be located in the active region of the device and / or externally.

[0083] Figure 2 This is a schematic cross-sectional view of a portion of a silicon carbide power MOSFET 1, including the trench shielding region 52. Figure 2The cross-section shows a complete unit cell of MOSFET 1 and portions of two adjacent unit cells. (See diagram for reference.) Figure 2 As shown, MOSFET 1 includes a silicon carbide semiconductor substrate 10. A silicon carbide drift region 20 is disposed on the upper surface of the substrate 10. A silicon carbide JFET region 22 is formed in the upper portion of the drift region 20. For illustrative purposes, in Figure 2 JFET region 22 is shown on drift region 20. However, it should be understood that JFET region 22 can be considered as being on or within the upper portion of drift region 20, and thus can be considered as part of drift region 20. In some embodiments, JFET region 22 may be more heavily doped than the remainder of drift region 20. In some other embodiments, JFET region 22 may have the same doping concentration as the remainder of drift region 20. Silicon carbide well region 30 is disposed on the upper surface of JFET region 22. Silicon carbide source region 40 is formed on the upper portion of well region 30. Channel regions of MOSFET 1 may be formed in a portion of each well region 30 adjacent to the gate trench 80. The channel regions may provide a channel or conductive path 78 (indicated by dashed arrows) allowing current to flow from source region 40 to drift region 20 during on-state operation. Substrate 10, drift region 20, JFET region 22, well region 30, and source region 40 are part of the semiconductor layer structure 60 of MOSFET 1. Substrate 10, drift region 20, JFET region 22, and source region 40 have a first conductivity type, while well region 30 has a second conductivity type. For example, when MOSFET 1 is an n-type MOSFET, substrate 10, drift region 20, JFET region 22, and source region 40 have n-type conductivity, while well region 30 has p-type conductivity. As another example, when MOSFET 1 is a p-type MOSFET, substrate 10, drift region 20, JFET region 22, and source region 40 have p-type conductivity, while well region 30 has n-type conductivity. Hereinafter, embodiments of the invention will be discussed with reference to n-type MOSFETs. However, it should be understood that embodiments of the invention are not limited thereto.

[0084] The semiconductor layer structure 60 also includes a p-type support shield 50 extending downward from the upper part (e.g., the upper surface) of the semiconductor layer structure 60. The p-type support shield 50 may be a moderately or heavily doped silicon carbide region and has the same conductivity type as the well region 30.

[0085] Multiple gate trenches 80 are formed in the upper portion of the semiconductor layer structure 60. The gate trenches 80 can extend longitudinally in a first direction X (also referred to herein as the longitudinal direction). The formation of the gate trenches 80 can convert the well layer and source layer into multiple well regions 30 and multiple source regions 40, respectively. A gate oxide layer 82 is conformally formed in each gate trench 80, and a gate electrode 84 is formed on the gate oxide layer 82 in the gate trench 80. An intermetallic dielectric layer 88 covers the gate electrode 84. A source metallization layer 90 is formed on the intermetallic dielectric layer 88 and on the upper portion of the n-type source region 40 and the p-type support shield 50. A drain contact 6 is formed on the lower surface of the substrate 10.

[0086] The semiconductor layer structure 60 also includes a p-type trench shielding region 52 formed beneath the respective gate trench 80. The p-type trench shielding region 52 extends in a first direction X over the entire or substantially the entire length of the gate trench 80 beneath the respective gate trench 80 (i.e., in...). Figure 2 (Entering page direction). The p-type trench shielding region 52 can be a moderately or heavily doped silicon carbide region and has the same conductivity type as the well region 30. The p-type support shielding portion 50 and the p-type trench shielding region 52 are used to reduce the electric field level formed in the gate oxide layer 82 during the reverse blocking operation of the MOSFET 1.

[0087] The p-type support shield 50 may extend downward through a portion or all of the JFET region 22. Similarly, the gate trench 80 and the p-type trench shield 52 below it may also extend downward through a portion or all of the JFET region 22. As a result, the JFET region 22 may horizontally overlap with the p-type support shield 50 and with one or both of the gate trench 80 and the p-type trench shield 52. As used herein, two elements of a semiconductor device are considered to "horizontally overlap" if an axis parallel to the main surface of the semiconductor layer structure intersects both elements. The main surface of the semiconductor layer structure may also be referred to herein as the lower surface and upper surface of the semiconductor layer structure.

[0088] like Figure 2As shown, the width of the JFET region 22 between the p-type trench shield region 52 and the adjacent p-type support shield 50 can be referred to as the JFET gap 24. The JFET gap 24 can be obtained in a second direction Y intersecting the first direction X. As the p-type trench shield region 52 and the adjacent p-type support shield 50 extend in the depth direction (e.g., the third direction Z) in the semiconductor layer structure 60, the width between them affects the conduction path 78 of the MOSFET 1. Since the conduction path 78 (i.e., source-to-drain current) flows through these JFET gaps 24 during on-state operation, the width of each JFET gap 24 directly affects the on-resistance of the MOSFET 1. Furthermore, the minimum width between the p-type trench shield region 52 and the adjacent p-type support shield 50 also directly affects the on-resistance of the MOSFET 1. Although embodiments of the present invention may not necessarily illustrate the JFET gap as corresponding to the minimum width between the p-type trench shield region and the adjacent p-type support shield, it should be understood that the minimum width is also a parameter affecting the on-resistance of the MOSFET. The first direction X and the second direction Y can be parallel to the main surface of the semiconductor layer structure of the semiconductor device. For example, the second direction Y can be perpendicular to the first direction X. The third direction Z intersects the first direction X and the second direction Y, and can be perpendicular to the main surface of the semiconductor layer structure of the semiconductor device.

[0089] While providing enhanced protection for the gate oxide layer 82 by including a trench shielding region 52 in the gate trench power MOSFET 1, the trench shielding region 52 may increase the on-resistance of the MOSFET 1, thereby increasing power consumption. Specifically, when the trench shielding region 52 is formed using a standard (random) ion implantation process, the width of the trench shielding region 52 tends to increase with increasing depth in the semiconductor layer structure 60 because the deeper the implantation, the greater the chance that the implanted dopant ions will collide with atoms in the crystal lattice and be laterally redirected. This phenomenon is sometimes referred to as "blooming." Figure 2 As shown, the diffusion expansion phenomenon can cause the trench shielding region 52 to have sidewalls that angle outwards with increasing depth in the semiconductor layer structure 60. The lateral expansion of the trench shielding region 52 reduces the width of the JFET gap 24, forcing current in the conduction path 78 to flow through the narrowed region, which increases the on-resistance of the MOSFET 1. Therefore, the distance between each trench shielding region 52 (or gate trench 80) and its adjacent support shield 50 can be set to satisfy a desired on-resistance value. However, this may require increasing the spacing between the trench shielding region 52 and the support shield 50 to obtain a sufficiently large JFET gap 24, which adversely increases the cell pitch of the power MOSFET 1.

[0090] Specifically, the cell pitch of a MOSFET refers to the center-to-center distance between adjacent unit cells. When adding a trench shielding region to a gate trench power MOSFET, it may be necessary to increase the spacing between adjacent gate trenches 80 to allow space for the trench shielding region 52 and to obtain a sufficiently large JFET gap 24, thereby increasing the cell pitch and reducing the integration density of MOSFET 1. Therefore, while providing the trench shielding region 52 in the gate trench power MOSFET 1 can provide enhanced protection for the gate oxide layer 82, there is a trade-off between the cell pitch and on-resistance of MOSFET 1.

[0091] According to embodiments of the present invention, gate trench silicon carbide power MOSFETs (and other power semiconductor devices) with improved trench shielding region designs are provided. For example, in some embodiments, trench shielding regions can be formed using channel ion implantation techniques to allow for reduced cell pitch and / or on-resistance of the MOSFET. Channel ion implantation can exhibit significantly less diffusion expansion compared to random (standard) ion implantation not performed along channels in the semiconductor lattice. Therefore, power MOSFETs according to embodiments of the present invention can exhibit reduced manufacturing costs and / or improved performance.

[0092] In some embodiments of the invention, gate trench silicon carbide-based power MOSFETs (and other gate trench power semiconductor devices) are provided, comprising trench shielding regions having substantially vertical sidewalls or sidewalls angled inwards with increasing depth. Therefore, the JFET gap in these devices can remain substantially constant or actually increase with increasing depth. As a result, the unit cells of the power MOSFETs according to embodiments of the invention can be packaged more tightly together while providing the same or even improved on-resistance performance.

[0093] According to a further embodiment of the invention, a gate trench silicon carbide-based power MOSFET (and other gate trench power semiconductor devices) is provided, comprising a trench shielding region extending into the drift region to provide a superjunction structure therein. The so-called superjunction drift region can increase the blocking voltage of the power MOSFET while reducing its effect on the on-resistance. Furthermore, the trench shielding region can be formed using the processes discussed above, such that the trench shielding region has substantially vertical sidewalls or sidewalls angled inwards with increasing depth.

[0094] Now refer to Figures 3A-16EEmbodiments of the invention will be described in more detail below. It should be understood that features of the different embodiments disclosed herein can be combined in any way to provide numerous additional embodiments. Therefore, it should be understood that various features of the invention are described below with reference to specific examples, but these features can be added to other embodiments and / or used to replace example features of other embodiments to provide numerous additional embodiments. Therefore, the invention should be understood to encompass these different combinations. Furthermore, while the example embodiments focus on MOSFET implementations, it should be understood that the same techniques can be used for other gate trench power semiconductor devices, such as insulated-gate bipolar transistors (IGBTs), gate-controlled thyristors, etc.

[0095] Figure 3A This is a schematic top view of a gate trench silicon carbide power MOSFET 100 according to some embodiments of the present invention. Figure 3B This is a schematic plan view of a power MOSFET 100 with its various top-side metal and dielectric layers omitted to show the gate electrode and gate bus. Figure 3C and Figure 3D They are along Figure 3A A schematic cross-sectional view of the gate trench silicon carbide power MOSFET 100, taken from lines AA and BB. It should be understood that... Figures 3A-3D The thicknesses of various layers and regions are not necessarily drawn to scale. The same applies to other figures included in this application.

[0096] The power MOSFET 100 includes a semiconductor layer structure 160 comprising one or more semiconductor substrates and / or layers (see...). Figure 3C and Figure 3D At least one of the semiconductor layers in the semiconductor layer structure 160 may be a silicon carbide layer. Various metal and / or dielectric layers are formed on both sides of the semiconductor layer structure 160 and embedded in the semiconductor layer structure 160.

[0097] like Figure 3A As shown, the top-side metal layer includes a gate bonding pad 102 and one or more source bonding pads 104-1, 104-2 formed on the upper side of the semiconductor layer structure 160. The metal drain pad 106 (in...) Figure 3A(Seen in dashed box) is disposed on the bottom side of semiconductor layer structure 160. Gate bonding pad 102, source bonding pads 104-1, 104-2, and drain pad 106 form the respective gate terminal, source terminal, and drain terminal of power MOSFET 100. Gate bonding pad 102 and source bonding pads 104-1, 104-2 can each be formed of metal (such as aluminum), and bonding wires 103 can be easily attached to these bonding pads by conventional techniques (such as hot pressing or soldering). Drain pad 106 can also be a metal pad. A protective layer 109 (such as a polyimide layer) can cover the entire upper surface of power MOSFET 100 except for gate bonding pads 102 and source bonding pads 104-1, 104-2.

[0098] Still referencing Figure 3A The power MOSFET 100 includes a source metallization layer 190 that electrically connects certain regions of the semiconductor layer structure 160 to source bonding pads 104-1, 104-2. Figure 3A (Indicated by dashed boxes). Source bonding pads 104-1 and 104-2 may be portions of the source metallization layer 190 exposed through openings in the guard layer 109, or may be separate metal layers. The source metallization layer 190 may typically cover or correspond to the “active region” 107 of the power MOSFET 100, where the unit transistor is located. The non-active region 108 of the power MOSFET 100 surrounds the active region 107. The non-active region 108 may include: a termination region extending around the MOSFET 100, which includes a guard ring, junction termination element, or other termination structure; a gate pad region located below the gate bonding pad 102; and a gate bus region (discussed below).

[0099] Figure 3A The diagram shows a bonding line 103, which can be used to connect the gate bonding pad 102 and the source bonding pads 104-1, 104-2 to external circuitry, etc. The drain pad 106 on the bottom side of the power MOSFET 100 can be connected to external circuitry, for example, via a base (not shown) below.

[0100] Figure 3B This is another planar view of the power MOSFET 100, in which the gate bonding pad 102 and source bonding pads 104-1, 104-2, the protective layer 109, the source metallization layer 190, and the intermetallic dielectric layer 188 have been removed (see [reference]). Figure 3C and Figure 3D ) and various other metal and dielectric layers to show the gate electrode 184 formed in the gate trench 180 in the semiconductor layer structure 160. Patterned field oxide layer 172 (see Figure 3DA semiconductor layer structure 160 is formed in the non-active region 108 of the power MOSFET 100. The field oxide layer 172 can be a relatively thick oxide layer (e.g., ten to twenty times thicker than the gate oxide layer discussed below). A polysilicon layer 101 can be formed on the field oxide layer 172 and can be formed in the region formed by the gate bonding pad 102, such that the gate bonding pad 102 vertically overlaps the field oxide layer 172 and the polysilicon layer 101. As used herein, two elements of a semiconductor device are considered to be “vertically overlapping” if an axis perpendicular to the main surface of the semiconductor layer structure of the semiconductor device intersects both elements.

[0101] One or more gate buses 186 are provided extending around the periphery of the active region 107. A field oxide layer 172 typically extends beneath each gate bus 186 and an underlying gate bonding pad 102. The gate buses 186 are typically electrically connected to the gate bonding pad 102 via gate resistors (not shown). A plurality of gate trenches 180 are formed throughout the active region 107. Gate electrodes 184 are formed in each gate trench 180. In the MOSFET 100, the gate electrode 184 extends longitudinally across the semiconductor layer structure 160 in a first direction X. In other cases, the gate electrode 184 may extend longitudinally across the semiconductor layer structure 160 in a second direction Y. Although not shown, gate electrodes 184 extending in both directions X and Y may be provided to form a mesh-like gate electrode structure. The gate electrodes 184 may be connected to the gate bonding pad 102 via gate buses 186. The gate electrodes 184 may include, for example, a doped polysilicon pattern. The gate bus 186 may include a polysilicon and / or metal structure in the example embodiment and is typically in the non-active region 108 of the power MOSFET 100.

[0102] Figure 3C It is along Figure 3A The schematic cross-sectional view taken from line AA illustrates approximately one and a half unit cells of the power MOSFET 100. (See diagram below.) Figure 3C As shown, the power MOSFET 100 includes an n-type silicon carbide semiconductor substrate 110. The substrate 110 may include, for example, a single-crystal 4H (or 6H) silicon carbide semiconductor substrate heavily doped with n-type impurities. The impurities may include, for example, nitrogen or phosphorus. In an example embodiment, the n-type substrate 110 may have, for example, a 1x10... 18 Up to 1x10 21 atoms / cm 3The term "doping concentration" for semiconductor materials refers to the number of dopant atoms present per cubic centimeter of semiconductor material that give the semiconductor a specific conductivity type (i.e., n-type or p-type), as measured using standard measurement techniques such as secondary ion mass spectrometry ("SIMS"). The doping concentration of a layer or region can be relatively constant or can vary (e.g., gradient with depth), and the term refers to the peak doping concentration of the layer or region. For n-type semiconductor materials, the term "doping concentration" refers to the concentration of n-type dopant, while for p-type semiconductor materials, the term "doping concentration" refers to the concentration of p-type dopant.

[0103] In some embodiments, substrate 110 may be relatively thick (e.g., 20-100 micrometers or more). It should be noted that although substrate 110 is depicted as a relatively thin layer, this is done to allow for scale-up. Figure 3C The thickness of other layers or regions in the figure should be noted, and it should be understood that the substrate 110 is typically much thicker than shown. Similarly, the thicknesses of various other layers or regions of the power MOSFET 100 may not be shown to scale to allow for magnification of other parts of the device in the figure.

[0104] Lightly doped n-type silicon carbide drift regions 120 (also referred to herein as drift layer 120) are disposed on the upper surface of substrate 110. Typically, drift regions 120 are formed via an epitaxial growth process and are doped during growth. The n-type drift regions 120 may have, for example, a size of 5 x 10⁻⁶. 15 Up to 5x10 17 atoms / cm 3 The doping concentration is specified. The drift region 120 can be a thick region with a vertical height of, for example, 3-50 micrometers above the substrate 110, and can be doped during growth. The upper portion of the drift region 120 may include an n-type JFET region 122. In some embodiments, the n-type JFET region 122 may be more heavily doped than the rest of the n-type drift region 120. In some other embodiments, the n-type JFET region 122 may have the same doping concentration as the rest of the n-type drift region 120. The JFET region 122 may have, for example, a doping concentration of 5 x 10⁻⁶. 16 Up to 1x10 18 atoms / cm 3 The concentration of the n-type dopant. For illustrative purposes, the JFET region 122 is shown on the drift region 120. However, it should be understood that the JFET region 122 can be considered to be on or in the upper part of the drift region 120, and therefore can be considered to be part of the drift region 120.

[0105] The drift region 120 and the substrate 110 together serve as the common drain region of the power MOSFET 100. The drain pad 106 is formed on the substrate 110 opposite to the drift region 120.

[0106] Still referencing Figure 3C A moderately doped p-type silicon carbide well region 130 (also referred to herein as well layer 130 or p-well 130) is formed on top of the n-type drift region 120 (i.e., on the n-type JFET region 122). The silicon carbide well region 130 can be formed by epitaxial growth or by implanting p-type dopant ions into the top of the n-type drift region 120 (i.e., into the n-type JFET region 122) to convert the top of the n-type drift region 120 into the p-type well region 130. In an example embodiment, the well region 130 may have, for example, a doped area of ​​5 x 10⁻⁶. 16 Up to 1x10 18 atoms / cm 3 The concentration of p-type dopant between.

[0107] A heavily doped n-type silicon carbide source region 140 (also referred to herein as source layer 140) is formed on the p-type silicon carbide well region 130. The n-type silicon carbide source region 140 can be formed by ion implantation. The n-type source region 140 can have, for example, [missing information - likely referring to a specific configuration or structure]. 1x10 19 Up to 5x10 21 atoms / cm 3 The doping concentration between them.

[0108] like Figure 3C As further shown, a p-type silicon carbide support shield 150 is provided, which extends downward from the upper part (e.g., the upper surface) of the semiconductor layer structure 160 into the drift region 120. The p-type support shield 150 can be a moderately or heavily doped silicon carbide region. For example, each p-type support shield 150 can have approximately 5 x 10⁻⁶ Ω·cm². 16 Up to 1x10 22 atoms / cm 3 The doping concentration is between [values]. In other embodiments, each p-type support shield 150 may have a doping concentration of approximately 1 x 10 [values]. 18 Up to 1x10 20 Between, in approximately 1x10 19 Up to 1x10 20 Between, in approximately 1x10 17 Up to 1x10 19 Between, in approximately 1x10 17 Up to 1x10 20 Between, or at approximately 1x10 18 Up to 1x10 21 atoms / cm 3The doping concentration varies with depth. The p-type support shield 150 can have a doping concentration that varies with depth. In an example embodiment, each p-type support shield 150 can extend from the upper surface of the semiconductor layer structure 160 to a depth between 0.1 micrometers and 4.0 micrometers. In other embodiments, the depth of each p-type support shield 150 can be between 1.0 and 3.0 micrometers, 1.0 and 2.5 micrometers, 1.5 and 3.0 micrometers, 1.5 and 2.5 micrometers, or 0.5 and 2.5 micrometers. Any of the above-described dopant concentration ranges of the p-type support shield 150 can be matched with any of the depths listed above for the p-type support shield 150. The p-type support shield 150 can be used to reduce the electric field level formed in the gate oxide layer 182 during reverse blocking operation, as will be discussed in more detail below.

[0109] A gate trench 180 is formed in the upper part of the semiconductor layer structure 160. For example... Figure 3C As shown, a p-type silicon carbide trench shielding region 152 is formed beneath the respective gate trench 180 and extends beneath the respective gate trench 180 for the entire or substantially the entire length of the gate trench 180 (e.g., in the first direction X). The p-type trench shielding region 152 may be a moderately or heavily doped silicon carbide region. For example, each p-type trench shielding region 152 may have a length of approximately 1 x 10⁻⁶. 16 Up to 1x10 22 atoms / cm 3 The doping concentration is between [a certain value]. In other embodiments, each p-type trench shielding region 152 may have a doping concentration of approximately 1 x 10 [units]. 18 Up to 1x10 20 Between, in approximately 1x10 19 Up to 1x10 20 Between, in approximately 1x10 17 Up to 1x10 19 Between, in approximately 1x10 17 Up to 1x10 20 Between, or at approximately 1x10 18 Up to 1x10 21 atoms / cm 3The doping concentration varies between these values. In an example embodiment, each p-type trench shielding region 152 may extend from the bottom surface of each gate trench 180 to a depth between 0.5 and 3.0 micrometers in the semiconductor layer structure 160. In other embodiments, the depth of each p-type trench shielding region 152 may be between 1.0 and 3.0 micrometers, 1.0 and 2.5 micrometers, 1.5 and 3.0 micrometers, 1.5 and 2.5 micrometers, or 0.5 and 2.5 micrometers. Any of the dopant concentrations described above can be matched to any of the depths listed above for the p-type trench shielding region 152. The p-type trench shielding region 152 is used to reduce the electric field level formed in the gate oxide layer 182 during reverse blocking operation, as will be discussed in more detail below. The p-type trench shielding region 152 may be doped to have a higher p-type dopant concentration, a lower p-type dopant concentration, or approximately the same p-type dopant concentration than the p-type support shield 150.

[0110] Although Figure 3C Not shown, but an electrical connection may be provided in and / or externally to the active region 107 to electrically connect the p-type trench shielding region 152 to the p-type well region 130. U.S. Patent Nos. 9,887,287 and 11,610,991 each illustrate designs for metal or p-type silicon carbide trench shielding connection patterns that can be used to electrically connect the p-type trench shielding region to the p-type well region. Any p-type silicon carbide trench shielding connection pattern disclosed in these patents (each incorporated herein by reference) may be used to electrically connect the p-type trench shielding region 152 to the p-type well region 130. Additionally or alternatively, the p-type trench shielding region 152 may be directly connected to the source metallization layer 190 via a p-type silicon carbide trench shielding connection pattern, such as one formed in the gate trench 180, as shown in U.S. Patent Publication No. 2022 / 0130998, the entire contents of which are also incorporated herein by reference.

[0111] The n-type silicon carbide substrate 110, the n-type silicon carbide drift region 120, the n-type silicon carbide JFET region 122, the p-type silicon carbide well region 130, the n-type silicon carbide source region 140, the p-type silicon carbide support shield 150, and the p-type silicon carbide trench shield 152 together provide the semiconductor layer structure 160 of the power MOSFET 100.

[0112] As described above, a plurality of gate trenches 180 are formed in the upper portion of the semiconductor layer structure 160. Although Figure 3C Only a complete gate trench 180 and a portion of the second gate trench 180 are shown in the cross-section, but from Figure 3BIt is understood that the MOSFET 100 may include a plurality of gate trenches 180. Each gate trench 180 may extend along a longitudinal axis through the semiconductor layer structure 160 (e.g., in the first direction X), and the gate trenches 180 may be as follows: Figure 3B They extend parallel to each other as best shown. It should be understood that the longitudinal axis of the gate trench 180 is in... Figure 3C The gate trench 180 extends into the page within the cross-section. It can be formed via an etching process.

[0113] Each gate trench 180 has a gate oxide layer 182 disposed therein to cover the sidewalls and bottom surface of the gate trench 180. In some embodiments, each gate oxide layer 182 may extend to the upper surface of the semiconductor layer structure 160. Each gate oxide layer 182 may include, for example, a silicon oxide (SiO2) pattern, but is not limited thereto. The gate oxide layer 182 may be Figure 3C They may be connected or not connected to each other outside the view. The gate oxide layer 182 may be formed substantially conformally within the corresponding gate trench 180.

[0114] In each gate trench 180, a gate electrode 184 is formed on a gate oxide layer 182. The gate electrode 184 may comprise a conductive material, such as a silicide (e.g., NiSi, TiSi, WSi, CoSi), doped polysilicon (poly-Si), and / or a stable conductor. Other suitable materials for the gate electrode 184 include various metals (e.g., Ti, Ta, or W) or metal nitrides (e.g., TiN, TaN, or WN). The gate oxide layer 182 insulates the gate electrode 184 from the semiconductor layer structure 160, thereby preventing short circuits between the gate electrode 184 and the semiconductor layer structure 160. Each gate electrode 184 may be connected to one of the gate buses 186 (see [link to relevant documentation]). Figure 3B ).exist Figure 3C In this embodiment, the gate electrode 184 is recessed such that the upper surface of each gate electrode 184 is lower than the upper surface of the semiconductor layer structure 160. It should be understood that in other embodiments, the gate electrode 184 may extend above and onto the upper surface of the semiconductor layer structure 160, and the gate oxide layer 182 insulates the gate electrode 184 from the upper surface of the semiconductor layer structure 160.

[0115] An intermetallic dielectric layer 188 is formed covering each gate electrode 184. The intermetallic dielectric layer 188 insulates the source metallization layer 190 from the gate electrode 184. The source metallization layer 190 is formed on the upper surface of the semiconductor layer structure 160 and on the intermetallic dielectric layer 188. Hereinafter, the source metallization layer 190 may also be referred to as a "source contact". The source metallization layer 190 may include a single metal layer or multiple metal layers. Typically, multiple metal layers are provided because the source metallization layer 190 may include a single or multiple adhesion layers contacting the semiconductor layer structure 160, one or more barrier layers, and a body metal layer (e.g., an aluminum layer).

[0116] In an exemplary embodiment of the invention, the p-type trench shielding region 152 can be formed using channel ion implantation. When using standard ion implantation techniques (also referred to herein as random ion implantation or non-channel ion implantation), dopant ions are implanted at high energy onto the upper surface of the semiconductor layer structure. As the dopant ions enter the semiconductor material, they collide with atoms in the crystal lattice, causing the dopant ions to lose energy and potentially redirecting them in different directions. Most typically, the dopant ions are implanted at an angle of 90° relative to the upper surface of the semiconductor layer structure (i.e., vertically). As the dopant ions collide with atoms in the crystal lattice, they are redirected, causing them to move laterally and vertically through the lattice. This lateral movement results in lateral expansion of the implanted region (the “diffusion expansion” phenomenon discussed above), and the amount of lateral expansion tends to increase with increasing depth in the semiconductor layer structure. This can be achieved through… Figure 2 As seen in the cross-section, the sidewalls of the trench shielding region 52 angle outwards with increasing depth within the semiconductor layer structure 60. (See above reference.) Figure 2 As discussed, this phenomenon reduces the JFET gap 24, which may increase the on-resistance of MOSFET 1.

[0117] In comparison, such as Figure 3C As shown, each trench shielding region 152 included in the MOSFET 100 has sidewalls that angle inwards with increasing depth in the semiconductor layer structure 160. Therefore, the cross-sectional area of ​​each trench shielding region 152 (cut along a horizontal section of the trench shielding region 152) decreases as the trench shielding region 152 extends further into the semiconductor layer structure 160 (from its upper surface). As a result, the JFET gap 124 does not narrow with increasing depth in the semiconductor layer structure 160, but remains substantially constant or actually widens. This can be used to reduce the on-resistance of the power MOSFET 100. As will be discussed in more detail below, the trench shielding regions 152 can be formed using a channel ion implantation process to provide... Figure 3C The trench shielding area 152 is shown in the figure.

[0118] The power MOSFET 100 can be connected to the gate pad 102 (see...) Figure 3A To enable the gate, a gate bias voltage higher than a threshold level is applied. The gate bias voltage is transmitted via gate bus 186 (see [link]). Figure 3B The current is transferred to the gate electrode 184 and forms a conductive n-type inversion layer in a portion of the p-type well region 130 adjacent to the gate trench 180. These portions of the p-type well region 130 are referred to herein as channel regions because the channel or conductive path 178 of the MOSFET 100 (shown by the dashed arrow) provides a path for current to flow from the source region 140 to the drift region 120 during on-state operation. The channel regions are vertically oriented (i.e., extending in the third direction Z), and the current in the conductive path 178 flows downward from the source region 140, through the channel region included in each well region 130, to the JFET region 122, the drift region 120, the substrate 110, and the drain contact 106.

[0119] As discussed above, a common failure mechanism in power semiconductor devices such as power MOSFETs is device failure due to gate oxide layer breakdown. Since the lifetime of the gate oxide layer (i.e., the time before breakdown) depends on the electric field strength in the gate oxide layer during device operation, one way to reduce device failure is to design the MOSFET to reduce the peak electric field value in the gate oxide layer during reverse blocking operation.

[0120] During reverse blocking operation, the electric field extends upward from the bottom of the MOSFET 100. Therefore, a strong electric field may extend upward toward the lower portion of the gate oxide layer 182. The p-type support shield 150 and the p-type trench shield region 152 act as shielding elements to reduce the electric field value. The support shield 150 helps reduce the electric field extending upward on both sides of each trench shield region 152, while the trench shield region 152 helps reduce the electric field level directly below the gate trench 180, where the gate oxide layer 182 may be most susceptible to breakdown.

[0121] The JFET gap can be set by the on-resistance requirements of the power MOSFET. This parameter directly affects the integration density of the MOSFET, because the wider the JFET gap required to meet the on-resistance requirements, the larger the size of each unit cell of the MOSFET. Figure 3C As shown, because the sidewalls of each trench shielding region 152 angle inward with increasing distance from the gate trench 180 in the third direction Z, the JFET gap 124 is larger than that described above. Figure 2The described JFET gap 24 is wider. This widening of the JFET gap 124 occurs without increasing the distance between the trench shielding region 152 (or gate trench 180) and its adjacent support shield 150. Therefore, the JFET gap 124 can be wider than required to meet the on-resistance requirements of the power MOSFET 100. This allows for higher integration in the MOSFET 100 without increasing its on-resistance, thereby reducing manufacturing costs and the size of the MOSFET 100.

[0122] Still referencing Figure 3C It can be seen that the trench shielding region 152 extends below the gate trench 180, and the trench shielding region 152 has sidewalls that angle inward with increasing depth in the semiconductor layer structure 160. In other words, the sidewalls of the trench shielding region 152 angle inward with increasing distance from the gate trench 180. As a result, the width of the trench shielding region 152 in the second direction Y decreases with increasing distance from the gate trench 180. The trench shielding region 152 can be in the first direction X (i.e., in...) Figure 3C (In the direction of entering the page) Extends longitudinally below the gate trench 180. It should be understood that, as used herein, the reference to the “depth” of a structure or element within the semiconductor layer structure 160 refers to the distance of that structure or element from the upper surface of the semiconductor layer structure 160 in the third direction Z, wherein the upper surface of the semiconductor layer structure 160 is the surface opposite to the substrate 110 and is also the surface in which the gate trench 180 is formed.

[0123] like Figure 3C As shown, the sidewalls of the trench shielding region 152 are angled inward in a direction perpendicular to the lower surface of the semiconductor layer structure 160 (i.e., the third direction Z) as the distance from the gate trench 180 increases. The sidewalls of the trench shielding region 152 can be angled in the first direction X (i.e., in the direction Z). Figure 3C The trench shielding region 152 extends longitudinally in the direction of the page entry and is opposite to each other in the second direction Y. The average width of the upper half of the trench shielding region 152 in the second direction Y can be greater than the average width of the lower half of the trench shielding region 152 in the second direction Y. The upper half of the trench shielding region 152 is located between the gate trench 180 and the lower half of the trench shielding region 152. The maximum width of the trench shielding region 152 in the second direction Y can be less than or equal to the maximum width of the gate trench 180 in the second direction Y.

[0124] As discussed above, the semiconductor layer structure 160 includes, among other components, a p-type support shield 150. The support shield 150 can be located on opposite sides of each gate trench 180 in a first direction X (i.e., in...). Figure 3C Extend vertically upwards (from the page orientation). For example... Figure 3CAs shown, two of the p-type support shields 150 may extend on a first side and a second side of one of the gate trenches 180, respectively. The first and second sides of the gate trenches 180 are opposite to each other in the second direction Y. A portion of the n-type drift region 120 may be located between one of the p-type support shields 150 and one of the p-type trench shield regions 152. In some embodiments, the width of this portion of the drift region 120 in the second direction Y may increase with increasing depth in the semiconductor layer structure 160 because the sidewalls of the trench shield region 152 are angled inward. In some other embodiments, depending on the shape of the support shield 150, the width of this portion of the drift region 120 in the second direction Y may be substantially constant with increasing depth in the semiconductor layer structure 160.

[0125] like Figure 3C As shown, the support shield 150 has a width in the second direction Y that increases with increasing depth in the semiconductor layer structure 160. As will be discussed in more detail below, in some embodiments, the support shield 150 can be formed by a random ion implantation process, which may result in the support shield 150 having… Figure 3C The shape shown.

[0126] As discussed above, MOSFET 100 includes a gate oxide layer 182 and a gate electrode 184 located in a gate trench 180. Semiconductor layer structure 160 includes a p-type well region 130 located on an n-type drift region 120 and an n-type source region 140 located on the p-type well region 130. Semiconductor layer structure 160 may also include an n-type JFET region 122, which may include at least a portion of the upper part of the drift region 120. In some embodiments, JFET region 122 may have a higher first conductivity type (n) doping concentration than drift region 120. In some other embodiments, JFET region 122 may have the same first conductivity type (n) doping concentration as drift region 120. Well region 130 may be located on the upper surface of JFET region 122. Figure 3C As shown, the portion of JFET region 122 located between one of the trench shielding regions 152 and one of the support shielding portions 150 may have a width in the second direction Y that increases with the distance from the well region 130 because the sidewalls of the trench shielding region 152 are angled inward. The trench shielding region 152 may extend into both the JFET region 122 and the drift region 120. Each trench shielding region 152 may include an upper portion horizontally overlapping the JFET region 122 and a lower portion horizontally overlapping the drift region 120. The width of the upper portion of each trench shielding region 152 in the second direction Y may be greater than the width of the lower portion of each trench shielding region 152 in the second direction Y.

[0127] refer to Figure 3D It can be seen that the trench shielding region 152 has end walls that are inclined relative to the lower surface of the semiconductor layer structure 160. In other words, the end walls of the trench shielding region 152 are neither parallel to nor perpendicular to the lower surface of the semiconductor layer structure 160. It should be understood that... Figure 3D The cross-section is taken along the longitudinal axis of the gate trench 180, the gate electrode 184, and the trench shielding region 152. It should also be understood that... Figure 3D The cross-section does not show all of these longitudinal axes; rather, the central portion (composed of...) is omitted for ease of explanation. Figure 3D (Represented by the vertical wavy line in the diagram). The end walls of the trench shielding region 152 are opposite to each other in the first direction X and may be adjacent to the non-active region 108 of the power MOSFET 100. Figure 3C The sidewalls of the trench shielding region 152 shown are different, such as... Figure 3D As shown, the end walls of the trench shielding region 152 can extend substantially parallel to each other. That is, the end walls of the trench shielding region 152 can be skewed in the same direction as the distance from the bottom of the gate trench 180 increases. The end walls of the trench shielding region 152 can be skewed in a second direction Y (i.e., in...). Figure 3D Extend vertically upwards (from the direction of the page entry).

[0128] The active region 108 of the power MOSFET 100 may include a gate bus 186, a field oxide layer 172, and a heavily doped silicon carbide p-type region 170. The p-type region 170 may be formed, for example, by ion implantation, on top of the n-type drift region 120. The p-type region 170 may be formed below the gate bus 186 and the field oxide layer 172. The p-type region 170 forms part of the semiconductor layer structure 160.

[0129] At the end of the gate trench 180, a gate electrode extension 185 may protrude from the gate trench 180 and extend laterally across the semiconductor layer structure 160. A gate oxide layer 182 and / or a field oxide layer 172 may separate each gate electrode extension 185 from the semiconductor layer structure 160. A gate bus 186 may be formed on the gate electrode extension 185 to provide an electrical connection between the gate electrode 184 and the gate bus 186.

[0130] like Figure 3D As shown, the trench shielding region 152 and the gate trench 180 extend within the active region 107 of the power MOSFET 100, and the end walls of the trench shielding region 152 and the gate trench 180 may abut the p-type region 170. One of the end walls of the trench shielding region 152 (e.g., Figure 3DThe right-side endwall may extend in the first direction X beyond one of the endwalls of the gate trench 180 toward the non-active region 108. One of the endwalls of the trench shielding region 152 may include a portion 152_EW (shown by a dashed circle) that does not vertically overlap with the gate trench 180. For example, the portion 152_EW may be the lower part of one of the endwalls of the trench shielding region 152. The endwalls of the trench shielding region 152 may extend along the crystal axis of the semiconductor layer structure 160. In some embodiments, the crystal axis is one of <11-23>, <-1-123>, <1-213>, <-12-13>, <2-1-13>, or <-2113> crystal axes. In some other embodiments, the crystal axis is <0001> Crystal axis. As will be discussed in more detail below, a trench shielding region 152 can be provided by using a trench ion implantation process to form a crystal axis. Figure 3D The trench shielding area 152 is shown in the figure.

[0131] Figures 4-12B These are respectively, according to some embodiments of the present invention, as Figures 3A-3D A schematic cross-sectional view of the modified version of the gate trench silicon carbide power MOSFET 100, namely the gate trench silicon carbide power MOSFET 100A-100O. Figures 4-12B The cross section is along Figure 3A The line AA is cut off. The same reference numerals refer to the same components described above. MOSFET 100A-100O is similar to MOSFET 100, therefore... Figures 4-12B The discussion will focus on the differences between them.

[0132] refer to Figure 4 The power MOSFET 100A includes trench shielding regions 152A with substantially vertical sidewalls. That is, each trench shielding region 152A has a sidewall that extends substantially perpendicular to the lower surface of the semiconductor layer structure 160 as the distance from the gate trench 180 in the third direction Z increases. As a result, the width of each trench shielding region 152A in the second direction Y can remain substantially constant as the distance from the gate trench 180 in the third direction Z increases. The average width of the upper half of each trench shielding region 152A can be equal to the average width of the lower half of each trench shielding region 152A.

[0133] Figure 3D The cross-section of MOSFET 100 shown is substantially the same as that of MOSFET 100A, therefore, reference... Figure 3D The description of trench shielding region 152 also applies to trench shielding region 152A.

[0134] Because each trench shielding region 152A has a vertical sidewall, the JFET gap 124A of the power MOSFET 100A can be larger than the referenced above. Figure 2 The described JFET gap 24 is wider. This can be used to reduce the on-resistance of the power MOSFET 100A. The trench shielding region 152A also allows for higher integration, thereby reducing manufacturing costs and the size of the MOSFET 100A. As will be discussed in more detail below, the trench shielding region 152A can be formed using a channel ion implantation process to provide... Figure 4 The trench shielding area 152A is shown in the figure.

[0135] refer to Figure 5 The power MOSFET 100B includes a p-type support shield 150A having a corresponding width in the second direction Y that decreases with increasing depth in the semiconductor layer structure 160. Although not shown, in some other embodiments, the p-type support shield 150A may have a corresponding width in the second direction Y that remains substantially constant with increasing depth in the semiconductor layer structure 160.

[0136] A portion of the n-type drift region 120 may be located between one of the p-type support shielding portions 150A and one of the p-type trench shielding regions 152. For example... Figure 5 As shown, the width of this portion of the drift region 120 in the second direction Y increases with increasing depth in the semiconductor layer structure 160 because both the sidewalls of the trench shielding region 152 and the sidewalls of the support shielding portion 150A are angled inward.

[0137] Because the p-type support shield 150A has a width in the second direction Y that decreases with increasing depth in the semiconductor layer structure 160, the JFET gap 124B of the power MOSFET 100B can be larger than that mentioned above. Figure 2 The described JFET gap 24 is wider. This can be used to reduce the on-resistance of the power MOSFET 100B. The support shield 150A also allows for higher integration, thereby reducing manufacturing costs and the size of the MOSFET 100B. As will be discussed in more detail below, the support shield 150A can be formed using a channel ion implantation process to provide... Figure 5 The support shield 150A is shown in the figure.

[0138] refer to Figure 6 The power MOSFET 100C includes the trench shielding region 152A and the support shielding portion 150A described above. As a result, the JFET gap 124C of the power MOSFET 100C can be larger than that described above. Figure 2The described JFET gap 24 is wider. This can be used to reduce the on-resistance of the power MOSFET 100C.

[0139] A portion of the n-type drift region 120 may be located between one of the p-type support shielding portions 150A and one of the p-type trench shielding regions 152A. For example... Figure 6 As shown, the width of this portion of the drift region 120 in the second direction Y increases with the increase of depth in the semiconductor layer structure 160 because the sidewalls of the trench shielding region 152A are substantially vertical and the sidewalls of the supporting shielding portion 150A are angled inward.

[0140] refer to Figure 7A The power MOSFET 100D includes a trench shielding region 152, and the trench shielding region 152 includes an upper portion 152_U located between the gate trench 180 and the lower portion of the trench shielding region 152. The upper portion 152_U of the trench shielding region 152 has a higher second conductivity type (p) doping concentration than the lower portion of the trench shielding region 152.

[0141] During reverse blocking operation, the bottom of the gate oxide layer 182 typically experiences the highest electric field level. Due to electric field crowding effects, the electric field level in the lower “corner” of the gate oxide layer 182 at the bottom edge of the gate trench 180 can be particularly high (i.e., the portion of the gate oxide layer 182 that covers the sidewalls of the gate trench 180 and merges into the bottom of the gate trench 180). The more heavily doped upper portion 152_U of the trench shielding region 152 can provide enhanced protection for the gate oxide layer 182 by reducing the electric field level in the region where the gate oxide layer 182 is most vulnerable to breakdown, thereby improving the lifetime of the gate oxide layer 182.

[0142] In some embodiments, the maximum width of the upper portion 152_U of the trench shielding region 152 in the second direction Y may be less than or equal to the maximum width of the gate trench 180 in the second direction Y. In some embodiments, the upper portion 152_U of the trench shielding region 152 may have sidewalls that angle inward as the distance from the gate trench 180 in the third direction Z increases.

[0143] In some other embodiments, the upper portion 152_U of the trench shielding region 152 may have substantially vertical (i.e., substantially perpendicular to the lower surface of the semiconductor layer structure 160) sidewalls, or sidewalls that are slightly angled outwards with increasing distance from the gate trench 180 in the third direction Z. This may be because the upper portion 152_U of the trench shielding region 152 is formed by a random ion implantation process. In this case, at least a portion (e.g., the lower half) of the trench shielding region 152 will have sidewalls that are angled inwards with increasing distance from the gate trench 180 in the third direction Z. The upper portion 152_U of the trench shielding region 152 may extend from the bottom surface of the gate trench 180 into the upper portion of the drift region 120 (i.e., into the JFET region 122). Because the upper portion 152_U of the trench shielding region 152 does not extend as deeply within the semiconductor layer structure 160, the upper portion 152_U can exhibit significantly less diffusion expansion than would occur if the entire trench shielding region 152 were formed by random ion implantation. As a result, the effect on the JFET gap 124 can be minimal or negligible.

[0144] refer to Figure 7B The power MOSFET 100E includes a trench shielding region 152 having an upper portion 152_U as described above. The power MOSFET 100E also includes a p-type support shielding portion 150A as described above. For ease of description, repeated descriptions of these components are omitted.

[0145] refer to Figure 8A The power MOSFET 100F includes a trench shielding region 152A, and the trench shielding region 152A includes an upper portion 152A_U located between the gate trench 180 and the lower portion of the trench shielding region 152A. The upper portion 152A_U of the trench shielding region 152A has a higher second conductivity type (p) doping concentration than the lower portion of the trench shielding region 152A.

[0146] As discussed above, the bottom of the gate oxide layer 182 typically experiences the highest electric field level during reverse blocking operation. The more heavily doped upper portion 152A_U of the trench shielding region 152A can provide enhanced protection for the gate oxide layer 182 by reducing the electric field level in the region of gate oxide layer 182 most susceptible to breakdown, thereby improving the lifetime of the gate oxide layer 182.

[0147] In some embodiments, the maximum width of the upper portion 152A_U of the trench shielding region 152A in the second direction Y may be less than or equal to the maximum width of the gate trench 180 in the second direction Y. In some embodiments, the upper portion 152A_U of the trench shielding region 152A may have sidewalls that are substantially vertical (i.e. substantially perpendicular to the lower surface of the semiconductor layer structure 160) as the distance from the gate trench 180 in the third direction Z increases.

[0148] In some other embodiments, the upper portion 152A_U of the trench shielding region 152A may have sidewalls that are slightly angled outwards with increasing distance from the gate trench 180 in the third direction Z. This may be because the upper portion 152A_U of the trench shielding region 152A is formed by a random ion implantation process. In this case, at least a portion (e.g., the lower half) of the trench shielding region 152A will have sidewalls that are substantially vertical (i.e., substantially perpendicular to the lower surface of the semiconductor layer structure 160) with increasing distance from the gate trench 180 in the third direction Z. The upper portion 152A_U of the trench shielding region 152A may extend from the bottom surface of the gate trench 180 into the upper portion of the drift region 120 (i.e., into the JFET region 122). Because the upper portion 152A_U of the trench shielding region 152A does not extend as deeply within the semiconductor layer structure 160, the upper portion 152A_U can exhibit significantly less diffusion expansion than would occur if the entire trench shielding region 152A were formed by random ion implantation. As a result, the effect on the JFET gap 124A can be minimal or negligible.

[0149] refer to Figure 8B The power MOSFET 100G includes a trench shielding region 152A having the upper portion 152A_U described above. The power MOSFET 100G also includes a p-type support shielding portion 150A described above. For ease of description, repeated descriptions of these components are omitted.

[0150] refer to Figure 9A The power MOSFET 100H does not include the p-type support shield 150 or p-type support shield 150A described above. As a result, the JFET gap 124D extends between the trench shield regions 152 and is therefore further widened. While omitting the p-type support shields 150 and 150A may result in reduced protection of the gate oxide layer 182 during reverse blocking operation, the wider JFET gap 124D can be used to reduce the on-resistance of the power MOSFET 100H. Omitting the p-type support shields 150 and 150A also allows for higher integration, thereby reducing manufacturing costs and the size of the MOSFET 100H.

[0151] refer to Figure 9B The power MOSFET 100I does not include the p-type support shield 150 or p-type support shield 150A described above. Furthermore, the power MOSFET 100I includes a trench shield region 152 having a more heavily doped upper portion 152_U as described above. For ease of description, repeated descriptions of these components are omitted.

[0152] refer to Figure 10A The power MOSFET 100J does not include the p-type support shield 150 or p-type support shield 150A described above. As a result, the JFET gap 124E can extend between the trench shield regions 152A and is therefore further widened. While omitting the p-type support shields 150 and 150A may result in reduced protection of the gate oxide layer 182 during reverse blocking operation, the wider JFET gap 124E can be used to reduce the on-resistance of the power MOSFET 100J. Omitting the p-type support shields 150 and 150A also allows for higher integration, thereby reducing manufacturing costs and the size of the MOSFET 100J.

[0153] refer to Figure 10B The power MOSFET 100K does not include the p-type support shield 150 or p-type support shield 150A described above. Furthermore, the power MOSFET 100K includes a trench shield region 152A with a more heavily doped upper portion 152A_U as described above. For ease of description, repeated descriptions of these components are omitted.

[0154] refer to Figure 11A The power MOSFET 100L includes a p-type trench shielding region 152B and an n-type drift region 120A (which may also be referred to herein as a superjunction drift region 120A). The power MOSFET 100L does not include the p-type support shielding portion 150 or p-type support shielding portion 150A described above. The trench shielding region 152B is similar to the trench shielding region 152 described above, but extends deeper into the drift region 120A to provide a superjunction structure within the drift region 120A. Therefore, the power MOSFET 100L can be referred to as a gate trench silicon carbide superjunction power MOSFET 100L.

[0155] The so-called superjunction drift region 120A can increase the blocking voltage of the power MOSFET 100L while reducing its impact on on-resistance. In the drift region 120A with the superjunction structure, the drift region 120A is divided into alternating, side-by-side n-type and p-type regions by the trench shielding region 152B. The portions of the drift region 120A divided by the trench shielding region 152B provide n-type regions, while the trench shielding region 152B provides p-type regions. In some embodiments, the n-type drift region 120A and the p-type trench shielding region 152B can be more heavily doped (e.g., 2 to 200 times more doped) than the drift region 120 and the p-type trench shielding regions 152 and 152A described above. These side-by-side n-type and p-type regions are commonly referred to as "pillars". The number of charge carriers in each n-type pillar (i.e., each portion of drift region 120A) can be approximately equal to (e.g., within 20%, or more preferably within 10%, or within 5%, or within 2%) the number of charge carriers in each p-type pillar (i.e., each trench shielding region 152B). The number of charge carriers in each pillar can be set by selecting the width and doping concentration of each pillar. When the number of charge carriers in adjacent n-type and p-type pillars is approximately equal, the interface between the pillars will be laterally depleted during reverse blocking operation, which serves to change the shape of the electric field formed in drift region 120A during reverse blocking operation. Specifically, the portion of the electric field beyond the first level can have a generally rectangular shape in the superjunction drift region 120A. The approximately rectangular electric field formed in the superjunction drift region 120A is used to better distribute the electric field in the lower part of the drift region 120A, thereby reducing the electric field value in the upper part of the semiconductor layer structure 160, where a high electric field value could damage the gate oxide layer 182. Therefore, the superjunction drift region 120A can exhibit superior performance during reverse blocking operation. Furthermore, since the drift region 120A can be more heavily doped, the resistance of the superjunction drift region 120A can be reduced during on-state operation.

[0156] In an exemplary embodiment of the invention, the trench shielding region 152B serves to provide a superjunction structure in the drift region 120A and to protect the gate oxide layer 182 from the effects of a high electric field during reverse blocking operation.

[0157] like Figure 11AAs shown, the trench shielding region 152B has sidewalls that angle inwards with increasing distance from the gate trench 180 in the third direction Z. As a result, the corresponding width of the trench shielding region 152B in the second direction Y decreases with increasing distance from the gate trench 180. The distance between adjacent trench shielding regions 152B in the second direction Y can increase with increasing depth in the semiconductor layer structure 160. A portion (i.e., an n-type pillar) of the n-type drift region 120A between adjacent p-type trench shielding regions 152B can have a width in the second direction Y that increases with increasing depth in the semiconductor layer structure 160. The average width of the upper half of each trench shielding region 152B in the second direction Y can be greater than the average width of the lower half of each trench shielding region 152B in the second direction Y. As will be discussed in more detail below, the trench shielding region 152B can be provided by forming it using a channel ion implantation process. Figure 11A The trench shielding region 152B is shown in the diagram. The channel ion implantation process can also allow the trench shielding region 152B to extend deeper into the drift region 120A to block very high voltages during reverse blocking operation. For example, the trench shielding region 152B can extend from the bottom surface of the gate trench 180 into the JFET region 122 (i.e., into the upper part of the drift region 120A) and into the drift region 120A to a depth greater than or equal to 4 micrometers. Figure 11A Aligned with the gate trench 180 over the entire or substantially the entire length of the gate trench 180 in the direction of entering the page.

[0158] refer to Figure 11B The power MOSFET 100M includes a trench shielding region 152B, and the trench shielding region 152B includes an upper portion 152B_U located between the gate trench 180 and the lower portion of the trench shielding region 152B. The upper portion 152B_U of the trench shielding region 152B has a higher second conductivity type (p) doping concentration than the lower portion of the trench shielding region 152B.

[0159] As discussed above, the bottom of the gate oxide layer 182 typically experiences the highest electric field level during reverse blocking operation. The more heavily doped upper portion 152B_U of the trench shielding region 152B can provide enhanced protection for the gate oxide layer 182 by reducing the electric field level in the region of gate oxide layer 182 most susceptible to breakdown, thereby improving the lifetime of the gate oxide layer 182.

[0160] In some embodiments, the maximum width of the upper portion 152B_U of the trench shielding region 152B in the second direction Y may be less than or equal to the maximum width of the gate trench 180 in the second direction Y. In some embodiments, the upper portion 152B_U of the trench shielding region 152B may have sidewalls that angle inward as the distance from the gate trench 180 in the third direction Z increases.

[0161] In some other embodiments, the upper portion 152B_U of the trench shielding region 152B may have substantially vertical (i.e., substantially perpendicular to the lower surface of the semiconductor layer structure 160) sidewalls, or sidewalls that are slightly angled outwards with increasing distance from the gate trench 180 in the third direction Z. This may be because the upper portion 152B_U of the trench shielding region 152B is formed by a random ion implantation process. In this case, at least a portion (e.g., the lower half) of the trench shielding region 152B will have sidewalls that are angled inwards with increasing distance from the gate trench 180 in the third direction Z. The upper portion 152B_U of the trench shielding region 152B may extend from the bottom surface of the gate trench 180 into the JFET region 122 (i.e., into the upper portion of the drift region 120A). Since the upper portion 152B_U of the trench shielding region 152B does not extend as deeply in the semiconductor layer structure 160, the upper portion 152B_U may exhibit significantly less diffusion expansion than would have occurred if the entire trench shielding region 152B were formed by random ion implantation.

[0162] refer to Figure 12A The power MOSFET 100N includes a p-type trench shielding region 152C and an n-type superjunction drift region 120A. The trench shielding region 152C is similar to the trench shielding region 152B described above, but has sidewalls that become substantially vertical (i.e. substantially perpendicular to the lower surface of the semiconductor layer structure 160) with increasing distance from the gate trench 180 in the third direction Z. As a result, the corresponding width of the trench shielding region 152C in the second direction Y can remain substantially constant with increasing distance from the gate trench 180 in the third direction Z. As discussed above, the so-called superjunction drift region 120A can increase the blocking voltage of the power MOSFET 100N while reducing its effect on the on-resistance.

[0163] like Figure 12AAs shown, the distance between adjacent trench shielding regions 152C in the second direction Y can be substantially constant with increasing depth in the semiconductor layer structure 160. The average width of the upper half of each trench shielding region 152C in the second direction Y can be equal to the average width of the lower half of each trench shielding region 152C in the second direction Y. As will be discussed in more detail below, the trench shielding regions 152C can be formed using a channel ion implantation process to provide... Figure 12A The trench shielding region 152C is shown in the diagram. The channel ion implantation process can also allow the trench shielding region 152C to extend deeper into the drift region 120A to block very high voltages during reverse blocking operation. For example, the trench shielding region 152C can extend from the bottom surface of the gate trench 180 into the JFET region 122 (i.e., into the upper part of the drift region 120A) and the drift region 120A to a depth greater than or equal to 4 micrometers. The trench shielding region 152C can extend in the first direction X (i.e., in...) Figure 12A Aligned with the gate trench 180 over the entire or substantially the entire length of the gate trench 180 in the direction of entering the page.

[0164] refer to Figure 12B The power MOSFET 100O includes a trench shielding region 152C, and the trench shielding region 152C includes an upper portion 152C_U located between the gate trench 180 and the lower portion of the trench shielding region 152C. The upper portion 152C_U of the trench shielding region 152C has a higher second conductivity type (p) doping concentration than the lower portion of the trench shielding region 152C.

[0165] As discussed above, the bottom of the gate oxide layer 182 typically experiences the highest electric field level during reverse blocking operation. The more heavily doped upper portion 152C_U of the trench shielding region 152C can provide enhanced protection for the gate oxide layer 182 by reducing the electric field level in the region of the gate oxide layer 182 most vulnerable to breakdown, thereby improving the lifetime of the gate oxide layer 182.

[0166] In some embodiments, the maximum width of the upper portion 152C_U of the trench shielding region 152C in the second direction Y may be less than or equal to the maximum width of the gate trench 180 in the second direction Y. In some embodiments, the upper portion 152C_U of the trench shielding region 152C may have sidewalls that are substantially vertical (i.e. substantially perpendicular to the lower surface of the semiconductor layer structure 160) as the distance from the gate trench 180 in the third direction Z increases.

[0167] In some other embodiments, the upper portion 152C_U of the trench shielding region 152C may have sidewalls that are slightly angled outwards with increasing distance from the gate trench 180 in the third direction Z. This is likely because the upper portion 152C_U of the trench shielding region 152C is formed by a random ion implantation process. In this case, at least a portion (e.g., the lower half) of the trench shielding region 152C will have sidewalls that are substantially vertical (i.e., substantially perpendicular to the lower surface of the semiconductor layer structure 160) with increasing distance from the gate trench 180 in the third direction Z. The upper portion 152C_U of the trench shielding region 152C may extend from the bottom surface of the gate trench 180 into the JFET region 122 (i.e., into the upper portion of the drift region 120A). Since the upper part 152C_U of the trench shielding region 152C does not extend as deeply in the semiconductor layer structure 160, the upper part 152C_U can exhibit significantly less diffusion expansion than would occur if the entire trench shielding region 152C were formed by random ion implantation.

[0168] Figures 13A-13F This is a schematic cross-sectional view illustrating a method for manufacturing a gate trench silicon carbide power MOSFET according to some embodiments of the present invention. Figures 13A-13F The same reference numerals in the figures refer to the same elements described above.

[0169] refer to Figure 13A An n-type silicon carbide substrate 110 is provided. A lightly doped n-type silicon carbide drift region 120 is then formed on the upper surface of the substrate 110, for example, by epitaxial growth. In some embodiments, the n-type dopant concentration may be increased during the growth of the upper portion of the drift region 120 to form a JFET region 122. In some other embodiments, the n-type dopant concentration may be kept constant during the growth of the upper portion of the drift region 120 to form the JFET region 122. A moderately doped p-type silicon carbide well region 130 (also referred to as well layer 130) is formed on the upper surface of the n-type drift region 120 (i.e., the upper surface of the JFET region 122) by epitaxial growth or, more commonly, by implanting p-type dopant ions into the upper portion of the n-type drift region 120 (i.e., into the JFET region 122). Figure 13A As shown in the image.

[0170] refer to Figure 13BA heavily doped silicon carbide source region 140 (also referred to as source layer 140) is formed in the upper part of the p-type silicon carbide well region 130 by, for example, implanting n-type dopant ions into the upper part of the well region 130. The silicon carbide substrate 110, drift region 120, JFET region 122, well region 130 and source region 140, and various regions formed therein, such as support shielding and trench shielding regions (discussed below), together constitute the semiconductor layer structure 160.

[0171] refer to Figure 13C A moderately or heavily doped silicon carbide support shield 150A is formed by implanting p-type dopant ions into the semiconductor layer structure 160. To form the support shield 150A, an ion implantation mask 191A is formed on the upper surface of the semiconductor layer structure 160. Figure 13C As shown, the ion implantation mask 191A is patterned to form openings 192 therein, these openings being located above the region in the semiconductor layer structure 160 where the support shield 150A will be formed. The support shield 150A is then formed by ion implantation, after which the ion implantation mask 191A is removed. The support shield 150A can be formed via a channel ion implantation process, which will be referenced below. Figure 13E A more detailed description. Although Figure 13C Not shown in the diagram, but in some other embodiments, the support shield 150 can be formed instead of the support shield 150A by implanting p-type dopant ions into the semiconductor layer structure 160. In this case, the support shield 150 can be formed by a random ion implantation process, which will be referred to below. Figure 13F To describe in more detail.

[0172] The support shield 150A may extend between 0.5 and 10 micrometers in the depth direction (i.e., the third direction Z) within the semiconductor layer structure 160. In some other embodiments, the support shield 150A may alternatively be formed prior to the formation of the source region 140. The support shield 150A helps reduce the electric field level in the gate oxide layer, which helps prevent premature breakdown of the gate oxide layer. If the MOSFET experiences avalanche breakdown, the support shield 150A can also provide a low-resistance current path between the source and drain terminals of the MOSFET. This lower-resistance current path helps reduce the amount of heat generated by the device during an avalanche breakdown event, thereby increasing the likelihood that the MOSFET can survive such an event without damage.

[0173] refer to Figure 13D An etching process can be performed to form a plurality of gate trenches 180 in the upper portion of the semiconductor layer structure 160. Each gate trench 180 can be formed in a first direction X (i.e., in the direction of the first direction X). Figure 13DThe gate trench 180 extends laterally (i.e., parallel to the main surface of the semiconductor layer structure 160) across the length (or width) of the power MOSFET in the direction of the page entry. The gate trench 180 may extend vertically in the third direction (Z) through the source region 140 and the well region 130, and enter the JFET region 122 (i.e., into the upper part of the drift region 120), as shown. Figure 13D As shown, the gate trenches 180 can be spaced apart from each other in the second direction Y. For example, the formation of the gate trenches 180 can convert the well region 130 and the source region 140 into a plurality of well regions 130 and a plurality of source regions 140, respectively. The formation of the gate trenches 180 can also convert the JFET region 122 into a plurality of JFET regions 122.

[0174] refer to Figure 13E By implanting p-type dopant ions into the semiconductor layer structure 160, a moderately or heavily doped p-type silicon carbide trench shielding region 152 is formed in the semiconductor layer structure 160 below each gate trench 180. Figure 13E As shown, an ion implantation mask 191B is formed on the upper surface of the semiconductor layer structure 160, and the ion implantation mask 191B is patterned to form an opening therein located above the gate trench 180. A trench shielding region 152 is then formed by implanting p-type dopant ions into the gate trench 180. Although not shown, in some embodiments, spacers, such as oxide spacers, may be formed on the sidewalls of the gate trench 180 before the implantation of p-type dopant ions. The spacers can be formed by thermally oxidizing silicon carbide in the portion of the semiconductor layer structure 160 surrounding the gate trench 180, or by depositing oxide in the gate trench 180 followed by full etching. The spacers can help prevent p-type ions from being implanted into the sidewalls of the gate trench 180, which helps avoid adversely altering the doping concentration in the region of the semiconductor layer structure 160 adjacent to the gate trench 180. For example, if a portion of the sidewalls of the JFET region 122 adjacent to the gate trench 180 transitions from n-type conductivity to p-type conductivity, the MOSFET may become inoperable. Spacers can be used to prevent this from happening.

[0175] Still referencing Figure 13EA channel ion implantation process is performed to implant p-type dopant ions into the semiconductor layer structure 160, thereby forming a p-type trench shielding region 152. As discussed, for example, in U.S. Patent No. 11,075,264 (“'264 Patent”), a channel ion implantation process refers to an ion implantation process that implants dopant ions along certain crystal axes forming channels in the silicon carbide semiconductor layer structure 160, where a channel is a region where no atoms are present when viewed along a crystal axis, the entire contents of which are incorporated herein by reference. Channel ion implantation can be performed by angulating the ion source relative to the semiconductor layer structure 160, such that the dopant ions are implanted along the desired crystal axis, as further explained in detail in the '264 Patent. When dopant ions are implanted along channels in the crystal axis, the dopant ions travel, on average, much further within the lattice of the semiconductor layer structure 160 before striking atoms within the lattice, compared to the case of performing a random ion implantation process. Therefore, ions implanted in channel ion implantation can, on average, be implanted to greater depths while using lower implantation energies (which advantageously reduces implantation damage to the silicon carbide semiconductor layer structure 160 and also reduces scattering of dopant ions to unintended locations in the lattice). Furthermore, channel ion implantation typically results in little or no diffusion expansion of the implanted region with depth because dopant ions end up striking fewer atoms and / or are more confined within the channel. As explained in the '264 patent, there exists a crystal axis supporting channel ion implantation. When using channel ion implantation, not only can dopant ions be implanted to greater depths with less implantation energy, but the reduced scattering allows the implanted region to have more vertical or inwardly angled sidewalls than could be achieved using standard (random) ion implantation techniques.

[0176] In a 4H silicon carbide-based device, there are three sets of crystal axes suitable for channel ion implantation, namely (1) <0001> Crystal axes, (2) <11-23> crystal axis (and symmetrical equivalents <-1-123>, <1-213>, <-12-13>, <2-1-13> and <-2113> crystal axes), and (3) <11-20> crystal axis. The channel ion implantation process for forming the trench shielding region 152 can be performed along any of these crystal axes of the semiconductor layer structure 160.

[0177] Although Figure 13EThe illustration shows a trench shielding region 152 with inwardly angled sidewalls; however, it should be understood that a trench shielding region 152A with substantially vertical sidewalls can also be formed using the aforementioned channel ion implantation process. The conditions of the channel ion implantation process can be carefully controlled to form the trench shielding region 152 or trench shielding region 152A. For example, during the channel ion implantation process, the implantation energy at which p-type dopant ions are accelerated before implantation, the doping dose per unit area of ​​p-type dopant ions, and / or the projected range of the depth to which p-type dopant ions stop in the semiconductor layer structure 160 can be carefully selected to form the trench shielding region 152 or trench shielding region 152A. After the channel ion implantation process, for example, an annealing step can be performed to help provide the trench shielding region 152 or trench shielding region 152A. As another example, the ion implantation mask 191B can be carefully designed to help form the trench shielding region 152 or trench shielding region 152A. In some embodiments, one or more materials of the ion implantation mask 191B may be selected and / or patterned openings in the ion implantation mask 191B may be designed to help provide trench shielding region 152 or trench shielding region 152A. For example, see reference below. Figure 14A As will be discussed in more detail, in some embodiments, during the trench ion implantation process, the ion implantation mask can be patterned to have angled sidewalls along its opening. The angled sidewalls of the ion implantation mask can be carefully patterned to help provide the desired distribution of the trench shielding region 152 or trench shielding region 152A.

[0178] have Figure 13E The trench shielding region 152 of the shape shown can be used to increase the JFET gap 124B, which can reduce the on-resistance of the MOSFET and / or allow the unit cells of the MOSFET to be more closely spaced by reducing the distance between adjacent gate trenches 180.

[0179] Although the above is about Figure 13E The description indicates the use of a trench ion implantation process to form the trench shielding region 152, but it should be understood that embodiments of the invention are not limited thereto. For example, in some other embodiments, a random ion implantation process may be used instead. However, since diffusion expansion typically occurs when using such implantation processes, it may be difficult to obtain a trench shielding region with inwardly angled or vertical sidewalls.

[0180] refer to Figure 13FIn some embodiments, a channel ion implantation process can be performed to initially form the trench shielding region 152, and then p-type dopant ions can be implanted into the upper portion of the trench shielding region 152 using a random ion implantation process (i.e., a non-channel ion implantation process). As a result, each trench shielding region 152 includes an upper portion 152_U having a higher second conductivity type (p) doping concentration than the lower portion of each trench shielding region 152. The more heavily doped upper portion 152_U of the trench shielding region 152 can provide enhanced protection for the gate oxide layer by reducing the electric field level in the most vulnerable breakdown region of the gate oxide layer. In some other embodiments, the random ion implantation process used to form the upper portion 152_U of each trench shielding region 152 can alternatively refer to the above-referenced... Figure 13E The described channel ion implantation process is performed prior to the process, and the remainder of each trench shielding region 152 can subsequently be formed by the channel ion implantation process.

[0181] The upper portion 152_U of each trench shielding region 152 is formed by implanting p-type dopant ions into the semiconductor layer structure 160 using a random ion implantation process. Therefore, each trench shielding region 152 can be formed using both channel ion implantation and random ion implantation processes. Figure 13F As shown, in some embodiments, the same ion implantation mask 191B used in the channel ion implantation process can be used to form the upper portion 152_U of each trench shielding region 152 in the random ion implantation process. In some other embodiments, the ion implantation mask 191B can be removed after the trench shielding region 152 is formed in the channel ion implantation process, and a new ion implantation mask can be used to form the upper portion 152_U of each trench shielding region 152 in the random ion implantation process. The ion implantation mask 191B includes an opening located above the gate trench 180 and forms the upper portion 152_U of the trench shielding region 152 by implanting p-type dopant ions into the gate trench 180. During the random ion implantation process, p-type dopant ions are implanted into the semiconductor layer structure 160 at high energy. Unlike the channel ion implantation process, p-type dopant ions are not implanted in an atom-free channel, so when p-type dopant ions enter the semiconductor layer structure 160, they may collide with atoms in the crystal lattice. During the random ion implantation process, p-type dopant ions can be positioned at a 90° angle relative to the upper surface of the semiconductor layer structure 160. 0The implantation is performed at an angle (i.e., vertically). Because the upper portion 152_U of the trench shielding region 152 extends less deeply within the semiconductor layer structure 160 than the rest of the trench shielding region 152, the upper portion 152_U can exhibit significantly less diffusion expansion than would occur if the entire trench shielding region 152 were formed by a random ion implantation process. As a result, the effect on the JFET gap 124B can be minimal or negligible.

[0182] Reference Back Figure 7B A gate oxide layer 182 can be formed in the gate trench 180 to cover the sidewalls and bottom surface of each gate trench 180. A gate electrode 184 can be formed on the gate oxide layer 182 in the gate trench 180. An intermetallic dielectric layer 188 can be formed to cover each gate electrode 184. A source metallization layer 190 can be formed on the upper surface of the semiconductor layer structure 160 and on the intermetallic dielectric layer 188. A drain pad 106 can be formed on the substrate 110, opposite to the drift region 120.

[0183] Although Figures 13A-13F The description mainly focuses on Figure 7B The components included in the power MOSFET 100E shown are not explicitly stated, but it should be understood that unless the context clearly indicates otherwise. Figures 13A-13F The description also applies to the components included in MOSFET 100, 100A-100D and 100F-100O.

[0184] Figures 14A-14C This is a schematic cross-sectional view illustrating a method for manufacturing a gate trench silicon carbide power MOSFET according to some embodiments of the present invention. Figures 14A-14C The same reference numerals in the figures refer to the same elements described above.

[0185] refer to Figure 14A In some embodiments, in reference Figures 13A-13C Following the described steps, a trench shielding region 152 is formed before the gate trench 180 is formed. Furthermore, in some embodiments, an ion implantation mask 191C including angled sidewalls may be used to form the trench shielding region 152.

[0186] An ion implantation mask 191C can be patterned to form openings 193 therein that expose selected portions of the semiconductor layer structure 160. The openings 193 can be centered above the location in the semiconductor layer structure 160 where trench shielding regions 152 will be formed, but the openings 193 can be narrower than the intended width of the top of each trench shielding region 152. Notably, the sidewalls of the mask 191C portions on either side of the openings 193 are angled outwards, such that the width of these portions of the mask 191C increases as they approach the semiconductor layer structure 160. Therefore, the sidewalls of the mask 191C defining each opening 193 are angled sidewalls, each sidewall defining an obtuse angle α relative to the upper surface of the semiconductor layer structure 160 exposed through the corresponding opening 193, such as... Figure 14A As shown in the illustration. In some embodiments, the obtuse angle α is an angle between 100° and 160°. The angled sidewalls of the mask 191C defining the opening 193 can be formed using various known etching techniques.

[0187] The thickness of mask 191C is sufficient to allow few or no dopant ions to penetrate its entire thickness for implantation into semiconductor layer structure 160. However, because the sidewalls of mask 191C defining opening 193 are angled sidewalls, dopant ions impacting the sidewalls will not need to penetrate the entire thickness of mask 191C to reach semiconductor layer structure 160. Therefore, when trench shielding region 152 is formed using the above-described channel ion implantation process, some of the dopant ions implanted into the angled sidewalls of mask 191C will penetrate mask 191C and be implanted into semiconductor layer structure 160. However, penetrating mask 191C reduces the energy of these dopant ions (because they impact atoms within mask 191C), so, on average, dopant ions that penetrate mask 191C before implantation into semiconductor layer structure 160 will not travel as far (i.e., as deep) into semiconductor layer structure 160 as dopant ions implanted directly into semiconductor layer structure 160 through opening 193. Furthermore, the higher the dopant ions are implanted into one of the sidewalls (i.e., the farther away from the bottom of port 193), the shallower, on average, the deeper the dopant ions are implanted into the semiconductor layer structure 160. As a result, the trench shielding regions 152 can be widest at the top and then narrower as they extend deeper into the semiconductor layer structure 160, such as... Figure 14A As shown in the diagram. In other words, the trench shielding region 152 may have sidewalls that angle inwards with increasing depth in the semiconductor layer structure 160. After the trench shielding region 152 is formed in the channel ion implantation process, the ion implantation mask 191C can be removed.

[0188] exist Figure 14AIn an example embodiment, a higher implantation energy can be used in the channel ion implantation process to account for the case where the trench shielding region 152 is formed before the gate trench 180. Although Figure 14A The illustration shows a trench shielding region 152 with inwardly angled sidewalls, but it should be understood that a trench shielding region 152A with substantially vertical sidewalls can also be formed as described above.

[0189] refer to Figure 14B An etching process can be performed on the semiconductor layer structure 160 to form a gate trench 180 in the semiconductor layer structure 160 on the corresponding trench shielding region 152.

[0190] refer to Figure 14C In some embodiments, a channel ion implantation process can be performed to initially form the trench shielding region 152, and then p-type dopant ions can be implanted into the upper portion of each trench shielding region 152 using the random ion implantation process described above. An ion implantation mask 191B can be formed on the upper surface of the semiconductor layer structure 160 and patterned to form openings therein above the gate trenches 180 into which p-type dopant ions are implanted. As a result, each trench shielding region 152 includes an upper portion 152_U having a higher second conductivity type (p) doping concentration than the lower portion of each trench shielding region 152. Therefore, each trench shielding region 152 can be formed using both a channel ion implantation process and a random ion implantation process. The ion implantation mask 191B can then be removed, and the gate oxide layer 182, gate electrode 184, intermetallic dielectric layer 188, source metallization layer 190, and drain pad 106 can be formed as described above.

[0191] Figure 15A and Figure 15B This is a schematic cross-sectional view illustrating a method for manufacturing a gate trench silicon carbide power MOSFET according to some embodiments of the present invention. Figure 15A and Figure 15B The same reference numerals in the figures refer to the same elements described above.

[0192] refer to Figure 15A In some embodiments, as referenced above Figures 13A-13D Following the described steps, a moderately or heavily doped p-type silicon carbide trench shielding region 152B is formed in the semiconductor layer structure 160 beneath each gate trench 180 by implanting p-type dopant ions into the gate trench 180, thereby providing a superjunction structure in the drift region 120A. In this case, the above references can be omitted. Figure 13CThe steps for forming the support shield 150A are described below. An ion implantation mask 191B is formed on the upper surface of the semiconductor layer structure 160, and the mask is patterned to form an opening therein located above the gate trench 180. The trench shielding region 152B is formed using the above-described channel ion implantation process. Figure 15A In an example embodiment, a higher implantation energy can be used in the channel ion implantation process, allowing the trench shielding region 152B to extend deeper into the drift region 120A to provide a superjunction structure therein. The channel ion implantation process allows the trench shielding region 152B to extend deeper into the drift region 120A than a random (non-channel) ion implantation process.

[0193] The channel ion implantation process for forming the trench shielding region 152B is performed in the gate trench 180, which provides two advantages. First, since p-type dopant ions are implanted into the gate trench 180 rather than into the upper surface of the semiconductor layer structure 160, the trench shielding region 152B can extend deeper into the drift region 120A while using the same amount of energy or less in the channel ion implantation process. Second, the trench shielding region 152B can extend deeper into the drift region 120A in the first direction X (i.e., in the direction X). Figure 15A The trench shielding region 152B is aligned with the gate trench 180 along its entire or substantially entire length (in the direction of entering the page). Therefore, the trench shielding region 152B can provide enhanced protection for the gate oxide layer along its entire or substantially entire length, while also providing a superjunction structure in the drift region 120A. Although Figure 15A The illustration shows a trench shielding region 152B with inwardly angled sidewalls, but it should be understood that a trench shielding region 152C with substantially vertical sidewalls can also be formed as described above.

[0194] refer to Figure 15BIn some embodiments, a channel ion implantation process can be performed to initially form the trench shielding region 152B, and then p-type dopant ions can be implanted into the upper portion of each trench shielding region 152B using the random ion implantation process described above. As a result, each trench shielding region 152B includes an upper portion 152B_U having a higher second conductivity type (p) doping concentration than the lower portion of each trench shielding region 152B. Therefore, each trench shielding region 152B can be formed using both a channel ion implantation process and a random ion implantation process. The ion implantation mask 191B can then be removed, and the gate oxide layer 182, gate electrode 184, intermetallic dielectric layer 188, source metallization layer 190, and drain pad 106 can be formed as described above. In some other embodiments, the random ion implantation process for forming the upper portion 152B_U of each trench shielding region 152B can alternatively be performed before the channel ion implantation process, and the remaining portion of each trench shielding region 152B can be subsequently formed by the channel ion implantation process.

[0195] Figures 16A-16E This is a schematic cross-sectional view illustrating a method for manufacturing a gate trench silicon carbide power MOSFET according to some embodiments of the present invention. Figures 16A-16E The same reference numerals in the figures refer to the same elements described above.

[0196] refer to Figure 16A As mentioned above (refer to the reference) Figure 13A The substrate 110, drift region 120, and JFET region 122 are formed. Then, referring to the above... Figure 13A The description differs in that a source region 140 is formed in the upper part of drift region 120 (i.e., the upper part of JFET region 122). The n-type source region 140 is typically formed via ion implantation because this provides a more uniform doping density, such as... Figure 16A As shown, but alternatively formed by epitaxial growth on silicon carbide drift region 120. Silicon carbide substrate 110, drift region 120, JFET region 122 and source region 140, and various regions formed therein, such as well regions, support shields and trench shields (discussed below), together constitute semiconductor layer structure 160.

[0197] refer to Figure 16BA silicon carbide support shield 150A is formed by implanting p-type dopant ions into the semiconductor layer structure 160. To form the support shield 150A, an ion implantation mask 191A is formed on the upper surface of the semiconductor layer structure 160, and the mask is patterned to form openings 192 therein, located above the region in the semiconductor layer structure 160 where the support shield 150A will be formed. The support shield 150A is then formed by ion implantation, after which the ion implantation mask 191A is removed. The support shield 150A can be formed using the channel ion implantation process discussed above. Although not shown, in some other embodiments, the support shield 150 can be formed instead of the support shield 150A by implanting p-type dopant ions into the semiconductor layer structure 160. In this case, the support shield 150 can be formed using the random ion implantation process described above.

[0198] refer to Figure 16C An etching process can be performed to form a plurality of gate trenches 180 in the upper surface of the semiconductor layer structure 160. For example, the formation of the gate trenches 180 can convert the source region 140 and the JFET region 122 into a plurality of source regions 140 and a plurality of JFET regions 122, respectively.

[0199] refer to Figure 16D The aforementioned channel ion implantation process is performed to implant p-type dopant ions into the semiconductor layer structure 160. (Refer to the above text.) Figure 13E Unlike the description, this ion implantation step is performed without an ion implantation mask. A p-type dopant is implanted and passes through the heavily doped n-type source region 140 into the underlying drift region 120 to form a moderately doped well region 130 in the upper portion of the drift region 120 below the source region 140 (i.e., the upper portion of the JFET region 122). A portion of the well region 130 adjacent to the gate trench 180 serves as a channel. P-type dopant is also implanted into portions of the drift region 120 located below the bottom surface of the gate trench 180 (i.e., these portions of the JFET region 122) to form a trench shielding region 152 extending therebelow. Figure 16D In an example embodiment, a higher ion implantation energy can be used to perform the channel ion implantation process because the p-type dopant is implanted through the n-type source region 140 to form a well region 130 below it.

[0200] Since the well region 130 and the trench shield region 152 are formed together (i.e., simultaneously) using the same channel ion implantation process, the doping distribution of p-type dopant in the well region 130 will substantially match (i.e., within 15%) the doping distribution of p-type dopant in the lower part of the trench shield region 152. In this document, the doping distribution of a region of a semiconductor layer structure (e.g., the doping distribution of the well region 130 or the trench shield region 152) refers to the variation of the concentration of a certain type of dopant with depth. Therefore, the doping distribution can be graphically depicted using a two-dimensional graph showing the variation of the concentration of a specified type of dopant with respect to a distance in the depth direction from a reference plane, such as, for example, the upper surface of the semiconductor layer structure 160. It should be understood that the doping distribution of a region is obtained through the central portion of the region that is not adjacent to another region, rather than through the edge portions of the region, because edge effects can cause unintended variations in the doping distribution that do not represent the doping distribution of that region.

[0201] refer to Figure 16E In some embodiments, a channel ion implantation process can be performed to initially form the trench shielding region 152, and then p-type dopant ions can be implanted into the upper portion of each trench shielding region 152 using the random ion implantation process described above. As a result, each trench shielding region 152 includes an upper portion 152_U having a higher second conductivity type (p) doping concentration than the lower portion of each trench shielding region 152. Therefore, each trench shielding region 152 can be formed using both the channel ion implantation process and the random ion implantation process. The ion implantation mask 191B can then be removed, and the gate oxide layer 182, gate electrode 184, intermetallic dielectric layer 188, source metallization layer 190, and drain pad 106 can be formed as described above. In some other embodiments, the random ion implantation process for forming the upper portion 152_U of each trench shielding region 152 can alternatively be performed before the channel ion implantation process, and the well region 130 can be formed together (i.e., simultaneously) using the same random ion implantation process. The remainder of each trench shielding region 152 was subsequently formed by a trench ion implantation process.

[0202] It should be understood that, in further embodiments, the above references Figures 13A-13F , Figures 14A-14C , Figures 15A-15B and Figures 16A-16E The process steps discussed can be performed in different orders. Therefore, it should be understood that various process steps can be performed in orders other than those shown. It should also be understood that in other embodiments, some process steps may be omitted, and / or other process steps may be added to the method.

[0203] As described above, one technique for forming a trench shielding region having sidewalls that angle inward or are substantially vertical with increasing depth in the semiconductor layer structure is to use a trench ion implantation process to form the trench shielding region. However, it should be understood that embodiments of the invention are not necessarily limited to this. For example, in other embodiments, the trench shielding region may be formed having sidewalls that angle outward with increasing depth in the semiconductor layer structure, and an n-type dopant may be implanted into the semiconductor layer structure using a buried random ion implantation process before or after this ion implantation process. The diffusion expansion that occurs with increasing depth during random ion implantation implants the n-type dopant to the outer edge of the trench shielding region, compensating for the p-type dopant, thereby converting the outer edge of the trench shielding region into an n-type semiconductor material. The degree of this conversion increases with increasing depth because the diffusion expansion increases with increasing depth. As a result, the trench shielding region may have sidewalls that angle inward or are substantially vertical with increasing depth in the semiconductor layer structure.

[0204] The exemplary embodiments of the present invention have been described above primarily with reference to the cross-sectional views. It should be understood that in each embodiment depicted in the present invention, the support shield, trench shield region, gate trench, etc., can be elongated structures that continuously extend into the page shown in the figures, spanning the active region of the semiconductor device. However, it should also be understood that in other embodiments, the support shield and / or trench shield region can instead be segmented structures, with some portions removed so that these structures do not continuously extend into the page shown in the figures, but instead have a structure with multiple collinear segments extending into the page.

[0205] In the above description, each example embodiment has a certain conductivity type. It should be understood that devices with opposite conductivity types can be formed by simply reversing the conductivity of the n-type and p-type layers in each of the above embodiments. Therefore, it should be understood that the present invention covers both n-channel and p-channel devices of every different device structure (e.g., MOSFET, IGBT, etc.).

[0206] The present invention has been primarily discussed above regarding silicon carbide-based power semiconductor devices. However, it should be understood that silicon carbide is used as an example herein, and the devices discussed herein can be formed in any suitable wide-bandgap semiconductor material system. As an example, in any of the embodiments described above, gallium nitride-based semiconductor materials (e.g., gallium nitride, aluminum gallium nitride, etc.) can be used instead of silicon carbide.

[0207] Embodiments of the invention have been described above with reference to the accompanying drawings, which illustrate exemplary embodiments of the invention. However, it should be understood that the invention can be embodied in many different forms and should not be construed as limited to the embodiments described above. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Throughout this specification, the same reference numerals refer to the same elements.

[0208] In this document, the term "multiple" means two or more. In this document, "substantially" means within + / - 10%.

[0209] It should be understood that although the terms first, second, etc., are used throughout the specification to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element may be referred to as a second element without departing from the scope of the invention, and similarly, a second element may be referred to as a first element. The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0210] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well. It will be further understood that, when used herein, the terms “comprising,” “including,” “containing,” “having,” and / or “having” designate the presence of the stated features, integers, steps, operations, elements, components, and / or groups, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0211] It should be understood that when a component, such as a layer, region, or substrate, is referred to as "on another component" or "extending to another component," it can be directly on or directly extended to another component, or intermediate components may exist. Conversely, when a component is referred to as "directly on another component" or "directly extending to another component," no intermediate components exist. It should also be understood that when a component is referred to as "connected" or "coupled" to another component, it can be directly connected or coupled to another component, or intermediate components may exist. Conversely, when a component is referred to as "directly connected" or "directly coupled" to another component, no intermediate components exist.

[0212] Relative terms such as “below” or “above” or “upper” or “lower” or “top” or “bottom” may be used herein to describe the relationship between one element, layer or region and another element, layer or region as shown in the figures. It should be understood that these terms are intended to cover different orientations of the device other than those depicted in the figures.

[0213] Embodiments of the invention are described herein with reference to cross-sectional views, which are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. For clarity, the thicknesses of layers and regions in the figures may be exaggerated. Furthermore, deviations from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected.

[0214] Some embodiments of the present invention are described with reference to semiconductor layers and / or regions characterized as having a conductivity type such as n-type or p-type, referring to the majority carrier concentration in the layer and / or region. Thus, n-type materials have a majority equilibrium concentration of negatively charged electrons, while p-type materials have a majority equilibrium concentration of positively charged holes. Some materials may be designated with "+" or "-" (e.g., n+, n-, p+, p-, n++, n--, p++, p--, etc.) to indicate a relatively large ("+") or small ("-") majority carrier concentration compared to another layer or region. However, such designation does not imply the presence of a specific concentration of majority or minority carriers in a layer or region.

[0215] Typical embodiments of the invention have been disclosed in the accompanying drawings and description, and although specific terminology has been used, it is used in a general and descriptive sense only and not for the purpose of limitation. The scope of the invention is set forth in the appended claims.

Claims

1. A semiconductor device, comprising: A semiconductor layer structure includes a drift region having a first conductivity type and a trench shielding region having a second conductivity type; as well as Gate trenches extend in the longitudinal direction within the semiconductor layer structure. The trench shielding region extends in the longitudinal direction below the gate trench, and at least a portion of the trench shielding region includes sidewalls that angle inward as the distance from the gate trench increases.

2. The semiconductor device according to claim 1, wherein, The portion of the trench shielding region includes at least the lower half of the trench shielding region.

3. The semiconductor device according to claim 2, wherein, The sidewalls of the portion of the trench shielding region angle inward as the distance from the gate trench increases in a direction perpendicular to the lower surface of the semiconductor layer structure.

4. The semiconductor device according to claim 2 or 3, wherein, The maximum width of the portion of the trench shielding region is less than or equal to the maximum width of the gate trench.

5. The semiconductor device according to any one of the preceding claims, wherein, The semiconductor layer structure further includes a first support shield and a second support shield having the second conductivity type, the first support shield and the second support shield extending in the longitudinal direction on the first side and the second side of the gate trench, respectively.

6. The semiconductor device according to claim 5, wherein, A portion of the drift region is located between the first support shield and the trench shield, and has a width that is substantially constant or increases with increasing depth in the semiconductor layer structure.

7. The semiconductor device according to claim 6, wherein, The width of the portion of the drift region increases with increasing depth in the semiconductor layer structure.

8. The semiconductor device according to claim 5, wherein, The first support shield and the second support shield have corresponding widths, which are substantially constant or decrease as the depth in the semiconductor layer structure increases.

9. The semiconductor device according to claim 5, wherein, The first support shield and the second support shield have corresponding widths, which increase with the increase of depth in the semiconductor layer structure.

10. The semiconductor device according to any one of the preceding claims, wherein, The upper part of the trench shielding region is located between the gate trench and the lower part of the trench shielding region, and has a higher second conductivity type doping concentration than the lower part of the trench shielding region.

11. The semiconductor device according to any one of the preceding claims, further comprising a gate oxide layer and a gate electrode located in the gate trench, wherein the semiconductor layer structure further comprises a well region having the second conductivity type located on the drift region and a source region having the first conductivity type located on the well region.

12. The semiconductor device according to any one of the preceding claims, wherein, The drift region includes silicon carbide.

13. A semiconductor device, comprising: A semiconductor layer structure includes a drift region having a first conductivity type and a trench shielding region having a second conductivity type; as well as Gate trenches extend in the longitudinal direction within the semiconductor layer structure. The trench shielding region extends below the gate trench in the longitudinal direction and includes end walls that are opposite to each other along the longitudinal direction and inclined relative to the lower surface of the semiconductor layer structure.

14. The semiconductor device according to claim 13, wherein, The end walls of the trench shielding region extend substantially parallel to each other.

15. The semiconductor device according to claim 13 or claim 14, wherein, The endwall of the trench shielding region is adjacent to the non-active region of the semiconductor device.

16. The semiconductor device according to any one of claims 13 to 15, wherein, One of the end walls of the trench shielding region extends beyond the end wall of the gate trench in the longitudinal direction.

17. The semiconductor device according to any one of claims 13 to 16, wherein, One of the end walls of the trench shielding region includes a lower portion that does not vertically overlap with the gate trench.

18. A semiconductor device, comprising: A semiconductor layer structure includes a drift region having a first conductivity type and a trench shielding region having a second conductivity type; as well as Gate trenches extend in the longitudinal direction within the semiconductor layer structure. The trench shielding region extends below the gate trench in the longitudinal direction, and the trench shielding region includes an end wall that extends beyond the end wall of the gate trench in the longitudinal direction.

19. The semiconductor device according to claim 18, wherein, The end wall of the trench shielding region is one of a pair of end walls of the trench shielding region, the pair of end walls being opposite each other along the longitudinal direction and inclined relative to the lower surface of the semiconductor layer structure.

20. The semiconductor device according to claim 18 or claim 19, wherein, The end wall of the trench shielding region includes a lower portion that does not vertically overlap with the gate trench.

21. The semiconductor device according to any one of claims 18 to 20, wherein, The endwall of the trench shielding region is adjacent to the non-active region of the semiconductor device.

22. The semiconductor device according to any one of claims 18 to 21, wherein, The endwall of the trench shielding region is inclined relative to the lower surface of the semiconductor layer structure.

23. A semiconductor device, comprising: A semiconductor layer structure includes a drift region having a first conductivity type and a trench shielding region having a second conductivity type; as well as Gate trenches extend in the longitudinal direction within the semiconductor layer structure. The trench shielding region extends in the longitudinal direction below the gate trench, and the average width of the upper half of the trench shielding region is greater than the average width of the lower half of the trench shielding region.

24. The semiconductor device according to claim 23, wherein, The upper part of the trench shielding region is located between the gate trench and the lower part of the trench shielding region, and has a higher second conductivity type doping concentration than the lower part of the trench shielding region.

25. The semiconductor device according to claim 23 or claim 24, wherein, The semiconductor layer structure further includes a first support shield and a second support shield, the first support shield and the second support shield having the second conductivity type and extending in the longitudinal direction on the first side and the second side of the gate trench, respectively.

26. The semiconductor device according to any one of claims 23 to 25, wherein, At least a portion of the trench shielding region includes sidewalls that angle inwards with increasing distance from the gate trench.

27. A semiconductor device, comprising: A semiconductor layer structure includes a drift region having a first conductivity type and a trench shielding region having a second conductivity type; as well as Gate trenches extend in the longitudinal direction within the semiconductor layer structure. The trench shielding region extends below the gate trench in the longitudinal direction and includes an end wall extending along the crystal axis of the semiconductor layer structure.

28. The semiconductor device according to claim 27, wherein, The crystal axis is one of the following crystal axes: <11-23>, <-1-123>, <1-213>, <-12-13>, <2-1-13>, or <-2113>.

29. The semiconductor device according to claim 27, wherein, The crystal axis is <0001> Crystal axis.

30. The semiconductor device according to any one of claims 27 to 29, wherein, The trench shielding region extends into the drift region, and the drift region comprises silicon carbide.

31. A semiconductor device, comprising: A semiconductor layer structure includes a drift region having a first conductivity type and a trench shielding region having a second conductivity type; as well as A gate trench extends longitudinally within the semiconductor layer structure over the trench shielding region. The trench shielding region extends below the gate trench into the drift region to provide a superjunction structure in the drift region.

32. The semiconductor device according to claim 31, wherein, At least a portion of the trench shielding region includes sidewalls that angle inwards with increasing distance from the gate trench.

33. The semiconductor device according to claim 31, wherein, At least a portion of the trench shielding region includes sidewalls that extend substantially perpendicular to the lower surface of the semiconductor layer structure as the distance from the gate trench increases.

34. The semiconductor device according to any one of claims 31 to 33, wherein, The upper part of the trench shielding region is located between the gate trench and the lower part of the trench shielding region, and has a higher second conductivity type doping concentration than the lower part of the trench shielding region.

35. The semiconductor device according to any one of claims 31 to 34, wherein, The trench shielding region extends from the bottom surface of the gate trench to a depth of at least 4 micrometers in the drift region.

36. A semiconductor device, comprising: A semiconductor layer structure includes a drift region having a first conductivity type and a trench shielding region having a second conductivity type; as well as Gate trenches extend in the longitudinal direction within the semiconductor layer structure. The trench shielding region extends below the gate trench in the longitudinal direction, and at least a portion of the trench shielding region includes sidewalls that extend substantially perpendicular to the lower surface of the semiconductor layer structure as the distance from the gate trench increases.

37. The semiconductor device of claim 36, wherein, The trench shielding region also includes end walls that are opposite to each other in the longitudinal direction and inclined relative to the lower surface of the semiconductor layer structure.

38. The semiconductor device according to claim 36 or claim 37, wherein, The upper part of the trench shielding region is located between the gate trench and the lower part of the trench shielding region, and has a higher second conductivity type doping concentration than the lower part of the trench shielding region.

39. A method of manufacturing a semiconductor device, the method comprising: A semiconductor layer structure including a drift region having a first conductivity type is provided; A gate trench extending in the longitudinal direction is formed in the semiconductor layer structure; as well as A trench shielding region is formed by implanting a dopant of a second conductivity type into the semiconductor layer structure using a trench ion implantation process. The trench shielding region extends in the longitudinal direction below the gate trench.

40. The method according to claim 39, wherein, The channel ion implantation process is performed along the crystal axis of the semiconductor layer structure.

41. The method according to claim 40, wherein, The drift region comprises silicon carbide, and the crystal axis is <0001> One of the crystal axes: <11-23>, <-1-123>, <1-213>, <-12-13>, <2-1-13>, <-2113>, or <11-20>.

42. The method according to any one of claims 39 to 41, wherein, The trench shielding region is formed after the gate trench.

43. The method according to claim 42, wherein, The trench shielding region is formed by injecting a dopant of the second conductivity type into the gate trench.

44. The method according to any one of claims 39 to 41, wherein, The trench shielding region is formed before the gate trench.

45. The method according to any one of claims 39 to 44, further comprising forming a well region on the drift region by implanting a second conductivity type dopant into the semiconductor layer structure using a channel ion implantation process.

46. ​​The method according to claim 45, wherein, The trap region and the trench shielding region are formed simultaneously using the same channel ion implantation process.

47. The method according to any one of claims 39 to 46, further comprising implanting a second conductivity type dopant into the upper part of the trench shielding region using a random ion implantation process.

48. The method according to claim 47, wherein, The upper part of the trench shielding region has a higher second conductivity type doping concentration than the lower part of the trench shielding region.

49. The method according to any one of claims 39 to 48, further comprising: A first support shield and a second support shield are formed by implanting a second type of conductivity dopant into the semiconductor layer structure using a channel ion implantation process. The first support shield and the second support shield extend in the longitudinal direction on the first side and the second side of the gate trench, respectively.

50. The method according to any one of claims 39 to 48, further comprising: A first support shield and a second support shield are formed by implanting a second conductivity type dopant into the semiconductor layer structure using a random ion implantation process. The first support shield and the second support shield extend in the longitudinal direction on the first side and the second side of the gate trench, respectively.

51. A method of manufacturing a semiconductor device, the method comprising: A semiconductor layer structure including a drift region having a first conductivity type is provided; A gate trench extending in the longitudinal direction is formed in the semiconductor layer structure; as well as A well region and a trench shielding region are simultaneously formed by implanting a second type of conductivity dopant into the semiconductor layer structure using a channel ion implantation process. The well region is located on the drift region, and the trench shielding region extends in the longitudinal direction below the gate trench.

52. A method of manufacturing a semiconductor device, the method comprising: A semiconductor layer structure including a drift region having a first conductivity type is provided; A gate trench extending in the longitudinal direction is formed in the semiconductor layer structure; as well as A trench shielding region is formed by implanting a second conductivity type dopant into the semiconductor layer structure using both channel ion implantation and random ion implantation processes. The trench shielding region extends in the longitudinal direction below the gate trench.

53. The method according to claim 52, wherein, After forming the trench shielding region using both the channel ion implantation process and the random ion implantation process, the upper part of the trench shielding region has a higher second conductivity type doping concentration than the lower part of the trench shielding region.

54. A method of manufacturing a semiconductor device, the method comprising: A semiconductor layer structure including a drift region having a first conductivity type is provided; A gate trench extending in the longitudinal direction is formed in the semiconductor layer structure; as well as A trench shielding region is formed by implanting a dopant of a second conductivity type into the gate trench, such that the trench shielding region is aligned with the gate trench in the longitudinal direction. The trench shielding region extends below the gate trench into the drift region to provide a superjunction structure in the drift region.

55. The method according to claim 54, wherein, Forming the trench shielding region includes performing a trench ion implantation process.

56. The method according to claim 54, wherein, The formation of the trench shielding region includes both channel ion implantation and random ion implantation processes.

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