Semiconductor device

Abstract

A semiconductor device includes first and second semiconductor chips. A first circuit of the first semiconductor chip includes a first power supply line, a second power supply line, a signal line connected to a second circuit of the second semiconductor chip, and a plurality of first transistors arranged between one of the first or second power supply lines and the signal line. The plurality of first transistors are arranged with the first source electrodes adjacent to each other and the drain electrodes adjacent to each other in plan view. By appropriately arranging circuit elements included in a circuit for transmitting or receiving a signal between the semiconductor chips, it is possible to suppress a decrease in characteristics of the semiconductor device.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device. Background Technology

[0002] Semiconductor devices with multiple semiconductor chips mounted on a substrate and semiconductor devices with multiple semiconductor chips stacked on top of each other are known. In such semiconductor devices, signals are sometimes transmitted and received between the multiple semiconductor chips. In addition, semiconductor chips with I / O (Input / Output) circuits for transmitting and receiving signals with external devices are also known.

[0003] <Prior art documents>

[0004] <Patent Documents>

[0005] Patent Document 1: US Patent No. 11024625

[0006] Patent Document 2: US Patent No. 10332871

[0007] Patent Document 3: U.S. Patent Application Publication No. 2023 / 0260987

[0008] Patent Document 4: U.S. Patent Application Publication No. 2023 / 0076856

[0009] Patent Document 5: US Patent No. 10,411,095 Summary of the Invention

[0010] <Problem to be solved by this invention>

[0011] There has not been sufficient research on how to construct I / O circuits for transmitting and receiving signals between multiple semiconductor chips mounted on a semiconductor device.

[0012] In view of the above-mentioned problems, the present invention aims to suppress the degradation of the characteristics of a semiconductor device by appropriately configuring the circuit elements included in the circuit for transmitting or receiving signals between the semiconductor chips in a semiconductor device in which multiple semiconductor chips are mounted.

[0013] <Methods for solving problems>

[0014] In one embodiment of the present invention, a semiconductor device includes: a first semiconductor chip having a first circuit; and a second semiconductor chip having a second circuit connected to the first circuit. The first circuit includes a first power line, a second power line, a signal line connected to the second circuit, and a plurality of first transistors each having a first source and a first drain. The plurality of first transistors, in plan view, are disposed between one of the first power line or the second power line and the signal line. In plan view, the first source of one first transistor is adjacent to the first source of another first transistor, and the first drain of one first transistor is adjacent to the first drain of another first transistor.

[0015] <The Effects of the Invention>

[0016] According to the technology disclosed herein, in a semiconductor device in which multiple semiconductor chips are mounted, the circuit elements included in the circuit for transmitting or receiving signals between the semiconductor chips can be appropriately configured to suppress the degradation of the semiconductor device's characteristics. Attached Figure Description

[0017] Figure 1 This shows the application. Figure 2 Cross-sectional views of examples of semiconductor devices in various embodiments thereafter.

[0018] Figure 2 It is shown in Figure 3 Explanatory diagrams of the circuit elements used in the circuit plan diagrams shown below.

[0019] Figure 3 This is a plan view showing an example of the circuit layout of the output circuit formed in the semiconductor device according to the first embodiment.

[0020] Figure 4 This is a plan view showing an example of the circuit layout of the input circuit of the semiconductor device in the first embodiment.

[0021] Figure 5 This is a plan view showing a first variation of the circuit layout of the output circuit of the semiconductor device in the first embodiment.

[0022] Figure 6 This is a plan view showing a second variation of the circuit layout of the output circuit of the semiconductor device in the first embodiment.

[0023] Figure 7 This is a plan view showing a third variation of the circuit layout of the output circuit of the semiconductor device in the first embodiment.

[0024] Figure 8This is a plan view of a fourth variation showing the circuit layout of the output circuit of the semiconductor device in the first embodiment.

[0025] Figure 9 This is a top view showing an example of the circuit layout of the output circuit of the semiconductor device in the second embodiment.

[0026] Figure 10 It shows along Figure 9 A cross-sectional view of an example of the Y1-Y1' line.

[0027] Figure 11 It is shown Figure 9 A top view of an example of a diode layout.

[0028] Figure 12 This is a top view showing a first variation of the circuit layout of the output circuit of the semiconductor device in the second embodiment.

[0029] Figure 13 This is a top view showing a second variation of the circuit layout of the output circuit of the semiconductor device in the second embodiment.

[0030] Figure 14 This is a top view showing an example of the circuit layout of the input circuit of the semiconductor device in the second embodiment.

[0031] Figure 15 This is a top view showing a third variation of the circuit layout of the output circuit of the semiconductor device in the second embodiment.

[0032] Figure 16 This is a top view showing a fourth variation of the circuit layout of the output circuit of the semiconductor device in the second embodiment.

[0033] Figure 17 This is a top view showing an example of the circuit layout of the output circuit of the semiconductor device in the third embodiment.

[0034] Figure 18 It shows along Figure 17 A cross-sectional view of an example of the Y2-Y2' line in the diagram.

[0035] Figure 19 It is shown Figure 17 A top view of an example layout of the resistive elements.

[0036] Figure 20 This is a top view showing a first variation of the circuit layout of the output circuit of the semiconductor device in the third embodiment.

[0037] Figure 21 It is shown Figure 20A cross-sectional view of an example of a section along line Y3-Y3'.

[0038] Figure 22 This is a top view showing a second variation of the circuit layout of the output circuit of the semiconductor device in the third embodiment.

[0039] Figure 23 This is a top view showing a third variation of the circuit layout of the output circuit of the semiconductor device in the third embodiment.

[0040] Figure 24 This is a top view showing an example of the circuit layout of the output circuit of the semiconductor device in the fourth embodiment.

[0041] Figure 25 This is a top view showing an example of the circuit layout of the input circuit of the semiconductor device in the fourth embodiment.

[0042] Figure 26 This is a diagram illustrating an example of the circuit structure of the output circuit of the semiconductor device in the fifth embodiment.

[0043] Figure 27 This is a diagram illustrating another example of the circuit structure of the output circuit of the semiconductor device in the fifth embodiment. Detailed Implementation

[0044] Hereinafter, embodiments will be described using the accompanying drawings. The symbols representing signals will also be used to represent signal lines or signal terminals. The symbols representing power supply potential will also be used to represent power lines or power terminals to which power supply potential is supplied.

[0045] (First Embodiment)

[0046] Figure 1 Show application Figure 2 Examples of cross-sectional views of semiconductor devices SEM1 and SEM2 according to various embodiments described below. Semiconductor device SEM1 includes a wiring substrate such as an inserter INTP, and chips CP1 and CP2 mounted on the inserter INTP. Each chip CP1 and CP2 is electrically connected to the inserter INTP via a bump BMP.

[0047] The inserter INTP has an external connection terminal EXT and wiring W for connecting the external connection terminal EXT to the bump BMP. Additionally, the inserter INTP also has wiring W for connecting multiple bump BMPs to each other. For example, the external connection terminal EXT can include a signal terminal SIG and a power terminal VDD1 for chip CP1, a signal terminal OUT2 and a power terminal VDD2 for chip CP2, and a ground terminal VSS shared by chips CP1 and CP2. The inserter INTP can be formed of silicon, organic materials, or other materials.

[0048] For example, chip CP1 has an input / output circuit IOC1 with an output terminal OUT1, and chip CP2 has an input / output circuit IOC2 with an input terminal IN2. The output terminal OUT1 of input / output circuit IOC1 is electrically connected to the input terminal IN2 of input / output circuit IOC2 via a bump BMP, wiring W within the inserter INTP, and the bump BMP. Furthermore, chips CP1 and CP2 receive and transmit signals through input / output circuits IOC1 and IOC2. This interconnection of two chips CP1 and CP2 in a semiconductor device is sometimes referred to as Die to Die (D2D).

[0049] in addition, Figure 1 This diagram illustrates an input / output circuit IOC1 as an output circuit and IOC2 as an input circuit, but it's also possible for IOC1 to be an input circuit and IOC2 to be an output circuit. Furthermore, input / output circuits IOC1 and IOC2 can each have both input and output circuits.

[0050] Semiconductor device SEM2 includes a wiring substrate such as an inserter INTP and chips CP1 and CP2 stacked on the inserter INTP. Chip CP1 is electrically connected to the inserter INTP via a bump BMP. The inserter INTP has an external connection terminal EXT and wiring W for connecting the external connection terminal EXT to the bump BMP. For example, as the external connection terminal EXT, a signal terminal IN1, a power supply terminal VDD1, and a ground terminal VSS can be provided electrically connected to chip CP1. Hereinafter, without distinguishing between semiconductor devices SEM1 and SEM2, they will also be referred to as semiconductor device SEM.

[0051] Chip CP2 is connected to chip CP1 via a via (Through Silicon Via), and the power supply terminal VDD1 and ground terminal VSS are also electrically connected to chip CP2 through chip CP1. Chip CP1 has an input / output circuit IOC1, and chip CP2 has an input / output circuit IOC2, which is connected to the input / output circuit IOC1 via a via VIA. Furthermore, chips CP1 and CP2 transmit and receive signals through the input / output circuits IOC1 and IOC2.

[0052] Chip CP1 is an example of either the first or second semiconductor chip, and chip CP2 is an example of the other semiconductor chip. Input / output circuit IOC1 is an example of either the first or second circuit, and input / output circuit IOC2 is an example of the other circuit. Ground line VSS is an example of either the first or second power supply line, and power supply line VDD is an example of the other power supply line.

[0053] Alternatively, chips CP1 and CP2 can also be configured so that input / output circuits IOC1 and IOC2 are relatively aligned. In this case, input / output circuits IOC1 and IOC2 can be interconnected via bumps or similar means.

[0054] Figure 2 Shown in Figure 3 The following diagrams illustrate the circuit elements used in the circuit plan. The symbol "diff" marked on the white circle (VIA) indicates either an N-type semiconductor layer (Ndiff, N-type impurity region) or a P-type semiconductor layer (Pdiff, P-type impurity region). Figure 3 In the circuit layout shown below, various vias are hidden in the upper wiring when viewed from above, but are shown on the wiring for easy viewing.

[0055] Figure 3 An example of the circuit layout of the output circuit OUTC formed in the semiconductor device SEM of the first embodiment is shown. The output circuit OUTC is included in Figure 1 The input / output circuit IOC1 of chip CP1 or the input / output circuit IOC2 of chip CP2 is included. When the input / output circuits IOC1 and IOC2 have signal transmission and reception functions, the output circuit OUTC can be included in either input / output circuits IOC1 or IOC2.

[0056] Referring to the circuit diagram, the output circuit OUTC includes an output transistor OTR and a protection circuit ESDC to protect the components from ESD (Electro-Static Discharge). For example, the output transistor OTR has a CMOS (Complementary Metal Oxide Semiconductor) inverter, which includes an NMOS transistor TN1 and a PMOS transistor TP1.

[0057] In NMOS transistor TN1, the source is connected to ground (VSS), the drain is connected to pad (Pad), and the gate (GT) is connected to the internal signal line (OUT). In PMOS transistor TP1, the source is connected to power supply (VDD), the drain is connected to pad (Pad) for the signal line, and the gate (GT) is connected to the internal signal line (OUT).

[0058] Hereinafter, NMOS transistor TN1 and PMOS transistor TP1 can be simply referred to as transistor TN1 and TP1, respectively, and gate GT can be simply referred to as gate GT. In addition, output transistor OTR can also be a tri-state buffer.

[0059] The protection circuit ESDC has diodes D1a and D1b connected in series between the ground line VSS and the power line VDD. The signal pads are connected to the output of the CMOS inverter, the cathode of diode D1a, and the anode of diode D1b. The pads are electrically connected via signal lines to the input circuit formed in the input / output circuit IOC1 of another chip CP1, or the input / output circuit formed in the input / output circuit IOC2 of chip CP2, which is connected to the output circuit OUTC. Furthermore, the output circuit OUTC outputs the output signal to the input circuit of another chip CP1 or another chip CP2 via the pads. Hereinafter, the wiring connected to the pads is also referred to as pad wiring.

[0060] Referring to the layout diagram, transistors TN1 and TP1 are arranged along the Y direction. Each transistor TN1 and TP1 is divided into multiple local transistors arranged along the X direction. Hereinafter, the local transistor contained in transistor TN1 is referred to as local transistor TN1, and the local transistor contained in transistor TP1 is referred to as local transistor TP1. Local transistor TN1 is an example of either the first transistor or the second transistor, and local transistor TP1 is an example of either the first transistor or the second transistor.

[0061] The source of each local transistor TN1 is connected to the ground line VSS of the wiring layer M2 via via VIA (diff-M1), wiring W1 of the wiring layer M1, and via VIA (M1-M2). The source of each local transistor TN1 is connected to the pad wiring Pad of the wiring layer M2 via via VIA (diff-M1), wiring W1 of the wiring layer M1, and via VIA (M1-M2).

[0062] The source of each local transistor TP1 is connected to the power line VDD of the wiring layer M2 via via VIA (diff-M1), wiring W1 of the wiring layer M1, and via VIA (M1-M2). The source of each local transistor TP1 is connected to the pad wiring Pad of the wiring layer M2 via via VIA (diff-M1), wiring W1 of the wiring layer M1, and via VIA (M1-M2).

[0063] Here, diodes D1a and D1b shown in the circuit diagram are positioned in an area not shown in the layout diagram. Additionally, the ground line VSS, power line VDD, and pad wiring are connected to the ground terminal VSS, power terminal VDD, and pad wiring respectively via vias (not shown) and upper-layer wiring. The gates GT of each local transistor TN1 and TP1 are connected to vias (not shown) and upper-layer wiring.

[0064] A pair of adjacent local transistors TN1 are configured such that their drain or source regions are adjacent in the X direction. Similarly, a pair of adjacent local transistors TP1 are configured such that their drain or source regions are adjacent in the X direction. That is, in the multiple local transistors TN1 and TP1, respectively, the drain regions opposite each other in the X direction are separated, and the source regions opposite each other in the X direction are separated.

[0065] By separating the drain region and the source region, the effect of localized heating of transistor TN1 on the adjacent localized transistor TN1 can be suppressed. Similarly, the effect of localized heating of transistor TP1 on the adjacent localized transistor TP1 can be suppressed. Thus, the localized temperature rise during the driving of transistors TN1 and TP1 can be suppressed.

[0066] Furthermore, in the Die-to-Die configuration, the signal lines connected between chips CP1 and CP2 are not electrically connected to the external terminals of the semiconductor device (SEM), thus eliminating the need for latch-up protection. Therefore, for example, protection against output transistor OTR can be omitted, or the layout area can be reduced. Additionally, in Figure 3 In subsequent circuit layouts, one or both of the power line VDD and the ground line VSS can be configured above the area forming transistors TN1 and TP1.

[0067] Figure 4An example of the circuit layout of the input circuit INC of the semiconductor device SEM according to the first embodiment is shown. For comparison with... Figure 3 Identical elements are labeled with the same symbols, and detailed descriptions are omitted. The input circuit INC is included. Figure 1 The input / output circuit IOC1 of chip CP1 or the input / output circuit IOC2 of chip CP2. When the input / output circuits IOC1 and IOC2 have signal transmission and reception functions, the input circuit INC can be included in both input / output circuits IOC1 and IOC2.

[0068] Referring to the circuit diagram, the input circuit INC includes the input transistor INR and the protection circuit ESDC. For example, the input transistor INR is a CMOS inverter. The source of transistor NP1 in the input transistor INR is connected to ground (VSS), the drain is connected to the internal signal line IN, and the gate GT is connected to the pad. The source of transistor TP1 in the input transistor INR is connected to the power supply line VDD, the drain is connected to the internal signal line IN, and the gate GT is connected to the pad.

[0069] The pad is electrically connected to the input / output circuit IOC1 of another chip CP1, which is connected to the input circuit INC, to form an output circuit, or to the input / output circuit IOC2 of chip CP2. Furthermore, the input circuit INC receives input signals from the output circuit of another chip CP1 or another chip CP2 via the pad.

[0070] The layout of the input circuit INC, except that the pads are connected to the gates GT of each local transistor TN1 and TP1, is otherwise connected to the drain via the pads. Figure 3 The layout of the output circuit is the same. That is, in the input circuit INC, in the multiple local transistors TN1, the drain regions opposite each other in the X direction are separated, and the source regions opposite each other in the X direction are separated. In the multiple local transistors TP1, the drain regions opposite each other in the X direction are separated, and the source regions opposite each other in the X direction are separated.

[0071] Therefore, in the input circuit INC, the effect of the heating of local transistor TN1 on the adjacent local transistor TN1 can be suppressed, and the effect of the heating of local transistor TP1 on the adjacent local transistor TN1 can also be suppressed. Thus, the rise in local temperature during the driving of transistors TN1 and TP1 can be suppressed.

[0072] Furthermore, the layout of the input circuit INC and the output circuit OUTC is identical, except for the connection targets of the pad routing. Therefore... Figure 5The layout of the output circuit OUTC shown below can also be applied to the input circuit INC. Similarly, Figure 5 The layout of the input circuit INC shown below can also be applied to the output circuit OUTC.

[0073] Figure 5 This is a first variation of the circuit layout of the output circuit OUTC of the semiconductor device SEM in the first embodiment. For... Figure 3 Identical elements are labeled with the same symbols, and detailed descriptions are omitted. In the layout diagram, the sources (Ndiff) of a pair of centrally located local transistors TN1, arranged along the X direction, are shared and connected to the ground line VSS via a common wiring W1 of wiring layer M1. The sources (Pdiff) of a pair of centrally located local transistors TP1, arranged along the X direction, are shared and connected to the power line VDD via a common wiring W1 of wiring layer M1. Other layouts are similar. Figure 3 same.

[0074] By sharing the sources of adjacent local transistors TN1 and TP1, the area of ​​the output transistor OUTC can be made smaller than that of the other transistors. Figure 3 The area of ​​the output circuit OUTC. Additionally, the source of the transistor is electrically connected to the back gate of the transistor and electrically disconnected from the node of the pad; therefore, the parasitic capacitance associated with the node of the pad does not change.

[0075] On the other hand, the heat generated by the multiple local transistors TN1 sharing the semiconductor layer Ndiff is transferred to each other, and the heat generated by the local transistors TP1 sharing the semiconductor layer Pdiff is transferred to each other. However, when the temperature rise caused by the operation of the output circuit OUTC is suppressed below the upper limit of the temperature specification of the semiconductor device SEM (e.g., when the operation frequency of the output circuit OUTC is low), there is no problem even if the source region is shared.

[0076] Figure 6 A second variation of the circuit layout of the output circuit OUTC of the semiconductor device SEM according to the first embodiment is shown. Figures 3 to 5 The layout of a planar transistor is shown. Figure 6 These are FinFETs (Field Effect Transistors) or nanosheet transistors. Therefore, the source and drain of local transistor TN1 are interconnected via fins (FIN) or nanosheets (NS), and a channel is formed by the fins (FIN) or nanosheets (NS) within the gate GT. Similarly, the source and drain of local transistor TP1 are interconnected via fins (FIN) or nanosheets (NS), and a channel is formed by the fins (FIN) or nanosheets (NS) within the gate GT.

[0077] In addition, Figure 6In this embodiment, local transistors TN1 and TP1 have four fins (FIN) or nanosheets (NS) arranged along the Y direction, but there can be one or more fins beyond four. In other embodiments or variations, FinFETs or nanosheet transistors can be used instead of planar transistors, but in this case, local transistors TN1 and TP1 also have more than one fin (FIN) or nanosheet (NS). Furthermore, in the case of FinFETs or nanosheet transistors, the wiring connecting the source and drain is also referred to as local wiring.

[0078] Figure 7 A third variation of the circuit layout of the output circuit OUTC of the semiconductor device SEM according to the first embodiment is shown. For... Figure 3 The same elements are labeled with the same symbols, and detailed descriptions are omitted. Figure 7 The output transistor OTR of the output circuit OUTC shown in the circuit diagram includes cascaded NMOS transistors TN1 and TN2 and cascaded PMOS transistors TP1 and TP2. The circuit structure other than the transistors is similar to... Figure 3 The output circuit OUTC shown is the same.

[0079] Hereinafter, NMOS transistors TN1 and TN2 and PMOS transistors TP1 and TP2 will be referred to as transistors TN1 and TN2 and transistors TP1 and TP2, respectively. In addition, a portion of NMOS transistors TN1 and TP2 and a portion of PMOS transistors TP1 and TP2 will be referred to as local transistors TN1 and TN2 and local transistors TP1 and TP2, respectively.

[0080] Referring to the layout diagram, four pairs of cascaded local transistors TN1 and TN2 are arranged along the X direction, and each pair of local transistors TN1 and TN2 is arranged along the Y direction. Similarly, four pairs of cascaded local transistors TP1 and TP2 are arranged along the X direction, and each pair of local transistors TP1 and TP2 is arranged along the Y direction.

[0081] Two adjacent pairs of local transistors TN1 and TN2 are configured such that their drain regions face each other in the X direction, and their source regions face each other in the X direction. Similarly, two adjacent pairs of local transistors TP1 and TP2 are configured such that their drain regions face each other in the X direction, or their source regions face each other in the X direction. Therefore, as... Figure 3 As shown, the effect of localized heating of transistors TN1 and TN2 on the adjacent localized transistors TN1 and TN2 can be suppressed. Similarly, the effect of localized heating of transistors TP1 and TP2 on the adjacent localized transistors TP1 and TP2 can be suppressed. Thus, the rise in local temperature during the operation of transistors TN1 and TP1 can be suppressed.

[0082] Figure 8 A fourth variation of the circuit layout of the output circuit OUTC of the semiconductor device SEM according to the first embodiment is shown. For... Figure 3 The same elements are labeled with the same symbols, and detailed descriptions are omitted. Figure 8 In the output circuit OUTC shown, as follows Figure 7 As shown, the output transistor OTR includes cascaded NMOS local transistors TN1 and TN2 and cascaded PMOS local transistors TP1 and TP2.

[0083] In addition, Figure 8 In the output circuit OUTC shown, and Figure 5 Similarly, the drains (semiconductor layer Ndiff) of the centrally located paired local transistors TN1 arranged along the X direction are shared, and the drains (semiconductor layer Ndiff) of the centrally located paired local transistors TN2 arranged along the X direction are shared. Likewise, the drains (semiconductor layer Pdiff) of the centrally located paired local transistors TP1 arranged along the X direction are shared, and the sources (semiconductor layer Pdiff) of the centrally located paired local transistors TP2 arranged along the X direction are shared.

[0084] The intermediate node (semiconductor layer Ndiff) used to connect transistors TN1 and TN2 is configured with two local transistors TN1 arranged along the X direction in an adjacent configuration, and two local transistors TN2 arranged along the X direction in an adjacent configuration. The intermediate node of local transistor TN1 is connected to the intermediate node of local transistor TN2 using a via VIA (Ndiff-M1) and wiring W1 of wiring layer M1.

[0085] Similarly, the intermediate node (semiconductor layer Pdiff) used to connect transistors TP1 and TP2 is configured with two local transistors TP1 arranged along the X direction in an adjacent configuration, and two local transistors TP2 arranged along the X direction in an adjacent configuration. The intermediate node of local transistor TP1 is connected to the intermediate node of local transistor TP2 using a via VIA (Ndiff-M1) and wiring W1 of wiring layer M1.

[0086] Furthermore, in Figure 8In this configuration, the cascaded transistor pair consisting of paired local transistors TN1 and TN2, each with shared source and drain, is positioned only at the center in the X direction. However, two cascaded transistor pairs consisting of TN1 and TN2 can also be arranged along the X direction. Similarly, two cascaded transistor pairs consisting of TP1 and TP2 can also be arranged along the X direction. Furthermore, Figure 7 and Figure 8 The circuit layout of the cascaded transistors shown can also be applied to Figure 9 The circuit layout shown below.

[0087] In the first embodiment, transistor TN1 is configured such that the drain and source regions of a plurality of local transistors TN1 arranged along the X direction are adjacent to each other, and transistor TP1 is configured such that the drain and source regions of a plurality of local transistors TP1 arranged along the X direction are adjacent to each other.

[0088] Therefore, the effect of localized heating of transistor TN1 on the adjacent localized transistor TN1 can be suppressed. Similarly, the effect of localized heating of transistor TP1 on the adjacent localized transistor TP1 can be suppressed. As a result, the localized temperature rise during the operation of transistors TN1 and TP1 can be suppressed, thereby suppressing the degradation of the characteristics of the semiconductor device SEM.

[0089] For example, when semiconductor chips CP1 and CP2 are stacked on a semiconductor device SEM, the stacking may reduce the overall heat dissipation performance of the SEM. However, by suppressing localized temperature rises, the degradation of the SEM's characteristics can be suppressed even with reduced heat dissipation performance.

[0090] (Second Implementation)

[0091] Figure 9 An example of the circuit layout of the output circuit OUTC of the semiconductor device SEM according to the second embodiment is shown. For comparison with... Figure 3 The same elements are labeled with the same symbols, and detailed descriptions are omitted. Figure 9 The circuit layout shown includes diodes D1a and D1b, and the others are similar to those shown. Figure 3 The circuit layout shown is the same.

[0092] Diode D1a is disposed between the pad wiring and transistor TN1, and diode D1b is disposed between the pad wiring and transistor TP1. Diodes D1a and D1b each have an elongated shape extending along the X direction. Diode D1a is an example of either a first diode or a second diode, and diode D1b is an example of either a first diode or a second diode.

[0093] The semiconductor layer Pdiff (anode) of diode D1a is connected to the source of local transistor TN1 via via VIA (diff-M1) and wiring W1 of wiring layer M1, and is connected to the ground line VSS of wiring layer M2 via via VIA (M1-M2). The semiconductor layer Ndiff (cathode) of diode D1a is connected to the drain of local transistor TN1 via via VIA (diff-M1) and wiring W1 of wiring layer M1, and is connected to the pad wiring Pad of wiring layer M2 via via VIA (M1-M2).

[0094] The semiconductor layer Ndiff (cathode) of diode D1b is connected to the source of local transistor TP1 via via VIA (diff-M1) and wiring W1 of wiring layer M1, and is connected to the power line VDD via via VIA (M1-M2). The semiconductor layer Pdiff (anode) of diode D1b is connected to the drain of local transistor TP1 via via VIA (diff-M1) and wiring W1 of wiring layer M1, and is connected to the pad wiring Pad of wiring layer M2 via via VIA (M1-M2). Here, one or both of the power line VDD and the ground line VSS can be arranged on the area forming transistors TN1 and TP1 or on the area forming diodes D1a and D1b.

[0095] like Figure 1 As shown, in the die-to-die output circuit OUTC where the signal lines connected between chips CP1 and CP2 are not electrically connected to the external terminals of the semiconductor device SEM, the capability (size) of the protection circuit ESDC can be reduced compared to a chip that outputs signals to the external terminals of the semiconductor device SEM. Therefore, as Figure 9 As shown, compared to the layout area of ​​the diodes mounted on the protection circuit ESDC used for outputting signals to external terminals, the layout area of ​​diodes D1a and D1b, which function as the protection circuit ESDC, can be reduced. As a result, the output transistor OTR and the protection circuit ESDC can be configured more efficiently.

[0096] By setting diodes D1a and D1b to be elongated shapes extending along the X direction, it is possible to suppress the increase in the distance from the pad wiring to each transistor TN1 and TP1, thereby suppressing the increase in parasitic capacitance of the pad wiring.

[0097] Figure 10 Show along Figure 9 An example of a cross-section of the Y1 to Y1' lines. For example, the semiconductor layer Ndiff of transistor TN1, the semiconductor layer Ndiff of diode D1a, the semiconductor layer Pdiff of diode D1b, and the semiconductor layer Pdiff of transistor TP1, formed in the P-type substrate SUB, are connected to wiring W1 via vias VIA. The semiconductor layers Pdiff of each diode D1a and Ndiff of each diode D1b are connected via the P-type substrate SUB to form a P / N junction. Furthermore, the semiconductor layer Pdiff of transistor TP1 is connected to the substrate SUB via the N-type well region NW. Wiring W1 is connected to the upper wiring pad Pad via vias VIA.

[0098] in addition, Figure 10 An example of a manufacturing process using planar transistors is shown, but as... Figure 10 As shown on the lower side, a FinFET manufacturing process can also be used. In this case, fins (FIN) of semiconductor material protruding from the substrate SUB are used to form transistors TN1, TP1 and diodes D1a, D1b. Local wiring LI formed on the fins (FIN) is connected to wiring W1 via vias (VIA) and, furthermore, to the upper wiring pad (Pad) via vias (VIA). Local wiring LI is formed using a wiring layer between the substrate SUB and wiring W1 of wiring layer M1.

[0099] Figure 11 Show Figure 9 An example of the layout of diodes D1a and D1b is shown. (Refer to...) Figure 10 As described above, each diode D1a, D1b, for example, has a P / N junction formed between a P-type semiconductor layer Pdiff and an N-type semiconductor layer Ndiff via a P-type substrate SUB. Figure 9 An example is shown where diodes D1a and D1b are formed extending in the X direction, but diodes D1a and D1b extending in the Y direction can also be formed.

[0100] Alternatively, the FinFET manufacturing process can be used to form diodes D1a and D1b. In this case, due to the manufacturing limitation that the gate GT is included in diodes D1a and D1b, the extension direction of the fins FIN and the arrangement direction of the gate GT must be aligned with the arrangement direction of the FinFET.

[0101] Figure 12 This is a first variation of the circuit layout of the output circuit OUTC of the semiconductor device SEM according to the second embodiment. For... Figure 3 and Figure 9The same elements are labeled with the same symbols, and detailed descriptions are omitted. Figure 12 The circuit layout shown, except that in top view, a portion of diodes D1a and D1b is configured to overlap with the pad wiring, is otherwise consistent with... Figure 9 The circuit layout shown is the same. Alternatively, if the width of the pad in the Y direction is large, the entire area of ​​diodes D1a and D1b arranged along the Y direction can be placed at the position overlapping with the pad.

[0102] By overlapping diodes D1a and D1b with the pad wiring in a top-down view, and compared with Figure 9 Compared to other methods, this allows for a smaller layout area for the output circuit (OUTC), enabling more efficient configuration of the output transistor (OTR) and protection circuit (ESDC). Furthermore, it reduces the distance from the pad wiring to each transistor (TN1, TP1) compared to other methods. Figure 9 Smaller capacitance, thus further suppressing the increase of parasitic capacitance in pad wiring.

[0103] Figure 13 This is a second variation of the circuit layout of the output circuit OUTC of the semiconductor device SEM in the second embodiment. For... Figure 3 and Figure 9 The same elements are labeled with the same symbols, and detailed descriptions are omitted. Figure 13 The circuit layout shown, except that diodes D1a and D1b are arranged along the X direction and, when viewed from above, are positioned to overlap with the pad wiring, is otherwise identical to... Figure 9 The circuit layout shown is the same.

[0104] By ensuring that diodes D1a and D1b completely overlap with the pad wiring when viewed from above, the layout area of ​​diodes D1a and D1b can be made practically zero. The result is similar to... Figure 12 Compared to other methods, this allows for a smaller layout area for the output circuit (OUTC) and enables more efficient configuration of the output transistor (OTR) and protection circuit (ESDC). Additionally, compared to... Figure 12 In comparison, this allows for a smaller distance from the pad to each transistor TN1 and TP1, thus further suppressing the increase of parasitic capacitance of the pad.

[0105] Figure 14 An example of the circuit layout of the input circuit INC of the semiconductor device SEM in the second embodiment is shown. For comparison with... Figure 3 and Figure 9Identical elements are labeled with the same symbols, and detailed descriptions are omitted. In the input circuit INC, the pad wiring Pad is electrically connected to the gate GT of transistors TN1 and TP1. Therefore, the connection between the cathode of diode D1a and the gate GT of local transistor TN1 can be achieved using wiring connected to the gate GT of transistor TN1. The connection between the anode of diode D1b and the gate GT of local transistor TP1 can be achieved using wiring connected to the gate GT of transistor TP1.

[0106] exist Figure 14 In the circuit layout shown, two diodes D1a extending in the Y direction are arranged adjacently in the X direction in the area where transistor TN1 is configured. Furthermore, two diodes D1b extending in the Y direction are arranged adjacently in the X direction in the area where transistor TP1 is configured. In this case, portions of diodes D1a and D1b can also be positioned overlapping with the pad wiring in a top view.

[0107] Furthermore, diode D1a can be positioned between local transistors TN1 arranged along the X direction, and diode D1b can be positioned between local transistors TP1 arranged along the X direction. By positioning diode D1a between local transistors TN1 and diode D1b between local transistors TP1, the distance between local transistors TN1 (which act as heat sources) and the distance between local transistors TP1 can be increased. As a result, the temperature rise of the input circuit INC can be suppressed.

[0108] Figure 15 A third variation of the circuit layout of the output circuit OUTC of the semiconductor device SEM in the second embodiment is shown. For... Figure 3 and Figure 14 The same elements are labeled with the same symbols, and detailed descriptions are omitted.

[0109] exist Figure 15 Nakaya and Figure 14 Similarly, two diodes D1a extending in the Y direction are arranged adjacently in the X direction in the region where transistor TN1 is configured, and two diodes D1b extending in the Y direction are arranged adjacently in the X direction in the region where transistor TP1 is configured. A portion of diodes D1a and D1b can be configured at a position overlapping with the pad wiring.

[0110] The layout area of ​​diodes D1a and D1b mounted on the input circuit INC and output circuit OUTC in a die-to-die configuration can be smaller than the layout area of ​​diodes mounted on the protection circuit ESDC of a chip that outputs signals to external terminals. Furthermore, when diodes D1a and D1b are formed using a planar transistor manufacturing process, unlike the case of a FinFET manufacturing process, there are no restrictions on the extension direction of the fins (FIN) and the configuration direction of the gate (GT). Therefore, for example, by aligning the elongated diodes D1a and D1b extending in the Y direction to match the lengths of each transistor TN1 and TP1 in the Y direction, free space can be effectively utilized.

[0111] Figure 16 A fourth variation of the circuit layout of the output circuit OUTC of the semiconductor device SEM in the second embodiment is shown. For... Figure 3 , Figure 11 as well as Figure 15 The same elements are labeled with the same symbols, and detailed descriptions are omitted.

[0112] Figure 16 The output circuit OUTC shown, besides using the FinFET manufacturing process to form transistors TN1 and TP1 and diodes D1a and D1b, has the same characteristics as... Figure 15 The output circuit OUTC shown has the same layout. Details regarding the FinFETs for transistors TN1 and TP1, as well as the wiring and vias connecting to the FinFETs, are omitted. For example, in... Figure 16 In China, the following is adopted Figure 11 The FinFET manufacturing process shown depicts diodes D1a and D1b arranged in units of six, adjacent to each other in the X-direction of the transistor TN1 and TP1 configuration areas. A portion of diodes D1a and D1b may be overlapped on the pad wiring. Figure 16 In addition, by configuring longitudinally elongated diodes D1a and D1b extending in the Y direction, the free space can be effectively utilized.

[0113] The same effects as in the first embodiment can be achieved in the second embodiment. For example, the effect of local transistor TN1 heating on another adjacent local transistor TN1 can be suppressed, and the effect of local transistor TP1 heating on another adjacent local transistor TP1 can be suppressed. As a result, local temperature rise during the driving of transistors TN1 and TP1 can be suppressed, and the degradation of the characteristics of the semiconductor device SEM can be suppressed.

[0114] Furthermore, in the second embodiment, by utilizing the advantage of the Die-to-Die principle, which reduces the layout area of ​​diodes D1a and D1b that function as the protection circuit ESDC, the diodes D1a and D1b with small layout areas can be positioned between transistors TN1 and TP1 and the solder wiring pad, or they can be positioned overlapping with the solder wiring pad. Alternatively, diodes D1a and D1b can be positioned adjacent to each other in the X direction of the configuration area of ​​transistors TN1 and TP1. As a result, the output transistor OTR or input transistor and the protection circuit ESDC can be configured with high efficiency.

[0115] (Third Implementation)

[0116] Figure 17 An example of the circuit layout of the output circuit OUTC of the semiconductor device SEM in the third embodiment is shown. For comparison with... Figure 3 and Figure 9 The same elements are labeled with the same symbols, and detailed descriptions are omitted.

[0117] Referring to the circuit diagram, the output circuit OUTC includes a resistor Rsn positioned between the pad Pad and the drain of transistor TN1, and a resistor Rsp positioned between the pad Pad and the drain of transistor TP1. Resistor Rsn is connected to the drain of transistor TN1 via node NA, and resistor Rsp is connected to the drain of transistor TP1 via node NB. Except for using wiring layer M2 to form the ground line VSS for diode D1a and the power line VDD for diode D1b, the other structures of the output circuit OUTC are similar to... Figure 9 The output circuit OUTC has the same structure.

[0118] Referring to the layout diagram, the resistor element Rsn is positioned between transistor TN1 and diode D1a. For example, the resistor element Rsn comprises 10 local resistor elements connected in parallel in units of two. Hereinafter, the local resistor elements of the resistor element Rsn are also referred to as local resistor element Rsn. The local resistor element Rsn is an example of either the first resistor element or the second resistor element.

[0119] Additionally, the two local resistor elements Rsn connected in parallel are also referred to as the local resistor pair Rsn. One end of the local resistor pair Rsn is connected to the drain of each local transistor TN1 via wiring W1 and wiring NA of node NA. The other end of the local resistor pair Rsn is connected to the cathode of diode D1a and the pad wiring Pad via wiring W1.

[0120] A resistive element Rsp is configured between multiple local transistors TP1 and diodes D1b. For example, the resistive element Rsp comprises 10 local resistive elements connected in parallel in units of two. Hereinafter, the local resistive elements of the resistive element Rsp are also referred to as local resistive element Rsp. The local resistive element Rsp is an example of either the first resistive element or the second resistive element.

[0121] Additionally, the two local resistor elements Rsp connected in parallel are also called a local resistor element pair Rsp. One end of the local resistor element pair Rsp is connected to the drain of each local transistor TP1 via wiring W1 and wiring NB of node NB. The other end of the local resistor element pair Rsp is connected to the anode of diode D1b and pad wiring Pad via wiring W1.

[0122] For example, local resistive elements Rsn and Rsp are formed using poly-Si as the material for the gate GT, and connected to wiring W1 of wiring layer M1 via via VIA. Here, wiring of wiring layer M2 or M3 can be used to form local resistive elements Rsn and Rsp.

[0123] Above (in the Z direction) the area overlapping the resistive element Rsn and diode D1a when viewed from above, a ground line VSS is formed using wiring layer M2. The anode of diode D1a is connected to the ground line VSS above diode D1a when viewed from above via via VIA (diff-M1), wiring W1, and via VIA (M1-M2). The cathode of diode D1a is connected to wiring W1 extending in the Y direction via via VIA (diff-M1).

[0124] Above (in the Z direction) of the area overlapping the resistive element Rsp and diode D1b in a top view, a power line VDD is formed using wiring layer M2. The cathode (Ndiff) of diode D1b is connected to the power line VDD above diode D1b in a top view via via VIA (diff-M1), wiring W1, and via VIA (M1-M2). The anode (Pdiff) of diode D1b is connected to wiring W1 extending in the Y direction via via VIA (diff-M1).

[0125] Alternatively, the anode of diode D1a can be connected to a ground wire VSS routed at the end opposite to the Y direction. In this case, instead of a ground wire VSS above the resistive element Rsn and diode D1a when viewed from above, a wiring W1 extending in the Y direction is used to connect the anode of diode D1a to the ground wire VSS located at the end opposite to the Y direction.

[0126] Similarly, the cathode of diode D1b can also be connected to the power line VDD, which is wired at the end in the Y direction. In this case, instead of placing the power line VDD above the resistive element Rsp and diode D1b in a top view, a wiring W1 extending in the Y direction is placed to connect the cathode of diode D1b to the power line VDD at the end in the Y direction.

[0127] In addition, with Figure 13 Similarly, diodes D1a and D1b can be positioned to overlap with the pad wiring when viewed from above. Furthermore, with... Figure 15 Similarly, diode D1a can also be disposed adjacent to transistor TN1 in the X direction, and diode D1b can also be disposed adjacent to transistor TP1 in the X direction.

[0128] By placing the resistive elements Rsn and Rsp in regions not above transistors TN1 and TP1, the areas where heat is generated by the resistive elements Rsn and Rsp can be dispersed from the areas where heat is generated by transistors TN1 and TP1, thereby suppressing localized temperature rise. Furthermore... Figure 17 The circuit layout shown can be applied to the input circuit INC.

[0129] Figure 18 Show along Figure 17 An example of a cross-section along the Y2-Y2' line. Regarding... Figure 10 The layout is the same; detailed descriptions are omitted. Figure 18 In this configuration, resistor Rsn is positioned between diode D1a and transistor TN1, and resistor Rsp is positioned between diode D1b and transistor TP1. Additionally, on both sides of the pad routing pad in the X direction, ground line VSS and routing NA, and power line VDD and routing NB are respectively positioned.

[0130] Figure 19 Show Figure 17 The diagram shows an example of the layout of resistive elements Rsn and Rsp. Resistive elements Rsn and Rsp can also be formed in a sawtooth shape using multiple wirings across multiple wiring layers. In this case, for example, multiple wirings W2 extending in the Y direction and arranged in the X direction can be interconnected via multiple wirings W3 extending in the X direction and vias VIA. Furthermore, one end and the other end of the sawtooth-shaped wiring are connected to a pad wiring Pad (not shown) and the drain of transistor TP1 (or TN1), respectively. Here, the wiring forming resistive elements Rsn and Rsp can also be wirings other than W2 and W3.

[0131] Alternatively, the resistive elements Rsn and Rsp can be formed in a sawtooth shape using poly-Si wiring and wiring layers. In this case, for example, multiple poly-Si wirings extending in the Y direction and arranged in the X direction can be interconnected through multiple wirings W2 extending in the X direction and vias VIA. Furthermore, for ease of understanding of the accompanying drawings, the vias VIA (white circles) used to connect the poly-Si wirings to wiring W1 and the vias VIA (black circles) used to connect wiring W1 (not shown) to wiring W2 are shown offset.

[0132] Additionally, one end of the serrated wiring (in this example, a poly-Si wiring) is connected to the pad wiring (not shown) and the drain of transistor TP1 (or TN1), respectively. Furthermore, the wiring used to connect the poly-Si wiring forming the resistive elements Rsn and Rsp can also be wiring other than wiring W2.

[0133] In addition, Figure 19 In this design, resistor elements Rsn and Rsp are formed using wiring below and above wiring W1 in a top-down view. However, resistor elements Rsn and Rsp can also be formed using only wiring W1 or only another wiring, or even using three or more layers of wiring. Furthermore, resistor elements Rsn and Rsp can be formed in shapes other than serrated. Furthermore, serrated resistor elements Rsn and Rsp can be formed using multiple wirings (including poly-Si wiring) extending in the X direction and arranged in the Y direction. Additionally, poly-Si wiring can be formed using the same process as the conductor used in the transistor gate. Furthermore, if the transistor gate is metal, a metal pattern formed using the same process as the gate can be used instead of poly-Si wiring.

[0134] Figure 20 This is a first variation of the circuit layout of the output circuit OUTC of the semiconductor device SEM in the third embodiment. For... Figure 17 The same elements are labeled with the same symbols, and detailed descriptions are omitted. Additionally, in Figure 20 In future layout diagrams, Figure 2 The main circuit elements shown are illustrated as examples.

[0135] Referring to the layout diagram, resistors Rsn and Rsp are positioned above the areas forming diodes D1a and D1b and the pad wiring in a top view. For example, resistors Rsn and Rsp are formed using wiring W4 of wiring layer M4. Alternatively, resistors Rsn and Rsp can also be formed using wiring other than wiring W4 of wiring layer M4.

[0136] For example, the resistor element Rsn has four pairs of local resistor elements Rsn connected in series in units of two along the Y direction and arranged along the X direction. One end of each local resistor element pair Rsn is connected to the drain of each local transistor TN1 via vias VIA (M3-M4), wiring W3, vias VIA (M2-M3), wiring NA (M2), vias VIA (M1-M2), wiring W1 (M1), and vias VIA (diff-M1). The other end of each local resistor element pair Rsn is connected to the pad wiring Pad vias VIA (M3-M4), wiring W3, vias VIA (M2-M3), wiring W2, and vias VIA (M1-M2). Here, for ease of observation, vias VIA (M3-M4) are depicted as protruding in the X direction of wiring W3.

[0137] For example, the resistor element Rsp has four local resistor element pairs Rsp (connected in series in units of two along the Y direction and arranged along the X direction). One end of each local resistor element pair Rsp is connected to the drain of each local transistor TP1 via vias VIA (M3-M4), wiring W3, vias VIA (M2-M3), wiring NB (M2), vias VIA (M1-M2), wiring W1 (M1), and vias VIA (diff-M1). The other end of each local resistor element pair Rsp is connected to the pad wiring Pad vias VIA (M3-M4), wiring W3, vias VIA (M2-M3), wiring W2, and vias VIA (M1-M2).

[0138] When the resistive elements Rsn and Rsp are formed by wiring in the wiring layer, the resistive elements Rsn and Rsp can be placed on one or both of the transistors TN1 and TP1 and the diodes D1a and D1b, thus reducing the layout area of ​​the output circuit OUTC. Here, the diodes D1a and D1b do not heat up regardless of the operation of the output circuit OUTC. Therefore, when the heat-generating resistive elements Rsn and Rsp are placed on the diodes D1a and D1b, the transistors TN1 and TP1 are less prone to localized temperature rise during operation. Furthermore, Figure 20 The circuit layout shown can also be applied to the input circuit INC.

[0139] Figure 21 Show along Figure 20 An example of a cross-section along line Y3-Y3' in [the image / image]. For [the image / image]... Figure 18 The same elements are labeled with the same symbols, and detailed descriptions are omitted. Figure 21In the circuit, the wiring of the wiring layer M4 is used to form the resistor elements Rsn and Rsp. The resistor elements Rsn and Rsp are connected to the pad wiring Pad via via VIA (M3-M4), the wiring W3 of the wiring layer M3, and another wiring and another via VIA (not shown), and are connected to the drain of the transistor TN1 (or TP1).

[0140] Figure 22 This is a second variation of the circuit layout of the output circuit OUTC of the semiconductor device SEM in the third embodiment. For... Figure 20 The same elements are labeled with the same symbols, and detailed descriptions are omitted. Figure 22 In the diagram, resistor Rsn is formed above the formation area of ​​transistor TN1 when viewed from above, and resistor Rsp is formed above the formation area of ​​transistor TP1 when viewed from above. For example, resistors Rsn and Rsp are formed using wiring W4 of wiring layer M4. Alternatively, resistors Rsn and Rsp can also be formed using wiring other than wiring W4 of wiring layer M4.

[0141] exist Figure 22 In this circuit, since no area for configuring resistors Rsn and Rsp is needed between transistors TN1 and TP1, the length of the output circuit OUTC in the Y direction can be increased compared to... Figure 20 Smaller, thus allowing the layout area of ​​the output circuit OUTC to be smaller than that of the output circuit OUTC. Figure 20 Smaller.

[0142] Furthermore, since transistors TN1 and TP1, as well as resistors Rsn and Rsp, all generate their own heat, localized temperature rises may occur. However, if the temperature rise caused by the operation of the output circuit OUTC is suppressed below the upper limit of the temperature specification of the semiconductor device SEM (e.g., when the operation frequency of the output circuit OUTC is low), there is no problem even if transistors TN1 and Rsn are arranged overlapping in a top-down view, and transistors TP1 and Rsp are also arranged overlapping in a top-down view. Figure 22 The circuit layout shown can also be applied to the input circuit INC.

[0143] Figure 23 This is a third variation of the circuit layout of the output circuit OUTC of the semiconductor device SEM in the third embodiment. For... Figure 22 The same elements are labeled with the same symbols, and detailed descriptions are omitted. Figure 23 In, with Figure 15 Similarly, diode D1a is arranged adjacent to transistor TN1 in the X direction, and diode D1b is arranged adjacent to transistor TP1 in the X direction.

[0144] Alternatively, diode D1a can be positioned between local transistors TN1 arranged along the X direction, and diode D1b can be positioned between local transistors TP1 arranged along the X direction. By positioning diode D1a between local transistors TN1 and diode D1b between local transistors TP1, the distance between the local transistors TN1, which act as heat sources, can be increased. As a result, the temperature rise of the output circuit OUTC can be suppressed. Furthermore, Figure 23 The circuit layout shown can also be applied to the input circuit INC.

[0145] As described above, the third embodiment also achieves the same effects as the first and second embodiments. For example, it can suppress the influence of local transistor TN1 heating on another adjacent local transistor TN1, and it can suppress the influence of local transistor TP1 heating on another adjacent local transistor TP1. As a result, it can suppress the local temperature rise during the driving of transistors TN1 and TP1, thereby suppressing the degradation of the characteristics of the semiconductor device SEM.

[0146] Furthermore, diodes D1a and D1b with small layout areas can be positioned between transistors TN1 and TP1 and the pad wiring, or they can be positioned adjacent to each other in the X direction of the configuration area of ​​transistors TN1 and TP1. As a result, output transistors OTR or input transistors and protection circuits ESDC can be configured efficiently.

[0147] Furthermore, in the third embodiment, such as Figure 17 and Figure 20 As shown, by placing the resistors Rsn and Rsp in areas not on transistors TN1 and TP1, the areas where resistors Rsn and Rsp generate heat, as well as the areas where transistors TN1 and TP1 generate heat, can be dispersed. As a result, localized temperature rise in the output circuit OUTC or the input circuit INC can be suppressed.

[0148] Furthermore, by placing the resistors Rsn and Rsp in a position that overlaps with the non-heating pad wiring Pad or diodes D1a and D1b when viewed from above, the transistors TN1 and TP1 are less prone to localized temperature rise during driving, and the layout area of ​​the output circuit OUTC or the input circuit INC can be reduced.

[0149] (Fourth implementation)

[0150] Figure 24 An example of the circuit layout of the output circuit OUTC of the semiconductor device SEM in the fourth embodiment is shown. For... Figure 9 and Figure 17The same elements are labeled with the same symbols, and detailed descriptions are omitted.

[0151] Referring to the circuit diagram, in the output circuit OUTC, replace... Figure 23 The resistors Rsn and Rsp shown have a resistor Rs positioned between the drain of transistors TN1 and TP1 and the pad Pad. The other circuit structures of the output circuit OUTC are similar. Figure 23 same.

[0152] exist Figure 24 In the example shown, for instance, the resistive element Rs is formed using poly-Si, the material used as the gate GT, but it can also be formed using wiring from the lower layers of wiring layers M1, M2, etc. For example, as the resistive element Rs, 16 local resistive elements are connected in parallel in units of 4. Hereinafter, the local resistive elements of the resistive element Rs are also referred to as local resistive elements Rs.

[0153] Referring to the layout diagram, diode D1a, pad wiring Pad, diode D1b, resistor Rs, power line VDD, transistors TP1 and TN1, and ground line VSS are arranged along the Y direction. The positional relationship between diode D1a, pad wiring Pad, and diode D1b is... Figure 9 Same, but Figure 24 In the diagram, the pad routing is formed using routing layer M4 with routing layer W4. Furthermore, from a top view, above diode D1a, a ground line VSS is configured using routing layer M4, and above diode D1b, a power line VDD is configured using routing layer M4.

[0154] Transistors TN1 and TP1 are arranged adjacent to each other without pads. The power line VDD and ground line VSS formed by wiring layer M2, and the arrangement order of transistors TN1 and TP1 in the Y direction are... Figure 9 Conversely, transistor TP1 is divided into four local transistors TP1 arranged along the X direction. Transistor TN1 is divided into four local transistors TN1 arranged along the X direction.

[0155] The drains of local transistors TN1 and TP1, arranged along the Y direction, are connected to one end of four local resistor elements RS, also arranged along the Y direction, via via VIA (diff-M1), wiring W1, and via VIA (GT-M1). The other ends of the four local resistor elements RS, arranged along the Y direction, are connected to the anode (Pdiff) of diode D1b and the cathode (Ndiff) of diode D1a via via VIA (GT-M1), wiring W1, via VIA (M1-M2), wiring W2, via VIA (M2-M3), and wiring W3, and are further connected to the pad wiring Pad formed on wiring layer M4 via via VIA (M3-M4). Figure 24 In the image, black circular vias VIA (M1-M2) and square vias VIA (M2-M3) located at the other end of the local resistor element RS are depicted overlappingly.

[0156] The cathode of diode D1b is connected to the power line VDD formed on wiring layer M4 via via VIA (diff-M1), wiring W1, via VIA (M1-M2), wiring W2, via VIA (M2-M3), wiring W3, and via VIA (M3-M4). The description of via VIA (M3-M4) is omitted here.

[0157] The anode of diode D1a is connected to the ground line VSS formed on wiring layer M4 via via VIA (diff-M1), wiring W1, via VIA (M1-M2), wiring W2, via VIA (M2-M3), wiring W3, and via VIA (M3-M4). The depiction of via VIA (M3-M4) is omitted here.

[0158] When forming the resistive element Rs using poly-Si as the gate material GT or wiring W1, W2, etc. in the underlying wiring layers M1, M2, can be employed... Figure 24 The layout shown is used to form the output circuit OUTC. Here, for example, if wiring W1 is used to form the resistive element Rs, via VIA (GT-M1) is not required. Furthermore, the order of the ground line VSS, transistors TN1 and TP1, and power line VDD in the Y direction can also be reversed. The order of the ground line VSS of diode D1a and wiring layer M4 in the Y direction can also be reversed compared to the order of the power line VDD of diode D1b and wiring layer M4. Additionally, Figure 24 The circuit layout shown can be applied to the input circuit INC.

[0159] Figure 25 An example of the circuit layout of the input circuit INC of the semiconductor device SEM in the fourth embodiment is shown. For comparison with... Figure 24 The same elements are labeled with the same symbols, and detailed descriptions are omitted.

[0160] Referring to the circuit diagram, the input circuit INC has a resistor Rs positioned between the gate of transistors TN1 and TP1 and the pad. The resistor Rs is connected to the gate of transistors TN1 and TP1 via node NC. The other circuit structures of the input circuit INC are similar to... Figure 14 same.

[0161] Referring to the layout diagram, the input circuit INC and Figure 24The output circuit OUTC shown is similar, with diode D1a, pad wiring Pad, diode D1b, resistor Rs, power line VDD, transistors TP1 and TN1, and ground line VSS arranged along the Y direction. However, the input circuit INC has a wiring NC formed by a node NC using wiring layer M2 extending in the X direction between resistor Rs and power line VDD using wiring layer M2. The layout of diode D1a, pad wiring Pad, diode D1b, resistor Rs, ground line VSS using wiring layer M4, and power line VDD is similar to... Figure 24 same.

[0162] The gates GT of transistors TN1 and TP1 are connected to wiring NC of wiring layer M2 via via VIA (GT-M1), wiring W1, and via VIA (M1-M2). Wiring NC is connected to one end of four local resistor elements RS arranged along the Y direction via via VIA (M1-M2), wiring W1, and via VIA (GT-M1).

[0163] Additionally, the order of the ground wire VSS, transistors TN1 and TP1, and power line VDD in the Y direction can also be reversed. Similarly, the order of the ground wire VSS of diode D1a and wiring layer M4 in the Y direction can be reversed compared to the order of the power line VDD of diode D1b and wiring layer M4. Furthermore, with... Figure 22 or Figure 23 Similarly, the output circuit OUTC can be laid out in the same way, and the resistor Rs can also be arranged in a position that overlaps with the transistors TN1 and TP1 when viewed from above.

[0164] In the fourth embodiment, the same effects as those described above can also be achieved.

[0165] (Fifth Embodiment)

[0166] Figure 26 An example of the circuit structure of the output circuit OUTC of the semiconductor device SEM in the fifth embodiment is shown. Figure 26 In the output circuit OUTC shown in (A), replace Figure 3 The output circuit OUTC has a PMOS transistor TP1 and an NMOS transistor TN3. Figure 26 In the output circuit OUTC shown in (B), replace Figure 17 The output circuit OUTC has a PMOS transistor TP1 and an NMOS transistor TN3.

[0167] Figure 26 In the output circuit OUTC shown in (C), replace Figure 24 The output circuit OUTC has a PMOS transistor TP1 and an NMOS transistor TN3. Figure 26 In the output circuit OUTC shown in (D), replace Figure 3 The output circuit OUTC has an NMOS transistor TN1 and a PMOS transistor TP3.

[0168] Figure 26 In the output circuit OUTC shown in (E), instead of... Figure 17 The output circuit OUTC has an NMOS transistor TN1 and a PMOS transistor TP3. Figure 26 In the output circuit OUTC shown in (F), instead of... Figure 24 The output circuit OUTC has an NMOS transistor TN1 and a PMOS transistor TP3.

[0169] In typical CMOS circuits, PMOS transistors are used to output high-level signals, while NMOS transistors are used to output low-level signals. Conversely, in output circuits requiring high-speed operation, the output transistor OTR can also be configured as an output circuit OUTC using NMOS and PMOS transistors with higher drive capability to output both high and low levels.

[0170] When replacing a PMOS transistor with an NMOS transistor, or vice versa, although the conductivity types of the semiconductor layers (source and drain) are different, the layout structure can remain the same as before the replacement. For example... Figure 26 As shown in (A) to (F), the circuit structure with one type of transistor conductivity is applicable to various embodiments of the above-described output circuit OUTC. Furthermore, Figure 26 The circuit structures shown in (A) to (F) are applicable to various implementations of the input circuit INC described above.

[0171] Figure 27 Another example of the circuit structure of the output circuit OUTC of the semiconductor device SEM in the fifth embodiment is shown. Figure 27 In the output circuit OUTC shown in (A), replace Figure 7 The output circuit OUTC has PMOS transistors TP1 and TP2, and NMOS transistors TN3 and TN4. Figure 27 Similarly, in the output circuits OUTC shown in (B) and (C), instead of the PMOS transistors TP1 and TP2 that are cascaded with the usual CMOS circuits, there are cascaded NMOS transistors TN3 and TN4.

[0172] Figure 27 In the output circuit OUTC shown in (D), replace Figure 7The output circuit OUTC has NMOS transistors TN1 and TN2, and PMOS transistors TP3 and TP4. Figure 27 Similarly, in the output circuit OUTC shown in (E) and (F), instead of the NMOS transistors TN1 and TN2 that are cascaded with the usual CMOS circuit, there are cascaded PMOS transistors TP3 and TP4.

[0173] Figure 27 The transistors shown in (A) to (F) have a single conductivity type, and their circuit structures are applicable to various embodiments of the output circuit OUTC described above. Furthermore, Figure 27 The circuit structures shown in (A) to (F) are applicable to various embodiments of the above-described input circuit INC.

[0174] In the fifth embodiment, the same effects as those described above can also be achieved.

[0175] The present invention has been described above according to various embodiments, but the present invention is not limited to the elements shown in the above embodiments. Changes can be made to these points without prejudice to the spirit of the invention, and appropriate adjustments can be made depending on the application method.

[0176] Symbol Explanation

[0177] BMP bumps

[0178] CP1 and CP2 chips

[0179] diodes D1b and D1a

[0180] ESD protection circuit

[0181] EXT external connection terminal

[0182] FIN fins

[0183] GT gate

[0184] IN internal signal line

[0185] IN2 input terminal

[0186] INC input circuit

[0187] INTP inserter

[0188] IOC1 and IOC2 input / output circuits

[0189] LI Local wiring

[0190] M1, M2, M3, M4 wiring layers

[0191] NA, NB, NC nodes

[0192] Ndiff and Pdiff semiconductor layers

[0193] NS nanosheets

[0194] NW well region

[0195] OTR output transistor

[0196] OUT internal signal line

[0197] OUT1 Output terminal

[0198] OUTC output circuit

[0199] Pad solder pad

[0200] Rs, Rsn, Rsp resistive elements

[0201] SEM1 and SEM2 semiconductor devices

[0202] SUB substrate

[0203] TP1 and TP2 PMOS transistors

[0204] TN1 and TN2 NMOS transistors

[0205] VDD power cord

[0206] VIA via

[0207] VSS grounding wire

[0208] Wiring for W, W1, W2, W3, W4

Claims

1. A semiconductor device comprising: A first semiconductor chip, having a first circuit; and The second semiconductor chip has a second circuit connected to the first circuit. The first circuit includes a first power line, a second power line, a signal line connected to the second circuit, and a plurality of first transistors, each having a first source and a first drain. The plurality of first transistors are arranged, in top view, between one of the first power line or the second power line and the signal line. From a top view, the first source of one of the first transistors is configured adjacent to the first source of the other first transistor. From a top view, the first drain of one of the first transistors is configured adjacent to the first drain of the other first transistor.

2. The semiconductor device according to claim 1, wherein, The first circuit includes a plurality of second transistors, each having a second source and a second drain. The plurality of second transistors are arranged, in top view, between the first power line or another of the second power lines and the signal line. Viewed from above, the second source of one of the second transistors is configured adjacent to the second source of the other second transistor. From a top view, the second drain of one of the second transistors is configured adjacent to the second drain of the other second transistor.

3. A semiconductor device comprising: A first semiconductor chip, having a first circuit; and The second semiconductor chip has a second circuit connected to the first circuit. The first circuit includes a first power line, a second power line, a signal line connected to the second circuit, a plurality of first transistors, and a first diode. The first diode includes a first semiconductor region connected to one of the first power line or the second power line and having a first conductivity type, and a second semiconductor region connected to the signal line and having a second conductivity type different from the first conductivity type. The plurality of first transistors are arranged, in top view, between one of the first power line or the second power line and the signal line. The first diode, viewed from above, is disposed between the plurality of first transistors and the signal line, or overlaps with the signal line, or is disposed adjacent to any one of the plurality of first transistors along the arrangement direction of the plurality of first transistors.

4. The semiconductor device according to claim 3, further comprising: Multiple second transistors; and The second diode includes a third semiconductor region connected to the first power line or another of the second power line and having the second conductivity type, and a fourth semiconductor region connected to the signal line and having the first conductivity type. The plurality of second transistors are arranged, in top view, between the first power line or another of the second power lines and the signal line. The second diode, viewed from above, is disposed between the plurality of second transistors and the signal line, or overlaps with the signal line, or is disposed adjacent to any one of the plurality of second transistors along the arrangement direction of the plurality of second transistors.

5. The semiconductor device according to claim 1, wherein, The semiconductor device includes a plurality of first resistive elements connected between the signal line and the first gate or the first drain of the plurality of first transistors. The plurality of first resistive elements, when viewed from above, are disposed between the plurality of first transistors and the signal lines, or are disposed overlapping with the plurality of first transistors, or are disposed overlapping with the signal lines.

6. The semiconductor device according to claim 5, wherein, The semiconductor device has a first diode, which includes a first semiconductor region connected to one of the first power line or the second power line and having a first conductivity type, and a second semiconductor region connected to the signal line and having a second conductivity type different from the first conductivity type. The plurality of first resistive elements are arranged overlapping the first diode when viewed from above.

7. The semiconductor device according to any one of claims 1, 5, and 6, further comprising: Multiple second transistors, each having a second gate and a second drain; Multiple second resistive elements are connected between the signal line and the second gate or second drain of the multiple second transistors. The plurality of second resistors, viewed from above, are disposed between the plurality of second transistors and the signal line, or are disposed overlapping with the plurality of second transistors, or are disposed overlapping with the signal line.

8. The semiconductor device according to claim 7, wherein, The semiconductor device has a second diode, which includes a third semiconductor region connected to the first power line or another of the second power lines, and a fourth semiconductor region connected to the signal line and having a conductivity type different from that of the third semiconductor region. The plurality of second resistive elements are arranged overlapping the second diode when viewed from above.

9. The semiconductor device according to claim 1, wherein, The first circuit has an output circuit that outputs a signal to the second circuit via the signal line.

10. The semiconductor device according to claim 1, wherein, The first circuit has an input circuit that receives signals from the second circuit via the signal line.

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