Embedded cooling system for advanced device packaging and method of manufacturing the same

Abstract

The present invention relates to a device package including an integrated cooling assembly including a semiconductor stack and a cooling channel, wherein the semiconductor stack includes a first semiconductor device and a second semiconductor device vertically stacked on the first semiconductor device; and spacers extending between opposite surfaces of the first and second semiconductor devices to space the first semiconductor device apart from the second semiconductor device, the spacers and the opposite surfaces of the first and second semiconductor devices collectively defining the cooling channel therebetween; and the spacers include vias electrically connecting the first semiconductor device and the second semiconductor device.

Description

Cross-reference of related applications

[0001] This application claims the benefits of U.S. Provisional Patent Application No. 63 / 550,702, filed February 7, 2024; U.S. Provisional Patent Application No. 63 / 575,161, filed April 5, 2024; and U.S. Patent Application No. 18 / 787,506, filed July 29, 2024, all of which are hereby incorporated herein by reference in their entirety. Technical Field

[0002] This disclosure relates to advanced packaging for microelectronic devices, and more particularly to cooling systems for device packaging and methods of manufacturing thereof. Background Technology

[0003] Energy consumption poses a significant challenge to the future of large-scale computing, as the world's computing energy demands are increasing at a rate that most consider unsustainable. Some models predict that by 2030, the information, communication, and technology (ICT) ecosystem could account for over 20% of global electricity consumption, with large computing centers directly consuming more than a third of that energy. A considerable portion of the energy used by such large computing centers is used for cooling, as even small increases in operating temperature can adversely affect the performance of microprocessors, memory devices, and other electronic components. While some of this energy is used to operate cooling systems that directly cool the chips (e.g., heat sinks, heat pipes), the energy consumption and cost of indirect cooling can also be substantial. Indirect cooling energy costs include, for example, the cooling or air conditioning of data center buildings. Data center buildings can house thousands, tens of thousands, or even more high-performance chips in server racks, each of which is a heat source. Uncontrolled ambient temperatures within data centers will adversely affect the performance of individual chips and the overall performance of the data center system.

[0004] Heat dissipation in high-power-density chips (semiconductor devices / dies) is also a significant challenge. This is because improvements in chip performance (e.g., increased gate or transistor density due to advanced processing nodes, the evolution of multi-core microprocessors, etc.) have led to increased power density and corresponding increased heat flux, which in turn causes chip temperatures to rise. Higher transistor density also increases the length of metal wiring on the chip, due to the additional heat flux generated by these lines due to Joule heating from higher currents. These high temperatures are undesirable because they can degrade chip operating performance, efficiency, reliability, and remaining lifetime. Cooling systems used to maintain the chip at the desired operating temperature typically use one or more heat dissipation devices (e.g., heat sinks, heat pipes, cold plates, liquid-cooled heat pipe systems, thermoelectric coolers, radiators, etc.) to remove heat. One or more thermal interface materials (such as thermal adhesives, thermal bonding agents, or thermal gap fillers) can be used to facilitate heat transfer between the chip surface and the heat dissipation device. Thermal interface material (TIM) is any material inserted between two components to enhance the thermal coupling between them. Unfortunately, the total thermal resistance formed by (i) the interface boundary region between the TIM and the wafer and / or heat sink, and (ii) the thermal resistance of the thermal interface material itself, can inhibit heat transfer from the wafer to the heat sink, thereby unintentionally reducing the cooling efficiency of the cooling system.

[0005] Generally speaking, there are multiple components between the heat source (i.e., the active circuit system) and the heat dissipation device in a chip. Each component accumulates along the heat transfer path, increasing the system thermal resistance and causing the chip junction temperature to be higher than the ambient temperature.

[0006] Due to the design and manufacturing of system components, these cooling systems may face reduced cooling efficiency.

[0007] Therefore, this technology requires improving the high-efficiency cooling system and its manufacturing method by reducing the system's thermal resistance. Summary of the Invention

[0008] Specific examples in this paper provide integrated cooling assemblies embedded in advanced device packages. Advantageously, the integrated cooling assembly includes cooling channels between stacked semiconductor devices while maintaining a relatively small distance between them. Therefore, cooling can be directly provided to two or more stacked semiconductor devices to efficiently cool the devices while maintaining a relatively close distance between them for optimal interconnect performance.

[0009] A general example includes a device package comprising an integrated cooling assembly. The integrated cooling assembly includes a semiconductor stack and cooling channels. The semiconductor stack includes a first semiconductor device and a second semiconductor device vertically stacked on top of the first semiconductor device. The semiconductor stack further includes spacers extending between opposing surfaces of the first and second semiconductor devices to space the first semiconductor device from the second semiconductor device. The spacers and the opposing surfaces of the first and second semiconductor devices together define cooling channels therebetween. The spacers include vias electrically connecting the first semiconductor device and the second semiconductor device.

[0010] The implementation of a device package may include one or more of the following features. In some specific instances, the thickness of the spacer in a direction orthogonal to the surface opposite the semiconductor device is less than 200 micrometers. In some specific instances, the cooling channel is a liquid cooling channel, and liquid can flow through the liquid cooling channel. The liquid may contain water and / or ethylene glycol.

[0011] Another general example includes a device package comprising an integrated cooling assembly. The integrated cooling assembly includes a semiconductor stack and cooling channels. The semiconductor stack includes a first semiconductor device and a second semiconductor device vertically stacked on top of the first semiconductor device. The first semiconductor device includes sidewalls extending upwards to the second semiconductor device to define a cavity volume. The sidewalls, a lower surface of the second semiconductor device facing the cavity volume, and an upper surface of the first semiconductor device together define a cooling channel. The sidewalls include vias electrically connecting the first semiconductor device and the second semiconductor device.

[0012] Another general example includes a method using a device package. This method includes supplying fluid via cooling channels to directly cool the semiconductor device.

[0013] Another general example includes a method of manufacturing a device package. The method includes forming a spacer on a first semiconductor device. The method further includes etching the spacer, the first semiconductor device, and a second semiconductor device to form a via. The method further includes depositing a conductive material in the via. The method further includes directly bonding the second semiconductor device to the spacer to form an integrated cooling assembly. The integrated cooling assembly includes a cooling channel formed between the first semiconductor device and the second semiconductor device, and an electrical connection via formed between the first semiconductor device and the second semiconductor device.

[0014] Another general example includes a method of manufacturing a device package. The method includes etching a surface of a first semiconductor device to form a cavity sidewall. The method further includes etching the cavity sidewall, the first semiconductor device, and a second semiconductor device to form a via. The method further includes depositing a conductive material in the via. The method further includes directly bonding the second semiconductor device to the cavity sidewall to form an integrated cooling assembly. The integrated cooling assembly includes a cooling channel formed between the first semiconductor device and the second semiconductor device, and an electrical connection via formed between the first semiconductor device and the second semiconductor device. Attached Figure Description

[0015] The above and other objectives and advantages of this disclosure will become apparent when considered in conjunction with the following detailed description, in which:

[0016] Figure 1 The diagram illustrates a device package with an external heat sink.

[0017] Figure 2A A schematic floor plan view of an example of a system panel according to a specific example of this disclosure;

[0018] Figure 2B This is a schematic partial cross-sectional side view of a device package mounted on a PCB according to a specific example of this disclosure;

[0019] Figure 2C for Figure 2B A schematic exploded isometric view of the device package in the diagram;

[0020] Figure 2D A schematic cross-sectional view of an example device package that can be used with a system panel, based on a specific example of the present disclosure;

[0021] Figure 2E A schematic cross-sectional view of an example semiconductor stack according to a specific example of the present disclosure;

[0022] Figure 3 A schematic cross-sectional view of an example semiconductor stack according to a specific example of the present disclosure;

[0023] Figure 4 A schematic cross-sectional view of an example semiconductor stack according to a specific example of the present disclosure;

[0024] Figure 5 A 3D view of a semiconductor stack based on a specific example;

[0025] Figure 6 A schematic cross-sectional view of an example semiconductor stack according to a specific example of the present disclosure;

[0026] Figure 7 A schematic cross-sectional view of an example semiconductor stack according to a specific example of the present disclosure;

[0027] Figure 8 A schematic cross-sectional view of an example semiconductor stack according to a specific example of the present disclosure;

[0028] Figure 9A A schematic cross-sectional view of an example semiconductor stack according to a specific example of the present disclosure;

[0029] Figure 9B A 3D view of a semiconductor stack based on a specific example;

[0030] Figure 10 A schematic cross-sectional view of an example semiconductor stack according to a specific example of the present disclosure;

[0031] Figure 11 The method of device encapsulation based on one or more specific instances is demonstrated;

[0032] Figure 12 Methods for manufacturing device packages, based on one or more specific examples, are demonstrated;

[0033] Figure 13 Methods for manufacturing device packages, based on one or more specific examples, are demonstrated;

[0034] The figures in this document are for illustrative purposes only and depict various specific examples of the disclosure. It should be understood that additional or alternative structures, assemblies, systems, and methods may be implemented within the principles set forth in this disclosure. Detailed Implementation

[0035] As used herein, the term "substrate" means and includes any workpiece, wafer, or article of manufacture that provides a base material or support surface from or on which components, elements, devices, assemblies, modules, systems, or features described herein may be formed or mounted. The term "substrate" also includes semiconductor substrates that provide support material for the fabrication or attachment of elements of semiconductor devices; and any layers of material, features, and / or electronic devices formed thereon, in, or through them. Examples of substrate materials that can be used for applications producing high heat density include, but are not limited to, Si, GaN, SiC, InP, GaP, InGaN, AlGaInP, AlGaAs, etc.

[0036] As described below, semiconductor substrates typically have a “device side,” such as the side on which semiconductor device elements, such as transistors, resistors, and capacitors, are fabricated, and a “back side” opposite to the device side. The term “active side” should be understood to include the surface of the device side of the substrate and may include the device side surface of the semiconductor substrate and / or the surface of any material layer, device element, or feature formed thereon or extending outward therefrom, and / or any opening formed therein. Therefore, it should be understood that the material forming the active side may vary depending on the stage of device fabrication and assembly. Similarly, the term “non-active side” (as opposed to the active side) includes the non-active side of the substrate at any stage of device fabrication, including the surface of any material layer, any feature formed thereon or extending outward therefrom, and / or any opening formed therein. Therefore, the terms “active side” or “non-active side” may include individual surfaces of the semiconductor substrate at the start of device fabrication and any surfaces formed during material removal (e.g., after a substrate thinning operation). Depending on the stage of device fabrication or assembly, the terms "active side" and "non-active side" are also used to describe the surface of a material layer or feature formed on, in, or through a semiconductor substrate, regardless of whether such material layer or feature is ultimately present in the fabricated or assembled device. For example, in some cases, the term "active side" is used to indicate the surface of a substrate that will later include, but does not currently include, semiconductor device elements.

[0037] Spatially relative terms are used herein to describe relationships between elements, such as substrates, heat-generating devices, cooling assembly components, device packaging components, and other features described below. Unless otherwise defined, terms such as “above,” “over,” “upper,” “upward,” “outward,” “on,” “below,” “below,” “under,” “lower,” “top,” “bottom,” and the like generally refer to the X, Y, and Z directions as illustrated in the figures. Therefore, it should be understood that the spatially relative terms used herein are intended to cover different orientations of the substrate, and unless otherwise indicated, these terms are not limited by the direction of gravity. Unless otherwise defined, terms such as “set on,” “embedded in,” “coupled to,” “connected by,” “attached to,” “joined to,” and the like, which describe relationships between elements individually or in combination with spatially related terms, include both relationships with intervening elements and direct relationships in the absence of intervening elements. Furthermore, the term “horizontal” generally refers to the X-axis and Y-axis directions as illustrated in the figures. The term "vertical" usually refers to the Z-axis direction as illustrated in the diagram.

[0038] The various specific examples disclosed herein include bonding structures in which two or more elements are directly bonded to each other without the intervention of an adhesive (referred to herein as "direct bonding," "direct dielectric bonding," or "direct bonding"). The resulting bonding formed by this technique can be described as "direct bonding" and / or "direct dielectric bonding." In some specific examples, direct bonding involves bonding a single material on a first of two or more elements and bonding a single material on a second of two or more elements, wherein the single material on the different elements may be the same or different. For example, bonding one layer of inorganic dielectric (e.g., silicon oxide) to another layer of the same or different inorganic dielectric. As discussed in more detail below, direct bonding (e.g., direct dielectric bonding) processes can reduce the thermal resistance between a semiconductor device and a cold plate. Examples of dielectric materials used in direct bonding include oxides, nitrides, oxynitrides, carbonitrides, and oxycarbonitrides (such as, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, etc.). Direct bonding can also include bonding multiple materials on one element to multiple materials on another element (e.g., hybrid bonding). As used herein, the term "hybrid bonding" refers to a type of direct bonding that has both of the following: i) being directly bonded to at least one (first) non-conductive feature of another (second) non-conductive feature; and ii) being directly bonded to at least one (first) conductive feature of another (second) conductive feature without the need for any intervening adhesive. The resulting bonding formed by this technique can be described as "hybrid bonding" and / or "direct hybrid bonding". In some specific instances of hybrid bonding, there are a plurality of first conductive features, each of which is directly bonded to a second conductive feature without the need for any intervening adhesive. In some specific instances, a non-conductive feature on a first element is directly bonded to a non-conductive feature of a second element at room temperature without the need for any intervening adhesive, which is then followed by annealing at a slightly higher temperature (e.g., >100°C, >200°C, >250°C, >300°C, etc.) to directly bond the conductive feature of the first element to the conductive feature of the second element. Direct bonding can include direct dielectric bonding techniques as described herein, and can produce direct dielectric bonding. Hybrid bonding can include hybrid bonding techniques as described herein, and can produce direct hybrid bonding.

[0039] Unless otherwise stated, the terms "cooling assembly" and "integrated cooling assembly" generally refer to semiconductor stacks in which cooling channels are formed. Typically, the cooling channels have recessed surfaces that define one or more fluid cavities (e.g., coolant chamber volumes) between first and second semiconductor devices in the semiconductor stack. Alternatively, the cooling channels may be defined therebetween by spacers disposed between opposing surfaces of the first and second semiconductor devices. In specific instances where the cooling channels form several fluid cavities, each fluid cavity may be defined by cavity separators and / or sidewalls of the cooling channels. For example, cavity separators may be spaced apart from each other and extend laterally between opposing cooling channel sidewalls (e.g., extending in one direction between first pairs of opposing cooling channel sidewalls, or in two directions between two pairs of opposing cold plate sidewalls). The cavity separators and cooling channel sidewalls may together define adjacent fluid cavities therebetween.

[0040] Advantageously, the opposing surfaces of the first and second semiconductor devices are directly exposed to the coolant fluid flowing through the integrated cooling assembly, thus providing direct heat transfer between them. Unless otherwise stated, the integrated cooling assembly described herein can be used with any desired fluid (e.g., liquid, gas, and / or vapor phase coolant), such as water, ethylene glycol, etc.

[0041] Exemplary fluids that can be used in various specific instances of thermal solutions include: water (pure or deionized water), ethylene glycol (e.g., ethylene glycol, propylene glycol), ethylene glycol mixtures with water (e.g., ethylene glycol-water mixtures (EGW) or propylene glycol-water mixtures (PGW)), dielectric fluids (e.g., fluorocarbons, polyalphaolefins (PAO), isoalkanes, synthetic esters, or very high viscosity index (VHVI) oils), or mineral oils. Furthermore, depending on design and operating conditions, these fluids can be used as single-phase liquids, single-phase vapors, two-phase liquid / vapor, or two-phase solid / liquid. All these fluids and fluid mixtures will change their thermohydraulic and heat transfer properties by varying the temperature at which the phase change occurs, and will meet the design temperature and pressure conditions of the components being cooled or heated and the deployed thermal solutions. Moreover, various combinations of fluid phases can be used in various mixing configurations to meet the specific cooling or heating requirements of individual implementations, still within the scope of the envisioned specific instances.

[0042] Furthermore, in some specific instances, cooling is provided partially or entirely by gases. Exemplary gases include the atmosphere and / or one or more inert gases, such as nitrogen. The atmosphere can be understood to mean the mixture of different gases in the Earth's atmosphere, consisting of approximately 78% nitrogen and 21% oxygen.

[0043] Depending on the design requirements of the thermal solution system using the specific examples disclosed, engineered dielectric cooling fluids may be used. Some examples of dielectric fluids used for cooling semiconductors include: 3M™ Fluorinert™ Liquid FC-40, a non-flammable dielectric fluid suitable for direct contact with charged electronic devices; 3M™ Novec™ Engineered Fluid, a non-flammable dielectric fluid suitable for direct contact with charged electronic devices; Galden® PFPE (perfluoropolyether) products used as heat transfer fluids; and EnSolv Fluoro HTF, a high-boiling-point, low-flow-point solvent suitable for semiconductor wafer cooling. It should be understood that system design parameters such as operating temperature and pressure, fluid flow rate, fluid viscosity, and other properties will need to be evaluated when selecting a cooling fluid.

[0044] In some specific instances, cooling fluids may contain microparticles and / or nanoparticle additives to enhance the conductivity of the cooling fluid within an integrated cooling assembly. The term "nanofluid" was coined by Choi and Eastman (1995) of Argonne National Institute (Yu et al., 2007). Nanofluids are engineered fluids prepared by suspending nanoscale (1-100 nm) particles of metals / nonmetals and their oxides in a base / conventional fluid. The suspension of high thermal conductivity metal / nonmetal and their oxide nanoparticles enhances the thermal conductivity and heat transfer capacity of the base fluid. Additives to the base cooling fluid may include, for example, carbon nanotube nanoparticles, graphene nanoparticles, or metal oxide nanoparticles. When the cooling fluid contains microparticles, the diameter of the microparticles is typically 10 micrometers or smaller. Silica microparticles can be used.

[0045] The volume concentration of these microparticles or nanoparticles can be less than 1%, less than 0.2%, or less than 0.05%. Depending on the type of liquid and microparticles / nanoparticles chosen for the cooling fluid, higher volume concentrations of 10% or less, 5% or less, or 2% or less can be used. The coolant fluid may also contain small amounts of ethylene glycol or multiple ethylene glycols (e.g., propylene glycol, ethylene glycol, etc.) to reduce frictional shear stress and drag coefficient in the coolant fluid within the integrated cooling assembly. The availability of different base fluids (e.g., water, ethylene glycol, mineral oil, or other stabilized oils) and different nanomaterials provides a wide range of nanomaterial options for nanofluidic solutions used in various specific examples. These nanomaterial options include the aforementioned metals (e.g., Cu, Ag, Fe, Au, etc.), metal oxides (e.g., TiO2, Al2O3, CuO, etc.), carbon (e.g., CNTS, graphene, diamond, graphite, etc.), or mixtures of different types of nanomaterials. Metal nanoparticles (Cu, Ag, Au…), metal oxide nanoparticles (Al₂O₃, TiO₂, CuO), and carbon-based nanoparticles are commonly used elements. Silica nanoparticles may also be used. In practicing the various specific examples disclosed herein, the use of cooling fluids containing microparticles and / or nanoparticles can result in improved heat removal efficiency and effectiveness.

[0046] Specific fluid control design scenarios may require nanofluids to be magnetic to facilitate fluid movement or cessation within semiconductor structures. Magnetic nanofluids (MNFs) are suspensions of non-magnetic substrate fluids and magnetic nanoparticles. Magnetic nanoparticles may be coated with a surfactant layer (such as oleic acid) to reduce particle aggregation and / or sedimentation. The magnetic nanoparticles used in MNFs are typically made of metals such as iron, nickel, and cobalt (ferromagnetic materials) and their oxides (such as spinel ferrites, magnetite (Fe3O4), etc.). The size range of magnetic nanoparticles used in MNFs is typically from about 1 to 100 nanometers (nm).

[0047] This disclosure describes specific examples of architectures involving system and component elements that can be used to provide cooling for semiconductor components, packages, and circuit boards. However, those skilled in the art will understand that the disclosed components and configurations can be deployed and used in situations requiring heating or thermal preheating of components currently outside the lower end of their desired operating range. Components exceeding the lower limit of their operating range may experience thermal warping or cracking, even thermal overexpansion and contact separation, if started up in a cold environment, which can impair successful system operation. Therefore, in these situations, the architectures and specific examples disclosed herein can be used, where indirect thermal solutions supporting these architectures and specific examples are reused or operated in a hybrid configuration to provide a heating fluid or heat transfer medium to achieve preheating or heating scenarios. These scenarios are controlled by a system not shown herein to raise the temperature at a certain rate or time, allowing materials to avoid excessive or uneven thermal expansion that can occur in the materials of the semiconductor or package served by the thermal solution. Once the component or package is within its normal operating range, it can be safely started up and enter a useful operating state.

[0048] Considering the specific examples of preheating or heating described above, the balance of this disclosure and the terminology used should be viewed from the perspective of design options considering such preheating or heating. Therefore, when terms such as cooling channels, cooling chamber volumes, and cooling ports are used, these terms can also be considered as thermal control channels, thermal control volumes, or thermal control ports, respectively. Those skilled in the art will understand that heat flux or heat transfer will proceed in different directions, but the design concepts are similar and can be successfully applied in various specific examples.

[0049] In some specific instances, the cooling passage is a liquid cooling passage, and liquid can flow through the liquid cooling passage. In some specific instances, the liquid may contain water and / or ethylene glycol (e.g., propylene glycol, ethylene glycol, and mixtures thereof).

[0050] As described below, the coolant fluid flowing through a cold plate can be used to control the temperature of a semiconductor device. The fluid flowing across the entire surface of the semiconductor device absorbs heat and conducts it away from the semiconductor device.

[0051] Figure 1 This is a schematic side view of device package 10 and heat sink 22 attached to device package 10. Device package 10 typically includes package substrate 12, first device 14, device stack 15, heat sink 18, and first TIM layers 16A, 16B thermally coupling the first device 14 and device stack 15 to heat sink 18. Device package 10 is thermally coupled to heat sink 22 via a second TIM layer 20. TIM layers 16A, 16B, 20 facilitate thermal contact between components in device package 10 and between device package 10 and heat sink 22.

[0052] As the power density of advanced semiconductor devices continues to increase, the heat flux density also increases accordingly. Figure 1 The accumulated thermal resistance problem of the system illustrated becomes increasingly severe because heat cannot dissipate quickly enough to prevent the semiconductor devices from operating at optimal power. Consequently, the energy efficiency of the semiconductor devices decreases. Furthermore, as shown by heat transfer path 24 (illustrated as a dashed line), heat is transferred between semiconductor devices within the device package 10, where heat can be unintentionally transferred from a first device 14 with high heat flux (such as a central processing unit (CPU) or graphics processing unit (GPU)) to a device stack 15 with low heat flux (such as memory) via heat sink 18.

[0053] For example, such as Figure 1 As shown, each device packaging component and its respective interface boundary have a corresponding thermal resistance, which forms a heat transfer path 26 (from... Figure 1 (As shown by arrow 26 in the image). Figure 1 The right side of the diagram illustrates the heat transfer path 26 as a series of thermal resistances R1 to R8 between the heat source and the heat sink. Here, R1 represents the thermal resistance of the bulk semiconductor material of the first device 14. R3 and R7 represent the thermal resistances of the first TIM layers 16A and 16B, and the second TIM layer 20, respectively. R5 represents the thermal resistance of the heat sink 18. R2, R4, R6, and R8 represent the thermal resistance (e.g., contact resistance) at the interface regions of the components. In a typical cooling system, R3 and R7 may account for 80% or more of the cumulative thermal resistance of the heat transfer path 26, and R5 may account for 5% or more. R1 of the first device 14 and R2, R4, R6, and R8 at the interfaces account for the remaining cumulative thermal resistance. Therefore, the specific examples described herein provide an integrated cooling assembly embedded within a device package. The embedded cooling assembly shortens the thermal resistance path between the semiconductor device and the heat sink and reduces heat conduction between several semiconductor devices disposed in the same device package, as described with respect to the figures below.

[0054] Figure 2AThis is a schematic plan view of an example of a system panel 100 according to a specific embodiment of this disclosure. Typically, the system panel 100 includes a printed circuit board (PCB) 102, several device packages 201 mounted to the PCB 102, and several coolant lines 108 fluidly coupling each of the device packages 201 to a coolant source 110. The coolant fluid is designed to be delivered to each of the device packages 201 in any desired fluid phase (e.g., liquid, vapor, gas, or a combination thereof) and can exit from each device package 201 in the same or different phases. In some specific embodiments, the coolant fluid is delivered to the device package 201 and returns as a liquid from the device package, whereby the coolant source 110 may include a heat exchanger or cooler to maintain the coolant fluid at a desired temperature. In other specific embodiments, the coolant fluid may be delivered as a liquid to the device package 201, evaporate into vapor within the device package 201, and return as vapor to the coolant source 110. In specific instances, device package 201 may be fluidly coupled in parallel to coolant source 110, and coolant source 110 may include or further include a compressor (not shown) for condensing received vapor into liquid form.

[0055] Figure 2B for Figure 2A A schematic partial cross-sectional side view of a portion of system panel 100. As shown, each device package 201 is fluidly coupled to several coolant lines 108 and disposed in a socket 114 of PCB 102, and connected to the socket using several pins 116, or by other suitable connection methods (such as solder bumps (not shown)). The device package 201 may be disposed in the socket 114 and secured to PCB 102 using a mounting frame 106 and several fasteners 112 (e.g., compression screws), which are collectively configured to apply a relatively uniform downward force on the upper edge of the device package 201. The uniform downward force ensures proper pin contact between the device package 201 and the socket 114.

[0056] Figure 2C This is a schematic exploded isometric view of an example device package 201 according to a specific embodiment of the present disclosure. Typically, the device package 201 includes a package substrate 202, an integrated cooling assembly 203 disposed on the package substrate 202, and a package cover 208 disposed on a peripheral portion of the package substrate 202. Suitable materials for the package cover 208 include copper, aluminum, metal alloys, etc. The package cover 208 extends to cover the integrated cooling assembly 203 such that the integrated cooling assembly 203 is disposed between the package substrate 202 and the package cover 208. The integrated cooling assembly 203 typically includes semiconductor stacks 204, with cooling channels formed between the semiconductor stacks.

[0057] As shown, the device package 201 further includes a sealing material layer 222 that forms a coolant fluid impermeable barrier between the package cover 208 and the integrated cooling assembly 203. This coolant fluid impermeable barrier prevents coolant fluid leakage outside the cooling assembly and prevents coolant fluid from reaching the active side 218 of the semiconductor stack 204 (hereinafter referred to as the active side 218). Figure 2D (As discussed) and cause damage to it. In some specific examples, the sealing material layer 222 includes an adhesive material that reliably attaches the package cap 208 to the integrated cooling assembly 203. In some specific examples, the sealing material layer 222 includes a polymer or epoxy material that extends upward from the package substrate 202 to encapsulate and / or surround at least a portion of the semiconductor stack 204. In some specific examples, the sealing material layer 222 may also include a conductive material, such as solder. In other specific examples, the sealing material layer 222 is formed of a molding compound (e.g., a thermosetting resin) that forms a hermetically sealed seal between the package cap 208 and the integrated cooling assembly 203 upon polymerization. Here, coolant fluid is delivered to the integrated cooling assembly 203 through an opening 222A provided through the sealing material layer 222. As shown, the opening 222A is aligned and in fluid communication with the inlet and outlet openings 212 of the package cap 208 above it and the inlet and outlet openings in the integrated cooling assembly 203 below it. In some specific instances, device package 201 may further include support member 207 attached to integrated cooling assembly 203, such as Figure 2D shown in.

[0058] It should be understood that openings are shown in cross-sectional views. Openings can have any cross-sectional shape that allows fluid to flow through them (e.g., rectangular, square, hexagonal, or circular cross-sections). For example, an opening 222A disposed through the sealing material layer 222 can be formed into an elongated shape extending from one side of the sealing material 222 to the other side. For example, opening 222A can be formed into any shape where the length in the XY plane is greater than the width (e.g., a rectangular or trapezoidal shape). Furthermore, it should be understood that all references to openings throughout this disclosure refer to openings defined by sidewalls (e.g., opening sidewalls).

[0059] Typically, the packaging substrate 202 includes a rigid material, such as epoxy resin or a resin-based laminate, which supports the integrated cooling assembly 203 and the package cover 208. The packaging substrate 202 may include conductive features disposed in or on the rigid material that electrically couple the integrated cooling assembly 203 to a system panel, such as a PCB 102.

[0060] Figure 2D For along Figure 2C A schematic cross-sectional view of device package 201 in the XZ plane, taken by line A-A'. (See figure) Figure 2D As illustrated, the integrated cooling assembly 203 typically includes a semiconductor stack, referred to herein as stack 204. Here, semiconductor stack 204 includes several semiconductor devices vertically stacked (in the Z-axis direction). Adjacent semiconductor devices include alignment and attachment surfaces. For example, the front side of a second semiconductor device is aligned and attached to the back side of a first semiconductor device below it. Each semiconductor device in semiconductor stack 204 includes an active side 218, which includes device components (e.g., transistors, resistors, and capacitors) formed thereon or therein, and a non-active side (here, semiconductor device back side 220) opposite the active side 218. As shown, the active side 218 is positioned adjacent to and facing the package substrate 202. The active side 218 can be electrically connected to the package substrate 202 by means of conductive bumps 219, which are encapsulated by a first bottom fill layer 221 disposed between the integrated cooling assembly 203 and the package substrate 202. The first bottom filler layer 221 may comprise a cured polymer resin or epoxy resin, which provides mechanical support for the conductive bumps 219 and prevents thermal fatigue. In some specific examples, the active side 218 may be electrically connected to another package substrate, another active die, or another passive die (e.g., an interposer) using hybrid bonding or conductive bumps 219. An integrated cooling assembly 203 may be disposed on the package substrate 202, wherein bottom semiconductor devices (e.g., bottom semiconductor devices of a device stack) are attached to the package substrate 202 (e.g., the front side of the bottom semiconductor device in the stack 204 is attached to the substrate 202).

[0061] Figure 2E for Figure 2C A schematic cross-sectional view of a semiconductor stack 204 in the ZY plane. The semiconductor stack 204 may include a first semiconductor device 204A and a second semiconductor device 204B vertically stacked on top of the first semiconductor device 204A. The semiconductor stack 204 may include spacers 260A and 260B that extend between opposing surfaces of the first and second semiconductor devices to space the first semiconductor device 204A and the second semiconductor device 204B.

[0062] Spacers 260A and 260B can be formed of any suitable material having sufficient structural strength to withstand the expected pressure of the coolant flowing through them. For example, spacers 260A and 260B can be formed of semiconductor materials (such as silicon) or other engineered materials (such as glass). For example, spacers 260A and 260B can be formed of materials selected from the group consisting of polymers, metals, ceramics, or composites thereof. In some specific examples, spacers 260A and 260B can be formed of stainless steel (e.g., from a stainless steel sheet) or sapphire plate. In some specific examples, spacers 260A and 260B can be formed of materials having a coefficient of thermal expansion (CTE) substantially different from the bulk material of the semiconductor device of substrate 202 and / or stack 204 (e.g., materials with mismatched CTE), where CTE is the fractional change in length (in the XY plane) of the material for each degree of temperature change. In these specific examples, spacers 260A and 260B may be attached between semiconductor devices by means of a compliant adhesive layer (not shown) or a molding material that absorbs the expansion differences between spacers 260A and 260B and the semiconductor devices during repeated thermal cycling. In some specific examples, the CTE of spacers 260A and 260B, substrate 202, and / or semiconductor stack 204 is matched such that when measured within a desired temperature range, the CTE of substrate 202 and / or semiconductor stack 204 falls within about + / -20% or less of the CTE of spacers 260A and 260B, such as within + / -15% or less, within + / -10% or less, or within about + / -5% or less. In some specific examples, the CTE is matched over a temperature range from about -60°C to about 100°C or from about 60°C to about 175°C. In a specific instance, the matched CTE materials each include silicon.

[0063] Spacers 260A and 260B can be attached between the opposing surfaces of the first semiconductor device 204A and the second semiconductor device 204B without the use of an intermediate adhesive material. For example, spacers 260A and 260B can be directly bonded, such that spacers 260A and 260B, the back side of the first semiconductor device, and the front side of the second semiconductor device (i.e., the opposing surfaces of the first semiconductor device 204A and the second semiconductor device 204B) are in direct thermal contact. For example, in some specific embodiments, one or all of spacers 260A and 260B, the back side 220 of the first semiconductor device, and the front side 218 of the second semiconductor device may comprise a dielectric material layer, and spacers 260A and 260B are directly bonded to the opposing surfaces of the first semiconductor device 204A and the second semiconductor device 204B by bonding formed between the dielectric material layers. In some specific examples, the opposing surfaces of one or the first semiconductor device 204A and the second semiconductor device 204B of spacers 260A and 260B may include a thin bonding dielectric layer (e.g., silicon nitride, etc.), and other components may not include any such defined bonding dielectric layer (or may only have a native oxide layer). For example, a first dielectric material layer 228A may be disposed on the upper surface of spacers 260A and 260B facing the front side of the second device, and a second dielectric material layer 228C may be disposed on the lower surface of spacers 260A and 260B facing the back side of the first device. Furthermore, a third dielectric material layer and a fourth dielectric material layer 228B may be disposed on the front side of the second device and the back side of the first device, respectively. Dielectric material layers 228A, 228B, and 228C may be continuous or discontinuous. In a specific example of forming spacers on the surface of a semiconductor device using lithography, only one surface of spacers 260A and 260B has a dielectric material layer disposed thereon, and only one side of the device has a dielectric material layer disposed thereon. Spacers 260A and 260B can then be directly bonded to the back side of the first semiconductor device and / or the front side of the second semiconductor device by means of bonding formed between the dielectric material layers.

[0064] In some specific instances, the back side of the first semiconductor device 204A may be etched to form a cavity sidewall to define a cooling channel. In such specific instances, spacers 260A and 260B are replaced by the cavity sidewall, and the second semiconductor device is directly bonded to the upper surface of the cavity sidewall using a dielectric material layer, as discussed above.

[0065] Hybrid bonding techniques can be used to attach spacers 260A and 260B between devices, wherein bonding is formed between dielectric material layers and between metal features, such as between a first metal pad and a second metal pad disposed in dielectric material layers 228A, 228B, and 228C. In some specific examples, the metal pad may be the upper portion of a conductive via.

[0066] Advantageously, as described above, directly bonding spacers 260A and 260B to the opposing surfaces of the first semiconductor device 204A and the second semiconductor device 204B reduces the thermal resistance between them and increases the heat transfer efficiency from the semiconductor devices 204A and 204B to the spacers 260A and 260B.

[0067] Suitable dielectrics that can be used as dielectric layers 228A, 228B, and 228C include silicon oxide, silicon nitride, silicon oxynitride, silicon nitride carbon, metal oxides, metal nitrides, silicon carbide, silicon carbon oxynitride, silicon carbonitride, diamond-like carbon (DLC), or combinations thereof. In some specific instances, one or both of the dielectric layers are formed of inorganic dielectric materials (e.g., dielectric materials that are substantially free of organic polymers). Typically, one or both of the dielectric layers are deposited to a thickness greater than that of the native oxide, such as about 1 nanometer (nm) or greater, 5 nm or greater, 10 nm or greater, 50 nm or greater, 100 nm or greater, or 100 nm or greater. In some specific instances, one or both of the layers are deposited to a thickness of 300 nm or less, such as 100 nm or less, 100 nm or less, or 50 nm or less.

[0068] Spacers 260A and 260B, along with the opposing surfaces of the first and second semiconductor devices, collectively define a cooling channel 270 therebetween. Here, inlet and outlet openings are formed between the sidewalls of spacers 260A and 260B and the opposing surfaces of the semiconductor devices, as discussed in more detail below. The cooling channel 270 is in fluid communication with the inlet and outlet openings. Spacers 260A and 260B each include through-holes 261A and 261B, electrically connecting the first semiconductor device 204A and the second semiconductor device 204B. It should be understood that in other specific embodiments, only one of spacers 260A and 260B may include a through-hole. As discussed in more detail below, photolithography can be used to form through-holes through the spacers to create a conductive channel through which the first and second semiconductor devices can transmit signals. The first semiconductor device 204A may include one or more electronic components with relatively high power dissipation rates, such as computing cores, neural cores, or graphics processing units. The second semiconductor device 204B may include one or more electronic components with relatively low power dissipation rates, such as memory cells, I / O cells, PHY cells, or analog cells.

[0069] The package cover 208 typically includes one or more vertical or inclined sidewall portions 208A and a lateral portion 208B that spans and connects to the sidewall portions 208A. The sidewall portions 208A may extend upward from the peripheral surface of the package substrate 202 to surround the integrated cooling assembly 203 disposed thereon. The lateral portions 208B may be disposed above the integrated cooling assembly 203 and are typically spaced apart from the integrated cooling assembly 203 by a gap corresponding to the thickness of the sealing material layer 222. Coolant circulates in the cooling channel 270 through package cover inlet and outlet openings 212 formed through the lateral portions 208B. The inlet and outlet openings of the integrated cooling assembly 203 may be in fluid communication with the inlet and outlet openings of the package cover 208 through openings formed in the sealing material layer disposed therebetween. In the specific examples described herein, coolant line 108 may be attached to device package 201 by means of connector features formed in package cover 208, such as threads formed in the sidewall of package cover inlet / outlet opening 212 and / or protruding features 214 surrounding opening 212 and extending upward from the surface of transverse portion 208B.

[0070] Typically, the package cover 208 is formed of a semi-rigid or rigid material such that at least a portion of the downward force exerted by the mounting frame on the package cover 208 is transferred to the support surface of the package substrate 202, rather than to the underlying semiconductor stack 204. In some specific examples, the package cover 208 is formed of a thermally conductive metal, such as aluminum or copper. In some specific examples, the package cover 208 functions as a heat sink, redistributing heat from one or more electronic components within a multi-component device package, as described below.

[0071] refer to Figure 2E Spacers 260A and 260B are in a direction orthogonal to the surface opposite to the semiconductor device (i.e., Figure 2D The thickness along the Z-axis (in the form of vias) can be less than 200 μm. In another specific example, the thickness can be less than or equal to 100 μm. This has the advantage of reducing the impedance and spacing of vias 261A and 261B, and increasing the density of vias. The increased density is beneficial for I / O connections.

[0072] In some specific examples, the opposing surfaces of the first semiconductor device 204A and the second semiconductor device 204B include a corrosion-resistant layer (not shown). The corrosion-resistant layer may be a continuous layer covering the entire surface of the first semiconductor device 204A and the second semiconductor device 204B. Advantageously, the corrosion-resistant layer provides a corrosion-resistant barrier layer, thus preventing undesirable corrosion of the first semiconductor device 204A and the second semiconductor device 204B, for example, where the semiconductor substrate material might otherwise be in direct contact with the coolant fluid flowing through the cooling channel 270.

[0073] In some specific instances, the height of the cooling channel 270 in the Z-axis direction may be greater than 100 μm, 100 μm to 1000 μm, or 100 μm to 700 μm. The width of the cooling channel 270 in the Y-axis direction may be greater than 100 μm, 100 μm to 1000 μm, or 100 μm to 700 μm. For example, the width of the cooling channel 270 may be greater than its height. The coolant chamber volume and / or the cross-section of the coolant channel in the YZ plane are sufficiently wide to allow pressure drops of 0 to 20 psi, 3 to 15 psi, or 4 to 10 psi.

[0074] Figure 3 This is a schematic cross-sectional view of a semiconductor stack 304 according to another specific example. Semiconductor stack 304 is similar to semiconductor stack 204, and therefore the same elements in semiconductor stack 304 are given the same reference numerals as those in semiconductor stack 204. For simplicity, the description of these elements is not repeated. The difference between semiconductor stack 304 and semiconductor stack 204 lies in the portion where spacers 360A and 360B form an interposer layer. The interposer layer forming spacers 360A and 360B may extend laterally beyond the vertical sidewalls of semiconductor stack 304 (e.g., ...). Figure 3 (As shown by the dashed lines in the diagram), to connect the devices of the semiconductor stack 204 to additional electronic components, circuits, or chips. An interposer can be considered a thin, flat substrate, typically made of silicon or organic materials, that acts as an intermediary between multiple semiconductor devices or dies, enabling these devices or dies to communicate and function together. The interposer acts as a bridge, connecting the electrical, signal, and power paths of the semiconductor devices.

[0075] Figure 4This is a schematic cross-sectional view of a semiconductor stack 404 according to another specific example. The semiconductor stack 404 may include a first semiconductor device 404A and a second semiconductor device 404B vertically stacked on top of the first semiconductor device 404A. The semiconductor stack 404 may include a first spacer 460A, a second spacer 460B, and a third spacer 460C, which extend between opposing surfaces of the first semiconductor device 404A and the second semiconductor device 404B to space them apart. The first spacer 460A and the third spacer 460B are disposed on opposing edges of the first semiconductor device 404A and the second semiconductor device 404B. That is, the semiconductor device is rectangular in shape, having a first pair of parallel opposing edges and a second pair of parallel opposing edges orthogonal to the first pair of edges. Therefore, the first spacer 460A and the third spacer 460B may be disposed along either the first pair of parallel opposing edges or the second pair of parallel opposing edges. The second spacer 460C is disposed across the center alignment region of the first semiconductor device 404A and the second semiconductor device 404B. For example, the second spacer 460C may be disposed between the first spacer 460A and the third spacer 460B (e.g., at an equidistant distance from each of the first spacer 460A and the third spacer 460B). The first spacer 460A and the second spacer 460C, together with adjacent portions of the opposing surfaces of the first semiconductor device 404A and the second semiconductor device 404B located above and below the first spacer 460A and the second spacer 460C, together define a first cooling channel 470A therebetween. The second spacer 460B and the third spacer 460C, together with adjacent portions of the opposing surfaces of the first semiconductor device 404A and the second semiconductor device 404B located between the second spacer 460B and the third spacer 460C, together define a second cooling channel 470B therebetween. The first spacer 460A, the second spacer 460B, and the third spacer 460C respectively include through-holes 461A, 461B, and 461C, and the through-holes 461A, 461B, and 461B are electrically connected to the first semiconductor device 404A and the second semiconductor device 404B. It should be understood that in other specific embodiments, one or more of the spacers 460A, 460B, and 460C may not include through-holes. It should also be understood that the spacers are illustrated herein as each including three through-holes. However, it should be understood that the spacers may each include fewer through-holes, and in some specific embodiments, each spacer may include a single through-hole.

[0076] In some specific examples, the semiconductor stack 404 may include more than three spacers disposed between opposing surfaces of the semiconductor device. For example, the semiconductor stack 404 may include four, five, or more spacers. Furthermore, the semiconductor stack 404 may include more than two cooling channels formed between the spacers, such as three, four, or more cooling channels. This is advantageous because it increases the surface area in contact with the coolant fluid. Additionally, the extra spacers can provide enhanced structural support.

[0077] In some specific instances, one or more spacers may not be along the width of the semiconductor stack 404 (i.e., in...). Figure 2B The spacers are spaced at equal distances along the Y-axis. For example, the distance between the first and second spacers may be less than the distance between the second and third spacers. In this way, the width of the cooling channel formed between the first and second spacers may be narrower than the width of the cooling channel formed between the second and third spacers. As an example, this allows a larger portion of the coolant fluid to be directed to the region of the semiconductor stack 404 with higher heat dissipation power.

[0078] Figure 5 A perspective view of a semiconductor stack 404 according to a specific example is illustrated. First arrow 471A and second arrow 471B indicate the directions of coolant fluid paths passing through respective first cooling channels 470A and second cooling channels 470B. In some specific examples, the coolant fluid paths may be part of the same coolant circuit. Alternatively, in another specific example, the fluid paths may be part of different coolant circuits.

[0079] Regarding the spacer discussed in this specific example, in a direction parallel to the opposite surfaces of semiconductor devices 404A and 404B (i.e., Figure 2B The width of the cooling channel (in the Y-axis direction) can be less than 500 micrometers. The height of the cooling channel can be determined by the direction of the spacer orthogonal to the opposite surfaces of semiconductor devices 404A and 404B (i.e., Figure 2B The thickness is defined along the Z-axis. In some specific instances, the width-to-height aspect ratio of the cooling channel can be 100:1. This can be advantageous because a cooling channel with a relatively wide aspect ratio (e.g., a channel cross-section with a large width and a small height) ensures that the coolant flowing through it maintains a relatively high fluid pressure.

[0080] Table 1:

[0081] Table 1 above provides information related to... Figure 4The exemplary parameters of the semiconductor stack 404 shown in Figure A are similar to those of a semiconductor stack including three spacers. In the table above, "L" represents the length, "W" represents the width, and "t" represents the thickness of the top die (e.g., the second semiconductor device 404B), the bottom die (e.g., the first semiconductor device 404A), or the spacers (e.g., spacers 460A, 460B, and 460C). Power is the output power associated with each die during operation, and power density is the output per unit surface area. In this specific example, the aspect ratio of the cooling channel width to height is 42.5:1 (42.5:1). As can be understood from Table 1, this is because the width of the upper and lower dies is 10 mm, and the width of each spacer is 0.5 mm. The presence of three spacers means that when the spacers are configured in a manner similar to... Figure 4 When the semiconductor stack 404 shown in Figure A is similar, the spacers occupy 1.5 mm of the total width, and 8.5 mm of the total width forms cooling channels between the spacers. Therefore, each cooling channel has a width of 4.25 mm and a height of 0.1 mm (spacer height), resulting in a width-to-height aspect ratio of 42.5:1. In some specific examples, the width-to-height aspect ratio of the cooling channels can be 100:1 (100:1).

[0082] Figure 6 This is a schematic cross-sectional view of an integrated cooling assembly 603 according to a specific example. The cooling assembly 603 may include a semiconductor stack 604 disposed on a substrate 602 and a heat sink 606 disposed on the semiconductor stack 604. The semiconductor stack 604 may include a first semiconductor device 604A, a second semiconductor device 604B, a third semiconductor device 604C, and a fourth semiconductor device 604D, each semiconductor device being vertically stacked on top of each other to form a three-dimensional (3D) semiconductor stack. The semiconductor stack 604 may include a first spacer 660A, a second spacer 660C, and a third spacer 660B, these spacers extending between opposing surfaces of the first and second semiconductor devices to space the first semiconductor device 604A and the second semiconductor device 604B apart. Figure 4Similar to the specific example described in A, the first spacer 660A and the third spacer 660B are disposed on opposite sides of the first semiconductor device 604A and the second semiconductor device 604B, and the second spacer 660C is disposed across the center alignment region of the first semiconductor device 604A and the second semiconductor device 604B. The first spacer 660A and the second spacer 660C, along with the adjacent portions of the opposite surfaces of the first and second semiconductor devices, together define a cooling channel 670A. The second spacer 660B and the third spacer 660C, along with the adjacent portions of the opposite surfaces of the first and second semiconductor devices, together define a cooling channel 670B therebetween. The first spacer 660A, the second spacer 660B, and the third spacer 660C each include a first through-hole 661A, a second through-hole 661B, and a third through-hole 661C, which electrically connect the first semiconductor device 604A and the second semiconductor device 604B. It should be understood that in other specific embodiments, one or more of spacers 660A, 660B, and 660C may not include through-holes. In some specific embodiments, only the second spacer 660C, which spans the center alignment region of the first semiconductor device 604A and the second semiconductor device 604B, includes through-holes.

[0083] Arrows 650A, 650B, and 650C illustrate the possible directions of heat propagation generated by semiconductor devices 604A to 604C. Most of the heat generated by semiconductor devices 604A and 604B can propagate towards and be transferred to cooling channels 670A and 670B, while most of the heat generated by semiconductor devices 604C and 604D can propagate to and be transferred to heat sink 606. In this way, heat generated in all layers of semiconductor stack 604 is effectively removed.

[0084] In some specific examples, the integrated cooling assembly comprising a semiconductor stack according to any prior embodiment may further include: an inlet opening and an outlet opening disposed between spacers, and a cooling channel in fluid communication with the inlet opening and the outlet opening. In some specific examples, the semiconductor stack according to any prior embodiment includes: a first spacer including an inlet opening and a second spacer including an outlet opening, and a cooling channel in fluid communication with the inlet opening and the outlet opening. That is, the inlet opening may be formed within the first spacer, and the outlet opening may be formed within the second spacer (e.g., by patterning the spacers and etching the respective openings). Here, the semiconductor stack 604 is illustrated as having four semiconductor devices 604B to 604E disposed above the cooling channel 670B and one semiconductor device 604A disposed below the cooling channel 670B. However, it should be understood that any number of semiconductor devices may be disposed above and / or below the cooling channel 670B. For example, several semiconductor devices may be disposed below the cooling channel 670B, and a single semiconductor device may be disposed above the cooling channel 670B. Alternatively, several semiconductor devices may be disposed both above and below the cooling channel 670B. This facilitates the extraction of heat (i.e., thermal energy) from between semiconductor devices at lower positions in the semiconductor stack, which would otherwise be difficult to cool. Furthermore, providing cooling channels between semiconductor devices in the semiconductor stack while minimizing the height of the cooling channels encourages the formation of vias in spacers with relatively short lengths to achieve optimal performance.

[0085] Figure 7This is a schematic cross-sectional view of a semiconductor stack 704 according to a specific example of the present disclosure. The semiconductor stack 704 may include a first semiconductor device 704A and a second semiconductor device 704B vertically stacked on top of the first semiconductor device 704A. The first semiconductor device 704A may include a first sidewall 760A and a second sidewall 760B extending upward to the second semiconductor device 704B to define a cavity volume. It should be understood that the first and second sidewalls may form portions of a single sidewall extending around the periphery of the first semiconductor device 704A. The first sidewall 760A and the second sidewall 760B, a lower surface (e.g., front side) of the second semiconductor device 704B facing the cavity volume, and an upper surface (e.g., back side) of the first semiconductor device 704A together define a cooling channel 770 therebetween. Sidewalls 760A and 760B may include vias 761A and 761B electrically connecting the first semiconductor device 704A and the second semiconductor device 704B. The first semiconductor device 704A may include one or more electronic components with relatively high power dissipation rates, such as computing cores, neural cores, or graphics processing units. The second semiconductor device 704A may include one or more electronic components with relatively low power dissipation rates, such as memory cells, I / O cells, PHY cells, or analog cells. Therefore, Figure 7 The cooling channel 770 shown in the figure differs from the previous cooling channel in that it is actually formed in the body of the first semiconductor device 704A by etching.

[0086] It should be understood that, although Figure 7 The illustration shows two sidewalls 760A and 760B forming a cavity volume, but this is not limiting, and in other specific embodiments, the first semiconductor device may include more than two sidewalls, such as three, four, or more sidewalls. An additional sidewall may be formed between sidewalls 760A and 760B. The sidewalls may form more than one cavity volume, such as two, three, or more cavity volumes, and the cavity volumes may form more than one cooling channel, such as two, three, or more cooling channels.

[0087] Figure 8This is a schematic cross-sectional view of a semiconductor stack 804 according to another specific example. Semiconductor stack 804 is similar to semiconductor stack 704, and therefore the same elements in semiconductor stack 804 are given the same reference numerals as those in semiconductor stack 704. For simplicity, a description of these elements is not repeated. The difference between semiconductor stack 804 and semiconductor stack 704 is that the lower surface of the first semiconductor device 704B includes channel sidewalls extending into the first semiconductor device to define at least one recess 806 (e.g., by etching). This has the advantage of increasing the surface contact area between the cooling fluid and the first semiconductor device 804A, which improves cooling efficiency. Furthermore, the coolant fluid penetrates deeper into the first semiconductor device 804A, further improving heat exchange between the coolant fluid and the first semiconductor device 804A.

[0088] In some specific examples, the thickness of the opposing sidewalls in the direction orthogonal to the lower surface of the second semiconductor device is less than 200 micrometers, or less than or equal to 100 micrometers. This has the advantage of reducing the impedance and spacing of the vias disposed in the sidewalls, and increasing the number density of vias.

[0089] Figure 9A For another specific instance Figure 2B A schematic cross-sectional view of a semiconductor stack 904 in the XZ plane. Figure 9B A 3D view of a 904 semiconductor stack is shown. (Reference) Figure 9A and Figure 9BThe semiconductor stack 904 may include one or more spacers similar to those according to any of the preceding specific examples. However, for simplicity, spacers are not shown. The spacers may extend laterally between opposing first and second edges of the semiconductor stack 904 in a first direction (i.e., in the X-axis direction). The semiconductor stack 904 further includes a first semiconductor device 904A, a second semiconductor device 904B, a cooling channel 970, reconstructed wafer portions 905 and 906, and edge supports 910A and 910B. At least one spacer may include a via electrically connecting the first semiconductor device 904A and the second semiconductor device 904B. The width of the second semiconductor device 904B in the first direction is smaller than the width of the first semiconductor device 904A in the same direction. The reconstructed wafer portion may be a portion of a reconstructed wafer or a dummy die. A dummy die may include a non-operating die, filler (encapsulation) material, a portion of a reconstructed wafer, a blank carrier, and / or the like. A reconstructed wafer portion is disposed orthogonal to a first direction (i.e., perpendicular to the first direction, in other words, orthogonal to the direction in which the spacer extends or the length of the spacer) on and across the spacer. A second semiconductor device is disposed between the reconstructed wafer portions. The second semiconductor device and the reconstructed wafer portions can form a reconstructed wafer and can be surrounded by a molding compound (e.g., epoxy resin) during the reconstructing process. The reconstructed wafer portions may include a first reconstructed wafer portion 905 and a second reconstructed wafer portion 906. Edge supports 910A and 910B can extend between the spacers along the edges of the semiconductor stack 904 perpendicular to the first direction. The first reconstructed wafer portion 905 is disposed on the first edge support 910B, and the second reconstructed wafer portion 906 is disposed on the second edge support 910A. The reconstructed wafer is considered to be a wafer comprising a die, a die interconnect, and a molding compound. For example, a semiconductor wafer can be monolithized into a die, and a molding compound can be disposed around the die to form a reconstructed wafer. Dies can be arranged in a layout according to the desired spacing between them. In some specific instances, the molded component is a dielectric layer. Reconstructing dies to form a reconstructed wafer allows dies previously monolithized from a wafer to be molded into a new wafer (i.e., a reconstructed wafer).

[0090] The first edge support 910A and the second edge support 910B can be formed in a manner similar to that of the spacer, as discussed in more detail below.

[0091] The first reconstructed wafer portion 905 may include an inlet opening 905A, and the second reconstructed wafer portion 906 may include an outlet opening 906A, with a cooling channel in fluid communication with both the inlet opening 905A and the outlet opening 906A. The inlet opening 905A and the outlet opening 906A may be formed using an etching process. (Reference) Figure 2C and Figure 2DThe inlet opening 905A is in fluid communication with the inlet opening of the encapsulation cover 208 and the inlet opening of the sealing material layer 222, and the outlet opening 906A is in fluid communication with the outlet opening of the encapsulation cover 208 and the outlet opening of the sealing material layer 222. Therefore, coolant fluid can enter through the inlet opening 905A, flow through the cooling channel 970, and flow out through the outlet opening 906A.

[0092] Figure 10 For another specific instance Figure 2B A schematic cross-sectional view of semiconductor stack 1004 in the XZ plane. Semiconductor stack 1004 is similar to semiconductor stack 904, and therefore the same elements in semiconductor stack 1004 are given the same reference numerals as those in semiconductor stack 904. For simplicity, the description of these elements is not repeated. The difference between semiconductor stack 1004 and semiconductor stack 904 is that semiconductor stack 1004 includes a first semiconductor device 1004A, which includes cavity sidewalls 1010A, 1010B extending vertically in a first direction (i.e., in the Y-axis direction). Cavity sidewalls 1010A, 1010B extend upward toward reconstructed wafer portions 905, 906, on which reconstructed wafer portions 905, 906 are disposed. The cavity sidewalls can be formed by using an etching process on the back side of the first semiconductor device 1004A. It should be understood that a perspective view of semiconductor stack 1004 can be similar to... Figure 9B The three-dimensional view of the semiconductor stack 904 shown in the figure shows that the sidewalls of the semiconductor stack 1004 extend toward the reconstructed wafer portions 905 and 906, and the reconstructed wafer portions 905 and 906 are disposed thereon.

[0093] Figure 11 A method 1100 for packaging a device according to one or more specific examples. In step 1101, fluid is supplied via cooling channels to directly cool the semiconductor stack. For example, refer to... Figure 2C and Figure 2D Coolant fluid can be supplied (e.g., delivered) from coolant line 108 to the inlet opening of package cap 208 and the inlet opening of sealant layer 222. The coolant fluid can then pass through cooling channels 270 within semiconductor stack 204. The coolant fluid can then flow out through the outlet opening of package cap 208 and the outlet opening of sealant layer 222 and into coolant line 108.

[0094] In some specific instances, the supply fluid may include different types of cooling fluid. For example, the fluid may include a mixture of water and ethylene glycol.

[0095] Figure 12A method 1200 for manufacturing an apparatus package according to one or more specific examples. At step 1201, the method includes forming a spacer on a first semiconductor device. For example, a lithography process can be used to form the spacer. At step 1202, the spacer, the first semiconductor device, and the second semiconductor device are etched to form a through-hole. The etching process may include using a patterned mask layer, and the anisotropic etching process uses substantially different etch rates for silicon material exposed to anisotropic etchants during the formation of the patterned mask layer.

[0096] In some specific instances, the etching process is controlled such that the etch rate of the exposed silicon material has a ratio between approximately 1:10 and approximately 1:200, for example, between approximately 1:10 and approximately 1:100, for example, between approximately 1:10 and 1:50, or between approximately 1:25 and 1:75. Examples of suitable anisotropic wet etchants include aqueous solutions of potassium hydroxide (KOH), ethylenediamine and catechol (EPD), ammonium hydroxide (HN4OH), hydrazine (N2H4), or tetramethylammonium hydroxide (TMAH). The actual different etch rates depend on the concentration of the etchant in the aqueous solution, the temperature of the aqueous solution, and the concentration of dopants in the substrate (if present).

[0097] Typically, the masking layer is formed of a material that exhibits selective anisotropic etching compared to the underlying monocrystalline silicon substrate. Examples of suitable masking materials include silicon oxide (SixOy) or silicon nitride (SixNy). In some specific instances, the masking layer has a thickness of about 100 nm or less, such as about 50 nm or less, or about 30 nm or less. The masking layer can be patterned using any suitable combination of lithography and material etching patterning methods.

[0098] At step 1203, a conductive material (e.g., a metal, such as copper) is deposited in the via. At step 1204, a second semiconductor device is directly bonded to the upper surface of the spacer to form an integrated cooling assembly including a cooling channel formed between the first and second semiconductor devices and an electrical connection via between the first and second semiconductor devices. The first semiconductor device may be formed on a first substrate, and the second semiconductor device may be formed on a second substrate. The substrate may include a body material and a plurality of material layers disposed on the body material. The body material may include any semiconductor material suitable for manufacturing a semiconductor device, such as silicon, silicon-germanium, germanium, group III-V semiconductor materials, group II-VI semiconductor materials, or combinations thereof. For example, in some specific instances, the substrate may include: a single-crystal wafer, such as a silicon wafer; a plurality of device components formed in or on the silicon wafer; and a plurality of interconnect layers formed above the plurality of device components. In other specific instances, the substrate may include a reconstructed substrate, for example, a substrate formed of a plurality of monolithic devices embedded in a support material. As described above, the bonding surfaces may each include a dielectric material layer, and directly bonding the surface of the spacer to the surfaces of the first and second substrates includes forming a dielectric bond between the dielectric material layers. If necessary, a mixture of dielectric bonds and metal bonds formed between metal features may be used to directly bond the spacer to the first and second substrates.

[0099] Generally, the surfaces directly bonded (dielectric material layers) include fabrication, alignment, and contact surfaces. Fabrication of surfaces may include: smoothing individual surfaces to achieve desired surface roughness, such as between 0.1 nm RMS and 3.0 nm RMS; activating surfaces to weaken or open chemical bonding in the dielectric material; and terminating surfaces with desired species. Surface smoothing may include polishing the substrate and spacers using a chemical mechanical polishing (CMP) process. Terminating and activating surfaces with desired species may include exposing the surface to free radical species formed in the plasma.

[0100] In some specific instances, a nitrogen-containing gas (e.g., N2) is used to form the plasma, and the terminating species include nitrogen and hydrogen. In some specific instances, a wet cleaning process can be used, such as activating the surface by exposing it to an aqueous ammonia solution. In some specific instances, dielectric bonding can be formed using dielectric material layers deposited between semiconductor devices. In other specific instances, direct dielectric bonding can be formed by directly contacting the deposited dielectric material layer with the surface of the semiconductor device's body material.

[0101] Forming a direct dielectric bond between a spacer and a semiconductor device involves bringing the prepared and aligned surfaces into direct contact at temperatures below 150°C (e.g., below 100°C, for example, below 30°C; or approximately room temperature, for example, between 20°C and 30°C). Without being bound by theory, it is understood that hydrogen-termining species diffuse from the interface bonding surfaces, and chemical bonding forms between the remaining nitrogen species during the direct bonding process. In some specific examples, an annealing process is used to enhance the direct bond, wherein the substrate and spacer are heated to and maintained at a temperature greater than about 30°C and less than about 450°C (e.g., greater than about 50°C and less than about 250°C, or about 150°C) for a duration of about 5 minutes or longer, such as about 15 minutes. Typically, the bond strengthens over time even without the application of heat. Therefore, in some specific examples, the method does not involve heating the semiconductor device.

[0102] After dielectric bonding is formed, the integrated cooling assembly can be heated to 150°C or higher and maintained at the elevated temperature for approximately one hour or longer (e.g., between 8 and 24 hours) to form a direct metallurgical bond between the metallic features. Suitable direct dielectric and hybrid bonding technologies that can be used to perform the methods described herein include ZiBond® and DBI®, both commercially available from Adeia Holding, Inc., San Jose, California, USA.

[0103] In some specific examples, at step 1201, forming a spacer on the first semiconductor device involves depositing an interposer on the first semiconductor device and etching a central portion of the interposer disposed between opposing surfaces of the device to form a spacer. The remaining portion of the interposer may extend around the periphery of the semiconductor stack to form the spacer and provide means for interconnection with external devices (e.g., by extending through the sidewalls of device cover 208). The centrally etched portion of the interposer forms a cooling channel through which coolant fluid can flow.

[0104] Figure 13A method 1300 for manufacturing an apparatus package according to one or more specific examples. The method includes: at step 1201, etching a surface of a first semiconductor device to form a cavity sidewall defining a cavity volume (e.g., a cooling channel); at step 1302, etching the cavity sidewall, the first semiconductor device, and a second semiconductor device to form a via; at step 1303, depositing a conductive material in the via; and at step 1304, directly bonding the second semiconductor device to the upper surface of the cavity sidewall to form an integrated cooling assembly including a cooling channel formed between the first and second semiconductor devices and an electrical connection via between the first and second semiconductor devices. The second semiconductor device can be bonded to the upper surface of the cavity sidewall using the direct bonding procedure described above with respect to method 1200.

[0105] The specific examples discussed above are intended to be illustrative and not limiting. Those skilled in the art will understand that individual aspects of the cooling assemblies, device packages, and methods discussed herein can be omitted, modified, combined, and / or reconfigured without departing from the scope of this disclosure.

Claims

1. A device package comprising: An integrated cooling assembly comprising semiconductor stacks and cooling channels, wherein: The semiconductor stack contains: A first semiconductor device and a second semiconductor device vertically stacked on the first semiconductor device; and A spacer extends between the opposing surfaces of the first and second semiconductor devices to space the first semiconductor device from the second semiconductor device; These spacers and the opposing surfaces of the first and second semiconductor devices together define the cooling channel; and These spacers include through-holes that electrically connect the first semiconductor device and the second semiconductor device.

2. The device package of claim 1, wherein the thickness of the spacers in a direction orthogonal to the opposite surfaces of the semiconductor devices is less than 200 micrometers.

3. The device package of claim 1, wherein the thickness of the spacers in a direction orthogonal to the opposite surfaces of the semiconductor devices is less than or equal to 100 micrometers.

4. The device package of any one of claims 1 to 3, wherein the spacers form portions of an interposer layer disposed between the first semiconductor device and the second semiconductor device.

5. The device package of claim 4, wherein the interposer extends at least beyond the edge of the first semiconductor device and / or the edge of the second semiconductor device.

6. The device package according to any one of claims 1 to 5, wherein: These spacers extend laterally along a first direction between opposing first and second edges of the semiconductor stack; The width of the second semiconductor device in the first direction is smaller than the width of the first semiconductor device in the same direction.

7. The device package of claim 6, wherein the semiconductor stack further comprises: The first and second reconstructed wafer portions are disposed on these spacers (not shown) and cross these spacers in a direction orthogonal to the first direction; The second semiconductor device is disposed between these first and second reconstructed wafer portions.

8. The device package of claim 6, wherein: The first reconstructed wafer portion includes an inlet opening, and the second reconstructed wafer portion includes an outlet opening; and The cooling channel is in fluid communication with the inlet opening and the outlet opening.

9. The device package according to any one of claims 1 to 6, wherein: The integrated cooling assembly includes inlet and outlet openings disposed between these spacers; and The cooling channel is in fluid communication with the inlet opening and the outlet opening.

10. The device package of any one of claims 1 to 9, wherein the width of the spacers is less than 500 micrometers in a direction parallel to the opposing surfaces of the semiconductor devices.

11. The device package of any one of claims 1 to 10, wherein the thickness of the spacers defines the height of the cooling channel in a direction orthogonal to the opposite surfaces of the semiconductor devices.

12. The device package according to any one of claims 1 to 10, wherein: The width of the cooling channel is defined by the distance between these spacers; The thickness of these spacers defines the height of the cooling channel in a direction orthogonal to these opposing surfaces of the semiconductor devices; and The width-to-height aspect ratio of the cooling channel is 100:

1.

13. The device package according to any one of claims 1 to 10, wherein: The width of the cooling channel is defined by the distance between these spacers; The thickness of these spacers defines the height of the cooling channel in a direction orthogonal to these opposing surfaces of the semiconductor devices; and The aspect ratio of the width to the height of the cooling channel is 42.5 to 1.

14. The device package of any one of claims 1 to 13, wherein at least one of the spacers is disposed across the center alignment region of the first semiconductor device and the second semiconductor device.

15. The device package of any one of claims 1 to 14, further comprising a liquid coolant disposed in the cooling channel.

16. The device package of any one of claims 1 to 15, wherein the cooling channel is a liquid cooling channel.

17. The device package of any one of claims 1 to 16, further comprising: A packaging substrate on which the integrated cooling assembly is disposed; A package cover, disposed on the package substrate and extending above the integrated cooling assembly, the package cover having an inlet opening and an outlet opening disposed therethrough; and A material layer is disposed between the encapsulation cover and the integrated cooling assembly, wherein The cooling channel is in fluid communication with the inlet opening and the outlet opening by means of openings configured to pass through each of the material layers.

18. A device package comprising: An integrated cooling assembly comprising semiconductor stacks and cooling channels, wherein: The semiconductor stack includes a first semiconductor device and a second semiconductor device vertically stacked on the first semiconductor device; The first semiconductor device includes opposing sidewalls that extend upwards to the second semiconductor to define a cavity volume; These opposing sidewalls, the lower surface of the second semiconductor device facing the cavity volume, and the upper surface of the first semiconductor device together define a cooling channel therebetween. and These opposing sidewalls contain vias that electrically connect the first semiconductor device and the second semiconductor device.

19. The device package of claim 18, wherein the lower surface of the first semiconductor device includes a channel sidewall extending into the first semiconductor device to define at least one recess.

20. The device package of claim 18 or 19, wherein the thickness of the opposing sidewalls in a direction orthogonal to the lower surface of the second semiconductor device is less than 200 micrometers.

21. The device package of claim 18 or 19, wherein the thickness of the opposing sidewalls in a direction orthogonal to the lower surface of the second semiconductor device is less than or equal to 100 micrometers.

22. The device package as claimed in any one of claims 20 to 21, wherein: The integrated cooling assembly includes inlet and outlet openings disposed between these opposing sidewalls; and The cooling channel is in fluid communication with the inlet opening and the outlet opening.

23. The device package of any one of claims 18 to 22, further comprising a liquid coolant disposed in the cooling channel.

24. The device package of any one of claims 18 to 23, wherein the cooling channel is a liquid cooling channel.

25. A method of packaging an apparatus as claimed in any one of claims 1 to 24, the method comprising: Semiconductor devices are directly cooled by supplying fluid through cooling channels.

26. A method of manufacturing a device package as claimed in any one of claims 1 to 17, the method comprising: Spacers are formed on the first semiconductor device. Etch these spacers, the first semiconductor device, and the second semiconductor device to form vias. Depositing conductive material in the through-hole, and The second semiconductor device is directly bonded to these spacers to form an integrated cooling assembly, wherein the integrated cooling assembly includes: A cooling channel is formed between the first semiconductor device and the second semiconductor device; and An electrical connection via is formed between the first semiconductor device and the second semiconductor device.

27. A method of manufacturing a device package as claimed in any one of claims 18 to 24, the method comprising: The surface of the first semiconductor device is etched to form the cavity sidewalls. Etch the cavity sidewalls, the first semiconductor device, and the second semiconductor device to form vias. Depositing conductive material in the through-hole, and The second semiconductor device is directly bonded to the cavity sidewalls to form an integrated cooling assembly, wherein the integrated cooling assembly comprises: A cooling channel is formed between the first semiconductor device and the second semiconductor device; and An electrical connection via is formed between the first semiconductor device and the second semiconductor device.

28. The device package of claim 1, wherein the spacers are attached to the opposing surfaces of the first and second semiconductor devices by direct dielectric bonding.

29. The device package of claim 1, wherein the spacers are attached to the opposing surfaces of the first and second semiconductor devices by direct hybrid bonding.

30. The device package of claim 1, wherein the spacers comprise silicon.

31. The device package of claim 18, wherein the first semiconductor device is attached to the second semiconductor device by direct dielectric bonding.

32. The device package of claim 18, wherein the first semiconductor device is attached to the second semiconductor device by direct hybrid bonding.

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