Stacked die extension on processor core

Abstract

Stacked die extensions on processor cores are described to improve thermal management, communication latency, and routing complexity of semiconductor devices. In one or more implementations, a stacked die semiconductor device includes a first die having a processor core and at least one second die including a processor core extension positioned above or below a portion of the processor core. In one or more implementations, a system includes a stacked die semiconductor device and a memory device. The stacked die semiconductor device has a first die including a processor core and at least one second die including a processor core extension positioned above or below a portion of the processor core. The memory device is operably coupled to the processor core extension to exchange data with the processor core.

Description

[0001] Related applications This application claims priority to U.S. Patent Application No. 18 / 622,376, filed March 29, 2024, the entire contents of which are incorporated herein by reference. Background Technology

[0002] Processing devices are typically implemented on a semiconductor die, which includes a processor core integrated with a hardware block comprising various other components that support the core's functionality. Among these other components are cache extensions or floating-point units located outside the core. The significant separation between the core and these external components results in high communication latency and increases the complexity of power and signal routing between them. When the core is geographically distant from the hardware block (e.g., cache extensions, floating-point units), overall thermal management of the processing device becomes more challenging. The core operates much hotter than the external components and requires complex heatsink designs to cool different areas of the die differently. Attached Figure Description

[0003] Figure 1 This is a block diagram of a non-limiting exemplary system that uses stacked die extensions on a processor core.

[0004] Figure 2 Non-limiting exemplary top and side views of a system having stacked die extensions on a processor core are depicted.

[0005] Figure 3 A non-limiting example of stacked die extensions on a processor core cooled by a heatsink is depicted.

[0006] Figure 4 A non-limiting example of stacked die extensions on a processor core including one or more die-to-die interconnects is described.

[0007] Figure 5 The process executed in an exemplary specific implementation of stacked die extension on a processor core is described.

[0008] Figure 6 An exemplary specific implementation of a process for forming a stacked die extension on a processor core is described. Detailed Implementation

[0009] Processing devices, such as central processing units (CPUs), graphics processing units (GPUs), accelerator units, and systems-on-a-chip (SoCs), are typically implemented on semiconductor dies. In conventional processing devices, the semiconductor die typically includes a processor core. This processor core includes various components, such as parts for L1 caches (e.g., data cache, instruction cache, cache controller, load memory). Partly surrounding the processor core are various supporting components. Typical supporting components include cache extensions (e.g., L2 cache, L3 cache) and floating-point units.

[0010] Performance in a typical system is impacted when support components are positioned on the same die as the processor core but outside the core. The greater separation between the processor core and support components results in higher communication latency and increases the complexity of power and signal routing between them. Overall thermal management of the processing device becomes more difficult because the core operates much hotter than external components, leading to an inconsistent thermal footprint across the die. Since the distal regions of the die generate less heat than the core, complex heatsink designs are used to cool the individual die regions differently.

[0011] Compared to conventional systems, a stacked die extension on a processor core is described. As an example, one system includes a processor core disposed within a first die (e.g., a main die) of a stacked die semiconductor device. In one or more embodiments, the first die is supported by a planar substrate defined by two orthogonal axes (e.g., an x-axis and a y-axis) extending in different lateral directions (e.g., the x-direction and the y-direction) on a common plane (e.g., the xy-plane). Unlike conventional systems, at least one supporting element for the core (referred to herein as a processor core extension) is stacked vertically (e.g., in the z-direction of the xy-plane) on at least one second die (e.g., a vertical die) above or below the first die. In one or more embodiments, the processor core extension is positioned within the second die. For example, processor core extensions include cache extensions (e.g., L2 cache, L3 cache), floating-point units, programmable accelerator extensions, matrix extensions for matrix mathematics, branch prediction units, artificial intelligence accelerators, audio accelerators, video accelerators, and / or cryptographic extensions for encrypting or decrypting data exchanged with the processor core. In one or more specific implementations, the use of stacked die extensions relative to the processor core stack according to the techniques described herein improves the thermal management, communication latency, and routing complexity of semiconductor devices.

[0012] Processor core extensions that stack one or more supporting elements containing the core overcome the communication and routing challenges of conventional systems. Although the stacked elements are located on dies vertically separated from the core, they are closer to the core than other elements arranged on main dies outside the core. This vertical arrangement reduces communication latency between the stacked elements and the core, as well as the complexity of power and signal routing. In one or more implementations, die-to-die interconnects are arranged between first and second dies to rapidly transfer power and signals between the processor core and the supporting elements of the processor core extension stacked above or below the first die.

[0013] Integrating processor core extensions on or under a portion of the core reduces the complexity of thermal management for stacked die semiconductor devices. In at least one aspect, a heatsink with approximately uniform thickness is added to the system on the stacked die semiconductor device to dissipate heat. Even though one or more components of the processor core extension within the second die tend to operate cooler than the core components on the first die, this simpler heatsink design is sufficient to cool the various regions of the stacked die semiconductor device because the overall thermal characteristics caused by stacking are consistent across the stacked die semiconductor device.

[0014] In some respects, the technology described herein relates to a stacked die semiconductor device including a first die and at least one second die, the first die having a processor core, and the at least one second die including a processor core extension positioned above or below a portion of the processor core.

[0015] In some respects, the technology described herein relates to a stacked die semiconductor device in which a processor core extension includes a cache extension operatively coupled to the processor core.

[0016] In some respects, the technology described herein relates to a stacked die semiconductor device, wherein the first die also includes a cache operatively coupled to a cache extension.

[0017] In some respects, the techniques described herein relate to a stacked die semiconductor device in which a cache extension is a higher-order cache than the cache within the first die.

[0018] In some respects, the technology described herein relates to a stacked die semiconductor device, wherein this portion of the processor core includes at least a portion of a cache within a first die.

[0019] In some respects, the technology described herein relates to a stacked die semiconductor device, wherein this portion of the processor core includes at least one of the following: a data cache of a cache within a first die, a load memory unit of a cache within the first die, or a load memory unit of a cache extension.

[0020] In some respects, the technology described herein relates to a stacked die semiconductor device, wherein a cache within a first die includes a first-order cache operatively coupled to a processor core, a cache extension includes a second-order cache operatively coupled to a processor core, and the stacked die semiconductor device further includes at least one third die having a third-order cache operatively coupled to a processor core.

[0021] In some aspects, the technology described herein relates to a stacked die semiconductor device that further includes a die-to-die interconnect disposed between a first die and at least one second die to transmit power and signals between a processor core and a processor core extension.

[0022] In some respects, the technology described herein relates to a stacked die semiconductor device, wherein die-to-die interconnects include at least one of microbumps, hybrid bonding elements, or through-silicon vias.

[0023] In some respects, the technology described herein relates to a stacked die semiconductor device in which a processor core extension includes a floating-point unit operatively coupled to the processor core.

[0024] In some aspects, the technology described herein relates to a system comprising: a stacked die semiconductor device including a first die and at least one second die, the first die including a processor core, the at least one second die including a processor core extension positioned above or below a portion of the processor core; and a memory device operatively coupled to the processor core extension to exchange data with the processor core.

[0025] In some respects, the technology described herein relates to a system that also includes a heat sink configured to dissipate heat energy from stacked die semiconductor devices.

[0026] In some respects, the technology described herein relates to a system in which at least one second die is positioned between a first die and a heat sink.

[0027] In some respects, the technology described herein relates to a system in which the heat sink comprises an approximately uniform thickness relative to the processor core extension and the processor core itself.

[0028] In some respects, the techniques described herein relate to a system in which a processor core extension includes a floating-point unit operatively coupled to the processor core.

[0029] In some respects, the techniques described herein relate to a system in which a processor core extension includes a cache extension operatively coupled to the processor core.

[0030] In some respects, the techniques described herein relate to a system in which a processor core extension includes at least one of the following: a programmable accelerator extension, a matrix extension for matrix mathematics, a branch prediction unit, an artificial intelligence accelerator, an audio accelerator, a video accelerator, or a cryptographic extension for encrypting or decrypting the data exchanged with the processor core.

[0031] In some aspects, the technology described herein relates to a method of forming a stacked die semiconductor device, the method comprising: integrating a processor core within a first die of the stacked die semiconductor device; disposing at least one second die of the stacked die semiconductor device above or below the first die; and extending the processor core into the at least one second die, above or below a portion of the processor core.

[0032] In some respects, the techniques described herein relate to a method in which this portion of a processor core includes a Level 1 cache and a Level 1 load memory unit, and integrating processor core extensions includes: integrating a Level 2 cache or a Level 3 cache within at least one second die, above or below the Level 1 load memory unit of the processor core.

[0033] In some respects, the technology described herein relates to a method that further includes arranging a heatsink having a near-uniform thickness adjacent to at least one second die, such that a processor core extension is located between the heatsink and the processor core.

[0034] Figure 1 This is a block diagram of a non-limiting example of a system 100 that uses stacked die extensions on a processor core. System 100 in Figure 1 The components are labeled as System 100-1, System 100-2, System 100-3, and System 100-4, respectively. Each system in System 100 represents an example of a processing device implemented on a stacked die semiconductor device referred to as Semiconductor Device 116. The components of System 100 are functionally similar; however, each system in System 100 provides a different layout to the components depending on the number of stacked die extensions used. System 100-1 represents a specific implementation that does not use stacked die extensions, and Systems 100-2, 100-3, and 100-4 are exemplary specific implementations that implement at least one stacked die extension.

[0035] It should be understood that, in variations, without departing from the spirit or scope of the described technology, system 100 and the various components exemplified therein may include more, fewer, and / or different hardware components, such as additional caches, semiconductor intellectual property (IP) cores, network interfaces, other controllers, memory devices, accelerator cores, etc. In one example, for instance, the interface with the memory device and / or accelerator device may operate in conjunction with the interface of processor core 102.

[0036] Examples of devices or apparatuses implementing system 100 include, but are not limited to, one or more server computers, personal computers (e.g., desktop or tower computers), smartphones or other wireless phones, tablets or tablet computers, laptop computers, laptop computers, wearable devices (e.g., smartwatches, augmented reality headsets or devices, virtual reality headsets or devices), entertainment devices (e.g., game consoles, portable gaming devices, streaming media players, digital video recorders, music or other audio playback devices, televisions, set-top boxes), Internet of Things (IoT) devices, automotive computers, and other computing devices or systems.

[0037] According to the described technique, each system in System 100 includes a processor core 102 and a processor core extension depicted as having a cache extension 104 and / or a floating-point unit (FPU) 106. The processor core 102 includes a first-order (e.g., Nth-order, Level 1, or simply "L1") data / instruction cache 108, a corresponding first-order cache load memory unit labeled LSU 110, and a next-order (e.g., N+1th-order, Level 2, or simply "L2") cache LSU labeled LSU 112. The cache extension 104 in each system of System 100 represents a next-order (e.g., N+1th-order, Level 2, or simply "L2") cache and includes a next-order (e.g., Level 2) cache controller 114. The cache extension 104 is a higher-order cache than the data / instruction cache 108 and, for ease of description, is referred to throughout this disclosure as an L2 cache, extending the capabilities of the L1 cache partially implemented with the data / instruction cache 108. In one or more specific implementations, cache extension 104 is a level 3 or higher cache (e.g., level 3 or "L3"), and data / instruction cache 108 is a level 2 or lower cache (e.g., L2).

[0038] Processor core 102, cache extension 104, and FPU 106 are communicatively coupled via interconnects or links (not shown for simplicity in the figures). Furthermore, one or more components of the processor core 102 (e.g., data / instruction cache 108, LSU 110, LSU 112) are communicatively coupled via interconnects or links (not shown for simplicity in the figures) to one or more components of the cache extension 104 (e.g., cache controller 114) and / or one or more components of the FPU 106.

[0039] In at least one variant, the processor core 102, cache extension 104, and FPU 106 are incorporated within the semiconductor device 116 as part of a common circuit board (e.g., a system-on-a-chip (SoC) or system-on-package (SoP)). In at least one aspect, the semiconductor device 116 uses a three-dimensional (3D) stack to support components of each system in system 100. The semiconductor device 116 includes an integrated circuit (IC) substrate located on a plurality of dies supporting multiple different chip layers containing the components of the processor core 102, cache extension 104, and FPU 106.

[0040] Processor core 102 is electronic circuitry that stores data in cache extension 104 and data / instruction cache 108 and / or performs various operations using that data. Examples of processor core 102 include, but are not limited to, processing cores of central processing units (CPUs), graphics processing units (GPUs), field-programmable gate arrays (FPGAs), accelerators, accelerated processing units (APUs), and digital signal processors (DSPs), to name just a few. Processor core 102 is a separate processing unit that reads and executes (e.g., instructions of a program), examples of which include appending, moving data, and branching. In one or more variations, processor core 102 includes multiple cores (i.e., processor core 102 is used in multi-core processors). In other variations, processor core 102 includes only one core (i.e., processor core 102 includes a single processor core).

[0041] In at least one example, cache extension 104 and data / instruction cache 108 are processor core extensions of components that store data (e.g., at least temporarily), such that future requests for data can be met more quickly from cache extension 104 or data / instruction cache 108 compared to data repositories maintained outside system 100 (e.g., in another memory not shown). For example, as an instruction cache, cache extension 104 and data / instruction cache 108 provide instructions or portions of instructions for performing functions. As a data cache, cache extension 104 and data / instruction cache 108 provide data or portions of data for performing instructions. Examples of data repositories include main memory (e.g., random access memory), caches of higher priority than cache extension 104 and data / instruction cache 108 (e.g., L3 cache when data / instruction cache 108 is an L1 cache and cache extension 104 is an L2 cache), secondary storage devices (e.g., mass storage devices), and removable media (e.g., flash drives, memory cards, optical discs, and digital video discs). In one or more specific implementations, the data / instruction cache 108 and the cache extension 104 are each at least one of the following: smaller than the data repository, providing data to the requester faster than the data repository, or providing data to the requester more efficiently than the data repository. Alternatively or additionally, such as Figure 1 As depicted, data / instruction cache 108 and cache extension 104 are each positioned closer to the requester (e.g., processor core 102) than the data repository. It should be understood that in various specific implementations, data / instruction cache 108 and cache extension 104 have additional or different characteristics that make providing at least some data to the requester from data / instruction cache 108 or cache extension 104 superior to providing such data from the data repository.

[0042] In one or more specific implementations, the data / instruction cache 108 and cache extension 104 are examples of memory caches, such as a cache at a specific level (e.g., L1 cache) included in a hierarchical structure of multiple cache levels (e.g., L0, L1, L2, L3, and L4). The data / instruction cache 108 and cache extension 104 are hardware components built into and used by the requester, for example, built into system 100 and used by processor core 102. In one or more examples, without departing from the spirit or scope of the described techniques, the data / instruction cache 108 and / or cache extension 104 are at least partially implemented in software or can be implemented in different ways.

[0043] The data / instruction cache 108 is controlled at least partially by the LSU 110. The LSU 110 coordinates data transfers between the registers or other logic units of the processor core 102 and the data / instruction cache 108. The LSU 110 uses signals to communicate with the data / instruction cache 108 to cause data to be stored in or loaded from the data / instruction cache 108. In at least one embodiment, the LSU 110 maintains one or more queues, such as a load queue (LDQ) and a store queue (STQ). When the processor core 102 executes an instruction that requires loading data from memory or a storage device, the LSU 110 calculates the load address of the instruction and inputs the calculated load address into the LDQ. If a cache hit occurs, the data at the load address is transferred from the data / instruction cache 108 to the processor core 102. When the processor core 102 executes an instruction that requires storing data in memory or a storage device, the LSU 110 generates a store address and determines the store data value, both of which are input into the STQ. If a cache hit occurs, the stored data and storage address are transferred from processor core 102 to data / instruction cache 108.

[0044] LSU 112 shares similar functionality with LSU 110 for controlling operations performed using cache extension 104. LSU 112 tends to be slower than LSU 110. LSU 110 is well-suited for performing low-latency, high-bandwidth operations that improve the performance of processor core 102. Conversely, LSU 112 processes larger volumes of data and achieves higher throughput than LSU 110. LSU 112 communicates with cache controller 114 by sending signals to it to ensure that data is stored within or loaded from cache extension 104.

[0045] Cache extension 104 is controlled by cache controller 114 based on signals generated by LSU 112. When processor core 102 executes an instruction that requires loading data from memory or a storage device, LSU 110 calculates the load address of the instruction and inputs the calculated load address into the LDQ. If a cache miss occurs at data / instruction cache 108, LSU 110 triggers LSU 112 to check cache extension 104. LSU 112 inputs the load address into its own LDQ, and if a cache hit occurs at cache extension 104, LSU 112 causes cache controller 114 to retrieve the data from cache extension 104 and then transfer the data from cache extension 104 to processor core 102.

[0046] When processor core 102 executes an instruction that requires data to be stored in memory or a storage device, LSU 110 generates a memory address and determines a stored data value, both of which are loaded into LSU 110's SDQ. If a cache miss occurs at data / instruction cache 108, LSU 110 triggers LSU 112 to check cache extension 104. LSU 112 inputs the memory address and stored value into its own SDQ, and if a cache hit occurs at cache extension 104, LSU 112 causes cache controller 114 to maintain the stored value and memory address at cache extension 104. The stored value and memory address are transferred from LSU 112 to cache controller 114 for writing to cache extension 104.

[0047] Cache controller 114 manages the retrieval, storage, and delivery of data at cache extension 104. Cache controller 114 determines where to store new data, when to fetch additional data from nearby addresses to prepare for processor core 102's future use of the data, and which older data to discard from cache extension 104 if it is full. In one or more embodiments, to improve the performance of cache extension 104, cache controller 114 maintains an address table associated with data already stored in cache extension 104. Cache controller 114 checks this table to determine if LSU 112 is referencing data already present in the memory of cache extension 104.

[0048] In at least one specific implementation, the FPU 106, as a floating-point unit, performs operations on floating-point numbers or fractions. In one or more aspects, the FPU 106 is operable to perform various arithmetic operations, such as addition, subtraction, multiplication, division, square root, exponential function, and trigonometric calculations. In one or more examples, the FPU 106 includes dedicated floating-point registers for receiving input from one or more parts of the processor core 102 and providing output thereto.

[0049] System 100-1 is an example that does not use stacked die extensions. System 100-1 includes a cache extension 104 and an FPU 106 located on the same die as the processor core 102 on semiconductor device 116. Figure 1 As depicted, cache extension 104 (e.g., L2 cache) and cache controller 114 are located on the far right of the same die of semiconductor device 116, away from processor core 102, data / instruction cache 108, LSU 110, and LSU 112. Additionally, FPU 106 is located on the far left of the same die of semiconductor device 116, away from processor core 102.

[0050] When the cache extension 104 and / or FPU 106 are located on the same die of semiconductor device 116 but far from processor core 102 and other supporting components, the performance of system 100-1 is compromised. Communication latency between LSU 112 and cache controller 114 is high, as is the complexity of power and signal routing between them. Furthermore, overall thermal management of the components on semiconductor device 116 is more difficult because processor core 102 operates hotter than cache extension 104 and / or FPU 106. System 100-1 has a die area that generates less heat than processor core 102, rather than having a consistent thermal footprint across semiconductor device 116. Complex heatsink designs are used to cool different areas of semiconductor device 116 differently.

[0051] According to the technology disclosed herein, which improves thermal management, communication latency and routing complexity within semiconductor device 116, systems 100-2, 100-3 and 100-4 each include a stacked die extension, the stacked die extension including at least one die arranged vertically adjacent to (e.g. above or below) the main die of semiconductor device 116 containing processor core 102.

[0052] Turning first to system 100-2, cache extension 104 and cache controller 114 are examples of processor core extensions located within at least one vertical die (e.g., adjacent die) of semiconductor device 116, which is situated above or below the main die of semiconductor device 116, on which a portion of processor core 102 is disposed. Cache extension 104 within system 100-2 is situated above a frequently used portion of the cache extension 104 of processor core 102. As... Figure 1 As described, cache extension 104 is disposed above portions of processor core 102 including data / instruction cache 108, LSU 110, and / or LSU 112. In one or more embodiments, at least a portion of data / instruction cache 108 is located on the master die of semiconductor device 116, which is located below at least one vertical die (e.g., adjacent die) supporting cache extension 104. In at least one embodiment, at least one vertical die including cache extension 104 is disposed above LSU 110 and / or LSU 112.

[0053] Next, referring to system 100-3, FPU 106 is a processor core extension located within at least one vertical die (e.g., adjacent die) of semiconductor device 116, the at least one vertical die being located above or below the main die of semiconductor device 116, on which a portion of processor core 102 is disposed. The FPU 106 within system 100-3 is located above a frequently used portion of processor core 102. Because FPU 106 is located on at least one die different from processor core 102, FPU 106 is sometimes referred to as a floating-point extension (e.g., FPU 106 is extended to the vertical die of semiconductor device 116).

[0054] Finally, system 100-4 is a specific implementation in which both FPU 106 (i.e., floating-point extension) and cache extension 104 represent processor core extensions located within at least one vertical die of semiconductor device 116, above or below a primary die (e.g., bottom die) on which a portion of processor core 102 is disposed. Cache extension 104 is placed on a component of processor core 102 that frequently communicates with cache controller 114, and similarly, FPU 106 is placed on a component of processor core 102 that initiates or benefits from computations performed by FPU 106.

[0055] In one or more specific implementations, another type of processor core extension (e.g., programmable accelerator extension, matrix extension for matrix mathematics, branch prediction unit, artificial intelligence accelerator, audio accelerator, video accelerator, cryptographic extension for encrypting or decrypting data exchanged with processor core 102) is implemented individually or in combination with cache extension 104 and / or FPU 106. This processor core extension is implemented in systems 100-2, 100-3, and 100-4, wherein the processor core extension is disposed on at least one vertical die of semiconductor device 116. The placement of the processor core extension results in a smaller distance from other components of processor core 102 than in the implementation in system 100-1.

[0056] In each of systems 100-2, 100-3, and 100-4, when the cache extension 104 and / or FPU 106 are arranged on at least one vertical die of semiconductor device 116, the distance between them and components of the processor core 102 on the main die of semiconductor device 116 is smaller than that of similar components found in system 100-1. Performance is improved by stacking FPU 106 and / or cache extension 104, as done in systems 100-2, 100-3, and 100-4. Signals and power are routed vertically (e.g., in the z-direction) between FPU 106 and / or cache extension 104 and processor core 102, which simplifies design and reduces communication latency, and offers other advantages. With the FPU 106 and / or cache extension 104 arranged closer to the support units of processor core 102, a consistent thermal footprint is achieved on semiconductor device 116, making overall thermal management of the components on semiconductor device 116 easier. In one or more specific implementations, less complex heatsink designs are used to similarly cool different areas of semiconductor device 116. The heatsinks for systems 100-2, 100-3, and 100-4 have relatively uniform thickness to apply the same cooling function to each part of semiconductor device 116, while the heatsink for system 100-1 has a greater thickness on processor core 102 than on other parts of system 100-1.

[0057] Figure 2 Non-limiting exemplary top view 200-1 and side view 200-2 depict a system with stacked die extensions on a processor core. (See also...) Figure 1 As described, the stacked die semiconductor device (referred to as semiconductor device 202) is depicted as Figure 1 An example of semiconductor device 116. Semiconductor device 202 includes a processor core 204 disposed on a master die 208 (e.g., a bottom die) of semiconductor device 202. Processor core 204 is derived from... Figure 1 Examples of processor core 102. Semiconductor device 202 also includes processor core extensions 206 located within at least one vertical die 210 of semiconductor device 202. Non-limiting examples of processor core extensions 206 include floating-point units, cache extensions, programmable accelerator extensions, matrix extensions for matrix mathematics, branch prediction units, artificial intelligence accelerators, audio accelerators, video accelerators, and cryptographic extensions for encrypting or decrypting data exchanged with processor core 204. For example, at least one vertical die 210 includes N dies, where N represents any positive integer. Further references Figure 1The components depicted, processor core extension 206, are examples of a standalone cache extension 104 (including cache controller 114) (e.g., as in system 100-2), a standalone FPU 106 (e.g., as in system 100-3), or a combination of cache extension 104 and FPU 106 (e.g., as in system 100-4). Although described primarily regarding cache and floating-point functionality, in other specific implementations, at least one vertical die 210 supports other variations of processor core extension 206. For example, instead of or in addition to cache extension 104 or FPU 106, processor core extension 206 integrated within at least one vertical die 210 may include one or more of the following: a programmable accelerator extension, a matrix extension for matrix mathematics, a branch prediction unit, an artificial intelligence accelerator, an audio accelerator, a video accelerator, a cryptographic extension for encrypting or decrypting data exchanged with processor core 204, and other types of hardware elements or hardware blocks for supporting the functionality of processor core 204.

[0058] At least one vertical die 210 is depicted having at least two dies disposed above a portion of the processor core 204; however, in one or more examples, at least one vertical die 210 is located below the main die 208. For simplicity of the figures, the main die 208 is depicted directly adjacent to at least one vertical die 210. In one or more embodiments, additional dies of the semiconductor device 202 are disposed between the main die 208 and at least one vertical die 210. In one or more embodiments, the main die 208 is disposed between at least one vertical die 210 (e.g., above the first vertical die and below the second vertical die). In one or more aspects, interconnect layers, epitaxial layers, oxide layers, polysilicon layers, and / or metal layers of the semiconductor device 202 are located between the main die 208 having the processor core 204 and at least one vertical die 210 having the processor core extension 206. Compared to the implementation of processor core extension 206 and processor core 204 together on the main core 208, the vertical stacking of processor core extension 206 relative to processor core 204 reduces communication latency, routing complexity, and achieves a more consistent thermal footprint.

[0059] Figure 2The document also depicts a memory device 212 operatively coupled to a semiconductor device 202. The memory device 212 is configured to store and retrieve data exchanged with processor core 204 and / or processor core extension 206. For example, the memory device 212 implements a data repository accessible from the semiconductor device 202. Examples of data repositories implemented by the memory device 212 include main memory (e.g., random access memory), caches of higher levels than first-level, second-level, and / or third-level caches, secondary storage devices (e.g., mass storage devices), and removable media (e.g., flash drives, memory cards, optical discs, and digital video discs).

[0060] As an exemplary implementation, semiconductor device 202 provides a multi-level cache supporting the operation of processor core 204. For example, primary die 208 includes a first-order cache (e.g., L1 cache) disposed near or between elements of processor core 204. At least one vertical die 210 includes at least two dies, including at least one second die and at least one third die, disposed above or below the first-order cache. A second-order cache (e.g., L2 cache) is implemented on at least one second die, which is adjacent to and vertically stacked from the primary die 208. A third-order cache (e.g., L3 cache) is implemented on at least one third die, which is stacked adjacent to the opposite side of the adjacent primary die 208 of the second die. Memory device 212 is operatively coupled to semiconductor device 202 to exchange data to be stored at or retrieved from memory device 212 on behalf of processor core extension 206 (e.g., first-order cache, second-order cache, third-order cache) and / or processor core 204. In this manner, processor core extension 206 provides at least two additional cache layers beyond the Level 1 cache implemented on the main die 208 within processor core 204. When the additional cache layers are vertically arranged above or below the Level 1 cache, the elements of the additional cache layers are positioned closer to the Level 1 cache elements compared to when the elements of the additional cache layers are arranged on the main die 208 outside processor core 204, which improves the performance of the multi-level cache. In at least one variant, the multi-level cache includes more than three cache layers (e.g., at least one vertical die 210 includes at least one fourth die to extend the capacity of the Level 3 cache or provide a Level 4 cache). In one or more examples, these additional cache layers are implemented on a single vertical die. In one or more implementations, the additional cache layers are implemented on multiple vertical dies.

[0061] Figure 3A non-limiting example 300 of a processor core extended by stacked dies cooled by a heatsink is depicted. Figure 3 The image depicts a stacked die semiconductor device referred to as semiconductor device 302. Semiconductor device 302 is an example of semiconductor device 116 and semiconductor device 202. Semiconductor device 302 includes a processor core 304, which is an example of processor cores 102 and 204, disposed on a main die 308 of semiconductor device 302. Semiconductor device 302 also includes a processor core extension depicted as being positioned within at least one vertical die 310 of semiconductor device 302, a floating-point / cache extension 306. Floating-point / cache extension 306 is an example of processor core extension 206, including... Figure 1 One or more variations of the cache extension 104 and / or FPU 106 described in the document.

[0062] like Figure 3 As depicted, components of the semiconductor device 302 are cooled by a heatsink 312. The heatsink 312 is configured to dissipate heat generated from the processor core 304 and the floating-point / cache extension 306. In cases where at least one vertical die 310 includes a floating-point / cache extension 306 disposed between the main die 308 and the processor core 304, the heatsink 312 is configured to uniformly cool the components on the semiconductor device 302. Figure 3 As depicted, the heatsink 312 has a (generally) uniform thickness 314 over different regions of the floating-point / cache extension 306 and the processor core 304 relative to the arrangement of the semiconductor device 302. This simpler design of the heatsink 312 is sufficient to cool the various regions of the semiconductor device 302 because stacking the floating-point / cache extension 306 above or below the processor core 304 achieves a consistent thermal profile across the semiconductor device 302. In one or more embodiments, a more complex heatsink design (e.g., not achieving a uniform thickness 314 on the semiconductor device 302) is used to address the variability of the thermal profile on the semiconductor device 302 caused by other factors unrelated to the stacking of the floating-point / cache extension 306 above or below the processor core 304. In all aspects, the heatsink 312 achieves a uniform thickness 314 over the floating-point / cache extension 306 and a portion of the processor core 304, and a variable thickness where the processor core 304 and other components on the main chip do not overlap with the floating-point / cache extension 306.

[0063] Figure 4 A non-limiting example 400 is depicted, illustrating a stacked die extension on a processor core comprising one or more die-to-die interconnects. Figure 4The image depicts a stacked die semiconductor device, referred to as semiconductor device 402, as examples of semiconductor devices 116, 202, and 302. Semiconductor device 402 includes a processor core 404, which is an example of processor core 102, processor core 204, and processor core 304. Processor core 404 is disposed on a primary die 408 of semiconductor device 402. In one or more embodiments, primary die 408 is a bottom die or a top die of semiconductor device 402. Semiconductor device 402 also includes a processor core extension depicted as being positioned within at least one vertical die 410 of semiconductor device 402. Floating-point / cache extension 406 is an example of processor core extension 206 and floating-point / cache extension 306, including... Figure 1 One or more variations of the cache extension 104 and / or FPU 106 depicted in reference systems 100-2, 100-3 and 100-4.

[0064] The floating-point / cache extension 406 is operatively coupled to the processor core 404. For example... Figure 4 As depicted, semiconductor device 402 includes an interconnect layer 412 positioned between a main die 408 and at least one vertical die 410. Interconnect layer 412 includes at least one die-to-die interconnect disposed between the main die 408 and the at least one vertical die 410. The die-to-die interconnect is configured to transmit power and signals between processor core 404 and floating-point / cache extension 406. The die-to-die interconnect of interconnect layer 412 extends vertically from the main die 408 to the at least one vertical die 410. Power and signals move vertically between processor core 404 and floating-point / cache extension 406 in the z-direction, which is substantially perpendicular to the xy-plane of the main die 408. The distance between processor core 404 and floating-point / cache extension 406 resulting from this stacking is smaller than if both processor core 404 and floating-point / cache extension 406 were implemented on the main die 408. The shorter distance between processor core 404 and floating-point / cache extension 406 improves communication latency through die-to-die interconnects and simplifies the complexity of its routing.

[0065] Interconnect layer 412 supports any type of vertical die-to-die interconnect. Figure 4 The document describes some non-limiting examples of die-to-die interconnects. In one or more specific implementations, multiple types of die-to-die interconnects are used in combination within interconnect layer 412.

[0066] In at least one embodiment, interconnect layer 412 includes one or more through-silicon vias (TSVs) designated TSV 414, which are configured to transmit power and signals between processor core 404 and floating-point / cache extension 406. TSV 414 represents a vertical conductor of electrically coupled stacked dies (e.g., main die 408 and at least one vertical die 410). TSV 414 is formed by etching trenches into the silicon of interconnect layer 412, the trenches being filled with metal lines (e.g., copper) and insulating material.

[0067] In one or more examples, interconnect layer 412 includes one or more microbumps labeled microbumps 416, which are configured to transmit power and signals between processor core 404 and floating-point / cache extension 406. Microbump 416 represents small solder bumps on electrically coupled stacked dies (e.g., main die 408 and at least one vertical die 410). In various aspects, microbump 416 is made of metal alloys such as copper, nickel, gold, and silver, and is soldered using soldering materials such as indium, tin, and tin-silver-copper (SAC) compounds.

[0068] In one or more embodiments, interconnect layer 412 includes one or more hybrid connectors designated as hybrid connectors 418, configured to transmit power and signals between processor core 404 and floating-point / cache extension 406. Hybrid connector 418 differs from TSV 414 and microbump 416. Hybrid connector 418 is formed using a combination of dielectric connectors and embedded metallic materials.

[0069] like Figure 4 As depicted, components of semiconductor device 402 are cooled by heat sink 420. Heat sink 420 is an example of heat sink 312 and is configured to dissipate heat generated from processor core 404 and floating-point / cache extension 406. Interconnect layer 412 maintains uniformity of thermal characteristics on semiconductor device 402 due to the stacking of floating-point / cache extension 406 above or below processor core 404. The consistent thermal footprint on semiconductor device 402 allows the implementation of heat sink 420 to have a uniform thickness for heat dissipation regulation.

[0070] Figure 5 A process 500 is depicted that is performed in an exemplary specific implementation of a stacked die extension on a processor core. For example, process 500 occurs within semiconductor device 116, semiconductor device 202, semiconductor device 302, or semiconductor device 402.

[0071] The first-order data / instruction cache communicates with the first-order load memory unit (box 502). In operation, when accessing the data / instruction cache 108, the LSU 110 performs a lookup to determine whether the cache request is a hit or a miss.

[0072] In response to a cache miss at the data / instruction cache, the first-level load memory communicates with the next-level load memory (box 504). LSU 110 sends a request to LSU 112 to check cache extension 104. At this time, communication between data / instruction cache 108 and LSU 110, and communication between LSU 110 and LSU 112, occurs within the interconnect on the main chip of the semiconductor device 116 containing processor core 102.

[0073] The next-level load memory unit communicates with the next-level cache controller (box 506) located above the next-level load memory unit. LSU 112 sends control signals from the main die of semiconductor device 116 to cache controller 114, which, together with cache extension 104, is located on at least one vertical die of semiconductor device 116. Control signals are transmitted from LSU 112 to cache controller 114 over a die-to-die interconnect that provides a vertical (e.g., z-direction relative to the main die with processor core 102) route or signal path.

[0074] The next-level cache controller responds to the request from the next-level cache controller (box 508). Cache controller 114 performs a lookup within cache extension 104 to access the data associated with the request. Cache controller 114 sends the response to the request back to LSU 112 on the same route or signaling path as the request, or on a different vertical route or signaling path formed between cache extension 104 and LSU 112 on the main chip of semiconductor device 116.

[0075] In response to the request, the first-order data / instruction cache outputs the data transferred from the next-order load memory to the first-order load memory (box 510). LSU 110 receives the response to the request from LSU 112 and sends the data indicated in the response to data / instruction cache 108.

[0076] By repositioning cache extension 104 above data / instruction cache 108, LSU 110, and LSU 112 (e.g., as in systems 100-2 and 100-3), communication latency between the first-order cache and the next-order cache is reduced relative to system 100-1. Stacking cache extension 104 in this manner eliminates the need to send signals from LSU 112 on the main die of semiconductor device 116 in the lateral direction (e.g., x-axis, y-axis). Instead, these signals are transmitted in the z-direction over die-to-die interconnects with much shorter routes. With cache extension 104 stacked on top of or near data / instruction cache 108, multi-cycle lateral routing is eliminated. Instead, short z-dimensional routes of a few cycles (e.g., one or two) are used to access cache extension 104. Figure 5 In this context, cache extension 104 becomes more centrally located within processor core 102 and the elements contained within processor core 102 utilizing cache extension 104.

[0077] Another benefit of repositioning cache extension 104 over data / instruction caches 108, LSU 110, and LSU 112 is that expanding cache extension 104 is less complex because its area or footprint is not constrained by the limited area available next to processor core 102. Typically, increasing cache size significantly increases the footprint of the semiconductor die, and manufacturing becomes difficult when the footprint is already constrained to a specific size or shape. Larger caches require signals to travel further and have larger addresses. Larger caches also increase latency due to the need for more clock cycles to perform lookups and data transfers.

[0078] In a conventional implementation of, for example, System 100-1, communication with cache extension 104 takes approximately 14 cycles. Communication between LSU 110, LSU 112, and cache controller 114 takes ten cycles, and cache controller 114 takes an additional four cycles to access cache extension 104. If the size of cache extension 104 is doubled and it is not stacked on processor core 102, cache controller 114 takes an additional four cycles to access cache extension 104, bringing the total latency to eighteen cycles.

[0079] In a specific implementation where cache extension 104 is stacked similarly to systems 100-2 and 100-4, increasing the size of cache extension 104 does not increase communication latency as it does when cache extension 104 is located on the same die of semiconductor device 116 as processor core 102. Stacking allows cache extension 104 to have a larger size and lower latency than even a smaller cache located next to processor core 102. Stacking cache extension 104 reduces communication latency between LSU 110, LSU 112, and cache controller 114 to approximately zero cycles. Cache controller 114 still takes an additional four cycles to access cache extension 104 (or eight cycles if the size of cache extension 104 is doubled). Even with a much larger size, communication with cache extension 104 when it is stacked on processor core 102 is much less than when cache extension 104 is not stacked.

[0080] Figure 6 A process 600 for forming a stacked die extension on a processor core is described. Process 600 is implemented at least in part using a semiconductor die manufacturing apparatus that executes programs or applications to control machinery configured to construct any of the semiconductor devices 116, 202, 302, and 402 described herein, including integrating their corresponding components.

[0081] The processor core is integrated within the first die of the stacked die semiconductor device (box 602). In one or more embodiments, manufacturing equipment performs semiconductor manufacturing techniques to form the processor core 102 within the main die (e.g., the bottom die) of the semiconductor device 116.

[0082] At least one second die of the stacked die semiconductor device is positioned above or below the first die (box 604). As an example, manufacturing equipment performs semiconductor manufacturing techniques to add at least one vertical die to semiconductor device 116, the at least one vertical die being positioned above or below the main die supporting processor core 102.

[0083] The processor core extension is integrated within a second die, above or below a portion of the processor core (box 606). As an example, manufacturing equipment performs semiconductor manufacturing techniques to integrate processor core extensions supporting processor core 102 (e.g., cache extension 104 and / or FPU 106) within at least one vertical die of semiconductor device 116 located above or below processor core 102. Non-limiting examples of processor core extensions integrated within the second die include floating-point units, cache extensions, programmable accelerator extensions, matrix extensions for matrix mathematics, branch prediction units, artificial intelligence accelerators, audio accelerators, video accelerators, and cryptographic extensions for encrypting or decrypting data exchanged with processor core 102.

[0084] In one or more aspects, a processor core extension integrated into at least one vertical die includes a cache extension 104, which in one or more embodiments includes a Level 2 or Level 3 cache. In one or more variations, a portion of the processor core 102 on which the cache extension is disposed (e.g., data / instruction cache 108) includes a Level 1 cache. Integrating the cache extension 104 includes arranging the Level 2 or Level 3 cache above or below the Level 1 data / instruction cache or Level 1 load memory.

[0085] In at least one embodiment, the processor core 102 includes a data / instruction cache 108 as a first-order cache, and at least one second die of the semiconductor device 116 includes multiple dies. In this case, integrating a processor core extension (e.g., cache extension 104) within the second die includes implementing both a second-order cache and a third-order cache within a die different from the multiple dies implementing the processor core extension. For example, as... Figure 2 As depicted, at least one vertical die 210 includes a number of N dies, where N represents any positive integer. An L2 cache is implemented within one or more dies in a first group included in at least one vertical die 210, and an L3 cache is implemented within one or more dies in a different group included in at least one vertical die 210.

[0086] Optionally, a heatsink with a nearly uniform thickness is arranged adjacent to the second die, such that the processor core extension is located between the heatsink and the processor core (box 608). As an example, manufacturing equipment performs semiconductor manufacturing techniques to attach a heatsink (e.g., heatsink 312, heatsink 420) on top of the processor core extension (e.g., cache extension 104 and / or FPU 106) and above the processor core 102. In one or more embodiments, the heatsink attached to at least one vertical die has a uniform thickness for heat dissipation, which, due to the stacking, produces a consistent thermal characteristic on the semiconductor device 116.

[0087] It should be understood that many variations are possible based on the disclosed content of this article. Although features and elements are described above in specific combinations, each feature or element can be used alone without other features and elements, or in various combinations with or without other features or elements.

[0088] The various functional units illustrated in the accompanying drawings and / or described herein are implemented in any of a variety of different ways, such as hardware circuitry, software or firmware executing on a programmable processor, or any combination of both or more of hardware, software, and firmware. The provided methods are implemented in any of a variety of devices, such as general-purpose computers, processors, or processor cores. As examples, suitable processors include general-purpose processors, special-purpose processors, conventional processors, CPUs, DSPs, GPUs, parallel accelerator processors, multiple microprocessors, one or more microprocessors associated with a DSP core, controllers, microcontrollers, application-specific integrated circuits (ASICs), FPGA circuitry, any other type of integrated circuit (IC), and / or state machines.

[0089] In one or more embodiments, the methods and processes provided herein are implemented in a computer program, software, or firmware incorporated in a non-transitory computer-readable storage medium for execution by a general-purpose computer or processor. Examples of non-transitory computer-readable storage media include read-only memory (ROM), random access memory (RAM), registers, cache memory, semiconductor memory devices, magnetic media (such as internal hard disks and removable disks), magneto-optical media, and optical media (such as CD-ROM discs) or digital versatile discs (DVDs).

[0090] Clause 1. A stacked die semiconductor device, the stacked die semiconductor device comprising: a first die having a processor core; and at least one second die including a processor core extension positioned above or below a portion of the processor core.

[0091] Clause 2. The stacked die semiconductor device according to Clause 1, wherein the processor core extension includes a cache extension operatively coupled to the processor core.

[0092] Clause 3. The stacked die semiconductor device according to Clause 2, wherein the first die further includes a cache operatively coupled to the cache extension.

[0093] Clause 4. The stacked die semiconductor device as described in Clause 3, wherein the cache extension is a higher-order cache than the cache within the first die.

[0094] Clause 5. The stacked die semiconductor device according to Clause 3 or 4, wherein the portion of the processor core includes at least a portion of the cache within the first die.

[0095] Clause 6. A stacked die semiconductor device according to any one of Clauses 3 to 5, wherein the portion of the processor core comprises at least one of: a data cache of the cache within the first die, a load memory unit of the cache within the first die, or a load memory unit of the cache extension.

[0096] Clause 7. The stacked die semiconductor device according to any one of Clauses 3 to 6, wherein the cache within the first die includes a first-order cache operatively coupled to the processor core, the cache extension includes a second-order cache operatively coupled to the processor core, and the stacked die semiconductor device further includes at least one third die having a third-order cache operatively coupled to the processor core.

[0097] Clause 8. The stacked die semiconductor device according to any one of Clauses 1 to 7, the stacked die semiconductor device further comprising a die-to-die interconnect disposed between the first die and the at least one second die for transmitting power and signals between the processor core and the processor core extension, wherein the die-to-die interconnect comprises at least one of microbumps, hybrid bonding elements, or through-silicon vias.

[0098] Clause 9. A stacked die semiconductor device according to any one of Clauses 1 to 8, wherein the processor core extension includes a floating-point unit operatively coupled to the processor core.

[0099] Clause 10. A system comprising: a stacked die semiconductor device including a first die and at least one second die, the first die including a processor core, the at least one second die including a processor core extension positioned above or below a portion of the processor core; and a memory device operatively coupled to the processor core extension to exchange data with the processor core.

[0100] Clause 11. The system according to Clause 10 further includes a heat sink configured to dissipate heat from the stacked die semiconductor device, wherein at least one second die is positioned between the first die and the heat sink, and the heat sink includes an approximately uniform thickness relative to the processor core extension and the processor core.

[0101] Clause 12. The system according to Clause 10 or 11, wherein the processor core extension includes at least one floating-point unit operatively coupled to the floating-point units of the processor core.

[0102] Clause 13. The system according to any one of Clauses 10 to 12, wherein the processor core extension includes a cache extension operatively coupled to the processor core.

[0103] Clause 14. The system according to any one of Clauses 10 to 13, wherein the processor core extension includes at least one of the following: a programmable accelerator extension, a matrix extension for matrix mathematics, a branch prediction unit, an artificial intelligence accelerator, an audio accelerator, a video accelerator, or a cryptographic extension for encrypting or decrypting the data exchanged with the processor core.

[0104] Clause 15. A method of forming a stacked die semiconductor device according to any one of Clauses 1 to 14, the method comprising: integrating a processor core within a first die of the stacked die semiconductor device; disposing at least one second die of the stacked die semiconductor device above or below the first die; and extending a processor core into the at least one second die, above or below a portion of the processor core, and optionally disposing a heat sink having a substantially uniform thickness adjacent to the at least one second die such that the processor core extension is located between the heat sink and the processor core.

Claims

1. A stacked die semiconductor device, the stacked die semiconductor device comprising: The first die has a processor core; and At least one second die, the at least one second die including a processor core extension positioned above or below a portion of the processor core.

2. The stacked die semiconductor device of claim 1, wherein the processor core extension includes a cache extension operatively coupled to the processor core.

3. The stacked die semiconductor device of claim 2, wherein the first die further comprises a cache operatively coupled to the cache extension.

4. The stacked die semiconductor device of claim 3, wherein the cache extension is a higher-order cache than the cache within the first die.

5. The stacked die semiconductor device of claim 3 or 4, wherein the portion of the processor core includes at least a portion of the cache within the first die.

6. The stacked die semiconductor device according to any one of claims 3 to 5, wherein the portion of the processor core comprises at least one of the following: a data cache of the cache within the first die, a load memory unit of the cache within the first die, or a load memory unit of the cache extension.

7. The stacked die semiconductor device according to any one of claims 3 to 6, wherein the cache within the first die includes a first-order cache operatively coupled to the processor core, the cache extension includes a second-order cache operatively coupled to the processor core, and the stacked die semiconductor device further includes at least one third die having a third-order cache operatively coupled to the processor core.

8. The stacked die semiconductor device according to any one of claims 1 to 7, the stacked die semiconductor device further comprising a die-to-die interconnect disposed between the first die and the at least one second die for transmitting power and signals between the processor core and the processor core extension, wherein the die-to-die interconnect comprises at least one of microbumps, hybrid bonding elements, or through-silicon vias.

9. The stacked die semiconductor device according to any one of claims 1 to 8, wherein the processor core extension includes a floating-point unit operatively coupled to the processor core.

10. A system comprising: A stacked die semiconductor device, the stacked die semiconductor device including a first die and at least one second die, the first die including a processor core, and the at least one second die including a processor core extension positioned above or below a portion of the processor core; and A memory device operatively coupled to the processor core extension to exchange data with the processor core.

11. The system of claim 10, further comprising a heat sink configured to dissipate heat from the stacked die semiconductor device, wherein at least one second die is positioned between the first die and the heat sink, and the heat sink comprises an approximately uniform thickness relative to the processor core extension and the processor core.

12. The system of claim 10 or 11, wherein the processor core extension includes at least one floating-point unit operatively coupled to the floating-point units of the processor core.

13. The system according to any one of claims 10 to 12, wherein the processor core extension includes a cache extension operatively coupled to the processor core.

14. The system according to any one of claims 10 to 13, wherein the processor core extension includes at least one of the following: a programmable accelerator extension, a matrix extension for matrix mathematics, a branch prediction unit, an artificial intelligence accelerator, an audio accelerator, a video accelerator, or a cryptographic extension for encrypting or decrypting the data exchanged with the processor core.

15. A method of forming a stacked die semiconductor device according to any one of claims 1 to 14, the method comprising: The processor core is integrated into the first die of the stacked die semiconductor device; At least one second die of the stacked die semiconductor device is arranged above or below the first die; as well as The processor core extension is integrated within at least one second die, above or below a portion of the processor core, and A heatsink with approximately uniform thickness may be optionally arranged adjacent to the at least one second die, such that the processor core extension is located between the heatsink and the processor core.

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