Stacked device, method of manufacturing stacked device, and electronic apparatus

Abstract

A layered device according to one embodiment of the present disclosure includes a first substrate, a second substrate, and an alignment mark. The first substrate includes a semiconductor layer having a first surface and a second surface opposite to each other, and includes a first functional element including the semiconductor layer. The second substrate is layered on the first substrate, and is opposite to the second surface of the semiconductor layer. The alignment mark is provided in the first substrate on a side of the second surface of the semiconductor layer. The alignment mark includes a conductive film having transparency to visible light.

Description

Technical Field

[0001] This disclosure relates to stacked devices, methods of manufacturing stacked devices, and electronic devices including stacked devices. Background Technology

[0002] For example, Patent Document 1 discloses an imaging device in which, after a CMOS circuit section is formed on a silicon substrate, an alignment mark is provided that penetrates the CMOS circuit section to reach the silicon substrate.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2019-201171 Summary of the Invention

[0006] Incidentally, for stacked devices with substrates of different sizes bonded together, there is a requirement to improve the accuracy of position alignment.

[0007] It is desirable to provide a stacked device that enables highly accurate position alignment, a method for manufacturing the stacked device, and an electronic device.

[0008] A stacked device according to an embodiment of the present disclosure includes a first substrate, a second substrate, and alignment marks. The first substrate includes a semiconductor layer having a first surface and a second surface opposite to each other, and includes a first functional element comprising the semiconductor layer. The second substrate is stacked on the first substrate and is opposite to the second surface of the semiconductor layer. Alignment marks are disposed in the first substrate on one side of the second surface of the semiconductor layer. The alignment marks include a conductive film that is transparent to visible light.

[0009] A method for manufacturing a stacked device according to an embodiment of the present disclosure includes: forming a semiconductor layer on a growth substrate by epitaxial growth; forming alignment marks by forming a conductive film that is transparent to visible light on the semiconductor layer; monolithically dividing the semiconductor layer into a plurality of said semiconductor layers; transferring the plurality of semiconductor layers generated by the monolithization onto a support substrate; forming a plurality of first functional elements by individually processing the plurality of semiconductor layers; and thereafter bonding a first substrate and a second substrate together by hybrid bonding, the first substrate including the plurality of first functional elements.

[0010] An electronic device according to an embodiment of the present disclosure includes a stacked device according to an embodiment of the present disclosure described above.

[0011] According to an embodiment of the stacked device, a method for manufacturing a stacked device according to an embodiment of the present disclosure, and an electronic device according to an embodiment of the present disclosure, in a configuration in which a first substrate and a second substrate, including a first functional element, are stacked on top of each other, alignment marks of a conductive film that is transparent to visible light are formed on one side of the surface (second surface) of the semiconductor layer constituting the first functional element opposite to the second substrate. This facilitates positional alignment when monolithically dividing the semiconductor layer into multiple semiconductor layers and transferring them during the step of forming the first functional element. Attached Figure Description

[0012] Figure 1 This is a schematic cross-sectional view illustrating an example of the configuration of a light-emitting device according to an embodiment of the present disclosure.

[0013] Figure 2 It shows Figure 1 A schematic diagram of an example of an overall planar configuration of the light-emitting device shown.

[0014] Figure 3 It is shown in an enlarged manner Figure 2 A schematic diagram of a portion of the planar configuration of the light-emitting device shown.

[0015] Figure 4A It shows Figure 1 An illustration of an example of the planar shape of the alignment mark, etc., as shown in the diagram.

[0016] Figure 4B It is shown in Figure 1 A diagram illustrating another example of the planar shape of the alignment mark shown in the figure.

[0017] Figure 4C It shows Figure 1 A diagram illustrating another instance of the planar shape of the alignment mark, etc., as shown in the diagram.

[0018] Figure 4D It shows Figure 1 A diagram illustrating another instance of the planar shape of the alignment mark, etc., as shown in the diagram.

[0019] Figure 4E It is shown in Figure 1 A diagram illustrating another example of the planar shape of the alignment mark shown in the figure.

[0020] Figure 4F It is shown in Figure 1 A diagram illustrating another example of the planar shape of the alignment mark shown in the figure.

[0021] Figure 4G It shows Figure 1 A diagram illustrating another instance of the planar shape of the alignment mark, etc., as shown in the diagram.

[0022] Figure 4H It shows Figure 1 A diagram illustrating another example of the planar shape of the alignment mark shown in the figure.

[0023] Figure 4I It shows Figure 1 A diagram illustrating another instance of the planar shape of the alignment mark, etc., as shown in the diagram.

[0024] Figure 5A It describes manufacturing Figure 1 A schematic cross-sectional view of an example of the steps of a light-emitting device shown in the figure.

[0025] Figure 5B It shows the continuation Figure 5A A schematic cross-sectional view of the subsequent steps.

[0026] Figure 5C It shows the continuation Figure 5B A schematic cross-sectional view of the subsequent steps.

[0027] Figure 5D It shows the continuation Figure 5C A schematic cross-sectional view of the subsequent steps.

[0028] Figure 5E It shows the continuation Figure 5D A schematic cross-sectional view of the subsequent steps.

[0029] Figure 5F It shows the continuation Figure 5E A schematic cross-sectional view of the subsequent steps.

[0030] Figure 5G It shows the continuation Figure 5F A schematic cross-sectional view of the subsequent steps.

[0031] Figure 5H It shows the continuation Figure 5G A schematic cross-sectional view of the subsequent steps.

[0032] Figure 5I It shows the continuation Figure 5H A schematic cross-sectional view of the subsequent steps.

[0033] Figure 5J It shows the continuation Figure 5I A schematic cross-sectional view of the subsequent steps.

[0034] Figure 5K It shows the continuation Figure 5J A schematic cross-sectional view of the subsequent steps.

[0035] Figure 5L It shows the continuation Figure 5KA schematic cross-sectional view of the subsequent steps.

[0036] Figure 6A It corresponds to Figure 5A A schematic floor plan.

[0037] Figure 6B It corresponds to Figure 5B A schematic floor plan.

[0038] Figure 6C It corresponds to Figure 5C A schematic floor plan.

[0039] Figure 6D It corresponds to Figure 5D A schematic floor plan.

[0040] Figure 7A It shows Figure 5H A schematic cross-sectional view of the subsequent steps.

[0041] Figure 7B It shows the continuation Figure 7A A schematic cross-sectional view of the subsequent steps.

[0042] Figure 7C It shows the continuation Figure 7B A schematic cross-sectional view of the subsequent steps.

[0043] Figure 7D It shows the continuation Figure 7C A schematic cross-sectional view of the subsequent steps.

[0044] Figure 7E It shows the continuation Figure 7D A schematic cross-sectional view of the subsequent steps.

[0045] Figure 7F It shows the continuation Figure 7E A schematic cross-sectional view of the subsequent steps.

[0046] Figure 7G It shows the continuation Figure 7F A schematic cross-sectional view of the subsequent steps.

[0047] Figure 7H It shows the continuation Figure 7G A schematic cross-sectional view of the subsequent steps.

[0048] Figure 7I It shows the continuation Figure 7H A schematic cross-sectional view of the subsequent steps.

[0049] Figure 7J It shows the continuation Figure 7I A schematic cross-sectional view of the subsequent steps.

[0050] Figure 7KIt shows the continuation Figure 7J A schematic cross-sectional view of the subsequent steps.

[0051] Figure 7L It shows that in the following Figure 7K A schematic cross-sectional view of the subsequent steps.

[0052] Figure 7M It shows the continuation Figure 7L A schematic cross-sectional view of the subsequent steps.

[0053] Figure 7N It shows the continuation Figure 7M A schematic cross-sectional view of the subsequent steps.

[0054] Figure 7O It shows the continuation Figure 7N A schematic cross-sectional view of the subsequent steps.

[0055] Figure 7P It shows the continuation Figure 7O A schematic cross-sectional view of the subsequent steps.

[0056] Figure 7Q It shows the continuation Figure 7P A schematic cross-sectional view of the subsequent steps.

[0057] Figure 7R It shows the continuation Figure 7Q A schematic cross-sectional view of the subsequent steps.

[0058] Figure 7S It shows the continuation Figure 7R A schematic cross-sectional view of the subsequent steps.

[0059] Figure 7T It shows the continuation Figure 7S A schematic cross-sectional view of the subsequent steps.

[0060] Figure 7U It shows the continuation Figure 7T A schematic cross-sectional view of the subsequent steps.

[0061] Figure 7V It shows the continuation Figure 7U A schematic cross-sectional view of the subsequent steps.

[0062] Figure 7W It shows the continuation Figure 7V A schematic cross-sectional view of the subsequent steps.

[0063] Figure 8A It includes descriptions of manufacturing Figure 1 The diagram shows a schematic cross-sectional view (A) and a schematic plan view (B) of an example of the alignment mark and the steps around it.

[0064] Figure 8BIt includes showing the continuation Figure 8A The following are schematic cross-sectional views (A) and schematic plan views (B) illustrating the subsequent steps.

[0065] Figure 8C It includes showing the continuation Figure 8B The following are schematic cross-sectional views (A) and schematic plan views (B) illustrating the subsequent steps.

[0066] Figure 8D It shows the continuation Figure 8C A schematic cross-sectional view of the subsequent steps.

[0067] Figure 8E It shows the continuation Figure 8D A schematic cross-sectional view of the subsequent steps.

[0068] Figure 8F It shows the continuation Figure 8E A schematic cross-sectional view of the subsequent steps.

[0069] Figure 9 This is a schematic cross-sectional view showing an example of the configuration of a light-emitting device according to a variation of 1 of this disclosure.

[0070] Figure 10 It shows Figure 9 A schematic diagram of an example of an overall planar configuration of the light-emitting device shown.

[0071] Figure 11A The diagram includes a schematic cross-sectional view (A) and a schematic plan view (B) illustrating an example of the steps for manufacturing alignment marks according to Modification 2 of this disclosure and its surroundings.

[0072] Figure 11B It includes showing the continuation Figure 11A The following are schematic cross-sectional views (A) and schematic plan views (B) illustrating the subsequent steps.

[0073] Figure 11C It includes showing the continuation Figure 11B The following are schematic sectional views (A) and schematic plan views (B) illustrating the subsequent steps.

[0074] Figure 11D It shows the continuation Figure 11C A schematic cross-sectional view of the subsequent steps.

[0075] Figure 11E It shows the continuation Figure 11D A schematic cross-sectional view of the subsequent steps.

[0076] Figure 11F It is shown in Figure 11E A schematic cross-sectional view of the subsequent steps.

[0077] Figure 12A The diagram includes a schematic cross-sectional view (A) and a schematic plan view (B) illustrating an example of the steps for manufacturing alignment marks according to Modification 3 of this disclosure and its surroundings.

[0078] Figure 12B It includes showing the continuation Figure 12A The following are schematic sectional views (A) and schematic plan views (B) illustrating the subsequent steps.

[0079] Figure 12C It includes showing the continuation Figure 12B The following are schematic cross-sectional views (A) and schematic plan views (B) illustrating the subsequent steps.

[0080] Figure 12D It shows the continuation Figure 12C A schematic cross-sectional view of the subsequent steps.

[0081] Figure 12E It shows the continuation Figure 12D A schematic cross-sectional view of the subsequent steps.

[0082] Figure 13A This is a front view showing an example of the appearance of a digital still camera used as an application example of this disclosure.

[0083] Figure 13B It shows Figure 13A The image shows a rear view of an example of the appearance of a digital camera.

[0084] Figure 14A This is a perspective view showing the appearance of an example of a head-mounted display used as an application example of this disclosure.

[0085] Figure 14B This is a perspective view showing the appearance of another example of a head-mounted display used as an application example of this disclosure.

[0086] Figure 15 This is a perspective view showing an example of the appearance of a television device used as an application example of this disclosure. Detailed Implementation

[0087] An embodiment according to the present disclosure will now be described in detail with reference to the accompanying drawings. The following description is given as a specific example of the present disclosure, and the present disclosure is not limited to the following exemplary embodiments. Furthermore, the present disclosure is not limited to the arrangement, dimensions, size ratios, etc., of the various components shown in the various drawings. Note that the description will proceed in the following order.

[0088] 1. First embodiment (example of a light-emitting device, the light-emitting device including alignment marks, the alignment marks comprising a transparent conductive film and disposed on the surface of a compound semiconductor layer opposite to the driving surface)

[0089] 2. Variations

[0090] 2-1. Variation Example 1 (Another example of forming the position of the alignment mark)

[0091] 2-2. Variation Example 2 (Another example of forming the position of the alignment mark)

[0092] 2-3. Variation Example 3 (Another example of forming the position of the alignment mark)

[0093] 3. Application Examples

[0094] <1. Implementation Method>

[0095] Figure 1 An example of a cross-sectional configuration of a light-emitting device (light-emitting device 1) according to an embodiment of the present disclosure is illustrated schematically. Figure 2 It schematically shows that in Figure 1 An example of a planar configuration of the light-emitting device 1 is shown. The light-emitting device 1 is advantageously suited for image display devices known as LED displays (e.g., the electronic viewfinder 1124 of a digital still camera 1120, etc., see [link]). Figure 13B ).

[0096] The light-emitting device 1 includes, for example, a component substrate 10 and a driving substrate 30, which are laminated together by bonding. The component substrate 10 includes a compound semiconductor layer 110 comprising a pair of surfaces (surface 11S1 and surface 11S2) facing each other, and also includes a light-emitting element 11 comprising the compound semiconductor layer 110 (see, for example, see...). Figure 5A The driving substrate 30 is configured to face the surface 11S2 of the compound semiconductor layer 110, which is located on the side opposite to the surface 11S1 used as the light extraction surface. The element substrate 10 has an alignment mark 116 on one side of the surface 11S2 of the compound semiconductor layer 110. The alignment mark 116 includes a transparent conductive film that is transparent to visible light.

[0097] Here, the light-emitting device 1 corresponds to a specific example of a "stacked device" according to an embodiment of the present disclosure. The element substrate 10 corresponds to a specific example of a "first substrate" according to an embodiment of the present disclosure. The compound semiconductor layer 110 corresponds to a specific example of a "semiconductor layer" according to an embodiment of the present disclosure. Surface 11S1 corresponds to a specific example of a "first surface" according to an embodiment of the present disclosure. Surface 11S2 corresponds to a specific example of a "second surface" according to an embodiment of the present disclosure. The driving substrate 30 corresponds to a specific example of a "second substrate" according to an embodiment of the present disclosure. The alignment mark 116 corresponds to a specific example of an "alignment mark" according to an embodiment of the present disclosure.

[0098] (Configuration of light-emitting devices)

[0099] The light-emitting device 1 includes: a pixel array portion 100A, wherein a plurality of light-emitting elements 11 are arranged in a two-dimensional array; and a peripheral portion 100B disposed around the pixel array portion 100A. The light-emitting device 1 has a configuration in which, for example, an element substrate 10 and a wavelength converter 20 are stacked in this order on the surface 30S1 side of a driving substrate 30, the driving substrate 30 having a front surface (surface 30S1) and a rear surface (surface 30S2) opposite to each other. The element substrate 10 includes a plurality of light-emitting elements 11 arranged in an array.

[0100] As described above, the component substrate 10 includes a plurality of light-emitting elements 11 arranged in a two-dimensional array in the pixel array section 100A. For example, the plurality of light-emitting elements 11 have, for example, Figure 3 The generally hexagonal shape shown is arranged, for example, in a honeycomb pattern. An electrode layer 12, an insulating layer 13, and an extraction electrode 14 are sequentially formed on the surface 11S1 side of the plurality of light-emitting elements 11. On the surface 11S2 side of the plurality of light-emitting elements 11, an electrode layer 114, an insulating layer 115, and a protective layer 117 are formed for each element. Furthermore, an insulating film 118A and a reflective film 118B are formed continuously through the plurality of light-emitting elements 11. Additionally, an embedding layer 119 is formed to embed the plurality of light-emitting elements 11. Furthermore, plugs 15, insulating layers 17 and 18 are formed in this order on the surface 11S2 side of the plurality of light-emitting elements 11. A plug 15 is provided for each element. The insulating layer 17 includes a pad portion 16A and a pad electrode 16B. The insulating layer 18 includes a pad portion 19, which electrically and physically bonds the element substrate 10 and the driving substrate 30. Furthermore, alignment marks 116 are formed on the surface 11S2 of the light-emitting elements 11. Alignment marks 116 are provided on the surface 11S2 of the compound semiconductor layer 110 constituting the light-emitting element 11, which exists in the pixel array portion 100A and the peripheral portion 100B. For example, Figure 2As shown, and for example, they are respectively provided in the peripheral portions of the pixel array portion 100A and the peripheral portion 100B.

[0101] The light-emitting element 11 includes a solid-state light-emitting element that emits light having a predetermined wavelength band from its surface 11S1, and includes, for example, an LED (light-emitting diode) chip. The LED chip is a chip in the state of being removed from a wafer used for crystal growth, and is not a packaged chip covered by a formed resin or the like. The LED chip, for example, has a size of not less than 5 μm and not more than 100 μm, and includes so-called micro LEDs.

[0102] In the light-emitting element 11, a first conductivity type layer 111 and a second conductivity type layer 113 are stacked sequentially. The upper surface of the second conductivity type layer 113 serves as a light output surface (surface 11S1). A light-emitting region 112 is formed between the first conductivity type layer 111 and the second conductivity type layer 113. Light in the blue band, for example, above 430 nm and below 500 nm, is emitted from the light-emitting region 112. Furthermore, light corresponding to wavelengths in the ultraviolet region, for example, can be extracted from the light-emitting region (ultraviolet light).

[0103] The first conductivity type layer 111 includes, for example, a p-type GaN-based semiconductor material. The second conductivity type layer 113 includes, for example, an n-type GaN-based semiconductor material.

[0104] The electrode layer 12 serves as a common electrode for the plurality of light-emitting elements 11 and is continuously formed on the surface 11S1 of each of the plurality of light-emitting elements 11. The electrode layer 12 is in ohmic contact with the second conductivity type layer 113 and includes a transparent electrode material such as indium tin oxide (ITO), indium zinc oxide (IZO), tin oxide (SnO) or TiO.

[0105] The insulating layer 13 is used to fill the unevenness formed on the upper side of the plurality of light-emitting elements 11. The insulating layer 13 includes, for example, silicon oxide (SiO), silicon nitride (SiN), etc.

[0106] Extraction electrode 14 is used to apply voltage to a second conductivity type layer 113 of each of the plurality of light-emitting elements 11, and through openings 13H, for example, provided in the insulating layer 13 between adjacent light-emitting elements 11 (see...). Figure 7QThe extraction electrode 14 is electrically coupled to the electrode layer 12. In the pixel array portion 100A, the extraction electrode 14 is continuously formed between adjacent light-emitting elements 11 to avoid the surface 11S1 of a plurality of light-emitting elements 11 arranged, for example, in a honeycomb pattern, and extends to a portion of the peripheral portion 100B. The extraction electrode 14 formed in the peripheral portion 100B is electrically coupled to the pad electrode 16B via an opening H1 that penetrates the insulating layer 13, the embedding layer 119, and the protective layer 117. For example, the extraction electrode 14 is formed by using a multilayer film including titanium (Ti) and aluminum (Al) (Ti / Al) or a multilayer film including chromium (Cr) and gold (Au) (Cr / Au).

[0107] An electrode layer 114 is formed on the lower surface (surface 11S2) of the first conductivity type layer 111 of the light-emitting element 11. The electrode layer 114 is in ohmic contact with the first conductivity type layer 111 and is formed by using, for example, a multilayer film (Ni / Au) comprising nickel (Ni) and gold (Au) or a transparent conductive material such as ITO.

[0108] An insulating layer 115 is disposed on the electrode layer 114. The insulating layer 115 includes, for example, silicon oxide (SiO) or silicon nitride (SiN).

[0109] Although described in detail later, the alignment mark 116 is used, for example, to perform position alignment when transferring multiple monolithic chips of the compound semiconductor layer 110 constituting the light-emitting element 11 to the transfer substrate 53. The alignment mark 116 is disposed on the surface 11S2 of the compound semiconductor layer 110 constituting the light-emitting element 11 and is present in the pixel array portion 100A and the peripheral portion 100B. As described above, the alignment mark 116 is respectively disposed on the periphery of the pixel array portion 100A and the peripheral portion 100B.

[0110] Figures 4A to 4I Each schematically illustrates an example of the planar shape of the alignment mark 116. It is sufficient for the alignment mark 116 to have a shape readable by the exposure machine. As an example, the alignment mark 116 may be cross-shaped, for example, as shown below. Figure 2 and Figure 4A As shown in the diagram. For example, alignment mark 116 can have, for example, as shown in the diagram. Figure 4B The "X" shape shown, or may have the following characteristics Figure 4C The circle shown. For example, alignment mark 116 may have a circle as shown. Figure 4D The flower shape shown, or may have the following characteristics: Figure 4E The quadrilateral shown, or may have the following characteristics: Figure 4F The diamond shape shown. For example, alignment mark 116 may have a shape like... Figure 4G The grid shape shown, or may have the following characteristics: Figure 4H The fence shape shown. For example, alignment mark 116 may have the following shape: Figure 4IThe shape shown is that of the so-called Dutch windmill.

[0111] Similarly, the size and film thickness of the alignment mark 116 are sufficient, for example, to allow the exposure machine to read the size and film thickness of the alignment mark 116. As an example, it is sufficient for the alignment mark 116 to have a size of not less than 10 μm and not more than 100 μm. The film thickness of the alignment mark 116 is, for example, 200 nm or more.

[0112] For example, alignment mark 116 may include a transparent conductive film that is transparent to visible light. Transparent conductive films that are transparent to visible light include, for example, ITO films, IZO films, SnO films, TiO films, etc.

[0113] It should be noted that an instance has already been described, in which, in Figure 2 An alignment mark 116 formed on each chip is provided at each position in the pixel array portion 100A and the peripheral portion 100B of the light-emitting device 1. However, this is not limiting. For example, the alignment mark 116 formed on each chip can be provided at either the position in the pixel array portion 100A or the position in the peripheral portion 100B of the light-emitting device 1. Furthermore, for example, regardless of the position in the pixel array portion 100A and the peripheral portion 100B of the light-emitting device 1, it can be provided at, for example, the position in the pixel array portion 100A and the peripheral portion 100B of the light-emitting device 1. Figure 6C An alignment mark 116 is set at each of the four corners of each of the rectangular chips shown.

[0114] The light-emitting element 11 has a mesa shape disposed on the side of the driving substrate 30 and including a first conductivity type layer 111, a light-emitting region 112, and a portion of a second conductivity type layer 113. A protective layer 117 covers the side surface of the light-emitting element 11, which is processed into a mesa shape, including the side surface of the first conductivity type layer 111, the light-emitting region 112, and a portion of the second conductivity type layer 113. The protective layer 117 includes, for example, silicon oxide (SiO) or silicon nitride (SiN).

[0115] Furthermore, the laminated film, including insulating film 118A and reflective film 118B, covers the upper side of protective layer 117 and the side surface of second conductivity type layer 113 exposed from protective layer 117. The laminated film is continuously formed on multiple light-emitting elements 11. The laminated film includes an opening 118H on the surface 11S2 of the light-emitting element 11. A plug 15 is formed in the opening 118H. Insulating film 118A is made of insulating materials such as silicon oxide (SiO) and silicon nitride (SiN). Reflective film 118B contains, for example, a metal with high reflectivity in the visible light region. Specific materials include, for example, silver (Ag), aluminum (Al), copper (Cu), gold (Au), platinum (Pt), rhodium (Rh), and alloys of these materials.

[0116] The embedding layer 119 is used to embed a plurality of light-emitting elements 11 and forms a flat front surface and a flat rear surface of the element substrate 10. The embedding layer 119 includes an insulating material such as silicon oxide (SiO) or silicon nitride (SiN).

[0117] The plug 15 is used to apply a voltage to the first conductive type layer 111 of each of the plurality of light-emitting elements 11. The plug 15 is formed by using, for example, copper (Cu), aluminum (Al), tungsten (W), silver (Ag), or alloys of these materials.

[0118] An insulating layer 17 is disposed on the driving substrate 30 side of the embedded layer 119. In the insulating layer 17, a plurality of pad portions 16A, which are provided in each light-emitting element 11A, are formed in the pixel array portion 100A. Furthermore, a plurality of pad electrodes 16B, which are provided in the peripheral portion 100B, are formed, and vias are formed. The insulating layer 17 includes, for example, silicon oxide (SiO) and silicon nitride (SiN). The pad portions 16A, pad electrodes 16B, and vias are formed using alloys of materials such as copper (Cu), aluminum (Al), tungsten (W), and silver (Ag).

[0119] An insulating layer 18 and pad portions 19 are further disposed on the driving substrate 30 side of the insulating layer 17. The insulating layer 18 forms a bonding surface with the driving substrate 30. The pad portions 19 are embedded in and formed within the insulating layer 18. The insulating layer 18 includes, for example, silicon oxide (SiO) or silicon nitride (SiN). The pad portions 19 include, for example, copper (Cu).

[0120] A wavelength converter 20 is disposed on the light extraction surface S1 side of the element substrate 10. The wavelength converter 20 includes a planarization layer 21, a partition layer 22 having, for example, an opening 22H for each light-emitting element 11, and a wavelength conversion layer 23 formed within the opening 22H. A reflective film 24 is also disposed between the partition layer 22 and the wavelength conversion layer 23. A protective layer 25 is further disposed on the light extraction surface S1 side of the wavelength conversion layer 23, and a wavelength selection layer 26 is disposed within the protective layer 25. An on-chip lens layer 27 is also disposed on the protective layer 25.

[0121] The planarization layer 21 is used to planarize the surface of the component substrate 10 on the light extraction surface S1 side. The planarization layer 21 includes, for example, silicon oxide (SiO) and silicon nitride (SiN).

[0122] When the light-emitting device 1 is applied to the image display device 100, the partition layer 22 is used to suppress color mixing caused by light leakage between adjacent RGB sub-pixels (red pixel Pr, green pixel Pg, and blue pixel Pb). The partition layer 22 has, for example, a honeycomb structure. Specifically, the partition layer 22 has, for example, an opening 22H, which has a generally regular hexagonal shape for each of the plurality of light-emitting elements 11 arranged in an array, such as... Figure 3 As shown. For example, when viewed in cross-section, the opening 22H has an inclined surface at an angle of less than 90° relative to the surface 20S2 of the wavelength converter 20, which is located on the opposite side of the surface 20S1. In other words, when viewed in cross-section, the partition layer 22 has a positively tapered shape between adjacent pixels Pr, Pg, and Pb. Preferably, the partition layer 22 is formed using a material with high thermal conductivity and high electrical conductivity, and for example, using a metallic material such as copper (Cu), aluminum (Al), gold (Au), nickel (Ni), platinum (Pt), etc.

[0123] A wavelength conversion layer 23 is used to convert light emitted from the plurality of light-emitting elements 11 into light of a desired wavelength (e.g., red (R) / green (G) / blue (B)) for output, and is formed within an opening 22H disposed on the upper side of each light-emitting element 11. Specifically, the red pixel Pr has a red wavelength conversion layer 23R that converts the light emitted from the light-emitting element 11 into light in the red band (red light). Furthermore, the green pixel Pg includes a green wavelength conversion layer 23G that converts the light emitted from the light-emitting element 11 into light in the green band (green light). Furthermore, the blue pixel Pb includes a blue wavelength conversion layer 23B that converts the light emitted from the light-emitting element 11 into light in the blue band (blue light).

[0124] Each of the wavelength conversion layers 23R, 23G, and 23B can be formed using quantum dots of corresponding colors. Specifically, in the case of obtaining red light, quantum dots can be selected from, for example, InP, GaInP, InAsP, CdSe, CdZnSe, CdTeSe, CdTe, etc. In the case of obtaining green light, quantum dots can be selected from, for example, InP, GaInP, ZnSeTe, ZnTe, CdSe, CdZnSe, CdS, CdSeS, etc. In the case of obtaining blue light, quantum dots can be selected from, for example, ZnSe, ZnTe, ZnSeTe, CdSe, CdZnSe, CdS, CdZnS, CdSeS, etc. It should be noted that in the case of emitting blue light from the light-emitting element 11 as described above, the blue wavelength conversion layer 23B can be formed using a resin layer with light transmittance.

[0125] A reflective film 24 is used to effectively extract light of each color emitted from the light-emitting element 11 and converted in each of the wavelength conversion layers 23R, 23G, and 23B from the light extraction surface (surface 22S1) of the wavelength conversion layer 23, and is disposed on the side surface of the opening 22H. The reflective film 24 is formed of a metallic material with light reflectivity. Metallic materials used to form the reflective film 24 include, for example, metals with high reflectivity in the visible light region. Specific examples of materials include, for example, silver (Ag), aluminum (Al), copper (Cu), gold (Au), platinum (Pt), rhodium (Rh), and alloys of these materials.

[0126] It should be noted that if the partition layer 22 is formed by using a metallic material with the above-mentioned light reflectivity, it is not necessary to form a reflective film 24.

[0127] The protective layer 25 is used to protect the front surface of the light-emitting device 1 and includes, for example, silicon oxide (SiO), silicon nitride (SiN), etc.

[0128] Within the protective layer 25, a wavelength selection layer 26 is disposed above the red pixel Pr and the green pixel Pg. The wavelength selection layer 26 is used to selectively reflect light, for example, in the blue band (blue light). As a result, the color purity of the red light and green light extracted from the red pixel Pr and the green pixel Pg, respectively, is improved.

[0129] The on-chip lens layer 27 is configured to cover the entire surface of the pixel array portion 100A and the peripheral portion 100B. The on-chip lens layer 27 includes a light-transmitting material and, for example, includes a single-layer film containing any one of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiCN), etc., or a laminated film containing two or more types of these materials.

[0130] An opening H2 is provided in the peripheral portion 100B. The opening H2 penetrates the on-chip lens layer 27, protective layer 25, partition layer 22, planarization layer 21, insulating layer 13, embedding layer 119, and protective layer 117, and reaches the pad electrode 18B. The pad electrode 18B exposed at the bottom of the opening H2 serves as an electrode coupled to the outside.

[0131] The driving substrate 30 includes a driving circuit for controlling the driving of a plurality of light-emitting elements 11 disposed in the pixel array section 100A. This driving circuit corresponds to a specific example of a "second functional element" according to an embodiment of the present disclosure. The driving substrate 30 includes: a support substrate 31, including, for example, silicon (Si); an interlayer insulating layer 32 disposed on the support substrate 31 and including a plurality of wiring layers (e.g., wiring layers M1, M2, M3, M4 and M5) and vias electrically coupled between the wiring layers; an insulating layer 33 forming a bonding surface with the element substrate 10; and a pad portion 34 formed in such a way as to embed the insulating layer 33.

[0132] The interlayer insulating layer 32 includes, for example, silicon oxide (SiO) and silicon nitride (SiN).

[0133] Wiring layers M1, M2, M3, M4, and M5, as well as vias electrically coupled between these wiring layers, are formed using materials such as copper (Cu), aluminum (Al), tungsten (W), silver (Ag), or alloys of these materials. Insulating layer 33 includes materials such as silicon oxide (SiO) or silicon nitride (SiN). Pad portion 35 is formed, for example, using copper (Cu).

[0134] (Manufacturing method of light-emitting device)

[0135] For example, the light-emitting device 1 according to this embodiment may be manufactured in the following manner. Figures 5A to 5L , Figures 6A to 6D , Figures 7A to 7W ,as well as Figures 8A to 8F Each describes an example of the steps involved in manufacturing the light-emitting device 1. Figures 5A to 5L and Figures 7A to 7W Each of these is a schematic cross-sectional view showing the steps involved in manufacturing the light-emitting device 1. Figures 6A to 6D It corresponds to Figures 5A to 5D A schematic plan view of each step. Figures 8A to 8F Each of these figures includes a schematic cross-sectional view (A) and a schematic plan view (B), and each shows the... Figure 5A and Figure 5B The steps involved in creating alignment marks between the steps.

[0136] First, such as Figure 5A and Figure 6A As shown, for example, a silicon substrate is used as the growth substrate 51 to perform a process such as metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). Subsequently, a transparent conductive film 116A comprising, for example, ITO is formed on the compound semiconductor layer 110 using, for example, chemical vapor deposition (CVD).

[0137] Next, for example, such as Figure 5B and Figure 6B As shown, alignment marks 116 are formed on the compound semiconductor layer 110 to align with the boundary when the compound semiconductor layer 110 is monolithically divided into multiple semiconductor layers 110 (see [reference]). Figure 6B (The dashed line in the image). Subsequently, after forming an electrode layer 114 including, for example, ITO, and an insulating layer 115, the front surface of the insulating layer 115 is planarized, for example, by chemical mechanical polishing (CMP).

[0138] Specifically, such as Figure 8AAs shown, after the compound semiconductor layer 110 and the transparent conductive film 116A are sequentially formed on the growth substrate 51, as... Figure 8B As shown, a resist film 201 is patterned on the transparent conductive film 116A, for example, formed in a cross shape. Next, the transparent conductive film 116A is processed, for example, by dry etching, and then, as... Figure 8C As shown, the resist film 201 is removed. Through this process, alignment marks 116 in a cross shape are formed on the compound semiconductor layer 110. Next, for example, an electrode layer 114 including, for example, ITO, a SiO film 115A as an insulating layer 115, and a SiN film 115B are sequentially formed on the compound semiconductor layer 110, as follows: Figure 8D As shown. Then, for example, as... Figure 8E As shown, a tetraethyl orthosilicate (TEOS) film 115C is further formed as an insulating layer 115, and then, as... Figure 8F As shown, the front surface of the insulating layer 115 (TEOS film 115C) is planarized by CMP.

[0139] Subsequently, the insulating layer 115, electrode layer 114, and compound semiconductor layer 110 are patterned by etching using techniques such as photolithography. Figure 5C and Figure 6C As shown. Next, as... Figure 5D and Figure 6D As shown, the growth substrate 51 is transferred such that the insulating layer 115 is opposite to the support substrate 52, and then the growth substrate 51 is monolithized by cutting.

[0140] Subsequently, as Figure 5E As shown, corresponding chips, including the monolithic growth substrate 51, are bonded to the transfer substrate 53 so as to be aligned with the insulating layer 115. At this time, the chips are bonded to the transfer substrate 53 while the alignment mark 116 is detected using a transfer mechanism. This reduces the positional misalignment of the chips relative to each other.

[0141] Next, for example, grinding and polishing are performed to reduce the thickness of the growth substrate 51 to, for example, 500 nm. Figure 5F As shown in the image. Next, as... Figure 5G As shown, a reverse substrate 54 is bonded to the growth substrate 51 side to reverse its orientation. Additionally, the transfer substrate 53 is removed. Next, after planarizing the front surface of the insulating layer 115 again by, for example, CMP, the insulating layer 115 is bonded to the support substrate 55, and the growth substrate 51 is removed, for example, by grinding and polishing. Figure 5H As shown in the image.

[0142] Subsequently, the embedded layer 119 is formed on the support substrate 55, for example by a CVD method, and is planarized, as shown below. Figure 5I As shown. Next, as Figure 5J As shown, the ends of the embedded layer 119 and the support substrate 55 are trimmed off. Next, the embedded layer 119 is bonded to the support substrate 56, for example, by plasma bonding, and then the support substrate 55 is removed, as shown. Figure 5K As shown in the image. Below, we will refer to the enlarged version. Figure 5L The interior of box X in the diagram is described.

[0143] First, the insulating layer 115 and the electrode layer 114 are etched using techniques such as photolithography, and then patterned, as follows: Figure 7A As shown in the figure. Subsequently, for example, a portion of the compound semiconductor layer 110 is etched using photolithography to form a mesa structure including a first conductivity type layer 111, a light-emitting region 112, and a portion of a second conductivity type layer 113, as shown. Figure 7B As shown.

[0144] Next, for example, by atomic layer deposition (ALD), an AlO film is formed on: the upper surface of the insulating layer 115, the side surface of the insulating layer 115; the side surface of the electrode layer 114; the side surfaces of the first conductivity type layer 111 constituting the mesa structure, the light-emitting region 112, and the second conductivity type layer 113; and the bottom surface of the second conductivity type layer 113. Then, a SiN film is further formed by, for example, CVD. Subsequently, the SiN film is etched using, for example, photolithography, and protective layers 117 serving as sidewalls are formed on the upper and side surfaces of the mesa structure. Figure 7C As shown.

[0145] Subsequently, as Figure 7D As shown, for example, photolithography is used to form a separation portion 110H that penetrates, for example, the second conductivity type layer 113 exposed from the protective layer 117 and the growth substrate 51, thereby forming a plurality of light-emitting elements 11. Next, for example, an A10 film covering the upper surface of the protective layer 117 and the exposed sides of the light-emitting elements 11 is formed using an ALD method. Next, for example, an insulating film 118A and a reflective film 118B are sequentially formed using a CVD method, and then an opening 118H is formed on the upper surface of the mesa structure, as shown. Figure 7E As shown.

[0146] Next, as Figure 7F As shown, for example, an embedding layer 119 is further formed by a CVD method to fill the separation portion 110H and the opening 118H. Then, after the embedding layer 119 is planarized, a plug 15 with multiple pad portions 16A and pad electrodes 16B embedded is formed for each light-emitting element 11, as shown. Figure 7G As shown. Subsequently, the thickness of the insulating layer 17 is increased, and an insulating layer 18 is formed on the insulating layer 17, as... Figure 7H As shown. Then, as Figure 7IAs shown, the end of the support substrate 55 is trimmed off.

[0147] Next, as Figure 7J As shown, an opening 18H is formed on each pad portion 16A and pad electrode 16B. The opening 18H is then filled with, for example, Cu to form a plurality of pad portions 19, as shown. Figure 7K As shown. Subsequently, for example, the front surfaces of the insulating layer 18 and the plurality of pad components 19 are polished by CMP to planarize the bonding surfaces with the drive substrate 30.

[0148] Subsequently, as Figure 7L As shown, for example, multiple pad portions 19 and multiple pad portions 34 of the separately formed drive substrate 30 are bonded to each other by CuCu bonding at 400°C. Thereafter, as... Figure 7M As shown, the support substrate 55 is removed. Next, for example, photolithography is used to expose the front surface of the plurality of light-emitting elements 11 (specifically, the second conductivity type layer 113), as shown. Figure 7N As shown. Then, as... Figure 7O As shown, for example, an ITO film is formed by a CVD method, and then, for example, a photolithography technique is used to pattern the ITO film to form an electrode layer 12.

[0149] Next, as Figure 7P As shown, for example, an insulating layer 13 is formed by a CVD method, and an opening 13H is formed between adjacent light-emitting elements 11 by using, for example, photolithography. Then, as... Figure 7Q As shown, for example, photolithography is used to form the opening H1 reaching the pad electrode 16B. Subsequently, for example, a Ti / W laminate is formed by a CVD method. Then, the laminate is patterned using, for example, photolithography to form the extraction electrode 14, as shown. Figure 7R As shown in the image.

[0150] Next, for example, planarization layer 21 and partition layer 22 are sequentially formed using a CVD method, such as... Figure 7S As shown in the figure. Subsequently, openings 22H are formed in the partition layer 22 on the upper part of each light-emitting element 11 using, for example, photolithography, as shown. Figure 7T As shown in the image. Next, as... Figure 7U As shown, for example, an Al film is formed on the upper surface of the partition layer 22 and the side and bottom surfaces of the opening 22H by CVD. Then, the Al film formed on the upper surface of the partition layer 22 and the bottom surface of the opening 22H is removed by deep etching, and a reflective film 24 is formed on the side surface of the opening 22H.

[0151] Subsequently, the various colors of the wavelength conversion layers 23 (23R, 23G, and 23B) are formed within the opening 22H, for example, by a coating method such as inkjet printing. Figure 7VAs shown in the image. Then, as... Figure 7W As shown, a protective layer 25, including a wavelength selection layer 26, is formed on the spacer layer 22 and the wavelength conversion layer 23. Then, an on-chip lens layer 27 is bonded to it. At this time, by bonding the on-chip lens layer 27 while simultaneously detecting the alignment mark 116 using a transfer mechanism, the individual microlenses of the on-chip lens layer 27 and the individual light-emitting elements 11 arranged in a two-dimensional array can be precisely bonded to each other. Through these processes, the... Figure 1 The light-emitting device 1 shown.

[0152] (1-3. Work and Results)

[0153] In the light-emitting device 1 according to this embodiment, alignment marks 116, including a transparent conductive film that is transparent to visible light, are provided at the surface 11S2 of the compound semiconductor layer 110, which constitutes a plurality of light-emitting elements 11 arranged in an array in the plane of the element substrate 10. This configuration facilitates positional alignment, for example, when transferring a monolithic chip of the compound semiconductor layer 110 to a transfer substrate 53 during the formation of the light-emitting elements 11. This will be described below.

[0154] In recent years, highly precise image display devices have been widely used. These devices utilize light-emitting devices, including miniature LEDs using gallium nitride (GaN) as the light source. In the case of such devices, monolithic fabrication and bonding are performed, where multiple GaN chips are arranged and bonded on a wafer. If the GaN chips bonded to the wafer are misaligned, a decrease in alignment accuracy with the individual GaN chips will occur in subsequent manufacturing processes.

[0155] Conversely, according to this embodiment, before monolithizing the compound semiconductor layer 110, alignment marks 116, including a transparent conductive film (e.g., ITO) that is transparent to visible light, are formed on the compound semiconductor layer 110. This allows the individual chips of the compound semiconductor layer 110 produced by monolithization to be accurately transferred, for example, to a transfer substrate 53. In the light-emitting device 1 in which the driving substrate 30 and the element substrate 10 having a plurality of light-emitting elements 11 are stacked on top of each other, the plurality of light-emitting elements 11 include the compound semiconductor layer 110 arranged in an array in a plane. For example, alignment marks 116 are retained in the peripheral portion and the outer periphery portion 100B of the pixel array portion 100A and on the surface 11S2 of the compound semiconductor layer 110 opposite to the driving substrate 30. With the light-emitting device 1, the on-chip lens layer 27 can be precisely bonded to each light-emitting element 11 by using the alignment marks 116 as a reference.

[0156] Using the above configuration, the light-emitting device 1 and the image display device 100 including the light-emitting device 1 according to this embodiment can each perform position alignment with high precision.

[0157] Furthermore, for the light-emitting device 1 according to this embodiment, the alignment mark 116 is formed on the same layer as the electrode layer 114. According to this structure, even if a step is generated around the alignment mark 116 due to its placement, the step can be eliminated, for example, by planarizing the surface of the insulating layer 115 (TEOS film 115C) formed on the alignment mark 116 using CMP. Therefore, the need to consider the impact on bonding to the driving substrate 30 can be eliminated.

[0158] Next, variations 1 to 3 and application examples of this disclosure will be described. Furthermore, the description of the same reference numerals used for the constituent elements corresponding to the light-emitting device 1 in the above embodiments will be omitted.

[0159] <2. Variations>

[0160] (2-1. Variation Example 1)

[0161] Figure 9 An example of the cross-sectional configuration of a light-emitting device (light-emitting device 2) according to a variation 1 of this disclosure is schematically shown. Figure 10 Schematic illustration Figure 9 An example of the planar configuration of the light-emitting device 2 shown. As in the above embodiments, the light-emitting device 2 can be advantageously applied to image display devices known as LED displays (e.g., the electronic viewfinder 1124 of a digital still camera 1120, etc.).

[0162] The above embodiment provides an example in which alignment marks 116 are provided in each of the peripheral portion and the outer periphery 100B of the pixel array portion 100A in a plan view. However, this is not limiting. The light-emitting device 2 according to this modification includes a virtual region 100C between the pixel array portion 100A, in which a plurality of light-emitting elements 11 are arranged in a two-dimensional array, and the outer periphery 100B provided around the pixel array portion 100A. Similar to the pixel array portion 100A, a compound semiconductor layer 110 constituting the light-emitting element 11 is provided in the virtual region 100C. For example, an alignment mark 116 is provided on the surface 11S2 of the compound semiconductor layer 110 provided in the virtual region 100C. Apart from this, the light-emitting device 2 has a structure substantially the same as the light-emitting device 1 of the above embodiment.

[0163] In this manner, in the light-emitting device 2 according to this modification, a virtual region 100C is formed between the pixel array portion 100A and the peripheral portion 100B, and an alignment mark 116 is provided in the virtual region 100C. Even with this configuration, the light-emitting device 2 according to this modification can achieve similar effects to the light-emitting device 1 according to the above embodiment.

[0164] (2-2. Variation Example 2)

[0165] Figures 11A to 11F Each describes an example of the steps for manufacturing a light-emitting device according to Variation 2 of this disclosure.

[0166] The above embodiments provide an example where the alignment mark 116 is formed directly on the compound semiconductor layer 110. However, this is not limiting. For example, in the three layers constituting the insulating layer 115 (SiO film 115A, SiN film 115B, and TEOS film 115C), the alignment mark 116 can be formed between the SiO film 115A and the SiN film 115B. Apart from this, this variation 2 has a configuration that is substantially the same as the above embodiments.

[0167] Here, SiO film 115A corresponds to a specific example of a "first insulating film" according to one embodiment of the present disclosure. SiN film 115B corresponds to a specific example of a "second insulating film" according to one embodiment of the present disclosure.

[0168] According to this variation, the alignment mark 116 can be formed in the following manner.

[0169] First, such as Figure 11A As shown, a compound semiconductor layer 110, an electrode layer 114, a SiO film 115A, and a transparent conductive film 116A are sequentially formed on the growth substrate 51. Next, as... Figure 11B As shown, a resist film 201 is patterned in, for example, a cross shape on a transparent conductive film 116A. Next, as... Figure 11C As shown, for example, the transparent conductive film 116A is processed by dry etching, and then the resist film 201 is removed. Through this process, a cross-shaped alignment mark 116 is formed on the SiO film 115A.

[0170] Next, for example, such as Figure 11D As shown, a SiN film 115B is formed on the SiO film 115A. Subsequently, for example, as... Figure 11E As shown, a TEOS film 115C is further formed, and then, as... Figure 11FAs shown, the front surface of the insulating layer 115 (TEOS film 115C) is planarized by CMP. Thereafter, a process similar to that described in the above embodiment is performed to complete the light-emitting device that includes alignment marks 116 between the SiO film 115A and the SiN film 115B.

[0171] In this manner, in this modified example, alignment marks 116 are formed between the SiO film 115A and the SiN film 115B in the three layers constituting the insulating layer 115 (SiO film 115A, SiN film 115B, and TEOS film 115C). Even with this configuration, the light-emitting device according to this modified example can achieve effects similar to those of the light-emitting device 1 according to the above embodiment.

[0172] (2-3. Variation Example 3)

[0173] Figures 12A to 12E Each describes an example of the steps for manufacturing a light-emitting device according to Variation 2 of this disclosure.

[0174] The above embodiments provide an example where the alignment mark 116 is formed directly on the compound semiconductor layer 110. However, this is not limiting. For example, in the three layers constituting the insulating layer 115 (SiO film 115A, SiN film 115B, and TEOS film 115C), the alignment mark 116 may be formed between the SiN film 115B and the TEOS film 115C. Apart from this, this variation 2 has a configuration that is substantially the same as the above embodiments.

[0175] Here, SiO film 115A corresponds to a specific example of a "first insulating film" according to one embodiment of the present disclosure. SiN film 115B corresponds to a specific example of a "second insulating film" according to one embodiment of the present disclosure.

[0176] The alignment mark 116 according to this variation can be formed in the following manner.

[0177] First, such as Figure 12A As shown, a compound semiconductor layer 110, an electrode layer 114, a SiO film 115A, a SiN film 115B, and a transparent conductive film 116A are sequentially formed on the growth substrate 51. Next, for example... Figure 12B As shown, a resist film 201 is patterned in a cross shape on a transparent conductive film 116A. Next, as... Figure 12C As shown, for example, the transparent conductive film 116A is processed by dry etching, and then the resist film 201 is removed. Through this process, a cross-shaped alignment mark 116 is formed on the SiO film 115A.

[0178] Next, for example, a TEOS film 115C is formed on the SiN film 115B, such as Figure 12DAs shown. Next, as Figure 12E As shown, the surface of the insulating layer 115 (TEOS film 115C) is planarized by CMP. Thereafter, a process similar to that described in the above embodiment is performed to complete the light-emitting device comprising alignment marks 116 between the SiN film 115B and the TEOS film 115C.

[0179] In this manner, in this modified example, alignment marks 116 are formed between the SiN film 115B and the TEOS film 115C of the three layers constituting the insulating layer 115 (SiO film 115A, SiN film 115B, and TEOS film 115C). Even with this configuration, the light-emitting device according to this modified example can achieve effects similar to those of the light-emitting device 1 according to the above embodiment.

[0180] <3. Application Examples>

[0181] (Application Example 1)

[0182] Figure 13A This is a front view showing an example of the appearance of a digital still camera (electronic device) 1120. Figure 13B This is a rear view showing an example of the appearance of a digital still camera 1120. The digital still camera 1120 is a single-lens reflex type with an interchangeable lens. The digital still camera 1120 includes an interchangeable shooting lens unit (interchangeable lens) 1121 approximately in the middle of the front surface of the camera body (camera body) 1122, and also includes a grip portion 1123 for the photographer to hold on the left side of the front surface.

[0183] The monitor 1126 is positioned offset to the left from the center of the back of the camera body 1122. An electronic viewfinder (viewfinder window) 1124 is located above the monitor 1126. The photographer views through the electronic viewfinder 1124 and visually identifies the optical image of the object guided by the shooting lens unit 1121, thereby determining the composition. The electronic viewfinder 1124 includes a light-emitting device 1.

[0184] (Application Example 2)

[0185] The light-emitting device (e.g., light-emitting device 1) according to this disclosure is suitable for head-mounted displays (hereinafter referred to as HMDs). The head-mounted display 1130A can be used for VR (virtual reality), AR (augmented reality), MR (mixed reality), SR (alternative reality), etc.

[0186] Figure 14AThis is a perspective view showing the appearance of a head-mounted display (electronic device) 1130A. The head-mounted display 1130A includes, for example, ear hooks 1131, which are provided on each of the two sides of an eyeglass-type display unit 1132 and are intended for mounting on a user's head. The display unit 1132 includes a light-emitting device 1.

[0187] Figure 14B This is a perspective view showing the appearance of another head-mounted display (electronic device). The head-mounted display includes smart glasses 1130B that display various types of information on glasses 1133. Smart glasses 1130B includes a main body, an arm 1135, and a lens barrel 1136. The main body 1134 is coupled to the arm 1135. The main body 1134 is configured to be attachable to and detachable from glasses 1133. The main body 1134 includes a control board for controlling the operation of smart glasses 1130B and the display device. The main body 1134 and the lens barrel 1136 are coupled to each other via the arm 1135. The lens barrel 1136 outputs imaging light from the main body 1134 to the lens 1137 side of glasses 1133 via the arm 1135. This imaging light enters the eye through the lens 1137. Like ordinary glasses, Figure 14B The wearer of the smart glasses 1130B is not only able to visually recognize the surrounding environment, but also to visually recognize various types of information output from the lens barrel 1136. The main body 1134 includes a light-emitting device 1.

[0188] (Application Example 3)

[0189] Figure 15 This is a perspective view showing an example of the appearance of a television device (electronic device) 1140. For example, the television device 1140 includes an image display unit 1141, which includes a front panel 1142 and a light filter glass 1143. The image display unit 1141 includes a light-emitting device 1.

[0190] These are descriptions of the present technology by providing embodiments, variations 1 to 3, and application examples. However, the present technology is not limited to the embodiments described above, and various variations are possible. For example, the embodiments described above provide examples where the light emitted from the light-emitting element 11 is blue light or ultraviolet light. However, this is not limiting. For example, for the light-emitting device 1, a light-emitting element that emits two or more types of light, such as blue and green light, or ultraviolet and green light, can be used.

[0191] Furthermore, the above embodiments provide examples in which the separation portion 11H, which separates the compound semiconductor layer 110 into a plurality of light-emitting elements 11, extends through the compound semiconductor layer 110 from the surface 11S2 side. However, this is not limiting. The separation portion 11H may be provided from both sides of the surface 11S1 and surface 11S2 of the compound semiconductor layer 110.

[0192] Furthermore, in the above embodiments, individual components constituting the light-emitting device 1, etc., have been specifically listed and described. However, it is not necessary to include all components. In addition, other components may be provided.

[0193] Furthermore, the above embodiments provide examples of light-emitting devices in which a driving substrate 30 and a component substrate 10 in which a plurality of light-emitting elements 11 are arranged in a two-dimensional array are stacked on top of each other, and the light-emitting device serves as an example of a stacking device. However, this is not limiting. For example, this technology can be applied to detection units in which component substrates (including light-emitting elements serving as first functional elements) and sensor substrates (including sensor elements serving as second functional elements) are stacked on top of each other, and similar effects can be obtained.

[0194] It should be noted that the effects described in this specification are given by way of example only, and the effects are not limited to those described in this specification. Other effects are also possible.

[0195] This technology enables the following configuration. This configuration facilitates position alignment during the separation and transfer of semiconductor layers in the step of forming the first functional element. This allows for position alignment to be performed with high precision. (1)

[0197] A stacked device, comprising: A first substrate includes a semiconductor layer having a first surface and a second surface opposite to each other, and the first substrate includes a first functional element, the first functional element including the semiconductor layer. A second substrate is stacked on the first substrate, and the second substrate is opposite to the second surface of the semiconductor layer; and Alignment marks are disposed on the second surface side of the semiconductor layer in the first substrate, and the alignment marks include a conductive film that is transparent to visible light. (2)

[0199] According to the stacked device described in (1) above, wherein, The first substrate includes a plurality of the first functional elements, and The plurality of first functional elements are arranged in an array in a plane. (3)

[0201] According to the stacked device described in (2) above, wherein

[0202] The first substrate includes: an array portion, wherein the plurality of first functional elements are arranged in the array; and a peripheral portion disposed around the array portion, and

[0203] The alignment marks are disposed in the array section. (4)

[0205] According to the stacked device described in (2) above, wherein

[0206] The first substrate includes: an array portion, wherein the plurality of first functional elements are arranged in the array; and a peripheral portion disposed around the array portion, and

[0207] The alignment mark is disposed in the peripheral portion. (5)

[0209] According to the stacked device described in (2) above, wherein

[0210] The first substrate includes: an array portion, wherein the plurality of first functional elements are arranged in the array; and a peripheral portion disposed around the array portion, and

[0211] The alignment mark is disposed in each of the array portion and the peripheral portion. (6)

[0213] According to any one of (2) to (5) above, the stacked device wherein

[0214] The first substrate includes: An array section, wherein multiple first functional elements are arranged in an array; The peripheral portion is disposed around the array portion; and A virtual region, disposed between the array section and the peripheral section, and having a component structure substantially the same as that of the array section, and The alignment markers are set in the virtual area. (7)

[0216] The stacked device according to any one of (1) to (6) above, wherein the semiconductor layer comprises a compound semiconductor. (8)

[0218] The stacked device according to any one of (1) to (7) above, wherein the semiconductor layer comprises gallium nitride. (9)

[0220] According to any one of (1) to (8) above, the stacked device wherein the alignment mark is directly disposed on the second surface of the semiconductor layer. (10)

[0222] According to any one of (1) to (9) above, the stacked device, wherein, The first substrate further includes a first insulating film and a second insulating film sequentially stacked on the second surface of the semiconductor layer, and The alignment mark is disposed between the first insulating film and the second insulating film. (11)

[0224] According to any one of (1) to (10) above, the stacked device, wherein, The first substrate further includes a first insulating film and a second insulating film sequentially stacked on the second surface of the semiconductor layer, and The alignment mark is disposed on the second insulating film. (12)

[0226] The stacked device according to any one of (1) to (11) above, wherein the alignment mark has a cross shape, a circle, a quadrilateral shape, a grid shape or a windmill shape. (13)

[0228] The stacked device according to any one of (1) to (12) above, wherein the first functional element includes a light-emitting element. (14)

[0230] According to any one of (1) to (13) above, the stacked device includes a second functional element whose function is different from that of the first functional element. (15)

[0232] According to the stacked device described in (14) above, the second functional element includes a sensor element. (16)

[0234] According to any one of (13) to (15) above, the stacked device, wherein, The second substrate includes a second functional element whose function differs from that of the first functional element, and The second functional element includes a driving circuit element that controls the driving of the light-emitting element. (17)

[0236] The stacked device according to any one of (1) to (16) above, wherein the first substrate and the second substrate are coupled to each other by hybrid bonding. (18)

[0238] The stacked device according to any one of (1) to (17) above, wherein the first substrate and the second substrate are coupled to each other by CuCu bonding. (19)

[0240] An electronic device includes stacked devices. The stacked device includes: A first substrate includes a semiconductor layer having a first surface and a second surface opposite to each other, and the first substrate includes a first functional element, the first functional element including the semiconductor layer. A second substrate is stacked on the first substrate, and the second substrate is opposite to the second surface of the semiconductor layer; and Alignment marks are disposed on the second surface side of the semiconductor layer in the first substrate, and the alignment marks include a conductive film that is transparent to visible light. (20)

[0242] A method for manufacturing a multilayer device, the method comprising: A semiconductor layer is formed on a growth substrate by epitaxial growth; Alignment marks are formed by forming a conductive film that is transparent to visible light on the semiconductor layer; The semiconductor layer is monolithically divided into multiple semiconductor layers; The plurality of semiconductor layers generated by the monolithization are transferred onto the support substrate; Multiple first functional elements are formed by processing the multiple semiconductor layers individually; and thereafter... The first substrate and the second substrate are bonded together by hybrid bonding, and the first substrate includes a plurality of first functional elements.

[0243] This application claims priority to Japanese Patent Application No. 2024-048449, filed with the Japan Patent Office on March 25, 2024, the entire contents of which are incorporated herein by reference.

[0244] It should be understood that, depending on design requirements and other factors, those skilled in the art will make various corrections, combinations, sub-combinations and modifications, and these are within the scope of the appended claims or their equivalents.

Claims

1. A stacked device, comprising: A first substrate includes a semiconductor layer having a first surface and a second surface opposite to each other, and the first substrate includes a first functional element, the first functional element including the semiconductor layer. A second substrate is stacked on the first substrate, and the second substrate is opposite to the second surface of the semiconductor layer; as well as Alignment marks are disposed on the second surface side of the semiconductor layer in the first substrate, and the alignment marks include a conductive film that is transparent to visible light.

2. The stacked device according to claim 1, wherein, The first substrate includes a plurality of the first functional elements, and Multiple first functional elements are arranged in an array in a plane.

3. The stacked device according to claim 2, wherein, The first substrate includes: an array portion, wherein a plurality of the first functional elements are arranged in the array configuration; and a peripheral portion disposed around the array portion. The alignment marks are disposed in the array section.

4. The stacked device according to claim 2, wherein, The first substrate includes: an array portion, wherein a plurality of the first functional elements are arranged in the array configuration; and a peripheral portion disposed around the array portion. The alignment mark is disposed in the outer portion.

5. The stacked device according to claim 2, wherein, The first substrate includes: an array portion, wherein a plurality of the first functional elements are arranged in the array configuration; and a peripheral portion disposed around the array portion. The alignment mark is disposed in each of the array portion and the peripheral portion.

6. The stacked device according to claim 2, wherein, The first substrate includes: An array section, wherein a plurality of the first functional elements are arranged in an array; The peripheral portion is disposed around the array portion; and A virtual region, disposed between the array section and the peripheral section, and having a component structure substantially the same as that of the array section, and The alignment markers are set in the virtual area.

7. The stacked device according to claim 1, wherein, The semiconductor layer includes a compound semiconductor.

8. The stacked device according to claim 1, wherein, The semiconductor layer includes gallium nitride.

9. The stacked device according to claim 1, wherein, The alignment mark is directly disposed on the second surface of the semiconductor layer.

10. The stacked device according to claim 1, wherein, The first substrate further includes a first insulating film and a second insulating film sequentially stacked on the second surface of the semiconductor layer, and The alignment mark is disposed between the first insulating film and the second insulating film.

11. The stacked device according to claim 1, wherein, The first substrate further includes a first insulating film and a second insulating film sequentially stacked on the second surface of the semiconductor layer, and The alignment mark is disposed on the second insulating film.

12. The stacked device according to claim 1, wherein, The alignment marks can be cross-shaped, circular, quadrilateral, grid-shaped, or windmill-shaped.

13. The stacked device according to claim 1, wherein, The first functional element includes a light-emitting element.

14. The stacked device according to claim 1, wherein, The second substrate includes a second functional element whose function is different from that of the first functional element.

15. The stacked device according to claim 14, wherein, The second functional element includes a sensor element.

16. The stacked device according to claim 13, wherein, The second substrate includes a second functional element whose function differs from that of the first functional element, and The second functional element includes a driving circuit element that controls the driving of the light-emitting element.

17. The stacked device according to claim 1, wherein, The first substrate and the second substrate are coupled to each other by hybrid bonding.

18. The stacked device according to claim 1, wherein, The first substrate and the second substrate are coupled to each other by CuCu bonding.

19. An electronic device comprising stacked devices, The stacked device includes: A first substrate includes a semiconductor layer having a first surface and a second surface opposite to each other, and the first substrate includes a first functional element, the first functional element including the semiconductor layer. A second substrate is stacked on the first substrate, and the second substrate is opposite to the second surface of the semiconductor layer; as well as Alignment marks are disposed on the second surface side of the semiconductor layer in the first substrate, and the alignment marks include a conductive film that is transparent to visible light.

20. A method for manufacturing a multilayer device, the method comprising: A semiconductor layer is formed on a growth substrate by epitaxial growth; Alignment marks are formed by forming a conductive film that is transparent to visible light on the semiconductor layer; The semiconductor layer is monolithically divided into multiple semiconductor layers; The multiple semiconductor layers generated by the monolithization are transferred onto the support substrate; Multiple first functional elements are formed by processing multiple semiconductor layers individually; And afterwards, The first substrate and the second substrate are bonded together by hybrid bonding, and the first substrate includes the plurality of first functional elements.

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