Silicon-based silver electroplated microelectrode array, preparation method and application thereof

Abstract

The application discloses a silicon-based electroplated silver microelectrode structure, a preparation method and application thereof, and belongs to the technical field of biosensors. The microelectrode array structure comprises a silicon substrate, a patterned composite seed layer, a silver metal electrode layer, an insulating layer, and a microchannel structure layer formed by stacking two layers of patterned dry film photoresists. In the preparation, the patterned composite seed layer is prepared on the silicon substrate; the silver electrode layer is electrochemically deposited on the basis of the composite seed layer; then, the insulating layer is coated and windowed, and the silver electrode working area is exposed; and then, the two layers of dry film photoresists are laminated and patterned in sequence to form a double-layer microchannel. The application realizes the accurate control of the electrode structure and function through twice key photoetching alignment, provides a flat and stable interface for the integration of the subsequent multilayer microchannel, and can accurately construct a one-to-one electrode-chamber alignment structure through the dry film photoetching technology, so that each detection unit is isolated in the physical space, and the ultrahigh-throughput, low-crosstalk parallel detection is realized.

Description

Technical Field

[0001] This invention relates to the field of biosensor technology, and more specifically to a silicon-based electroplated silver microelectrode structure, its preparation method, and its application. Background Technology

[0002] Microfluidic chips, especially biosensor chips integrating functional microelectrodes, have become a core technology platform in modern in vitro diagnostics, gene sequencing, and single-molecule analysis. The performance of these chips largely depends on the electrical properties, chemical stability, and manufacturing precision of their built-in microelectrodes. In high-precision applications such as nanopore sequencing, cell impedance analysis, and electrochemical biosensing, the electrodes need to possess extremely low background noise, excellent electrochemical activity, good long-term stability, and manufacturability capable of high-density integration.

[0003] Currently, the mainstream fabrication technologies for metal microelectrodes in microfluidic chips mainly include physical vapor deposition (such as magnetron sputtering and electron beam evaporation), screen printing, and electrochemical deposition. While physical vapor deposition (PVD) can produce thin-film electrodes with high patterning accuracy, its high cost—including precious metal targets and complex vacuum equipment—makes it difficult to meet the cost control requirements of consumer-grade or large-scale screening applications. Secondly, electrode performance is limited, introducing significant thermal noise (Johnson noise) when detecting high-frequency or weak current signals. Furthermore, it suffers from insufficient process compatibility and scalability; subsequent patterning typically requires additional photolithography and etching steps, differing from standard semiconductor integration processes. Moreover, when scaling to larger wafers and higher-density arrays, thin-film uniformity and yield control face challenges.

[0004] Screen printing is a low-cost alternative suitable for mass production, typically using metal pastes (such as carbon paste or silver paste) to print electrodes. However, this method suffers from poor accuracy and consistency, and unstable electrochemical performance of the electrodes, making it unsuitable for quantitative detection scenarios requiring long-term stability or high sensitivity.

[0005] To address the aforementioned issues, electrochemical deposition has attracted attention due to its ability to selectively grow metals in specific regions, obtain thick films with properties approaching those of bulk materials, and its relatively low equipment cost. Existing technologies have reported the use of gold electroplating for electrode fabrication. However, gold ions exhibit poor stability in most electrolytes, and to obtain good coating quality, highly toxic electroplating solutions containing cyanide are often required, posing a serious challenge to production safety and environmental protection. Moreover, gold itself is an expensive strategic metal, and its raw material costs negate the economic advantages of this approach in large-scale applications.

[0006] In summary, current microfluidic chip electrode manufacturing technology faces a significant "technology triangle" dilemma: achieving high precision and high performance (e.g., sputtered gold), low cost and scalability (e.g., printing), and excellent electrochemical properties and process safety (e.g., cyanide-free electroplating) simultaneously is difficult. As biosensing advances towards high throughput (e.g., hundreds to thousands of parallel channels), high sensitivity (e.g., single-molecule detection), and portability, developing a novel electrode fabrication technology that can simultaneously overcome the bottlenecks of cost, performance, and manufacturability has become crucial for driving the field's development. Particularly in cutting-edge applications such as ultra-high-throughput nanopore gene sequencing chips with 256 channels and above, achieving wafer-level, highly consistent, low-cost manufacturing while ensuring ultra-high performance for individual electrodes remains an industry challenge that current technologies have not effectively addressed. Summary of the Invention

[0007] In view of this, the present invention provides a silicon-based electroplated silver microelectrode array structure, a preparation method thereof, and its application, in order to solve the bottleneck problems existing in the prior art.

[0008] To achieve the above objectives, the present invention adopts the following technical solution.

[0009] On the one hand, the present invention proposes a silicon-based electroplated silver microelectrode array structure, comprising: A silicon substrate, including a silicon wafer and a silicon dioxide insulating layer formed on the surface of the silicon wafer; A patterned composite seed layer is formed on the silicon substrate; A metal electrode layer is formed on the patterned composite seed layer; An insulating layer is formed on the metal electrode layer; The first microfluidic structure layer is formed by patterning a first dry film layer of photoresist and is stacked on the insulating layer. The second microfluidic channel structure layer is formed by patterning the second dry film layer and is stacked on the first microfluidic channel structure layer.

[0010] In the aforementioned silicon-based electroplated silver microelectrode array structure, the silicon substrate is a silicon wafer with a silicon dioxide insulating layer on its surface; the thickness of the silicon wafer is 1000-3000 nm; and the thickness of the silicon dioxide insulating layer is 50 nm-500 nm.

[0011] In the aforementioned silicon-based electroplated silver microelectrode array structure, the composite seed layer includes at least one metal layer, wherein the metal layer material is at least one of chromium, nickel, titanium, copper, aluminum, silver, gold, and platinum, and the thickness of the composite seed layer is greater than 10 nm.

[0012] In the aforementioned silicon-based electroplated silver microelectrode array structure, the metal layer includes a chromium layer and a copper layer located on top of the chromium layer.

[0013] In the aforementioned silicon-based electroplated silver microelectrode array structure, the metal electrode is a silver electrode.

[0014] The aforementioned silicon-based electroplated silver microelectrode array has a silver electrode thickness greater than 10 nm.

[0015] On the other hand, the present invention also provides a method for fabricating a silicon-based electroplated silver microelectrode array structure, comprising the following steps: Step S1: Form a patterned composite seed layer on a silicon substrate, wherein the patterned composite seed layer includes at least a chromium layer and a copper layer; Step S2: Using the patterned composite seed layer as a conductive substrate, a metal electrode layer is formed on it through an electrochemical deposition process; the material of the metal electrode layer is silver. Step S3: Form an insulating layer on the metal electrode layer and the uncovered substrate area; pattern the insulating layer to form an opening that exposes at least a portion of the metal electrode layer; Step S4: On the patterned insulating layer, the first microchannel structure layer and the second microchannel structure layer are laminated sequentially to form a microelectrode array structure.

[0016] The above-mentioned method for fabricating a silicon-based electroplated silver microelectrode array structure, wherein the patterned composite seed layer is formed by a lift-off process, includes: forming a first photolithographic pattern on the silicon substrate to expose the substrate surface of a predetermined electrode region; and sequentially forming a chromium layer and a copper layer covering the photolithographic pattern and the exposed substrate surface by physical vapor deposition.

[0017] In the above-mentioned method for preparing the silicon-based electroplated silver microelectrode array structure, the electrochemical deposition process in step S2 uses a cyanide-free electroplated silver solution, adopts a constant voltage mode, sets the voltage range to 0.2-2 V, the electroplating time to 0-30 min, and the electroplating solution temperature to 20-50℃.

[0018] The above-mentioned method for fabricating a silicon-based electroplated silver microelectrode array structure includes, in step S3, patterning the insulating layer by forming a second photolithographic pattern on the insulating layer, and using the second photolithographic pattern as a mask to etch the insulating layer to form an opening.

[0019] The present invention also provides the application of the above-mentioned silicon-based electroplated silver microelectrode array structure in microfluidic chips.

[0020] In the fabrication of microfluidic chips, precise control of electrode structure and function is achieved through two key photolithographic alignments. The first alignment involves forming a first photolithographic pattern on a silicon substrate to define the position of the patterned composite seed layer and subsequent metal electrode layers. The second alignment involves forming a second photolithographic pattern on an insulating layer covering the metal electrode layers. The second photolithographic pattern is aligned with the position of the metal electrode layers to define the insulating layer window that exposes the active region of the electrodes. The size of the insulating layer window is smaller than the size of its corresponding metal electrode layer.

[0021] As can be seen from the above technical solutions, compared with the prior art, the silicon-based electroplated silver microelectrode array structure of the present invention is natural, providing a flat and stable interface for the subsequent integration of multi-layer microchannels. Dry film lithography technology can precisely construct a one-to-one electrode-chamber alignment structure, physically isolating each detection unit, which is a key architecture for achieving ultra-high throughput, low crosstalk parallel detection (such as large-scale nanopore sequencing). The electrode layer uses a dual-electrode system to electroplat silver electrodes, with controllable electrode thickness, effectively reducing resistance and thermal noise, suitable for detecting pA-level weak current signals such as nanopore sequencing. Moreover, using silver electrodes results in a much lower raw material cost than precious metals such as gold and platinum, and the investment and operating costs of electroplating equipment are much lower than those of high-vacuum sputtering systems, significantly reducing overall manufacturing costs and clearing a key obstacle to the widespread adoption of consumer-grade biosensor chips. Simultaneously, the use of a cyanide-free electroplating solution avoids the use of highly toxic cyanide, making the production process safer and more environmentally friendly, in line with the green development direction of modern electronics manufacturing.

[0022] The entire process flow of this invention (thermal oxidation, sputtering, photolithography, electroplating) is highly compatible with standard silicon-based semiconductor (CMOS) processes. The electroplating, guided by dry film photoresist and patterned seed layers, facilitates high-precision, high-uniformity large-scale array fabrication (e.g., 256 channels, 1024 channels) at the wafer level, with high yield, good repeatability, and strong potential for industrial scale-up. Attached Figure Description

[0023] Figure 1 This is a flowchart of the preparation method of the present invention; Figure 2 The chronocurrent curves show the deposition of Ag on the substrate surface at a voltage of 1 V. Figure 3 This is a topographic image of the electrode surface of the metal electrode layer obtained after desizing. Detailed Implementation

[0024] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0025] This invention discloses a silicon-based silver-plated microelectrode array structure, which comprises, from bottom to top: Silicon substrate: serving as the mechanical support for the entire structure; using a silicon substrate with a silicon dioxide or silicon nitride insulating layer on the surface formed by thermal oxidation or deposition, with a silicon wafer thickness of 1000 nm-3000 nm and a silicon dioxide or silicon nitride insulating layer thickness of 50 nm-500 nm; Composite seed layer: formed on the silicon substrate, the composite seed layer comprising at least one metal layer; Metal electrode layer: A metal electrode formed on the patterned composite seed layer by selectively growing it through an electroplating process. Insulating layer: covering the electrode layer and the composite seed layer not covered by the electrode layer; The first microchannel structure layer is stacked on top of the insulating layer and is specifically formed by patterning using S2045 dry film photoresist. The second microchannel structure layer is stacked on top of the first microchannel structure layer and is specifically formed by patterning using dry film photoresist of model S2030.

[0026] This embodiment provides a specific method for fabricating a silicon-based electroplated silver microelectrode array structure, such as... Figure 1 As shown, it includes the following steps: S1. Preparation of the composite seed layer, the steps are as follows: (1) The silicon substrate was ultrasonically cleaned in acetone and isopropanol for 10 min in sequence and then dried with nitrogen. It was then treated with oxygen plasma at 200 W power for 5 min. The silicon substrate was made by thermal oxidation or deposition of a silicon dioxide insulating layer on the surface of the silicon wafer. The thickness of the silicon wafer was 1000 nm-3000 nm and the thickness of the silicon dioxide was 50 nm-500 nm. (2) A layer of negative photoresist is spin-coated on a silicon substrate using a spin coater at a speed of 3000 rpm / min for 60 s to obtain a photoresist layer with a thickness of 3 μm; then the photoresist layer is baked at 100℃ for 10 min; in addition to spin coating, other methods such as spraying, slot coating, dip coating, lamination, and electrophoretic deposition can be used to bond the photoresist to the silicon substrate.

[0027] Contact UV lithography is used to transfer the pattern on the photomask to the photoresist. In this embodiment, the pattern on the mask is a series of rectangular and circular windows arranged in an array. The window size is between 10 μm*10 μm and 25 μm*25 μm, and the distance between different windows is 1.27 mm. There are 16 cycles in both the vertical and horizontal directions.

[0028] (4) Place the silicon substrate and photomask on the worktable of the UV exposure machine in sequence. Expose with UV light with a power of 15 s according to the thickness of the photoresist, and then bake on a hot plate at 120°C for 10 min.

[0029] (5) The silicon substrate is then cleaned with photoresist developer and deionized water in sequence to form a window pattern of the electrode area; (6) Place the patterned silicon wafer in the sputtering chamber and evacuate to 5×10⁻⁶. -4 Pa, power of 100-300 W, argon flow rate of 10-50 sccm, deposition time of 100-500 s; a Cr metal adhesion layer with a thickness of 10 nm-500 nm was prepared on a silicon substrate with photolithographic pattern; then a Cu seed layer was sputtered at a power of 200 W for a deposition of 200 nm.

[0030] In this example, the composite seed layer consists of a chromium layer and a copper layer on top of the chromium layer; in addition, materials including but not limited to chromium, nickel, titanium, copper, aluminum, silver, gold, and platinum can also be used.

[0031] S2. Prepare the Ag electrode layer, the steps are as follows: (1) Immerse the sample in the activation solution for 5 min to remove the oxide layer on the surface. Rinse with deionized water and immediately transfer to the electroplating tank. The temperature of the electroplating solution is maintained at 25℃±2℃. The electroplating solution includes, but is not limited to, imino disulfate system, succinimide system, thiosulfate system, and methanesulfonic acid silver plating solution. (2) A dual-electrode system was adopted, with the positive electrode connected to the counter electrode and the negative electrode connected to the working electrode. A constant voltage mode was used, with the voltage set between 0.2-2V and the electroplating time between 5 min, to obtain a silver electrode array with a thickness of 30 nm. Figure 2 As shown, when the voltage is constant at 1V, the process of metal deposition during electroplating is observed. It is found that as time increases, the current gradually increases and tends to stabilize.

[0032] Electroplating can also be performed using constant current method or pulse deposition method in this step.

[0033] (3) The sample was immersed in 100℃ NMP solution, ultrasonically assisted peeling was performed for 30 min, residual photoresist was rinsed with acetone, and dried with nitrogen to obtain a Cr / Cu / Ag electrode layer that remained only in the electrode window, with the morphology as shown. Figure 3 As shown.

[0034] S3. Prepare the insulating layer, the specific steps are as follows: (1) Use oxygen plasma at 200 W power for 5 min to increase the adhesion between the electrode layer and the insulating layer. The argon flow rate is 30 sccm, the power is 300 W, and a 500 nm thick silicon oxide insulating layer is sputtered at 300 °C. (2) Spin-coat negative photoresist and pattern it to expose the active area of ​​the electrode. Use reactive ion etching: use a CF4 / O2 mixed gas with a flow rate ratio of 4:1, power of 150 W, and etch for 10-120 min until the surface of the silver electrode is exposed. (3) Immerse the sample in 100℃ NMP solution, ultrasonically assisted peeling for 30 min, rinse the residual photoresist with acetone, and dry the sample with nitrogen for later use.

[0035] S4. Preparation of the first microfluidic structure layer: The S2045 dry film is pressed onto the chip surface using a dry film press at 90℃ and 0.5 MPa pressure. It is exposed through a mask and baked on a hot plate at 90℃ for 30 minutes to solidify the dry film. Then, it is developed with a 4% sodium carbonate solution for 5 minutes to form a micro-pit array with a specific morphology, with each pit aligned with an electrode active window.

[0036] S5. Preparation of the second microfluidic structure layer: Press the S2030 dry film onto the first microfluidic structure layer prepared in S5. After pressing, place the chip in a vacuum hot press bonding machine and expose and develop it under the same conditions to fuse the two dry film layers together and form a closed three-dimensional channel.

[0037] Similar or identical parts between the various embodiments in this specification can be referred to mutually. The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A silicon-based electroplated silver microelectrode array structure, characterized in that, include; A silicon substrate, including a silicon wafer and a silicon dioxide insulating layer formed on the surface of the silicon wafer; A patterned composite seed layer is formed on the silicon substrate; A metal electrode layer is formed on the patterned composite seed layer; An insulating layer is formed on the metal electrode layer; The first microfluidic structure layer is formed by patterning a first dry film layer of photoresist and is stacked on the insulating layer. The second microfluidic channel structure layer is formed by patterning the second dry film layer and is stacked on the first microfluidic channel structure layer.

2. The silicon-based electroplated silver microelectrode array structure according to claim 1, characterized in that, The silicon substrate is a silicon wafer with a silicon dioxide or silicon nitride insulating layer on its surface; the thickness of the silicon wafer is 1000-3000 nm; the thickness of the silicon dioxide or silicon nitride insulating layer is 50 nm-500 nm.

3. The silicon-based electroplated silver microelectrode array structure according to claim 1, characterized in that, The composite seed layer includes at least one metal layer, the metal layer material being at least one of chromium, nickel, titanium, copper, aluminum, silver, gold, and platinum, and the thickness of the composite seed layer is greater than 10 nm.

4. The silicon-based electroplated silver microelectrode array structure according to any one of claims 1-3, characterized in that, The metal electrode is a silver electrode.

5. The silicon-based electroplated silver microelectrode array according to claim 4, characterized in that, The thickness of the silver electrode is greater than 10 nm.

6. The method for fabricating a silicon-based electroplated silver microelectrode array structure as described in any one of claims 1-5, characterized in that, Includes the following steps: Step S1: Form a patterned composite seed layer on a silicon substrate, wherein the patterned composite seed layer includes at least a chromium layer and a copper layer; Step S2: Using the patterned composite seed layer as a conductive substrate, a metal electrode layer is formed on it through an electrochemical deposition process; the material of the metal electrode layer is silver. Step S3: Form an insulating layer on the metal electrode layer and the uncovered substrate area; The insulating layer is patterned to form an opening that exposes at least a portion of the metal electrode layer; Step S4: On the patterned insulating layer, the first microchannel structure layer and the second microchannel structure layer are laminated sequentially to form a microelectrode array structure.

7. The method for fabricating a silicon-based electroplated silver microelectrode array structure according to claim 6, characterized in that, The patterned composite seed layer is formed using a stripping process, including: forming a first photolithographic pattern on the silicon substrate to expose the substrate surface of a predetermined electrode region; and sequentially forming a chromium layer and a copper layer covering the photolithographic pattern and the exposed substrate surface by physical vapor deposition.

8. The method for fabricating a silicon-based electroplated silver microelectrode array structure according to claim 6, characterized in that, In step S2, the electrochemical deposition process uses a cyanide-free silver plating solution, employs a constant voltage mode, sets the voltage range to 0.2-2 V, and sets the plating time to 0-30 min. The plating solution temperature is 20℃ to 50℃.

9. The method for fabricating a silicon-based electroplated silver microelectrode array structure according to claim 6, characterized in that, Step S3 involves patterning the insulating layer by forming a second photolithographic pattern on the insulating layer and using the second photolithographic pattern as a mask to etch the insulating layer to form an opening.

10. The application of the silicon-based electroplated silver microelectrode array structure as described in any one of claims 1-5 in microfluidic chips.

Images