Microelectromechanical package

Abstract

A microelectromechanical package includes a first substrate, an interconnect layer, a microelectromechanical element layer, a pedestal structure, a bonding material layer, and a second substrate. The interconnect layer is disposed on the first substrate, and the microelectromechanical element layer includes a microelectromechanical element disposed above the interconnect layer. The pedestal structure is disposed below the microelectromechanical element layer, surrounds the microelectromechanical element, and is bonded to the interconnect layer. The pedestal structure includes an inner sidewall, an outer sidewall, and a bottom surface, and the bonding material layer is coated on the outer sidewall and a portion of the bottom surface of the pedestal structure. In addition, the second substrate includes a cavity and is bonded to the microelectromechanical element layer.

Description

Technical Field

[0001] This invention relates to microelectromechanical systems (MEMS) technology, and more particularly to MEMS packaging containing bonding structures that can prevent bonding misalignment and bonding material spillage. Background Technology

[0002] Microelectromechanical systems (MEMS) components are miniature devices that integrate mechanical and electrical components to sense physical quantities and / or interact with their surroundings. MEMS components, such as accelerometers, gyroscopes, pressure sensors, and microphones, are widely used in many modern electronic products, including tablet computers, automobiles, and smartphones. In MEMS packaging, MEMS wafers are typically aligned and bonded to another support wafer using eutectic bonding. During eutectic bonding, the molten bonding material can cause misalignment between the two wafers. Furthermore, the molten bonding material can overflow and be extruded in various directions. Therefore, current MEMS packaging still faces several problems caused by eutectic bonding that need to be overcome. Summary of the Invention

[0003] In view of this, the present invention provides a microelectromechanical (MEMS) package comprising a bonding material layer and a dielectric barrier to control and / or prevent bonding misalignment and bonding material spillage. The bonding material layer is recessed inward from the inner sidewall of the support structure to provide the bonding structure. Furthermore, the dielectric barrier is disposed around the bonding material layer and the support structure.

[0004] According to an embodiment of the present invention, a microelectromechanical package (MEMS) is provided, comprising a first substrate, an interconnect layer, a MEMS element layer, a support structure, a bonding material layer, and a second substrate. The interconnect layer is disposed on the first substrate, and the MEMS element layer, including MEMS elements, is disposed above the interconnect layer. The support structure is disposed below the MEMS element layer, surrounding the MEMS elements, and bonded to the interconnect layer. The support structure includes an inner sidewall, an outer sidewall, and a bottom surface, and the bonding material layer is coated on the outer sidewall and a portion of the bottom surface of the support structure. Furthermore, the second substrate includes a cavity and is bonded to the MEMS element layer.

[0005] To make the features of the present invention clear and easy to understand, embodiments are provided below, along with accompanying drawings, for detailed explanation. Attached Figure Description

[0006] To facilitate understanding of the following text, reference should be made to the accompanying drawings and their detailed description while reading this invention. Specific embodiments of the invention are explained in detail through reference to the corresponding drawings, which illustrate the working principles of these embodiments. Furthermore, for clarity, features in the drawings may not be drawn to scale, and therefore the dimensions of some features in certain drawings may be intentionally enlarged or reduced. Figure 1 This is a cross-sectional schematic diagram of a microelectromechanical (MEMS) package according to an embodiment of the present invention. Figure 2 It is illustrated according to an embodiment of the present invention. Figure 1 A magnified cross-sectional view of a portion A in a microelectromechanical package. Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 and Figure 9 This is a cross-sectional schematic diagram illustrating some stages of a manufacturing method for a microelectromechanical package according to an embodiment of the present invention. Detailed Implementation

[0007] This invention provides several different embodiments for implementing various features of the invention. For the sake of simplicity, examples of specific components and arrangements are also described. These embodiments are provided for illustrative purposes only and are not intended to be limiting. For example, the following description of "a first feature forming on or above a second feature" can mean "the first feature and the second feature are in direct contact," or it can mean "there are other features between the first feature and the second feature," such that the first feature and the second feature are not in direct contact. Furthermore, various embodiments of this invention may use repeated reference numerals and / or textual annotations. The use of these repeated reference numerals and annotations is for the purpose of making the description more concise and clear, and not to indicate any correlation between different embodiments and / or configurations.

[0008] Furthermore, for the purposes of this invention, spatially related terms such as "below," "low," "under," "above," "above," "upper," "top," "bottom," and similar terms are used to describe the relative relationship between one element or feature and another (or more) elements or features in the accompanying drawings. In addition to the orientation shown in the drawings, these spatially related terms are also used to describe the possible orientations of the MEMS package during use and operation. As the orientation of the MEMS package varies (rotation 90 degrees or other orientations), the spatially related descriptions used to describe its orientation should be interpreted in a similar manner.

[0009] Although this invention uses terms such as first, second, third, etc., to describe various elements, components, regions, layers, and / or blocks, it should be understood that such elements, components, regions, layers, and / or blocks should not be limited by such terminology. Such terminology is only used to distinguish one element, component, region, layer, and / or block from another, and does not in itself imply or represent any prior ordinal number of the element, nor does it represent the arrangement order of one element with another, or the order of manufacturing methods. Therefore, without departing from the scope of the specific embodiments of this invention, the first element, component, region, layer, or block discussed below may also be named as a second element, component, region, layer, or block.

[0010] The terms "about" or "substantially" as used in this invention generally mean within 20% of a given value or range, preferably within 10%, and even more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities; that is, the meaning of "about" or "substantially" may be implied even without specific mention of it.

[0011] The terms "coupled," "coupled," and "electrically connected" as used in this invention include any direct or indirect means of electrical connection. For example, if the text describes a first component coupled to a second component, it means that the first component can be directly electrically connected to the second component, or indirectly electrically connected to the second component through other means of connection.

[0012] Although the invention is described below by way of specific embodiments, the inventive principles of the invention can also be applied to other embodiments. Furthermore, in order to avoid obscuring the spirit of the invention, certain details have been omitted; these omitted details are within the scope of knowledge of those skilled in the art.

[0013] This invention relates to microelectromechanical systems (MEMS) packaging, comprising a bonding material layer and a dielectric barrier to control and / or prevent bonding misalignment and molten bonding material overflow within the bonding element region. The bonding material layer is recessed inward from the inner sidewall of the support structure to prevent lateral overflow of molten bonding material. The dielectric barrier is disposed around the bonding material layer and the support structure, and is sufficiently thick to physically prevent wafer slippage during bonding, thereby preventing bonding misalignment. Furthermore, the dielectric barrier has a sufficiently wide opening to allow for bonding misalignment errors in the bonding equipment, thereby improving the yield and quality of the MEMS package.

[0014] Figure 1This is a cross-sectional schematic diagram of a microelectromechanical (MEMS) package 100 according to an embodiment of the present invention. The MEMS package 100 includes a first substrate 101, an interconnect layer 120, a MEMS element layer 110, a support structure 112, a bonding material layer 114, and a second substrate 103. The first substrate 101 is, for example, a silicon wafer, and includes a plurality of complementary metal-oxide-semiconductor (CMOS) transistors and / or other components formed therein. An interconnect layer 120 is disposed on a first substrate 101. The interconnect layer 120 includes multiple metal layers, such as a top metal layer 121 and a penultimate metal layer 122, multiple inter-metal dielectric layers 124 and 126, and multiple vias 125 located in these inter-metal dielectric layers. Some vias 125 electrically connect the top metal layer 121 to the penultimate metal layer 122, and other vias 125 electrically connect the penultimate metal layer 122 to CMOS transistors and / or other components in the first substrate 101, so that the interconnect layer 120 is electrically coupled to CMOS transistors and / or other components in the first substrate 101. The interconnect layer 120 and the first substrate 101 can be referred to together as a CMOS and / or interconnect wafer. In addition, dielectric barrier 130 and protective layer 128 are disposed on interconnect layer 120, with openings in protective layer 128 exposing bonding pads on top metal layer 121, which are configured to be electrically connected to ground voltage, and sealing rings on top metal layer 121 are exposed through openings in dielectric barrier 130.

[0015] Microelectromechanical systems (MEMS) element layer 110 includes MEMS elements 116 and is disposed above interconnect layer 120. MEMS element layer 110 includes features such as trenches, cantilevered structures, diaphragms, and mass blocks to construct MEMS elements 116, such as accelerometers, gyroscopes, inertial measurement unit elements, and / or other MEMS elements. Support structure 112 is disposed below MEMS element layer 110, surrounding MEMS elements 116. Support structure 112 is a bonding loop projecting toward interconnect layer 120, and is integrated with MEMS element layer 110 such that support structure 112 has the same composition as MEMS element layer 110. In some embodiments, the composition of MEMS element layer 110 and support structure 112 is, for example, doped silicon or doped polysilicon. MEMS element layer 110 is bonded to interconnect layer 120 via support structure 112 and bonding material layer 114, thereby providing a hermetically sealed environment for MEMS elements 116. In addition, the bonding material layer 114 is recessed inward from the side of the support structure 112 facing the microelectromechanical component 116.

[0016] Figure 2 This is an embodiment of the present invention. Figure 1 A magnified cross-sectional view of a portion A in the microelectromechanical package 100, see reference. Figure 2The support structure 112 includes an inner sidewall 112S1, an outer sidewall 112S2, and a bottom surface 112B. A bonding material layer 114 is coated on the outer sidewall 112S2 and a portion of the bottom surface 112B of the support structure 112, but not on the inner sidewall 112S1. Therefore, the bonding material layer 114 on the bottom surface 112B of the support structure 112 is recessed inward from the inner sidewall 112S1 by a recess distance S. In some embodiments, the recess distance S may be less than 10% of the width W of the support structure 112; for example, the recess distance S may be less than about 5 μm. According to an embodiment of the invention, the bonding material layer 114 has a lateral recess 115 located directly below the support structure 112 and close to the inner sidewall 112S1 of the support structure. See also... Figure 1 and Figure 2 The lateral recess 115 of the bonding material layer 114 faces the microelectromechanical component 116.

[0017] Furthermore, the bonding material layer 114 may comprise a eutectic bonding material or a hot-pressed bonding material. In some embodiments, the eutectic bonding material may comprise a eutectic alloy of aluminum (Al) and germanium (Ge), i.e., an aluminum-germanium (Al-Ge) alloy. Additionally, the eutectic bonding material may also comprise other eutectic alloys, such as gold-germanium (Au-Ge), copper-tin (Cu-Sn), gold-tin (Au-Sn), gold-silicon (Au-Si), or aluminum-silicon (Al-Si), but is not limited thereto. In some embodiments, the hot-pressed bonding material may comprise copper (Cu), gold (Au), aluminum (Al), germanium (Ge), or tin (Sn), but is not limited thereto.

[0018] The dielectric barrier 130 includes a first portion 131, a second portion 132, and an opening 133. In some embodiments, the dielectric barrier 130 is composed of silicon oxide, silicon nitride, or a combination thereof, and the dielectric barrier 130 and the protective layer 128 may have the same composition. Figure 1 As shown, the support structure 112 is a bonding ring, the first portion 131 of the dielectric barrier 130 is located inside the support structure 112, and the second portion 132 of the dielectric barrier 130 is located outside the support structure 112. The sealing ring located in the top metal layer 121 can be exposed through the opening 133 of the dielectric barrier 130. The support structure 112 and the bonding material layer 114 are disposed in the opening 133 of the dielectric barrier 130 and bonded to the sealing ring of the interconnect layer 120.

[0019] Additionally, see Figure 2The inner sidewall 112S1 of the support structure 112 is spaced apart from the first portion 131 of the dielectric barrier 130 by a first distance d1. In some embodiments, the first distance d1 is at least about 5 μm and is typically greater than 5 μm. The bonding material layer 114 on the outer sidewall 112S2 of the support structure 112 is spaced apart from the second portion 132 of the dielectric barrier 130 by a second distance d2. In some embodiments, the second distance d2 is at least about 5 μm and is typically greater than 5 μm. Furthermore, the first distance d1 and the second distance d2 may be substantially the same, or the first distance d1 may be slightly larger than the second distance d2.

[0020] See also Figure 2 The top surface of the dielectric barrier 130 is higher than the bottom surface 112B of the support structure 112. The dielectric barrier 130 has a first thickness H1, and the support structure 112 has a second thickness H2. The first thickness H1 is greater than the thickness of the bonding material layer 114 on the support structure 112, and less than half of the second thickness H2. Furthermore, the bottom surface of the opening 133 of the dielectric barrier 130, the bottom surface of the dielectric barrier 130, and the bottom surface of the bonding material layer 114 are all located on the same plane.

[0021] like Figure 1 and Figure 2 As shown, the dielectric barrier 130 and the bonding material layer 114 can directly contact the top metal layer 121, and both the dielectric barrier 130 and the bonding material layer 114 are disposed on the sealing ring of the top metal layer 121. Additionally, the interconnect layer 120 includes a stepped groove 127 located directly below the microelectromechanical component 116. An intermetallic dielectric layer 124 is disposed between the top metal layer 121 and the penultimate metal layer 122, and the stepped groove 127 is disposed within the top metal layer 121 and the intermetallic dielectric layer 124, with a portion of the penultimate metal layer 122 exposed via the stepped groove 127. Furthermore, a first portion 131 of the dielectric barrier 130 is adjacent to and surrounds the stepped groove 127.

[0022] See also Figure 1The second substrate 103 is bonded to the MEMS device layer 110 via a bonding layer 107 (e.g., a silicon oxide layer). The second substrate 103 is, for example, a silicon wafer, also known as a cap wafer, having a front side 103F and a back side 103B on opposite sides. A cavity 105 is formed in the second substrate 103 near the front side 103F, and the cavity 105 is located directly above the microelectromechanical component 116. Furthermore, a stop bump 104 can be formed within the cavity 105, protruding towards the microelectromechanical component 116, and a gap exists between the stop bump 104 and the microelectromechanical component 116. The stop bump 104 corresponds to the mass block of the microelectromechanical component 116, and the stop bump 104 can limit the range of movement of the microelectromechanical component 116, thereby preventing the microelectromechanical component 116 from breaking due to excessive vertical vibration. The stop bump 104 is typically integrated into the second substrate 103, such that the stop bump 104 and the second substrate 103 have the same composition. Additionally, a bonding layer 107 is disposed between the MEMS element layer 110 and the second substrate 103, and the bonding layer 107 may further extend unidirectionally into the cavity 105 and onto the stop bump 104. Furthermore, a metal layer 109 may be disposed on the back surface 103B of the second substrate 103 for radio frequency (RF) shielding and / or grounding. For example, the metal layer 109 may be electrically connected to the bonding pad located in the top metal layer 121 of the interconnect layer 120, thereby grounding.

[0023] According to an embodiment of the present invention, the bonding material layer 114 included in the MEMS package 100 is recessed inward from the inner sidewall 112S1 of the support structure 112 by a recess distance S. When the MEMS element layer 110 is bonded to the interconnect layer 120, the recess distance S of the bonding material layer 114 can prevent molten bonding material from overflowing. Furthermore, since the bonding material layer 114 is recessed, under high-pressure bonding, the recessed bonding material layer 114 can prevent molten bonding material from overflowing and being extruded. By controlling and / or preventing the overflow of molten bonding material in the MEMS package, electrical short circuits in the interconnect layer 120 can be avoided, and metal contamination of adjacent structures on the interconnect layer 120 can also be prevented.

[0024] Furthermore, the MEMS package 100 also includes a dielectric barrier 130 disposed on the interconnect layer 120 and surrounding the support structure 112 and the bonding material layer 114. During the bonding of the MEMS element layer 110 to the interconnect layer 120, the dielectric barrier 130 is sufficiently thick to physically prevent the support structure 112 from sliding, thereby preventing misalignment when the MEMS element layer 110 is bonded to the interconnect layer 120. In addition, the dielectric barrier 130 has a sufficiently wide opening 133 to accommodate the support structure 112 and the bonding material layer 114, thereby increasing the bonding alignment tolerance of the bonding equipment. Furthermore, the opening 133 of the dielectric barrier 130 also facilitates the self-alignment of the support structure 112 with the sealing ring of the interconnect layer 120, and the width of the opening 133 of the dielectric barrier 130 can be adjusted according to the capabilities of the bonding equipment.

[0025] The bonding material layer 114 and dielectric barrier 130 included in the MEMS package 100 are particularly advantageous for high-pressure and / or high-temperature bonding conditions. For example, the bonding pressure for bonding the MEMS element layer 110 to the interconnect layer 120 can be in the range of 20kN to 60kN, and the thickness of the dielectric barrier 130 can be adjusted as needed according to the bonding pressure and / or bonding temperature. Furthermore, according to embodiments of the invention, the bonding material layer is recessed inward from the inner sidewall of the support structure, located within the opening of the dielectric barrier, and disposed above the sealing ring of the interconnect layer. This architecture of the bonding material layers is also suitable for the fabrication of three-dimensional integrated circuits (3D-ICs), and can be used to prevent misalignment during bonding and overflow of bonding material.

[0026] Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 and Figure 9 This is a cross-sectional schematic diagram showing some stages of a manufacturing method for a microelectromechanical package 100 according to an embodiment of the present invention. (See attached diagram) Figure 3 In step S101, a second substrate 103, such as a silicon wafer, is provided as a support wafer or a cover wafer, and both the front and back sides of the second substrate 103 are polished. Then, a plurality of alignment marks 108 are formed on the back side of the second substrate 103 through a patterning and etching process. Next, a patterned hard mask 141, such as a silicon oxide layer, is formed on the front side of the second substrate 103 through a deposition and patterning process.

[0027] See also Figure 3In step S103, a patterned hard mask 141 is used as an etching mask to form a plurality of shallow cavities 143 with a depth P1, for example, about 2 μm, on the front side of the second substrate 103 through an etching process. Then, in step S105, a patterned photoresist mask 145 is formed on the bottom surface of the shallow cavities 143 through a coating, exposure and development process.

[0028] Next, refer to Figure 4 In step S107, a patterned photoresist mask 145 and a patterned hard mask 141 are used together as an etching mask to form a plurality of stop bumps 104 and deep cavities 147 on the front side of the second substrate 103 through an etching process. The stop bumps 104 have a height P2, for example, approximately 18 μm. The deep cavities 147 have a depth P3, for example, approximately 20 μm. The deep cavities 147 and shallow cavities 143 constitute a cavity 105, and the stop bumps 104 are formed within the cavity 105. The depth of the cavity 105 is greater than the height of the stop bumps 104, and the top surface of the stop bumps 104 is lower than the front side of the second substrate 103. Subsequently, the patterned photoresist mask 145 and the patterned hard mask 141 are removed through a stripping process. Then, in step S109, a bonding layer 106 is formed in a forward orientation on the second substrate 103, inside the cavity 105, and on the stop bump 104 to cover the second substrate 103. The bonding layer 106 is composed of, for example, silicon oxide, and can be formed by thermal oxidation.

[0029] Next, refer to Figure 5 In step S111, a component wafer 150, such as a silicon wafer, is provided. The front side of the component wafer 150 is polished and ground, and the component wafer 150 may be heavily doped with boron to achieve a resistivity of approximately 0.008 ohm·cm to approximately 0.02 ohm·cm. Then, the front edge 152 of the component wafer 150 is trimmed without plasma treatment, and the component wafer 150 is bonded to the second substrate 103 via a bonding layer 106 using direct wafer bonding (oxide bonding to silicon), covering the cavity 105 and the stop bump 104. In step S111, the component wafer 150 has a thickness T1. Then, in step S113, the component wafer 150 is thinned by back-side grinding to achieve a thickness T2 less than the thickness T1. Furthermore, a chemical-mechanical polishing (CMP) process is performed on the back side of the thinned component wafer 150 to obtain a flat surface.

[0030] Next, refer to Figure 6In step S115, the thinned device wafer 150 is patterned using photolithography and etching processes to form a support structure 112 and a MEMS device layer 110. The support structure 112 is integrated with the MEMS device layer 110, and the support structure 112 protrudes from the surface of the MEMS device layer 110. Then, in step S117, bonding material 113 is formed on the outer sidewall 112S2 and part of the bottom surface 112B of the support structure 112 using deposition and patterning processes, and the bonding material 113 is not on the inner sidewall 112S1 of the support structure 112. Through this patterning process, the bonding material 113 on the bottom surface 112B of the support structure 112 can be recessed inward from the inner sidewall 112S1 to create a lateral recess 115, and the width of the lateral recess 115 can be less than 5 μm. In some embodiments, the bonding material 113 may be a eutectic bonding material or a hot-pressed bonding material. For example, the bonding material 113 may be germanium (Ge) for eutectic bonding, but is not limited thereto.

[0031] See also Figure 6 In step S119, the MEMS element layer 110 is patterned using photolithography and etching processes to form a microelectromechanical component 116. A support structure 112 surrounds the microelectromechanical component 116, and the microelectromechanical component 116 is located directly above the cavity 105 and the stop bump 104. In some embodiments, the microelectromechanical component 116 may be a gyroscope, accelerometer, inertial measurement unit element, and / or other microelectromechanical components.

[0032] Next, refer to Figure 7 In step S121, a first substrate 101, such as a CMOS wafer, is provided, having a plurality of CMOS transistors formed therein. Then, an interconnect layer 120 is formed on the front side of the first substrate 101; details of the interconnect layer 120 can be found in the foregoing. Figure 1The relevant description of the MEMS package 100 will not be repeated here. Then, a dielectric barrier 130 and a protective layer 128 are simultaneously formed on the interconnect layer 120 through deposition and patterning processes. The dielectric barrier 130 includes a first portion 131, a second portion 132, and an opening 133. The dielectric barrier 130 is formed on a sealing ring of the interconnect layer 120, which is part of the top metal layer 121, and the sealing ring may be composed of aluminum (Al). Furthermore, a pre-cut line 149 is formed in the protective layer 128. The opening 133 of the dielectric barrier 130 and the pre-cut line 149 in the protective layer 128 can be formed simultaneously through the same etching process. In some embodiments, the dielectric barrier 130 and the protective layer 128 are composed, for example, silicon oxide, silicon nitride, or a combination thereof. Subsequently, in step S123, the top dielectric layer and the interlayer dielectric (intermetallic dielectric) layer 124 of the interconnect layer 120 are etched sequentially to form a stepped groove 127, exposing a portion of the penultimate metal layer 122, and the first portion 131 of the dielectric barrier 130 is located around the stepped groove 127.

[0033] Next, refer to Figure 8 In step S125, Figure 6 In step S119, the structure is flipped upside down, and the MEMS element layer 110 is bonded to the interconnect layer 120 via the support structure 112 and the bonding material 113. In one embodiment, the bonding material 113 is, for example, germanium (Ge) for eutectic bonding, and the sealing ring in the interconnect layer 120 is composed of, for example, aluminum (Al). After the MEMS element layer 110 is bonded to the interconnect layer 120 via eutectic bonding, an aluminum-germanium (Al-Ge) alloy bonding material layer 114 is formed, and the bonding material layer 114 is also recessed inward from the inner sidewall of the support structure 112 by a certain distance. During the bonding of the MEMS element layer 110 to the interconnect layer 120, the inward recess of the bonding material layer 114 can prevent molten bonding material from overflowing. Furthermore, the support structure 112 and the bonding material layer 114 within the opening 133 of the dielectric barrier 130 can achieve self-alignment. Furthermore, since the first portion 131 and the second portion 132 of the dielectric barrier 130 are sufficiently thick, the dielectric barrier 130 can physically prevent the support structure 112 from sliding during the bonding of the MEMS element layer 110 to the interconnect layer 120, thereby preventing misalignment during bonding. In step S125, the first substrate 101 has a thickness T3.

[0034] Next, refer to Figure 8In step S127, the first substrate 101 is thinned by back-side grinding to achieve a thickness T4 less than the thickness T3. Then, the edges of the second substrate 103 are trimmed to remove the bonding layer 106 on the side surface of the second substrate 103, thereby forming a bonding layer 107 on the front surface 103F of the second substrate 103, with the remaining bonding layer 106B remaining on the back surface 103B of the second substrate 103. In step S127, the second substrate 103 has a thickness T5.

[0035] Next, refer to Figure 9 In step S129, the second substrate 103 is thinned by back-side grinding to achieve a thickness T6 less than the thickness T5. Then, a metal layer 109, for example an aluminum (Al) layer, is deposited on the back side of the second substrate 103, with a thickness of approximately 0.8 μm. Then, in step S131, a tab dicing process is performed using a saw to cut a portion of the metal layer 109, a portion of the second substrate 103, and a portion of the MEMS element layer 110 located at the dicing slit SL, thereby exposing the bonding pads located in the top metal layer 121 and the pre-cut line 149 located in the protective layer 128. Afterwards, the interconnect layer 120 and the first substrate 101 are cut along the pre-cut line 149 to complete the process. Figure 1 MEMS package 100.

[0036] According to embodiments of the present invention, a MEMS package includes a bonding material layer and a dielectric barrier, thereby controlling and / or preventing bonding misalignment and bonding material overflow within the bonding element region. The formation of the bonding material layer and the dielectric barrier can be integrated into the MEMS package manufacturing process without adding additional process steps, and while maintaining manufacturing costs, the reliability and yield of the MEMS package can be improved. The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made within the scope of the claims of the present invention should be included within the scope of the present invention. Explanation of reference numerals in the attached figures

[0037] 100: Microelectromechanical Package 101: First substrate 103: Second substrate 103B: Back 103F: Front 104: Stop bump 105: Cavity 106: Bonding layer 106B: Remaining bonding layer 107: Bonding layer 108: Alignment Marks 109: Metal layer 110: Microelectromechanical Components Layer 112: Support structure 112S1: Inner wall 112S2: Lateral wall 112B: Bottom surface 113: Bonding materials 114: Bonding material layer 115: Lateral depression 116: Microelectromechanical components 120: Interconnection Layer 121: Top metal layer 122: Second to last metal layer 124, 126: Intermetallic dielectric layer 125: Through hole 127: Stepped groove 128: Protective layer 130: Dielectric barrier 131: Part One 132: Part Two 133: Opening 141: Patterned Hard Mask 143: Shallow cavity 145: Patterned photoresist mask 147: Deep Cavity 149: Pre-cut line 150: Component wafers 152: Front edge A: Partial areas d1: First distance d2: Second distance H1: First thickness H2: Second thickness P1: Depth P2: Height P3: Depth S: Depression distance W: Width SL: Cutting Track T1, T2, T3, T4, T5, T6: Thickness S101, S103, S105, S107, S109, S111, S113, S115, S117, S119, S121, S123, S125, S127, S129, S131: Steps

Claims

1. A microelectromechanical package, characterized in that, include: First substrate; An interconnect layer is disposed on the first substrate; A microelectromechanical component (MEMS) layer, including a microelectromechanical component, is disposed above the interconnect layer; A support structure is disposed below the microelectromechanical component layer, surrounds the microelectromechanical component, and is bonded to the interconnect layer, wherein the support structure includes an inner sidewall, an outer sidewall, and a bottom surface; A bonding material layer is applied to a portion of the outer sidewall and the bottom surface of the support structure; and A second substrate includes a cavity and is bonded to the microelectromechanical component layer.

2. The microelectromechanical package as described in claim 1, characterized in that, The bonding material layer is not coated on the inner sidewall of the support structure, and the bonding material layer on the bottom surface is recessed inward from the inner sidewall by a certain distance.

3. The microelectromechanical package as described in claim 2, characterized in that, The recessed distance is less than 10% of the width of the support structure.

4. The microelectromechanical package as described in claim 1, characterized in that, It also includes a dielectric barrier disposed on the interconnect layer and having an opening, wherein the support structure and the bonding material layer are disposed within the opening of the dielectric barrier.

5. The microelectromechanical package as described in claim 4, characterized in that, One top surface of the dielectric barrier is higher than the bottom surface of the support structure.

6. The microelectromechanical package as described in claim 4, characterized in that, The support structure is a bonded ring, and the dielectric barrier includes a first part located inside the support structure and a second part located outside the support structure, and the inner sidewall of the support structure is spaced apart from the first part of the dielectric barrier by a first distance.

7. The microelectromechanical package as described in claim 6, characterized in that, The first distance is at least 5 μm.

8. The microelectromechanical package as described in claim 6, characterized in that, The bonding material layer on the outer side wall of the support structure is spaced apart from the second portion of the dielectric barrier by a second distance.

9. The microelectromechanical package as described in claim 8, characterized in that, The second distance is at least 5 μm.

10. The microelectromechanical package as described in claim 4, characterized in that, The dielectric barrier has a first thickness, and the support structure has a second thickness. The first thickness is greater than the thickness of the bonding material layer coated on the support structure and less than half of the second thickness.

11. The microelectromechanical package as described in claim 4, characterized in that, The bottom surface of the opening of the dielectric barrier and the bottom surface of the bonding material layer are located on the same plane.

12. The microelectromechanical package as described in claim 4, characterized in that, One bottom surface of the dielectric barrier layer and one bottom surface of the bonding material layer are located on the same plane.

13. The microelectromechanical package as described in claim 1, characterized in that, The bonding material layer includes a eutectic bonding material or a hot-pressed bonding material.

14. The microelectromechanical package as described in claim 13, characterized in that, The bonding material layer comprises aluminum, germanium, copper, tin, gold, aluminum-germanium alloy, copper-tin alloy, or gold-tin alloy.

15. The microelectromechanical package as described in claim 1, characterized in that, It also includes a protective layer disposed on the interconnect layer, wherein the dielectric barrier and the protective layer have the same composition.

16. The microelectromechanical package as described in claim 1, characterized in that, The dielectric barrier is composed of silicon oxide, silicon nitride, or a combination thereof.

17. The microelectromechanical package as described in claim 1, characterized in that, The support structure and the microelectromechanical component layer are integrated together, and the support structure and the microelectromechanical component layer have the same composition.

18. The microelectromechanical package as described in claim 1, characterized in that, The bonding material layer has a lateral recess located directly below the support structure and close to the inner sidewall of the support structure.

19. The microelectromechanical package as described in claim 1, characterized in that, The interconnection layer includes: A top metal layer, wherein the dielectric barrier and the bonding material layer are both in direct contact with a portion of the top metal layer and are both disposed on the portion of the top metal layer; A penultimate metal layer is disposed below the top metal layer; A dielectric layer is disposed between the top metal layer and the penultimate metal layer; and A stepped groove is provided in the top metal layer and the dielectric layer, exposing a portion of the penultimate metal layer, and located directly below the microelectromechanical component.

20. The microelectromechanical package as described in claim 19, characterized in that, The dielectric barrier is adjacent to and surrounds the stepped groove.

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