Air pulse generating device, semiconductor device, and method for manufacturing semiconductor device

Abstract

The present disclosure provides an air pulse generating device, a semiconductor device, and a method of manufacturing a semiconductor device. An air pulse generating device includes a membrane structure and a protrusion structure. The protrusion structure is formed on a free edge of a portion of the membrane structure, the protrusion structure to elevate a thickness of the free edge in cross-section.

Description

Technical Field

[0001] This invention relates to an air pulse generating device, a semiconductor device, and a method for manufacturing the semiconductor device, and more particularly to an air pulse generating device and a semiconductor device capable of reducing unwanted backflow during operation, as well as a method for manufacturing the semiconductor device. Background Technology

[0002] Semiconductor devices are now widely used in a variety of electronic devices to achieve a wide range of functions. For example, some semiconductor devices (such as acoustic devices, like speakers or air pulse generators) can be used to generate sound, some semiconductor devices (such as air pulse generators or airflow generating devices) can be used to generate airflow, and some semiconductor devices (such as venting devices) can be used to control the opening or closing of their valves.

[0003] However, during the operation of the aforementioned semiconductor devices, undesirable backflow or leakage often occurs, adversely affecting the intended functions of these devices. Therefore, it is necessary to improve these semiconductor devices to reduce or avoid undesirable backflow or leakage during operation. Summary of the Invention

[0004] Therefore, the main objective of this invention is to provide an air pulse generating device and a semiconductor device having a protrusion structure adjacent to the free edge of a film structure to reduce unwanted backflow during operation. Furthermore, this invention also provides a method for manufacturing this semiconductor device.

[0005] This invention provides an air pulse generating device, which includes a membrane structure and a protrusion structure. The protrusion structure is formed on a free edge of a portion of the membrane structure, and the protrusion structure is used to increase the thickness of the free edge in cross-section.

[0006] This invention provides a semiconductor device including a film structure and a protrusion structure. The protrusion structure is formed on a free edge of a portion of the film structure, and the protrusion structure is used to increase the thickness of the free edge in cross-section.

[0007] This invention provides a method for manufacturing a semiconductor device, comprising: providing a wafer; forming a slit on the wafer, wherein the slit defines a free edge of a film structure; and forming a protrusion structure on the free edge of the film structure, wherein the protrusion structure is used to increase the thickness of the free edge in a cross-section.

[0008] After reading the following detailed description of embodiments illustrated with various figures, the object of the present invention should be clearly understood by those skilled in the art. Attached Figure Description

[0009] Figure 1 The diagram shown is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention.

[0010] Figure 2 The diagram shown is a cross-sectional view of the semiconductor device in three states according to the first embodiment of the present invention.

[0011] Figure 3 and Figure 4 The diagram shown is a cross-sectional view illustrating a motion example of a semiconductor device according to a first embodiment of the present invention.

[0012] Figure 5 The diagram shown is a cross-sectional view of another motion example of the semiconductor device according to the first embodiment of the present invention.

[0013] Figures 6 to 11 The diagram shown is a cross-sectional view of the structure of the semiconductor device manufacturing method according to the first embodiment of the present invention at different process stages.

[0014] Figures 12 to 17 The diagram shown is a cross-sectional view of the structure of the semiconductor device manufacturing method according to the second embodiment of the present invention at different process stages.

[0015] Figure 18 The diagram shown is a cross-sectional view of a semiconductor device according to a third embodiment of the present invention.

[0016] Figure 19 The diagram shown is a cross-sectional view of a semiconductor device according to a fourth embodiment of the present invention.

[0017] Symbol Explanation

[0018] AE, AE1, AE2: Anchored Edges

[0019] AL: Actuation layer

[0020] AR: Anchoring Structure

[0021] ATR: Actuator

[0022] ATR1: First Actuator

[0023] ATR2: Second Actuator

[0024] CT1: First conductive layer

[0025] CT2: Second conductive layer

[0026] CV: Overlay

[0027] E1, E2: Electrodes

[0028] FE: Free Edge

[0029] FE1: First Free Edge

[0030] FE2: Second Free Edge

[0031] FF: Filled Structure

[0032] FL: petals

[0033] FL1: First lobe

[0034] FL2: Second lobe

[0035] FP: Lobe Pair

[0036] FS: Membrane Structure

[0037] HL: Horizontal reference

[0038] IL1: First insulating layer

[0039] IL2: Second insulating layer

[0040] PD: Connecting pad

[0041] PS: Protruding structure

[0042] PS1: First protruding structure

[0043] PS2: Second protrusion structure

[0044] RG1, RG2: Swing range

[0045] SD1, SD1_1, SD1_2, SD2: Semiconductor devices

[0046] SL: Slit

[0047] SS1: First substructure

[0048] SS2: Second Substructure

[0049] SSL: Structure Layer

[0050] ST1: First State

[0051] ST2: Second State

[0052] ST3: Third State

[0053] T 11 ,T 12 ,T 13 ,T 14 ,T 15 ,T 21,T 22 ,T 23 ,T 24 ,T 25 :time

[0054] TE: trench

[0055] VV: Virtual Valve

[0056] WF: Wafer

[0057] WL1: First Layer

[0058] WL2: Second Layer

[0059] WL3: Wafer Insulation Layer

[0060] X, Y, Z: Direction 0,FL1 , 0,FL2 , A,FL1 , A,FL2 , I,FL1 , I,FL2 , max,FL1 , max,FL2 , min,FL1 , min,FL2 , U,FL1 , U,FL2 :Location Detailed Implementation

[0061] To enable those skilled in the art to further understand the present invention, the preferred embodiments of the present invention, typical materials or parameter ranges of key elements, and the composition and desired effects of the present invention will be described in detail below with reference to the marked drawings. It should be noted that the drawings are simplified schematic diagrams, and the materials and parameter ranges of key elements are illustrated based on current technology. Therefore, only elements and combinations related to the present invention are shown to provide a clearer description of the basic structure, implementation method, or operation of the present invention. Actual elements and layouts may be more complex, and the materials or parameter ranges used may change with future technological developments. Furthermore, for ease of explanation, the elements shown in the various drawings of the present invention may not be drawn to scale in terms of actual number, shape, or size; their details can be adjusted according to design requirements.

[0062] In the following description and claims, when a component or membrane is referred to as being "connected to" another component or membrane, it may be directly connected to this other component or membrane, or there may be an inserted component or membrane between the two. When a component is referred to as being "directly connected to" another component or membrane, there may be no inserted component or membrane between the two.

[0063] In the following description and claims, when “component A1 is formed by B1”, B1 is present in the formation of component A1 or B1 is used in the formation of component A1, and the formation of component A1 does not exclude the presence and use of one or more other features, areas, steps, operations and / or components.

[0064] In the following description and claims, the term "substantially" means that a slight deviation may or may not exist. For example, the terms "substantially parallel" or "substantially along" mean that the angle between two components may be less than or equal to a specific angular threshold, such as 10 degrees, 5 degrees, 3 degrees, or 1 degree. For example, the term "substantially aligned" means that the deviation between two components may be less than or equal to a specific difference threshold, such as 2 μm or 1 μm. For example, the term "substantially identical" means that the deviation is within a given value or a given range, such as within 10%, 5%, 3%, 2%, 1%, or 0.5%.

[0065] In the following description and claims, the term "horizontal direction" refers to a direction parallel to a horizontal plane; the term "horizontal plane" refers to a plane parallel to directions X and Y in the drawings (i.e., directions X and Y of the present invention can be considered horizontal directions); the terms "vertical direction" and "top view direction" refer to directions parallel to direction Z and perpendicular to the horizontal direction in the drawings, wherein directions X, Y, and Z are perpendicular to each other. In the following description and claims, the term "top view" refers to the result of viewing along the vertical direction. In the following description and claims, the term "section" refers to the result of cutting the structure along the vertical direction and viewing it from a horizontal direction.

[0066] It should be understood that the features described in the following embodiments can be replaced, recombined, or mixed in several different embodiments to complete other embodiments without departing from the spirit of the invention. Features between embodiments can be arbitrarily mixed and combined as long as they do not violate the spirit of the invention or conflict with it.

[0067] This invention provides a semiconductor device formed by a semiconductor process and used to perform at least one function. For example, the semiconductor device may be a microelectromechanical system (MEMS) chip and includes a MEMS structure, but is not limited thereto.

[0068] For example, semiconductor devices (such as acoustic devices, like loudspeakers or air pulse generating devices) can be used to generate acoustic waves, but are not limited to this. For example, a loudspeaker can generate sound by producing acoustic waves with frequencies less than or equal to the maximum audible frequency for humans (e.g., 16 kHz, 20 kHz, or 22 kHz), or by producing ultrasonic sound by producing acoustic waves with frequencies greater than the maximum audible frequency for humans. For example, an air pulse generating device can generate multiple air pulses, and acoustic waves can be formed by the contours or envelopes of these air pulses, wherein the air pulses can be generated using an ultrasonic pulse rate.

[0069] For example, a semiconductor device (such as an air pulse generator or an airflow generator) can be used to generate airflow to create air movement, but is not limited thereto. For example, airflow generated by an airflow generator, or airflow formed by air pulses generated by an air pulse generator, can be used for heat dissipation, air sampling, or air extraction. The air pulses generated by the air pulse generator can be generated at any suitable pulse rate. For example, air pulses can be generated at an ultrasonic pulse rate, making it inaudible to the user, but is not limited thereto.

[0070] For example, a semiconductor device (such as a venting device) can control the opening or closing of its valve, but is not limited to this. For instance, a venting device can be used to suppress the occlusion effect during the operation of acoustic devices (such as in-ear earbuds, on-ear earphones, or over-ear earphones), where the occlusion effect is caused by the sealed volume of the ear canal resulting in a higher perceived sound pressure level for the user (i.e., the listener). Because of the presence of the venting device, when the valve of the venting device is open, the volume within the ear canal is not sealed, thus suppressing the occlusion effect and improving the performance of the acoustic device and the user's experience using the acoustic device.

[0071] Please refer to Figure 1 , Figure 1 The diagram shown is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention. Figure 1As shown, the semiconductor device SD1 may include at least one anchoring structure AR and at least one film structure FS, wherein the film structure FS is anchored to the anchoring structure AR. The film structure FS and the anchoring structure AR may include any suitable material. In some embodiments, the film structure FS and the anchoring structure AR may respectively include silicon (e.g., single crystalline silicon, polycrystalline silicon), silicon compounds (e.g., silicon carbide, silicon oxide), germanium, germanium compounds, gallium, gallium compounds (e.g., gallium nitride, gallium arsenide), other suitable materials, or combinations thereof, but are not limited thereto. In some embodiments, the film structure FS and the anchoring structure AR may have the same material.

[0072] During the operation of the semiconductor device SD1, the film structure FS can be actuated to produce movement parallel to the Z direction, while the anchoring structure AR remains stationary. That is, during the operation of the semiconductor device SD1, the anchoring structure AR can serve as a fixed end (or fixed edge) relative to the film structure FS.

[0073] like Figure 1 As shown, the film structure FS of the semiconductor device SD1 includes at least one slit SL, and the film structure FS is divided into multiple lobes FL by the slit SL (i.e., the slit SL penetrates the film structure FS). In this invention, the slit SL can be a straight slit, a curved slit, a combination of multiple straight slits, a combination of multiple curved slits, or a combination of straight slits and curved slits. For example, such as Figure 1 As shown, the membrane structure FS can be divided into a first lobe FL1 and a second lobe FL2 by means of a slit SL (or because of the slit SL), wherein the first lobe FL1 and the second lobe FL2 are arranged opposite to each other, and the slit SL is arranged / formed in the horizontal direction between the first lobe FL1 and the second lobe FL2. It should be noted that the first lobe FL1 and the second lobe FL2 can together form a lobe pair FP in the membrane structure FS.

[0074] exist Figure 1 In the membrane structure FS, the lobes FL have at least one anchoring edge AE (or anchoring end) and at least one free edge FE (or free end). The anchoring edge AE is anchored to the anchoring structure AR, and the free edge FE is not permanently anchored to any component of the semiconductor device SD1. The anchoring edge AE and the free edge FE of each lobe FL can be designed as needed. For example (e.g.) Figure 1As shown), the slit SL can define the first free edge FE1 of the first lobe FL1 and the second free edge FE2 of the second lobe FL2, and the slit SL can be disposed / formed between the first free edge FE1 and the second free edge FE2 (i.e., the first free edge FE1 is separated from the second free edge FE2 by the slit SL). For example, the first free edge FE1 of the first lobe FL1 and the anchoring edge AE1 can be opposite each other, and the second free edge FE2 of the second lobe FL2 and the anchoring edge AE2 can be opposite each other, but are not limited thereto.

[0075] The semiconductor device SD1 may include an actuator ATR for actuating a film structure FS, wherein the actuator ATR may overlap the film structure FS in the Z direction. For example, such as Figure 1 As shown, the actuator ATR may include a first actuating part ATR1 disposed on the first lobe FL1 and a second actuating part ATR2 disposed on the second lobe FL2. The actuator ATR has a monotonic electromechanical conversion function for the movement of the membrane structure FS along the Z direction. For example, the actuator ATR may include a piezoelectric actuator, an electrostatic actuator, a nanoscopic-electrostatic-drive (NED) actuator, an electromagnetic actuator, or any other suitable actuator. For example, in Figure 1 In this process, the actuator ATR can be a piezoelectric actuator and includes two electrodes E1 and E2 and an actuation layer AL disposed between the two electrodes E1 and E2. The actuation layer AL includes, but is not limited to, a suitable piezoelectric material (e.g., lead zirconate titanate, PZT).

[0076] In this invention, at least one protrusion structure PS may be disposed on (or adjacent to) a portion of the free edge FE of the membrane structure FS (e.g., on the free edge FE of the flap FL), wherein the protrusion structure PS is used to increase / enlarge the thickness of the free edge FE in cross-section (e.g., the protrusion structure PS may overlap the free edge FE in the Z direction). The free edge FE on which the protrusion structure PS is disposed has a greater thickness than the thickness of the flap FL located adjacent to or near the anchoring edge AE. The protrusion structure PS may have a suitable thickness, and the slit SL may be located (in the horizontal direction) between two protrusion structures PS. Figure 1 In the middle, the first protrusion structure PS1 is disposed adjacent to the first free edge FE1 and is used to increase the thickness of the first free edge FE1 in the cross section, and the second protrusion structure PS2 is disposed adjacent to the second free edge FE2 and is used to increase the thickness of the second free edge FE2 in the cross section.

[0077] The position of the protruding structure PS can be designed according to actual needs. For example... Figure 1As shown, protruding structures PS (e.g., first protruding structure PS1 and second protruding structure PS2) can be disposed at or adjacent to the free edge FE. In cross-section, the protruding structures PS can be disposed on the same side of the membrane structure FS. For example, as Figure 1 As shown, the protruding structure PS can be disposed above the membrane structure FS, but is not limited thereto. Furthermore, the cross-sectional geometry of the protruding structure PS is not limited; it can be quadrilateral (e.g., rectangular, trapezoidal), etc., but is not limited thereto. As long as the protruding structure PS can increase the thickness of the slit edge (i.e., the free edge defined by the slit), it meets the requirements for the protruding structure PS in this invention and falls within the scope of this invention.

[0078] The protrusion structure PS can comprise any suitable material and can be a single-layer or multi-layer structure. For example, the protrusion structure PS can comprise, but is not limited to, silicon (e.g., monocrystalline silicon, polycrystalline silicon), silicon compounds (e.g., silicon carbide, silicon oxide), germanium, germanium compounds, gallium, gallium compounds (e.g., gallium nitride, gallium arsenide), other suitable materials, or combinations thereof. For example, the protrusion structure PS can be formed of an insulating material, but is not limited to this. For example, the film structure FS and the protrusion structure PS can be formed of the same material, but are not limited to this.

[0079] During the operation of the semiconductor device SD1, the membrane structure FS (i.e., the flap pair FP) is actuated / controlled by the actuator ATR. In this embodiment, the membrane structure FS can be actuated to produce movement in the Z direction, allowing the membrane structure FS to... Figure 2 The transitions between the first state ST1, the second state ST2, and the third state ST3 are shown.

[0080] exist Figure 2 In the first state ST1 shown, the membrane structure FS (lobe pair FP) can be (substantially) horizontal in cross-section (this position can be aligned with the horizontal reference HL), and / or the first free edge FE1 of the first lobe FL1 and the second free edge FE2 of the second lobe FL2 can partially or completely overlap each other in the horizontal direction. Therefore, the virtual valve VV (or opening) associated with the slit SL can be temporarily closed or considered closed in the first state ST1, making it difficult for air to flow through the space between the first free edge FE1 and the second free edge FE2 (i.e., the space between the two opposite sidewalls of the slit SL), thus causing the virtual valve VV to have a large acoustic impedance or flow resistance in the first state ST1. When the virtual valve VV is closed, the acoustic impedance or flow resistance of the virtual valve VV is large or greater than a specific threshold.

[0081] In the first state ST1, because the size of the slit SL (or the width of the slit SL) is sufficiently small, the airflow through the gap (i.e., the narrow channel) can be highly damped due to the viscous forces / resistance along the wall along the airflow path (which can be referred to as the intra-field boundary layer effect in fluid dynamics). Therefore, in the first state ST1, the airflow through the slit SL is sufficiently small and negligible. In other words, when the semiconductor device SD1 is in the first state ST1, the virtual valve VV is closed, or even sealed. The size of the slit SL (or the width of the slit SL) can be designed according to requirements. For example, the size of the slit SL (or the width of the slit SL) can be less than or equal to 5 μm, less than or equal to 3 μm, less than or equal to 2 μm, or 1 μm to 2 μm, but is not limited thereto.

[0082] exist Figure 2 In the second state ST2 shown, the flap FL can be actuated to bend in the same direction, such that the first free edge FE1 and the second free edge FE2 can simultaneously be above or below a certain horizontal reference (e.g., horizontal reference HL). For example, in the second state ST2, the distance between the first free edge FE1 and the horizontal reference HL can be equal to the distance between the second free edge FE2 and the horizontal reference HL. For example, the first free edge FE1 and the second free edge FE2 can also partially or completely overlap each other in the horizontal direction. In the second state ST2, the virtual valve VV can be temporarily closed, making it difficult for air to flow through the space between the first free edge FE1 and the second free edge FE2 (i.e., the space between the two opposite sidewalls of the slit SL), thereby giving the virtual valve VV a larger flow resistance in the second state ST2.

[0083] exist Figure 2 In the second state ST2 shown, due to the temporary closure of the virtual valve VV and its significant flow resistance, a pressure difference occurs across the membrane structure FS, resulting in a pressure differential. That is, when the membrane structure FS is in the second state ST2 and / or when it is actuated to transition to the second state ST2, an air pressure variation occurs within the membrane structure FS. It should be noted that this air pressure variation is formed at a pressure change frequency.

[0084] exist Figure 2In the third state ST3 shown, the lobes FL can be actuated to bend in opposite directions (e.g., the first lobe FL1 can be actuated to bend in direction Z, and the second lobe FL2 can be actuated to bend in the opposite direction Z), such that the first free edge FE1 and the second free edge FE2 are located on opposite sides of a certain horizontal reference (e.g., horizontal reference HL). For example, in the third state ST3, the distance between the first free edge FE1 and the horizontal reference HL can be equal to the distance between the second free edge FE2 and the horizontal reference HL.

[0085] In the third state ST3, the first free edge FE1 and the second free edge FE2 do not overlap in the horizontal direction, such that the displacement U of the first free edge FE1 is... z,FL1 Displacement U of the second free edge FE2 z,FL2 The difference ΔU z (For example, ΔU) z =|U z,FL1 - U z,FL2 The thickness of the slit SL is greater than that of the first free edge FE1 (and / or greater than that of the second free edge FE2). Therefore, the virtual valve VV associated with the slit SL can be temporarily formed (opened) in the third state ST3, allowing air to flow easily through the space between the first free edge FE1 and the second free edge FE2 (i.e., the space between the two opposite sidewalls of the slit SL), thereby giving the virtual valve VV lower flow resistance in the third state ST3. That is, the virtual valve VV is formed because of the slit SL. It should be noted that the virtual valve VV is formed at a valve opening frequency. When the virtual valve VV is formed / opened, the flow resistance of the virtual valve VV is lower or below another specific threshold.

[0086] In the third state ST3, if a pressure difference exists between the two opposite sides of the membrane structure FS, air flows naturally through the virtual valve VV based on the lower flow resistance of the virtual valve VV and the pressure difference, thereby generating airflow and / or air pulses. In some embodiments, during a time period when the membrane structure FS is in the third state ST3, airflow will pass through the virtual valve VV.

[0087] Based on the above, by actuating the membrane structure FS, the virtual valve VV associated with the slit SL can be formed / opened or closed (i.e., the membrane structure FS can be used to form / open or close the virtual valve VV), thereby generating airflow, air pulses and / or acoustic waves.

[0088] In some embodiments, the membrane structure FS can be actuated to perform common-mode movement and differential-mode movement to change its state. The common-mode movement causes the first flap FL1 and the second flap FL2 to be simultaneously actuated and move in the same direction, while the differential-mode movement causes the first flap FL1 and the second flap FL2 to be simultaneously actuated and move in opposite directions. For example, the membrane structure FS can be in a second state ST2 (i.e., the membrane structure FS creates an air pressure change by performing common-mode movement) and can be in a third state ST3 (i.e., the membrane structure FS creates a virtual valve VV by performing differential-mode movement) by performing differential-mode movement, but this is not a limitation. For example, the membrane structure FS can also be actuated to perform both common-mode and differential-mode movement simultaneously, but this is not a limitation.

[0089] In this invention, the actuator ATR can receive any suitable signal to actuate the membrane structure FS. In some embodiments, the membrane structure FS can be actuated by a modulation driving signal (which may also be referred to as a pressure driving signal in some cases) to perform common-mode motion and / or be in the second state ST2, and the membrane structure FS can be actuated by a demodulation driving signal (which may also be referred to as a valve driving signal in some cases) to perform differential-mode motion and / or be in the third state ST3. In some embodiments, the actuator ATR can receive the modulation driving signal and the demodulation driving signal at different times, but is not limited thereto.

[0090] It should be noted that the first state ST1, the second state ST2, and the third state ST3 are for illustrative purposes only and are not restrictive. The operation of the semiconductor device of this invention can be found in U.S. Patent Nos. 11,399,228, 11,943,585, and U.S. Patent Application Nos. 19 / 007,580, 19 / 424,094, and 19 / 446,931, the contents of which are incorporated herein by reference and, for the sake of brevity, will not be repeated here.

[0091] For example, in the embodiment disclosed in U.S. Patent No. 11,943,585 filed by the applicant, electrodes E1 and E2 of the actuator ATR receive a demodulation (valve) drive signal and a modulation (pressure) drive signal (e.g., electrode E2 receives the demodulation (valve) drive signal, and electrode E1 receives the modulation (pressure) drive signal), but are not limited thereto. The modulation (pressure) drive signal is used to drive the membrane structure FS to perform common-mode motion, while the demodulation (valve) drive signal is used to drive the membrane structure FS to perform differential-mode motion.

[0092] In the operation of existing semiconductor devices, when a virtual valve is opened or closed at an incorrect time, or fails to open or close properly, undesirable backflow often occurs, adversely affecting the operation of the semiconductor device. In some cases, due to the thinness of the fins in existing technologies, the closing time of the virtual valve is often insufficient when it is significantly opened to achieve a larger airflow, larger air pulse, and / or higher sound pressure level (SPL). However, in this invention, as... Figure 1 and Figure 2 As shown, due to the presence of the protruding structure PS used to increase the thickness of the free edge FE, the free edges FE can easily overlap each other (in the horizontal direction), allowing the virtual valve VV to be precisely opened or closed at the correct time, and ensuring proper opening or closing of the virtual valve VV, thereby effectively reducing the generation of undesirable backflow during operation. Furthermore, based on the presence of the protruding structure PS, the time required to close the virtual valve VV can be further shortened. On the other hand, the semiconductor device SD1 of the present invention has the protruding structure PS, rather than uniformly increasing the overall thickness of the flap FL, so that the flap FL can still maintain good mobility and continuously generate high airflow, large air pulses, and / or high sound pressure levels. In addition, the protruding structure PS can also improve the tolerance for undesirable leakage during operation and actuation.

[0093] In an embodiment where the semiconductor device SD1 is an air pulse generating device, the membrane structure FS can be actuated to generate multiple air pulses, and the air pulses can be formed by changes in the state of the membrane structure FS. In some embodiments, the flow direction of the air pulses and / or the flow direction of the airflow formed by the air pulses can be reversible. In some embodiments, the air pulses can be asymmetric.

[0094] Furthermore, air pulses can be generated at a suitable pulse rate, and the frequency of air pressure changes and the valve opening frequency of the virtual valve VV can be synchronized at this pulse rate. For example, the membrane structure FS (valve pair FP) can operate at an ultrasonic frequency, allowing air pulses to be generated at an ultrasonic pulse rate, and the frequency of pressure changes and the valve opening frequency can also be synchronized at this ultrasonic pulse rate, but this is not a limitation.

[0095] Furthermore, the modulation drive signal and demodulation drive signal can be correlated with the output amplitude of the air pulse, and the modulation frequency of the modulation drive signal and the demodulation frequency of the demodulation drive signal can also be correlated with the pulse rate of the air pulse. For example, the modulation frequency and demodulation frequency can be synchronized with the pulse rate of the air pulse, the pressure change frequency of the air pressure change, and the valve opening frequency of the virtual valve VV, but are not limited thereto.

[0096] Figure 3 and Figure 4 An embodiment of the semiconductor device SD1 as an air pulse generating device and related to asymmetric deflection is shown (the technology of which is disclosed in U.S. Patent Application No. 19 / 424,094). Figure 3 As shown, during the operation of the semiconductor device SD1 (i.e., the air pulse generating device), the flap pair FP (film structure FS) has an initial deflection difference or exhibits an average displacement difference between the first flap FL1 and the second flap FL2.

[0097] exist Figure 3 In the illustrated embodiment, the first lobe FL1 is actuated to bend in the Z direction (upward bending), while the second lobe FL2 is actuated to bend in the opposite direction (downward bending). When the semiconductor device SD1 has an asymmetric initial deflection, the first lobe FL1 is in its initial position. 0,FL1 An initial deflection occurs, while the second lobe FL2 remains in its initial position. 0,FL2 An initial deflection is generated to prepare for differential mode motion. Additionally, the first lobe FL1 is positioned... min,FL1 , max,FL1 The second lobe FL2 oscillates within the range RG1. min,FL2 , max,FL2 The oscillation occurs within the range RG2 (i.e., the first average displacement corresponding to the first lobe FL1 differs from the second average displacement corresponding to the second lobe FL2). In other words, the position... min,FL1 , max,FL1 The reversal point / turning point / extreme point of the first lobe FL1, and its position min,FL2 and max,FL2 This is the reversal point / turning point / extreme point of the second lobe FL2. Here, the symbol... It can be considered as the (angular) position of the tip of the FL relative to its anchoring position.

[0098] In one embodiment, such as Figure 3 As shown, location min,FL1 With position max,FL2 Alignment with horizontal reference HL. The swing range RG1 of the first lobe FL1 is (substantially) above the horizontal reference HL, while the swing range RG2 of the second lobe FL2 is (substantially) below the horizontal reference HL.

[0099] Therefore, there is an initial deflection difference or an average displacement difference (i.e., the difference between the first average displacement and the second average displacement) between the first lobe FL1 and the second lobe FL2, wherein both the initial deflection difference and the average displacement difference are greater than the thickness of the membrane structure FS and the thickness of the free edge FE.

[0100] In the case of asymmetric deflection, when the first lobe FL1 swings to position min,FL1 And the second petal FL2 swings to position max,FL2 When the membrane structure FS is in the first state ST1, the virtual valve VV is considered closed; and when the first flap FL1 swings to position max,FL1 And the second petal FL2 swings to position min,FL2 At this time (when the membrane structure FS is in the third state ST3), the virtual valve VV is considered to be formed. In other words, when the first lobe FL1 is at or near position... min,FL1 (Reversal point / Turning point / Extreme point), and the second lobe FL2 is located at or near the position. max,FL2 At (reversal point / turning point / extreme point), the virtual valve VV is closed; when the first disc FL1 is at or near the position... max,FL1 (Reversal point / Turning point / Extreme point), and the second lobe FL2 is located at or near the position. min,FL2 At (reversal point / turning point / extreme point), the virtual valve VV is formed.

[0101] For example, during one movement cycle of asymmetric deflection (e.g., Figure 4 ), the first lobe FL1 from position 0,FL1 (Time T) 21 Start by moving sequentially to the desired position. min,FL1 , 0,FL1 , max,FL1 , 0,FL1 (corresponding to time T respectively) 22T 23 T 24 T 25 ), while the second lobe FL2 is located from position 0,FL2 (Time T) 21 Start by moving sequentially to the desired position. max,FL2 , 0,FL2 , min,FL2 , 0,FL2 (corresponding to time T respectively) 22 T 23 T 24 T 25 This allows the membrane structure FS to be viewed as transitioning between a first state ST1 and a third state ST3 from the perspective of differential mode motion. During this movement cycle of asymmetric deflection, the virtual valve VV closes only once per movement cycle. For example, since the virtual valve VV closes only once per movement cycle, the pressure change frequency corresponding to common mode motion and the valve opening frequency corresponding to differential mode motion can be the same.

[0102] In the asymmetric deflection design, the first lobe FL1 and the second lobe FL2 can be driven by a first valve drive signal and a second valve drive signal, respectively, and the first valve drive signal and the second valve drive signal have different bias voltages (that is, the first bias voltage of the first valve drive signal is different from the second bias voltage of the second valve drive signal). Because the first bias voltage and the second bias voltage are different from each other, the initial deflection of the first lobe FL1 is significantly different from the initial deflection of the second lobe FL2.

[0103] In asymmetric deflection, as disclosed in U.S. Patent Applications Nos. 19 / 424,094 and 19 / 446,931, a first valve drive signal has a first polarity relative to a first bias voltage, and a second valve drive signal has a second polarity relative to a second bias voltage, with the first and second polarities being opposite to each other. For example, at time T... 21 With T 22 During the time interval between these intervals, the first valve drive signal may have a negative polarity relative to the first bias voltage, while the second valve drive signal may have a positive polarity relative to the second bias voltage, causing the first valve FL1 to swing to position [position missing]. min,FL1 And the second lobe FL2 swings to position max,FL2 This closes the virtual valve VV.

[0104] For details regarding the drive signal for asymmetric deflection and the effects of asymmetric deflection, please refer to the applicant's U.S. Patent Application No. 19 / 424,094. For the sake of brevity, these details will not be elaborated here.

[0105] In addition to the aforementioned asymmetric deflection Figure 5 An embodiment of the semiconductor device SD1 as an air pulse generating device and related to symmetric deflection is shown (the technology of which is disclosed in U.S. Patent No. 11,943,585). Figure 5 In the process, the membrane structure FS (lobe pair FP) can initially be in the first state ST1, such that the first lobe FL1 and the second lobe FL2 can be respectively positioned aligned with the horizontal reference HL. I,FL1 , I,FL2 Begin. The first lobe FL1 can be actuated at a position higher than [position missing]. I,FL1 Location A,FL1 and below position I,FL1 Location U,FL1 Between, the second lobe FL2 can be actuated at a position higher than [position]. I,FL2 Location A,FL2 and below position I,FL2 Location U,FL2 Therefore, the average displacement of the first lobe FL1 is (substantially) the same as the average displacement of the second lobe FL2, and the initial deflection of the first lobe FL1 is (substantially) the same as the initial deflection of the second lobe FL2.

[0106] For example, in one movement cycle of symmetrical deflection (e.g., Figure 5 ), the first lobe FL1 from position I,FL1 (Time T) 11 Start by moving sequentially to the desired position. A,FL1 , I,FL1 , U,FL1 , I,FL1 (corresponding to time T respectively) 12 T 13 T 14 T 15 ), the second lobe FL2 from position I,FL2 (Time T) 11 Start by moving sequentially to the desired position. U,FL2 , I,FL2 , A,FL2 , I,FL2 (corresponding to time T respectively) 12 T 13 T 14 T 15 This allows the membrane structure FS to transition between the first state ST1 and the third state ST3 from the perspective of differential mode motion.

[0107] In this symmetrical deflection design, the first valve FL1 and the second valve FL2 can be driven by a first valve drive signal and a second valve drive signal, respectively, and the first valve drive signal and the second valve drive signal have the same bias voltage. Furthermore, during certain time intervals, the first valve drive signal has a first polarity relative to this bias voltage, and the second valve drive signal has a second polarity relative to this bias voltage, with the first polarity and the second polarity being opposite to each other.

[0108] The following describes a method for manufacturing the aforementioned semiconductor device SD1 (e.g., the aforementioned air pulse generating device), wherein the semiconductor device SD1 of the present invention can be manufactured by any suitable process. For example, Figures 6 to 11 An embodiment of the manufacturing method of the aforementioned semiconductor device SD1 is illustrated, wherein... Figures 6 to 11 The diagram shows a cross-sectional view of the structure of the semiconductor device SD1 at different process stages in the manufacturing method. It should be noted that the manufacturing method of the semiconductor device SD1 of the present invention is not limited to the embodiments and figures described below. In some embodiments, any other suitable steps may be added (or removed) before or after any step in the manufacturing method, and / or some steps may be performed simultaneously or separately. In some embodiments, the process sequence of the manufacturing method may also be adjusted according to actual needs.

[0109] For example, the semiconductor device SD1 can be formed by at least one semiconductor process, such that the semiconductor device SD1 can be a MEMS wafer including a MEMS structure, but is not limited thereto. In the manufacturing method of the semiconductor device SD1 described below, the process for forming the film or structure may include atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), coating process, any other suitable process, or a combination thereof, but is not limited thereto. In the manufacturing method of the semiconductor device SD1 described below, the patterning process may include photolithography, etching process, any other suitable process, or a combination thereof, wherein the etching process may be a wet etching process, a dry etching process, any other suitable etching process, or a combination thereof, but is not limited thereto.

[0110] like Figure 6 As shown, a wafer WF is provided, wherein the wafer WF may include a first layer WL1 and a second layer WL2, and may optionally include a wafer insulating layer WL3 located between the first layer WL1 and the second layer WL2.

[0111] The first layer WL1, the wafer insulating layer WL3, and the second layer WL2 may each comprise any suitable material, such that the wafer WF can be of any suitable type. For example, the first layer WL1 and the second layer WL2 may each comprise silicon (e.g., monocrystalline silicon, polycrystalline silicon), silicon compounds (e.g., silicon carbide, silicon oxide), germanium, germanium compounds, gallium, gallium compounds (e.g., gallium nitride, gallium arsenide), other suitable materials, or combinations thereof. For example, the wafer insulating layer WL3 may comprise an oxide, such as silicon oxide (e.g., silicon dioxide), but is not limited thereto. For example, the first layer WL1 may comprise monocrystalline silicon, while the wafer insulating layer WL3 may comprise an oxide layer, such that the wafer WF can be a silicon-on-insulator (SOI) wafer, but is not limited thereto.

[0112] After completion Figure 6 Following the steps shown, an insulating layer (e.g., first insulating layer IL1), a conductive layer (e.g., first conductive layer CT1), and an actuation layer (e.g., actuation layer AL) can be formed on the wafer WF and patterned, as shown in the schematic cross-sectional view. Figure 7 As shown.

[0113] exist Figure 7In this process, a patterned first insulating layer IL1 can be formed on the upper side of the wafer WF, such that the first layer WL1 is between the first insulating layer IL1 and the second layer WL2. The material contained in the first insulating layer IL1 can be designed according to actual needs. For example, the first insulating layer IL1 may include oxides (e.g., silicon dioxide, compensating oxides), but is not limited thereto.

[0114] exist Figure 7 In this process, the first insulating layer IL1 may further include a first substructure SS1. For example, the first substructure SS1 may be disposed at the location of the subsequently formed protrusion structure PS and the slit SL.

[0115] exist Figure 7 In this process, a patterned first conductive layer CT1 and a patterned actuation layer AL can be sequentially formed on the upper side of the wafer WF (i.e., formed on the first layer WL1), such that the first conductive layer CT1 is located between the actuation layer AL and the first layer WL1. Figure 7 In this configuration, the first conductive layer CT1 may be located between the actuating layer AL and the first insulating layer IL1. The first conductive layer CT1 may comprise any suitable conductive material. For example, the first conductive layer CT1 may comprise a metal (e.g., platinum, Pt), but is not limited thereto.

[0116] For example, the first insulating layer IL1, the first conductive layer CT1 and the actuating layer AL can be formed sequentially, and then the actuating layer AL, the first conductive layer CT1 and the first insulating layer IL1 can be patterned sequentially, but this is not a limitation.

[0117] like Figure 8 As shown, the second insulating layer IL2 can be formed on the actuation layer AL and patterned thereon. The material of the second insulating layer IL2 can be designed according to actual needs. For example, the second insulating layer IL2 may include oxides, but is not limited thereto.

[0118] exist Figure 8 In this process, the second insulating layer IL2 may include a second substructure SS2. For example, the second substructure SS2 may be disposed at the location of the subsequently formed protrusion structure PS and the slit SL. Figure 8 In the structure, the first substructure SS1 and the second substructure SS2 overlap each other, and the first substructure SS1 and the second substructure SS2 together form the structural layer SSL.

[0119] It should be noted that the second substructure SS2 may be an optional or adjustable component in the structural layer SSL. In one embodiment, the second substructure SS2 can be used to adjust the thickness of the free edge of the petal. In some embodiments, the second substructure SS2 may also be omitted, which is also within the scope of this invention.

[0120] like Figure 8As shown, the second conductive layer CT2 can be formed on the actuation layer AL and the second insulating layer IL2, and then the second conductive layer CT2 is patterned. The material of the second conductive layer CT2 can be designed as needed. For example, the second conductive layer CT2 may include metals (such as aluminum-copper alloy (AlCu) or titanium nitride (TiN)), but is not limited thereto. It should be noted that the second insulating layer IL2 can be used to isolate at least a portion of the first conductive layer CT1 from at least a portion of the second conductive layer CT2.

[0121] exist Figure 8 In this process, the actuator ATR can be formed from the actuation layer AL, the electrode E1 belonging to the first conductive layer CT1, and the electrode E2 belonging to the second conductive layer CT2. Therefore, the actuator ATR can be formed on the first layer WL1 of the wafer WF.

[0122] like Figure 9 As shown, the structural layer SSL can be patterned to form protrusion structures PS (e.g., a first protrusion structure PS1 and a second protrusion structure PS2). Subsequently, the first layer WL1 of the wafer WF can be patterned to form a slit SL (i.e., the slit SL penetrates the first layer WL1), wherein the slit SL is located horizontally between the two protrusion structures PS. Figure 9 In the middle, the slit SL is the part that is removed / etched in the first layer WL1.

[0123] In this invention, the structural layer SSL and the first layer WL1 can be patterned using any suitable process. For example, the structural layer SSL and the first layer WL1 can be patterned simultaneously in the same patterning process, such that the same etch stop layer can be used in the step of patterning the first layer WL1 and the step of patterning the structural layer SSL, but this is not a limitation. For example, the protrusion structure PS can be formed before the formation of the second conductive layer CT2 (e.g., during the patterning process of the structural layer SSL), while the first layer WL1 can be patterned after the formation of the second conductive layer CT2, but this is not a limitation.

[0124] Optionally, such as Figure 10 As shown, a capping layer CV can be formed on the second conductive layer CT2, the second insulating layer IL2, and the wafer WF using any suitable process (e.g., atomic layer deposition). Subsequently, the capping layer CV is patterned, and the capping layer CV may include any suitable insulating material (e.g., aluminum oxide). Furthermore, in Figure 10 In the process, after the patterned cover layer CV, the portion of the second conductive layer CT2 that is not covered by the cover layer CV can be used as a connecting pad PD.

[0125] like Figure 11 As shown, the second layer WL2 of the wafer WF can be patterned to release a portion of the first layer WL1 from the second layer WL2 as a film structure FS (i.e., the film structure FS is formed in the first layer WL1). Specifically, the second layer WL2 of the wafer WF can include a first portion and a second portion. The first portion of the second layer WL2 can be removed, while the second portion of the second layer WL2 is retained. The portion of the first layer WL1 corresponding to the removed first portion in the second layer WL2 in the Z direction can serve as or be considered as the film structure FS, while the second portion of the second layer WL2 can serve as or be considered as an anchoring structure AR. For example, the first portion of the second layer WL2 can be removed by a deep reactive ion etching (DRIE) process, but is not limited thereto.

[0126] Furthermore, since there is a wafer insulating layer WL3 in the wafer WF, after the patterning process of the second layer WL2 of the wafer WF, the corresponding portion of the wafer insulating layer WL3 corresponding to the first part of the second layer WL2 can be further removed.

[0127] Please refer to Figures 12 to 17 , Figures 12 to 17 The diagram shown is a cross-sectional view of the structure of a semiconductor device manufacturing method according to a second embodiment of the present invention at different process stages. Figure 12 The final structure of the semiconductor device SD2 according to the second embodiment is shown. Figure 12 As shown, the difference between this embodiment and the first embodiment lies in the design / position of the protrusion structure PS of the semiconductor device SD2. Figure 12 In this process, the protruding structure PS can be placed below the membrane structure FS.

[0128] The following describes a method for manufacturing a semiconductor device SD2, which is not limited to the embodiments and figures disclosed below.

[0129] like Figure 13 and Figure 14 As shown, a wafer WF is provided, wherein a second layer WL2 has multiple trenches TE, and a portion of a first layer WL1 is filled in the trenches TE, such that the first layer WL1 has multiple filling structures FF filling the trenches TE. The filling structures FF and the trenches TE can be positioned at the locations of subsequently formed protrusion structures PS. Alternatively, since a wafer insulating layer WL3 may exist between the first layer WL1 and the second layer WL2, a portion of the wafer insulating layer WL3 can also be disposed in the trenches TE.

[0130] For example, the formation process of a wafer WF is shown in Figure 13 and Figure 14 However, the formation process of wafer fuzzy surfaces (WF) is not limited to this. Figure 13 In this process, trenches TE can be formed on the second layer WL2 through an etching process. Alternatively, in Figure 13 In this process, a wafer insulating layer WL3 can be formed on the second layer WL2, such that a portion of the wafer insulating layer WL3 is disposed in the trench TE. Figure 14 In this process, a first layer WL1 can be formed on the second layer WL2 and the wafer insulating layer WL3, wherein a portion of the first layer WL1 is filled into the trench TE, so that the first layer WL1 has a filling structure FF that fills the trench TE.

[0131] like Figure 15 As shown, similar to the manufacturing method of the semiconductor device SD1 in the first embodiment, a patterned first insulating layer IL1, a patterned first conductive layer CT1, a patterned actuation layer AL, a patterned second insulating layer IL2, and a patterned second conductive layer CT2 can be formed on a wafer WF.

[0132] like Figure 16 As shown, the first layer WL1 can be patterned to form a slit SL (i.e., the slit SL extends through the first layer WL1), wherein the slit SL can be located in the horizontal direction between the two filling structures FF.

[0133] Optionally, such as Figure 17 As shown, a patterned capping layer CV can be formed on the second conductive layer CT2, the second insulating layer IL2, and the wafer WF.

[0134] Finally, a patterning process can be performed on the second layer WL2 of the wafer WF to remove the first part of the second layer WL2 (such as...). Figure 12 As shown), the portion of the first layer WL1 corresponding to the first part removed in the second layer WL2 in the Z direction is released from the second layer WL2 to form the film structure FS (i.e., the film structure FS is formed in the first layer WL1), and the protrusion structure PS is formed by the filling structure FF (i.e., the filling structure FF also corresponds to the first part removed in the second layer WL2 in the Z direction). Since there is a wafer insulating layer WL3 in the wafer WF, this process can also pattern the wafer insulating layer WL3.

[0135] In this embodiment, since the protrusion structure PS is formed by the filling structure FF of the first layer WL1, the membrane structure FS, the protrusion structure PS and the first layer WL1 can be formed by the same material.

[0136] It should be noted that in the foregoing embodiments, the protrusion structure PS is formed on both leaflets FL of the leaflet pair FP, but this is not a limitation. In one embodiment, the protrusion structure PS may also be formed only on one of the leaflets FL of the leaflet pair FP (e.g., Figure 18 The semiconductor device SD1_1 shown is sufficient to satisfy the requirements of this invention and fall within its scope, as long as the thickness of the free edge FE of the lobe FL can be increased.

[0137] Furthermore, the semiconductor device of the present invention (e.g., Figure 19 The semiconductor device SD1_2 shown may include a flap FL disposed opposite to a portion of the film structure FS. The flap FL can be actuated such that it moves up / down relative to that portion of the film structure FS, forming a virtual valve between the flap FL and that portion of the film structure FS. Figure 19 As shown, the protrusion structure PS can be formed on the free edge FE of the lobule FL (this portion of the lobule FL and the membrane structure FS are opposite each other) to increase / enlarge the thickness of the free edge FE of the lobule FL. In another embodiment (e.g., Figure 19 (As shown in the variant of the semiconductor device SD1_2), a protrusion structure PS can be formed on the free edge of this portion of the membrane structure FS (this portion of the membrane structure FS is opposite to the free edge FE of the flap FL) to increase the thickness of the free edge of the membrane structure FS. Given a specific drive signal, the closing time of the virtual valve can be extended compared to the case without the protrusion structure. In other words, the time the virtual valve remains in the closed state is extended due to the thickness provided by the protrusion structure PS, which is also within the scope of this invention.

[0138] In summary, the presence of the protruding structure of this invention increases the thickness of the free edge of the film structure. Therefore, during the operation of the semiconductor device, while maintaining good flap mobility, it is possible to effectively reduce undesirable backflow and improve tolerance to undesirable leakage.

[0139] The foregoing outlines the features of several embodiments, enabling those skilled in the art to fully understand the various aspects of the invention. Those skilled in the art should recognize that the invention provides a basis for designing or modifying other processes and structures to achieve substantially the same functionality and / or substantially the same results as the embodiments described above. Furthermore, such equivalent configurations do not depart from the spirit and scope of the invention, and various changes, substitutions, and modifications can be made without departing from that spirit and scope.

Claims

1. An air pulse generating device, comprising: A membrane structure; as well as A protrusion structure is formed on a free edge of a portion of the membrane structure, the protrusion structure being used to increase the thickness of the free edge in cross-section.

2. The air pulse generating device of claim 1, wherein the membrane structure includes a pair of lobes, the pair of lobes including a first lobe and a second lobe, and the air pulse generating device comprises: A first protrusion structure is disposed adjacent to a first free edge of the first lobe and is used to increase the thickness of the first free edge in cross section; as well as A second protrusion structure is disposed adjacent to a second free edge of the second lobe and is used to increase the thickness of the second free edge in cross section.

3. The air pulse generating device as claimed in claim 2, wherein the first protrusion structure and the second protrusion structure are disposed on the same side of the membrane structure.

4. The air pulse generating device of claim 2, wherein the pair of lobes has an initial deflection difference or exhibits an average displacement difference between the first lobe and the second lobe.

5. The air pulse generating device as claimed in claim 2, wherein the flap pair performs a differential motion to form a virtual valve at a valve opening frequency.

6. The air pulse generating device of claim 5, wherein the flap pair performs a common-mode motion to generate an air pressure change.

7. The air pulse generating device as claimed in claim 6, wherein a pressure change frequency corresponding to the common-mode motion is the same as the valve opening frequency corresponding to the differential-mode motion.

8. The air pulse generating device of claim 5, wherein the virtual valve is closed when the first lobe is located at a first reversal point and the second lobe is located at a second reversal point.

9. The air pulse generating device of claim 2, wherein the first lobe is actuated to bend in a first direction, and the second lobe is actuated to bend in a second direction, the first direction being opposite to the second direction.

10. The air pulse generating device as claimed in claim 1, The membrane structure includes a pair of lobes, the pair of lobes including a first lobe and a second lobe; The first valve is driven by a first valve drive signal, and the second valve is driven by a second valve drive signal to form a virtual valve. The first valve drive signal includes a first bias voltage, the second valve drive signal includes a second bias voltage, and the first bias voltage is different from the second bias voltage.

11. The air pulse generating apparatus of claim 10, wherein the first valve drive signal has a first polarity relative to the first bias voltage, the second valve drive signal has a second polarity relative to the second bias voltage, and the first polarity and the second polarity are opposite to each other.

12. The air pulse generating device of claim 10, wherein the first and second lobes are driven by a pressure drive signal to perform a common-mode motion and generate an air pressure change.

13. A semiconductor device, comprising: A membrane structure; as well as A protrusion structure is formed on a free edge of a portion of the membrane structure, the protrusion structure being used to increase the thickness of the free edge in cross-section.

14. The semiconductor device of claim 13, wherein the film structure includes a pair of lobes, the pair of lobes including a first lobe and a second lobe, the semiconductor device comprising: A first protrusion structure is disposed adjacent to a first free edge of the first lobe and is used to increase the thickness of the first free edge in cross section; as well as A second protrusion structure is disposed adjacent to a second free edge of the second lobe and is used to increase the thickness of the second free edge in cross section.

15. The semiconductor device of claim 14, wherein the first protrusion structure and the second protrusion structure are disposed above the film structure.

16. The semiconductor device of claim 14, wherein the first protrusion structure and the second protrusion structure are disposed below the film structure.

17. The semiconductor device of claim 13, wherein the film structure is actuated within a time period to form a virtual valve, and an airflow passes through the virtual valve within the time period.

18. The semiconductor device of claim 13, wherein the semiconductor device is a loudspeaker, an air pulse generating device, an airflow generating device, or a ventilation device.

19. A method for manufacturing a semiconductor device, comprising: Provide one wafer; A slit is formed on the wafer, wherein the slit defines a free edge of a film structure; as well as A protrusion structure is formed on the free edge of the membrane structure, wherein the protrusion structure is used to increase the thickness of the free edge in cross-section.

20. The manufacturing method of claim 19, wherein the wafer comprises a first layer and a second layer, and the manufacturing method comprises: Pattern the first layer to form the slit; as well as The second layer is patterned such that the membrane structure is formed in the first layer; The membrane structure includes a pair of lobes, the pair of lobes including a first lobe and a second lobe opposite to each other, the first lobe having a first free edge, the second lobe having a second free edge, and the first free edge and the second free edge being separated from each other by the slit.

21. The manufacturing method of claim 19, wherein the wafer comprises a first layer and a second layer, and the manufacturing method comprises: A first protrusion structure is formed, the first protrusion structure being adjacent to a first free edge and used to increase the thickness of the first free edge in cross section; as well as A second protrusion structure is formed, which is adjacent to a second free edge and is used to increase the thickness of the second free edge in the cross section.

22. The manufacturing method of claim 21, wherein the first protrusion structure and the second protrusion structure are formed by the following steps: A structural layer is formed on the first layer; and The structural layer is patterned to form the first protrusion structure and the second protrusion structure.

23. The manufacturing method of claim 21, wherein the first protrusion structure and the second protrusion structure are formed by the following steps: Multiple trenches are formed on the second layer; The first layer is formed on the second layer having the trench to form the wafer, wherein the first layer has a plurality of filling structures filling the trench; The first layer is patterned to form the slit between two of the filling structures; as well as The second layer is patterned such that the membrane structure is formed in the first layer, and the first protrusion structure and the second protrusion structure are respectively formed by the two of the filling structures.

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