A zoned pulsed PEALD coating process

Abstract

The application discloses a kind of partition pulse PEALD coating processes, including silicon wafer partition plasma pretreatment, partition ozone step pulse circulation PEALD deposition, gradient pressure dynamic partition control, in-situ deposition doped amorphous silicon passivation layer in the same cavity, by extending the edge zone silicon source, ozone pulse length, make up large silicon wafer edge precursor diffusion deficiency, relieve edge film thickness thin defect;With edge zone large flow partition purging, quickly take away the excess precursor adsorbed on the side of silicon wafer, reduce the front, side edge wrap plating;Ozone oxidation activity is high simultaneously, can shorten single-step reaction time, reduce the precursor lateral diffusion range, further inhibit the wrap plating generation. Thus can reduce the non-uniformity of film thickness in the wafer, reduce the silicon wafer edge leakage defect, simplify the back-end alkali etching, laser grooving process, reduce processing cost and improve battery yield.

Description

Technical Field

[0001] This invention relates to the field of building foundation construction technology, and in particular to a partitioned pulsed PEALD coating process. Background Technology

[0002] TOPCon (tunneling oxide passivated contact) solar cells are currently the mainstream high-efficiency photovoltaic cell technology. The core structure on the back of the cell is an ultra-thin silicon dioxide tunneling oxide layer plus a heavily doped polycrystalline silicon layer. The thickness uniformity, film density, and interface defect level of the tunneling oxide layer directly determine the cell's open-circuit voltage, saturation dark current, and batch yield. PEALD (plasma-enhanced atomic layer deposition) has the advantages of atomic-level precise film control and low-temperature, low-ion damage. It is a new generation of differentiated coating route that differs from tubular thermal oxidation and conventional PECVD oxidation, and is suitable for upgrading high-end production lines with 210mm large-size silicon wafers. Atomic layer deposition relies on the self-limiting reaction of the precursor to achieve nanoscale film growth, and theoretically has excellent film thickness uniformity. However, in plate-type mass production chambers, uneven airflow distribution on large silicon wafers brings unsolvable mass production pain points.

[0003] Existing traditional technical solutions and their shortcomings ① Traditional single-zone constant-pressure PEALD process The entire cavity employs a unified spray gas supply, consistent pulse timing across the entire area, and constant pressure throughout the cavity to complete the pulsed cyclic deposition of silicon source and oxidant. Defects: Insufficient gas molecule diffusion flux at the inner edge of the 210mm large silicon wafer cavity results in a significantly thinner oxide layer at the wafer edge; during subsequent annealing, phosphorus doping atoms easily penetrate the thin edge layer, causing intensified local carrier recombination, large open-circuit voltage differences within a single silicon wafer, and poor electrical consistency in batches of cells; if the pulse duration is uniformly extended across the entire area, the thin film at the center of the silicon wafer becomes too thick, increasing tunneling resistance and decreasing the cell fill factor. Simultaneously, precursor gases easily adsorb and deposit along the sides and front edges of the silicon wafer, forming a large amount of wrap-around coating. This necessitates additional alkaline polishing and laser grooving processes to remove the wrap-around coating, increasing production costs. Furthermore, the etching process can damage the silicon substrate, inducing edge leakage defects.

[0004] ② PEALD process with zoned pulse and constant pressure throughout the cavity Differentiated silicon sources and ozone pulse durations are set only for the center and edge of the silicon wafer, while maintaining uniform cavity pressure throughout. Drawbacks: Relying solely on pulse duration to compensate for airflow differences cannot fundamentally balance the precursor supply between the center and edge of the silicon wafer. The edge of the silicon wafer still suffers from thinner film thickness, and the improvement in intra-wafer film thickness uniformity is limited. Poor suppression of side-mounted plating on the silicon wafer fails to address the shortcomings in mass production yield.

[0005] ③ Partial-cavity PEALD+PECVD process The PEALD oxidation chamber and the doped silicon deposition chamber are independent of each other. After the silicon wafer is oxidized, it is transferred out of the chamber and then sent into the PECVD equipment to deposit polycrystalline silicon. Disadvantages: During the silicon wafer transfer process, it comes into contact with air, causing the regeneration of a native oxide layer on the silicon surface, introducing a large number of interface defects and increasing the interface state density; the dual-chamber layout increases the equipment footprint and loading / unloading processes, reducing production line cycle time and capacity.

[0006] In summary, the existing PEALD process cannot simultaneously solve multiple problems such as thin film thickness at the edge of large silicon wafers, severe wrap-around plating, high interface defects, and high mass production costs.

[0007] Therefore, it is necessary to develop a partitioned pulsed PEALD coating process to solve the above problems. Summary of the Invention

[0008] The purpose of this invention is to design a partitioned pulsed PEALD coating process to solve the above problems.

[0009] The present invention achieves the above objectives through the following technical solutions: A partitioned pulsed PEALD coating process is described, in which the coating process is continuously completed without breaking the vacuum in the same plate-type integrated cavity. The cavity is divided into a central deposition zone and surrounding edge deposition zones. The central deposition zone and the edge deposition zones are equipped with independent spray air supply pipelines and independent air extraction pressure regulating valves, respectively. The coating process includes: Partitioned ozone stepwise pulsed cyclic PEALD deposition: Using silicon source and oxidant, a single complete deposition cycle is divided into four stages: partitioned silicon source pulse, partitioned nitrogen purging, partitioned oxidation pulse, and full-area nitrogen purging. The duration of silicon source pulse and oxidation pulse in the edge deposition area is longer than that in the center deposition area. In the partitioned nitrogen purging stage, the nitrogen purging flow rate in the edge deposition area is higher than that in the center deposition area to quickly remove excess precursors from the sides of the silicon wafer. Gradient pressure dynamic zoning control: During each round of pulse deposition, the central deposition area maintains a low pressure, while the edge deposition area maintains a higher pressure than the central deposition area. The pressure difference between the central deposition area and the edge deposition area is adjusted in real time to compensate for insufficient precursor molecule flux at the edge of the silicon wafer. In-situ deposition of doped amorphous silicon passivation layer in the same cavity: After the ultrathin tunnel oxide layer is deposited, the cavity is not opened or the vacuum is broken. The silane and phosphine gas sources are directly switched, and a phosphorus-doped amorphous silicon layer is deposited in-situ using a plate-type PECVD process. Subsequent high-temperature annealing and crystallization form n-type heavily doped polycrystalline silicon, and SiO2 is obtained completely. x / Poly-Si passivated contact structure.

[0010] Furthermore, prior to the partitioned ozone step-by-step pulsed cyclic PEALD deposition step, a partitioned plasma pretreatment of the silicon wafer is also included: the silicon wafer is placed on a plate-type PEALD partitioned stage, hydrogen is introduced into the partitioned cavity, and the partitioned remote plasma cleaning is started to remove organic contaminants and native natural oxide layer on the silicon wafer surface; after cleaning, the cavity is kept in a vacuum-sealed state and the furnace door is not opened.

[0011] Preferably, during the silicon wafer partitioned plasma pretreatment, the deposition temperature is 280-380℃; the pressure in the central deposition zone is 20-60Pa, and the pressure in the edge deposition zone is 60-120Pa; the hydrogen flow rate in the edge zone is greater than that in the central zone; the plasma partitions have independent power output; and the cleaning time is 30-90s.

[0012] Preferably, the silicon source is aminosilane and the oxidant is ozone.

[0013] Preferably, during the stepwise pulsed cyclic PEALD deposition of ozone, the total duration of a single cycle is 2–8 s; the silicon source pulse in the central deposition area is 0.3–0.8 s, and the silicon source pulse in the edge deposition area is 0.6–1.2 s; the ozone oxidation pulse in the central deposition area is 0.4–0.9 s, and the ozone oxidation pulse in the edge deposition area is 0.7–1.4 s.

[0014] Preferably, the process involves partitioned ozone stepwise pulsed cyclic PEALD deposition with a total of 80 to 200 pulse cycles, ultimately forming an ultrathin tunneling oxide layer with a thickness of 0.8 to 1.4 nm.

[0015] Preferably, during gradient pressure dynamic zoning control, the zoning pressure difference between the central deposition zone and the edge deposition zone is automatically corrected every 10 to 30 pulse cycles, with a correction range of 5 to 15 Pa.

[0016] The beneficial effects of this invention are as follows: By extending the duration of the silicon source and ozone pulse in the edge region, insufficient diffusion of precursors at the edge of large silicon wafers is compensated, alleviating the defect of thin film thickness at the edge. Combined with high-flow-rate zonal purging in the edge region, excess precursors adsorbed on the sides of the silicon wafer are quickly removed, reducing the need for front-side and side-side plating. Simultaneously, the high oxidation activity of ozone shortens the single-step reaction time, reduces the lateral diffusion range of precursors, and further suppresses the formation of side-side plating. This reduces intra-wafer film thickness non-uniformity, reduces leakage defects at the silicon wafer edge, simplifies the subsequent alkaline polishing and laser grooving processes, reduces processing costs, and improves cell yield. Furthermore, the ozone low-temperature PEALD deposition process avoids high-energy ion bombardment of the silicon substrate, which helps reduce the Si / silicon oxide interface state density, improves cell passivation performance, increases the implicit open-circuit voltage, and reduces saturation dark current.

[0017] High voltage in the edge region increases the molecular concentration of silicon source and ozone in the edge region of the silicon wafer, while low voltage in the center region prevents excessive growth of the central film, making the deposition rate of the center and the edge more consistent, significantly reducing the film thickness non-uniformity coefficient (CV) within the wafer, thereby reducing the open circuit voltage difference of a single cell and improving the electrical consistency of batch products.

[0018] The entire process of cleaning, PEALD oxidation, and polysilicon deposition is conducted without contact with air, which helps to avoid the regenerated oxide layer generated during silicon wafer transfer and reduces additional interface defects. The entire process only optimizes the software control timing and does not require modification of the plate-type PECVD equipment hardware. It has low mass production implementation costs, is easy to directly introduce into mass production lines, and can be adapted to various silicon wafer sizes such as 182 / 210. Attached Figure Description

[0019] Figure 1 This is a flowchart of the present invention. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0021] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0022] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0023] In the description of this invention, it should be understood that the terms "upper," "lower," "inner," "outer," "left," "right," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of this invention is in use, or the orientation or positional relationship commonly understood by those skilled in the art. They are only used to facilitate the description of this invention and to simplify the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0024] Furthermore, the terms "first," "second," etc., are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0025] In the description of this invention, it should also be noted that, unless otherwise explicitly specified and limited, terms such as "set" and "connection" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0026] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0027] like Figure 1 As shown, this scheme is a zoned pulsed PEALD coating process. The entire process is completed continuously without breaking the vacuum in the same plate-type integrated cavity. The cavity is divided into a central deposition zone and a surrounding edge deposition zone. The two zones are equipped with independent spray air supply pipelines and independent air extraction and pressure regulating valves, and include four major steps: S1-S4. S1. Silicon Wafer Partition Plasma Pretreatment: Place the 210mm N-type crystalline silicon wafer that has been alkaline polished on the back side onto a plate-type PEALD partitioned wafer stage, with independent temperature control for each partition; introduce hydrogen into each partition of the cavity and start remote plasma cleaning of each partition to remove organic contaminants and native natural oxide layer from the silicon wafer surface; after cleaning, maintain the cavity in a vacuum-sealed state and do not open the furnace door.

[0028] Process parameter range: deposition temperature 280-380℃; central zone pressure 20-60Pa, edge zone pressure 60-120Pa; hydrogen flow rate is greater in the edge zone than in the central zone; plasma zones have independent power output; cleaning time 30-90s.

[0029] S2, Partitioned Ozone Step-by-Step Pulse Cyclic PEALD Deposition: Using aminosilane as the silicon source and ozone as the oxidant, a single complete deposition cycle is divided into four stages: partitioned silicon source pulse, partitioned nitrogen purging, partitioned ozone oxidation pulse, and full-area nitrogen purging; to address the problem of insufficient gas supply at the edge of the silicon wafer, longer silicon source pulses and longer ozone pulses are set in the edge area; during the partitioned purging stage, the nitrogen purging flow rate in the edge area is higher than that in the center area, which quickly removes excess precursors from the side of the silicon wafer, inhibiting circumferential plating from the source; the strong oxidizing property of ozone can shorten the reaction pulse duration and reduce the lateral diffusion distance of the precursors.

[0030] Process parameter range: total cycle time 2-8s; central silicon source pulse 0.3-0.8s, edge silicon source pulse 0.6-1.2s; central ozone pulse 0.4-0.9s, edge ozone pulse 0.7-1.4s; total number of pulse cycles 80-200, ultimately forming an ultrathin tunneling oxide layer of 0.8-1.4nm.

[0031] S3. Gradient pressure dynamic zone control: During each pulse deposition cycle, the central deposition zone maintains low pressure and the edge deposition zone maintains higher partial pressure. The pressure difference between the two zones is adjusted in real time through an independent air extraction valve to compensate for insufficient precursor molecule flux at the edge of the silicon wafer. Every 10-30 pulse cycles, the zone pressure difference is automatically and slightly corrected (correction range 5-15Pa) to offset the airflow drift in the cavity caused by long-term deposition and to continuously stabilize the overall deposition rate.

[0032] S4. In-situ deposition of doped amorphous silicon passivation layer in the same cavity: After the ultrathin tunneling oxide layer is deposited, the cavity is not opened or the vacuum is broken. The silane and phosphine gas sources are directly switched, and a phosphorus-doped amorphous silicon layer is deposited in-situ using a plate-type PECVD process. Subsequent high-temperature annealing and crystallization form n-type heavily doped polycrystalline silicon, resulting in complete SiO₂. x / Poly-Si passivated contact structure.

[0033] Example 1 (Partitioned pulse + gradient pressure process of the present invention, 210mm silicon wafer) S1. Pretreatment: Temperature 320℃, center pressure 30Pa, edge pressure 70Pa, hydrogen zone flow rate differentiation, plasma cleaning 60s; S2, Partitioned Pulse Deposition: Silicon source TDMAS, center silicon source pulse 0.5s, edge 0.9s; ozone pulse 0.6s center, edge 1.1s; edge purging nitrogen flow rate is higher than center, total cycle 130 rounds; S3, Gradient pressure control: The pressure difference is kept constant at 30Pa throughout the entire process, and dynamically adjusted to 60-90Pa at the edge, with the pressure difference corrected every 20 cycles; S4. Phosphorus-doped amorphous silicon is deposited in the same cavity and annealed to prepare TOPCon passivated contact structures.

[0034] Measured data: tunneling oxide layer thickness 1.0 nm, in-wafer film thickness CV = 0.95%; edge-wrap coating thickness is 37% of conventional process; interface state density Dit = 5.8 × 10⁻⁶ 10 cm -2 eV -1 For the symmetrical sample, iVoc = 726mV and the saturation dark current J0 = 11.2fA / cm².

[0035] Comparative Example 1 (Traditional Single-Zone Constant Pressure PEALD) Using the same 210 silicon wafers, with no zoned gas supply, uniform pulse throughout, constant cavity pressure of 45Pa, and consistent temperature and cycle count as in the previous example.

[0036] Actual measured data: The edge film thickness of the silicon wafer is only 0.68 nm, and the on-wafer CV is 3.6%; severe edge-wrap plating is present; Dit = 1.02 × 10⁻⁶. 11 cm -2 eV-2 ; iVoc=719mV, J0=19.8fA / cm².

[0037] Comparative Example 2 (Partial pulse only, no gradient pressure control) Differentiated pulses are used in different zones, and the pressure is uniform throughout the cavity. All other process conditions are exactly the same as in Example 1.

[0038] Actual measurement data: The edge film thickness is slightly thinner, the in-wafer CV is 2.1%, the wrap-around coating only slightly improves the performance, and the passivation performance is only slightly improved.

[0039] Experimental conclusion: The combination of zoned ozone stepwise pulse circulation and gradient zoned pressure synergistic regulation can simultaneously solve three major mass production pain points: thin film thickness at the edge of large silicon wafers, severe over-plating, and poor interface passivation, demonstrating significant technical advantages.

[0040] The above are merely preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A partitioned pulsed PEALD coating process, characterized in that, The coating process is completed continuously without breaking the vacuum within the same integrated plate-type cavity. The cavity is divided into a central deposition zone and surrounding edge deposition zones. Each of the central and edge deposition zones is equipped with independent spray gas supply lines and independent suction pressure regulating valves. The coating process includes: Partitioned ozone stepwise pulsed cyclic PEALD deposition: Using silicon source and oxidant, a single complete deposition cycle is divided into four stages: partitioned silicon source pulse, partitioned nitrogen purging, partitioned oxidation pulse, and full-area nitrogen purging. The duration of silicon source pulse and oxidation pulse in the edge deposition area is longer than that in the center deposition area. In the partitioned nitrogen purging stage, the nitrogen purging flow rate in the edge deposition area is higher than that in the center deposition area to quickly remove excess precursors from the sides of the silicon wafer. Gradient pressure dynamic zoning control: During each round of pulse deposition, the central deposition area maintains a low pressure, while the edge deposition area maintains a higher pressure than the central deposition area. The pressure difference between the central deposition area and the edge deposition area is adjusted in real time to compensate for insufficient precursor molecule flux at the edge of the silicon wafer. In-situ deposition of doped amorphous silicon passivation layer in the same cavity: After the ultrathin tunnel oxide layer is deposited, without opening the cavity or breaking the vacuum, the silane and phosphine gas sources are directly switched to deposit a phosphorus-doped amorphous silicon layer in situ using a plate-type PECVD process; subsequent high-temperature annealing and crystallization form n-type heavily doped polycrystalline silicon, thus obtaining SiO2 completely. x / Poly-Si passivated contact structure.

2. The partitioned pulsed PEALD coating process according to claim 1, characterized in that, Before the partitioned ozone step-by-step pulsed cycle PEALD deposition step, a partitioned plasma pretreatment of the silicon wafer is also included: the silicon wafer is placed on a plate-type PEALD partitioned stage, hydrogen is introduced into the partitioned cavity, and the partitioned remote plasma cleaning is started to remove organic contaminants and native natural oxide layer on the surface of the silicon wafer; after cleaning, the cavity is kept in a vacuum-sealed state and the furnace door is not opened.

3. The partitioned pulsed PEALD coating process according to claim 2, characterized in that, During the silicon wafer partitioned plasma pretreatment, the deposition temperature is 280-380℃; the pressure in the central deposition zone is 20-60Pa, and the pressure in the edge deposition zone is 60-120Pa; the hydrogen flow rate in the edge zone is greater than that in the central zone; the plasma partitions have independent power output; and the cleaning time is 30-90s.

4. The partitioned pulsed PEALD coating process according to claim 1, characterized in that, The silicon source is aminosilane, and the oxidant is ozone.

5. The partitioned pulsed PEALD coating process according to claim 1, characterized in that, During the stepwise pulsed cyclic PEALD deposition of ozone, the total duration of a single cycle is 2–8 s; the silicon source pulse in the central deposition area is 0.3–0.8 s, and the silicon source pulse in the edge deposition area is 0.6–1.2 s; the ozone oxidation pulse in the central deposition area is 0.4–0.9 s, and the ozone oxidation pulse in the edge deposition area is 0.7–1.4 s.

6. The partitioned pulsed PEALD coating process according to claim 5, characterized in that, Partitioned ozone stepwise pulsed cyclic PEALD deposition, with a total of 80 to 200 pulse cycles, ultimately forms an ultrathin tunneling oxide layer with a thickness of 0.8 to 1.4 nm.

7. The partitioned pulsed PEALD coating process according to claim 1, characterized in that, During gradient pressure dynamic zonal control, the zonal pressure difference between the central deposition zone and the edge deposition zone is automatically corrected every 10 to 30 pulse cycles, with a correction range of 5 to 15 Pa.

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